A vertical power semiconductor device with a trench isolation layer and its preparation

Abstract

The present invention provides a vertical III-type nitride power semiconductor device structure with a trench isolation layer, which includes, from bottom to top, a cathode electrode, a heavily doped N-type nitride substrate region, a lightly doped N-type nitride drift region, a heavily doped P-type nitride region, and an anode electrode, wherein an isolation layer is provided between the vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region. The provision of the trench isolation layer structure of the present invention optimizes the electric field distribution inside the device, effectively improves the reverse performance of the device, and ensures excellent forward characteristics.

Description

Technical Field

[0001] The invention relates to a vertical III-group nitride power semiconductor device structure with a trench isolation layer and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Compared with the first-generation semiconductors represented by silicon and the second-generation semiconductors represented by gallium arsenide, the third-generation semiconductors represented by silicon carbide and group III nitrides have broad application prospects in high-frequency communications, power electronics and other fields due to their excellent properties such as large bandgap, high critical breakdown field strength, high thermal conductivity, and high electron saturation drift rate.

[0003] At present, the widely used nitride devices are mainly gallium nitride-based lateral high electron mobility transistors (HEMTs). However, the main disadvantage of lateral devices is that the reverse breakdown voltage of the device is proportional to the lateral electrode spacing of the device, resulting in a larger device size required in high-voltage working scenarios, which greatly increases the process manufacturing cost of the device. In order to solve this problem, fully vertical devices can achieve a higher reverse breakdown voltage by increasing the thickness of the vertical drift layer of the device, while effectively avoiding the current crowding effect that occurs in lateral structures and quasi-vertical structures, and reducing the forward on-resistance.

[0004] Schottky barrier diodes have become an important part of modern power electronic systems due to their advantages such as low voltage drop and fast switching speed. In order to meet the application of consumer electronics and high-frequency communication devices, higher requirements are placed on traditional Schottky diodes in high-voltage and high-power application scenarios, and the performance limitations of the devices are becoming more and more prominent. In high reverse bias scenarios, Schottky barrier diodes (SBDs) often produce a significant barrier lowering effect due to the strong electric field concentration under the Schottky contact barrier, resulting in a large reverse leakage current, which limits the reverse breakdown characteristics of the Schottky barrier diode.

[0005] The above problems can be solved by adopting a new structure of hybrid PiN junction barrier Schottky diode (MPS diode). Compared with the traditional planar Schottky barrier diode, the gallium nitride vertical hybrid PiN junction barrier Schottky diode can effectively modulate the electric field distribution under the Schottky contact barrier. By superimposing the depletion regions of adjacent PN junctions, a good electric field shielding effect can be formed on the Schottky contact barrier, avoiding the large leakage current and premature breakdown caused by the barrier lowering effect. However, if good depletion region protection is to be formed, the distance between adjacent PN junctions must be designed to be as small as possible, and a small channel width will show a large forward on-resistance under forward bias conditions, which is not conducive to the forward conduction of the device.

[0006] The present invention is proposed to solve the above-mentioned problems. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention provides a vertical III-nitride power semiconductor device structure with a trench isolation layer and a preparation method thereof by adjusting the distance between adjacent PN junctions while effectively ensuring that the forward characteristics are not degraded. The arrangement of the trench isolation layer structure of the present invention optimizes the electric field distribution inside the device, effectively improves the reverse performance of the device, and ensures excellent forward characteristics.

[0008] The technical solution of the present invention is as follows:

[0009] A vertical III-type group III nitride power semiconductor device structure with a trench isolation layer comprises, from bottom to top, a cathode electrode, a heavily doped N-type nitride substrate region, a lightly doped N-type nitride drift region, a heavily doped P-type nitride region, and an anode electrode, wherein an isolation layer is provided between vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region.

[0010] Preferably according to the present invention, the isolation layer is silicon dioxide, silicon nitride, hafnium oxide, aluminum nitride or aluminum oxide.

[0011] Preferably according to the present invention, an isolation layer is provided between the two vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region, and the lateral thickness of each isolation layer is 50 nm - 300 nm; preferably, the lateral thickness of each isolation layer is 50 nm - 150 nm, more preferably 50 nm.

[0012] Preferably according to the present invention, the lightly doped N-type nitride drift region is composed of a lightly doped N-type nitride drift layer and a lightly doped N-type nitride protrusion; the lightly doped N-type nitride protrusion is a rectangular structure, the lightly doped N-type nitride protrusion is arranged at a middle position above the lightly doped N-type nitride drift layer along the length direction of the lightly doped N-type nitride drift layer, and the lightly doped N-type nitride protrusion and the lightly doped N-type nitride drift layer form a "convex" shaped vertical cross-section; the heavily doped P-type nitride region is arranged on both sides of the lightly doped N-type nitride protrusion and on the upper surface of the lightly doped N-type nitride drift layer, and the thickness of the heavily doped P-type nitride region is the same as the thickness of the lightly doped N-type nitride protrusion.

[0013] Preferably, the lightly doped N-type nitride protrusion has a thickness of 0.5 μm-3.0 μm and a width of 1 μm-10 μm; preferably, the width of the lightly doped N-type nitride protrusion is 1 μm-5 μm, and more preferably 1 μm.

[0014] Preferably, the height of the isolation layer is the same as the thickness of the lightly doped N-type nitride protrusion.

[0015] Preferably, the sum of the width of one side of the heavily doped P-type nitride region, the thickness of a single isolation layer, and half the width of the lightly doped N-type nitride protrusion is equal to half the width of the lightly doped N-type nitride drift layer.

[0016] According to the preferred embodiment of the present invention, the doping element of the heavily doped P-type nitride region is magnesium ion, and the effective doping concentration is 1e16 cm -3 ~3e17 cm -3 Preferably, the effective doping concentration is 1e16 cm -3 ~2e17 cm -3 , and more preferably 1e17cm -3 .

[0017] According to the preferred embodiment of the present invention, the doping element of the lightly doped N-type nitride drift region is silicon, and the doping concentration is 5×10 14 ~3×10 16 cm -3 , the preferred doping concentration is 2e16 cm -3 .

[0018] Preferably according to the present invention, the anode electrode includes a Schottky contact anode electrode and an ohmic contact anode electrode; the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type nitride region.

[0019] Preferably according to the present invention, the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.

[0020] According to the present invention, the material types and thicknesses of the cathode electrode, the heavily doped N-type nitride substrate region, the lightly doped N-type nitride drift region, the anode electrode, etc. may be based on the prior art.

[0021] The method for preparing the vertical III-nitride power semiconductor device structure with a trench isolation layer comprises the steps of:

[0022] (1) Using MOCVD method to prepare heavily doped N-type nitride substrate region;

[0023] (2) homoepitaxially growing a lightly doped N-type nitride drift region on a heavily doped N-type nitride substrate region using a MOCVD method;

[0024] (3) using a dry etching process to etch trench regions on both sides of the upper surface of the lightly doped N-type nitride drift region; and then performing damage treatment on the etched surface;

[0025] (4) depositing an isolation layer at the bottom and sidewalls of the trench by plasma enhanced chemical vapor deposition (PECVD), and then removing the isolation layer at the bottom of the trench by anisotropic reactive ion etching (RIE);

[0026] (5) epitaxially growing a heavily doped P-type nitride region at the bottom of the trench;

[0027] (6) The cathode electrode and the anode electrode are prepared using an electron beam evaporator.

[0028] Preferably, according to the present invention, in step (4), the chamber reaction gas of plasma enhanced chemical vapor deposition (PECVD) is silane (SiH4) and oxygen (O2) diluted with hydrogen.

[0029] Preferably, according to the present invention, in step (4), the reactants of anisotropic reactive ion etching (RIE) are boron trichloride (BCl3) and chlorine (Cl2).

[0030] Preferably, according to the present invention, in step (5), the step of growing the heavily doped P-type nitride region by MOCVD method comprises:

[0031] ① Using silicon dioxide as a hard mask to cover the unetched top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer, ammonia is used as a nitrogen source, bismuth magnesium is used as a doping source, and H2 is used as a carrier gas. A layer of P-type nitride is homoepitaxially grown on both sides of the isolation layer and the upper surface of the lightly doped N-type nitride drift region by MOCVD method;

[0032] ② Then, in-situ annealing is performed in a MOCVD furnace to activate the P-type doped magnesium ions and grow a heavily doped P-type nitride region; the annealing temperature is 400-1500° C. and the annealing time is 10-90 minutes.

[0033] Preferably, according to the present invention, in step (5), the step of growing the heavily doped P-type nitride region by multiple epitaxy and ion implantation processes comprises:

[0034] ① Using silicon dioxide as a hard mask to cover the unetched top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer, ammonia gas was used as the nitrogen source, SiH3CH3 as the doping source, and H2 as the carrier gas. The MOCVD method was used to homogeneously epitaxially grow a layer of N-type nitride on both sides of the isolation layer and the upper surface of the lightly doped N-type nitride drift region. The doping concentration of silicon was 5×10 14 ~3×10 16 cm -3 , the preferred doping concentration is 2e16 cm -3 ;

[0035] ② Using an ion implanter to implant Mg ions into the N-type nitride region formed in step ①;

[0036] ③ Performing rapid thermal annealing in a gas atmosphere of one or a mixture of two or more of nitrogen, ammonia, argon, and hydrogen in any ratio; the annealing temperature is 400-1500° C., and the annealing time is 10-90 min;

[0037] ④ Repeat steps ① to ③ until a heavily doped P-type nitride region of a specified thickness is generated.

[0038] Preferably, according to the present invention, in step (5), the step of growing the heavily doped P-type nitride region using a low temperature pulsed sputtering deposition (PSD) process comprises:

[0039] ① Using silicon dioxide as a hard mask to block the unetched top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer, ammonia is used as a nitrogen source, bismuth magnesium is used as a doping source, and H2 is used as a carrier gas. A layer of P-type nitride is homoepitaxially grown on both sides of the isolation layer and the upper surface of the lightly doped N-type nitride drift region by the PSD method;

[0040] ② Then, the P-type doped magnesium ions are activated by in-situ annealing in the furnace to grow and form a heavily doped P-type nitride region; the annealing temperature is 400-1500° C. and the annealing time is 10-90 minutes.

[0041] Other processes of the present invention can be carried out according to the prior art.

[0042] The technical features and beneficial effects of the present invention are as follows:

[0043] 1. The present invention proposes a nitride vertical hybrid PiN junction barrier Schottky diode with a trench isolation layer that effectively improves reverse characteristics, and the specific beneficial effects are as follows: ① Under reverse bias conditions, the critical breakdown electric field strength of the isolation layer with a high bandgap width is large, and at the same time, the difference in dielectric constants can attract and withstand strong electric fields, thereby optimizing the electric field distribution inside the device and effectively improving the reverse performance of the device; ② The presence of the trench isolation layer strengthens the electric field shielding protection for the Schottky barrier electrode, so that the device structure can have a wider lateral Schottky electrode width, which greatly reduces the forward on-resistance and improves the forward performance.

[0044] 2. The preparation method of the present invention is applicable to the group III nitride system, the process is relatively simple, and the specific process conditions and deposition temperature are also well known to those skilled in the art.

[0045] 3. The present invention uses TCAD simulation to assist in analyzing device structural parameters, which can save a lot of time and cost and better guide the preparation of subsequent processes.

[0046] 4. The present invention continuously optimizes the structural parameters (heavily doped P-type nitride region doping concentration, Schottky contact width, and lateral thickness of the isolation layer) to achieve the optimal electrical breakdown characteristics of the hybrid PiN junction barrier Schottky diode. Through a large number of simulation calculations and analyses, in the nitride vertical hybrid PiN junction barrier Schottky diode structure with a trench isolation layer, the reverse voltage withstand capability of the device can be greatly improved while keeping the device size unchanged, making it possible to use the device in higher voltage scenarios. Therefore, this nitride vertical hybrid PiN junction barrier Schottky diode structure with a trench isolation layer will be very promising for the application of nitride vertical Schottky diodes in high-frequency, high-voltage, and high-power power electronics and integrated systems in the future, demonstrating that gallium nitride vertical power devices have the potential to become a new generation of ideal alternative products that break through the physical limits of traditional power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Schematic diagram of the structure of a vertical III-group gallium nitride power semiconductor device with a trench isolation layer in Example 1;

[0048] Figure 2 A schematic diagram of the structure of a conventional gallium nitride vertical power semiconductor device in Comparative Example 1;

[0049] Figure 3 is a graph showing the relationship between the doping concentration of the heavily doped P-type nitride region and the reverse breakdown voltage of the device in Experimental Example 1;

[0050] Figure 4 is a graph showing the relationship between the width of the Schottky contact anode electrode and the reverse breakdown voltage of the device in Experimental Example 2;

[0051] Figure 5 This is a graph showing the relationship between the lateral thickness of the isolation layer and the reverse breakdown voltage of the device in Experimental Example 3. DETAILED DESCRIPTION

[0052] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] The methods involved in the examples are all existing methods unless otherwise specified; the reagents and materials used are all commercially available unless otherwise specified.

[0054] Example 1

[0055] A vertical III-type gallium nitride power semiconductor device structure with a trench isolation layer, the structure is as follows Figure 1As shown, from bottom to top, it includes a cathode electrode, a heavily doped N-type gallium nitride substrate region, a lightly doped N-type gallium nitride drift region, a heavily doped P-type gallium nitride region, and an anode electrode; an isolation layer of silicon dioxide is respectively arranged between the two vertical contact surfaces of the heavily doped P-type gallium nitride region and the lightly doped N-type gallium nitride drift region, and the lateral thickness of each isolation layer is 50nm, and the height of the isolation layer is 1.5 μm.

[0056] The doping element of the lightly doped N-type gallium nitride drift region is silicon, and the doping concentration is 2e16 cm -3 . The lightly doped N-type gallium nitride drift region is composed of a lightly doped N-type gallium nitride drift layer and a lightly doped N-type gallium nitride protrusion; the lightly doped N-type gallium nitride protrusion is a rectangular parallelepiped structure, and the lightly doped N-type gallium nitride protrusion is arranged in the middle position above the lightly doped N-type gallium nitride drift layer along the length direction of the lightly doped N-type gallium nitride drift layer, and the lightly doped N-type gallium nitride protrusion and the lightly doped N-type gallium nitride drift layer form a "convex" shaped vertical cross section. The thickness of the lightly doped N-type gallium nitride drift layer is 13.5 μm, the thickness of the lightly doped N-type gallium nitride protrusion is 1.5 μm, the width of the lightly doped N-type gallium nitride protrusion is 1 μm, and the length of the lightly doped N-type gallium nitride protrusion is the same as the length of the lightly doped N-type gallium nitride drift layer.

[0057] The heavily doped P-type gallium nitride region is arranged on both sides of the lightly doped N-type gallium nitride protrusion and on the upper surface of the lightly doped N-type gallium nitride drift layer. The thickness of the heavily doped P-type gallium nitride region is the same as that of the lightly doped N-type gallium nitride protrusion, which is 1.5 μm. The doping element of the heavily doped P-type gallium nitride region is magnesium ion, and the effective doping concentration is 1e17 cm -3 .

[0058] The sum of the width of one side of the heavily doped P-type nitride region, the thickness of a single isolation layer, and half the width of the lightly doped N-type nitride protrusion is equal to half the width of the lightly doped N-type nitride drift layer.

[0059] The cathode electrode is: Ti / Al / Ni / Au, with corresponding thicknesses of 20 / 150 / 50 / 60nm.

[0060] The doping source of the heavily doped N-type gallium nitride substrate region is silicon, and the doping concentration is 5e18cm -3 , thickness is 2μm.

[0061] The anode electrode includes a Schottky contact anode electrode and an ohmic contact anode electrode, and the electrode material is Pd / Au with a corresponding thickness of 20 / 100nm; wherein the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type gallium nitride drift region and the upper surface of the isolation layer; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type gallium nitride region.

[0062] Example 2

[0063] A method for preparing a vertical III-type gallium nitride power semiconductor device structure with a trench isolation layer according to Embodiment 1, using a secondary epitaxial growth process to grow a heavily doped P-type gallium nitride region, comprises the following steps:

[0064] (1) Using trimethylgallium (TMGa) and ammonia (NH3) as Ga and N sources, SiH3CH3 as N-type impurity source, and H2 as carrier gas, a 2μm thick low-defect, low-dislocation heavily doped N-type GaN substrate region is achieved in MOCVD, with a silicon doping concentration of 5e18cm -3 ;

[0065] (2) Using trimethylgallium (TMGa) and ammonia (NH3) as Ga and N sources, SiH3CH3 as N-type impurity source, and H2 as carrier gas, a 15 μm thick lightly doped N-type GaN drift region was homoepitaxially grown on the surface of the heavily doped N-type GaN substrate region by MOCVD. The doping concentration of silicon was 2e16 cm -3 ;

[0066] (3) Using SiO2 as a hard mask on the epitaxial wafer to shield the non-etched area of ​​the epitaxial wafer, and etching the step groove area using inductively coupled plasma etching (ICP) in a mixed atmosphere of Cl2 / BCl3 / Ar;

[0067] (4) After dry etching, there are a large number of sloped peaks and burrs on the surface of the material. The sample is placed in a 25wt% TMAH solution and treated at 85°C for 1 hour to remove surface damage caused by etching: then the sample is placed in acetone and heated to 85°C, and heated in a water bath for 10 minutes; ultrasonic cleaning with isopropanol for 5 minutes, rinsed with deionized water 6 times, dried with nitrogen, and dried on a hot plate; a 25wt% ammonia solution is heated to 85°C in a water bath, and the sample is placed in the water bath and heated for 10 minutes; after taking the sample out of the ammonia solution, it is rinsed with deionized water 6 times to remove the ammonia on the surface and terminate the surface treatment effect of the ammonia solution, and then dried on a hot plate after drying; the etching depth and etching morphology are tested using an atomic force microscope;

[0068] (5) Depositing an isolation layer at the bottom and sidewalls of the trench by plasma enhanced chemical vapor deposition (PECVD), with the chamber reaction gases being hydrogen-diluted silane (SiH4) and oxygen (O2), and then removing the isolation layer at the bottom of the trench by anisotropic reactive ion etching (RIE), with the reactants being boron trichloride (BCl3) and chlorine (Cl2);

[0069] (6) Using MOCVD to perform secondary epitaxial growth of heavily doped P-type gallium nitride regions, the material layers have clear contours and are evenly distributed, including the following steps:

[0070] ① Using silicon dioxide as a hard mask to block the unetched top surface of the lightly doped N-type GaN drift region and the upper surface of the isolation layer, ammonia is used as the nitrogen source, bismuth magnesium is used as the doping source, trimethyl gallium (TMGa) is used as the Ga source, and H2 is used as the carrier gas. A layer of P-type GaN is homoepitaxially grown on both sides of the isolation layer and the upper surface of the lightly doped N-type GaN drift region by MOCVD method;

[0071] ② Then, in-situ annealing is performed in a MOCVD furnace to activate the P-type doped magnesium ions and grow a heavily doped P-type gallium nitride region; the annealing temperature is 850° C., the annealing time is 25 minutes, and the annealing atmosphere is nitrogen.

[0072] (7) The cathode electrode and the anode electrode are prepared using an electron beam evaporator.

[0073] Example 3

[0074] A method for preparing a vertical III-type gallium nitride power semiconductor device structure with a trench isolation layer according to Embodiment 1 is as described in Embodiment 2, except that: in step (6), a heavily doped P-type gallium nitride region is grown by a process of multiple epitaxy plus ion implantation, and the specific steps are as follows:

[0075] ① Using silicon dioxide as a hard mask to block the unetched top surface of the lightly doped N-type GaN drift region and the upper surface of the isolation layer, ammonia was used as the nitrogen source, SiH3CH3 was used as the doping source, trimethyl gallium (TMGa) was used as the Ga source, and H2 was used as the carrier gas. The MOCVD method was used to homogeneously epitaxially grow a layer of N-type GaN with a thickness of 0.3 ~ 0.6μm on both sides of the isolation layer and the upper surface of the lightly doped N-type GaN drift region. The doping concentration of silicon was 2e16 cm -3 ;

[0076] ② Using an ion implanter, Mg ions are implanted into the N-type gallium nitride region formed in step ①; the power energy of the ion implantation is set to 150 ~ 300 keV, and the implantation depth is 0.3 ~ 0.6 μm;

[0077] ③ Perform rapid thermal annealing in a nitrogen atmosphere; the annealing temperature is 850° C., the annealing time is 25 min, and the annealing atmosphere is nitrogen.

[0078] ④ Repeat steps ① to ③ until a heavily doped P-type gallium nitride region with a specified thickness of 1.5 μm is generated.

[0079] The ion implantation process achieves the elimination of an interface between the implanted layer and the substrate, resulting in high bonding strength and good adhesion, and will not change the device's dimensions and surface finish.

[0080] The other steps and conditions are consistent with those in Example 2.

[0081] Example 4

[0082] A method for preparing a vertical III-type gallium nitride power semiconductor device structure with a trench isolation layer according to embodiment 1 is as described in embodiment 2, except that: in step (6), a low-temperature pulsed sputtering deposition (PSD) process is used to grow a heavily doped P-type gallium nitride region, and the specific steps are as follows:

[0083] ① Using silicon dioxide as a hard mask to block the unetched top surface of the lightly doped N-type GaN drift region and the upper surface of the isolation layer, ammonia is used as the nitrogen source, bismuth magnesium is used as the doping source, trimethyl gallium (TMGa) is used as the Ga source, and H2 is used as the carrier gas. A layer of P-type GaN is homoepitaxially grown on both sides of the isolation layer and the upper surface of the lightly doped N-type GaN drift region by the PSD method. The temperature is set to 480°C, and the gas atmosphere is nitrogen / argon (N2 / Ar);

[0084] ② Then, the P-type doped magnesium ions are activated by in-situ annealing in the furnace to grow and form a heavily doped P-type gallium nitride region; the annealing temperature is 850° C., the annealing time is 25 minutes, and the annealing atmosphere is nitrogen.

[0085] PSD is used for sputtering growth, and the growth quality is high, close to the quality of MOCVD secondary epitaxial growth.

[0086] The other steps and conditions are consistent with those in Example 2.

[0087] Comparative Example 1

[0088] A conventional III-group gallium nitride vertical power semiconductor device structure, such as Figure 2 As shown, as described in Example 1, the difference is that no isolation layer is set between the vertical contact surfaces of the heavily doped P-type gallium nitride region and the lightly doped N-type gallium nitride drift region, but they are in direct contact; other structures and parameters are consistent with Example 1.

[0089] The specific structure is as follows: from bottom to top, it includes a cathode electrode, a heavily doped N-type gallium nitride substrate region, a lightly doped N-type gallium nitride drift region, a heavily doped P-type gallium nitride region, and an anode electrode.

[0090] The doping element of the lightly doped N-type gallium nitride drift region is silicon, and the doping concentration is 2e16 cm -3. The lightly doped N-type gallium nitride drift region is composed of a lightly doped N-type gallium nitride drift layer and a lightly doped N-type gallium nitride protrusion; the lightly doped N-type gallium nitride protrusion is a rectangular parallelepiped structure, and the lightly doped N-type gallium nitride protrusion is arranged in the middle position above the lightly doped N-type gallium nitride drift layer along the length direction of the lightly doped N-type gallium nitride drift layer, and the lightly doped N-type gallium nitride protrusion and the lightly doped N-type gallium nitride drift layer form a "convex" shaped vertical cross section. The thickness of the lightly doped N-type gallium nitride drift layer is 13.5 μm, the thickness of the lightly doped N-type gallium nitride protrusion is 1.5 μm, the width of the lightly doped N-type gallium nitride protrusion is 1 μm, and the length of the lightly doped N-type gallium nitride protrusion is the same as the length of the lightly doped N-type gallium nitride drift layer.

[0091] The heavily doped P-type gallium nitride region is arranged on both sides of the lightly doped N-type gallium nitride protrusion and on the upper surface of the lightly doped N-type gallium nitride drift layer. The thickness of the heavily doped P-type gallium nitride region is the same as that of the lightly doped N-type gallium nitride protrusion, which is 1.5 μm. The doping element of the heavily doped P-type gallium nitride region is magnesium ion, and the effective doping concentration is 1e17 cm -3 .

[0092] The sum of the width of one side of the heavily doped P-type nitride region, the thickness of a single isolation layer, and half the width of the lightly doped N-type nitride protrusion is equal to half the width of the lightly doped N-type nitride drift layer.

[0093] The cathode electrode is: Ti / Al / Ni / Au, with corresponding thicknesses of 20 / 150 / 50 / 60nm.

[0094] The doping source of the heavily doped N-type gallium nitride substrate region is silicon, and the doping concentration is 5e18cm -3 , thickness is 2μm.

[0095] The anode electrode includes a Schottky contact anode electrode and an ohmic contact anode electrode, and the electrode materials are both Pd / Au, with a corresponding thickness of 20 / 100nm; wherein the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type gallium nitride drift region; and the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type gallium nitride region.

[0096] The method for preparing the above-mentioned conventional III-group gallium nitride vertical power semiconductor device structure is as described in Example 2, except that step (5) is omitted; the other steps and conditions are consistent with Example 2.

[0097] Test Example 1

[0098] The magnesium ion doping concentration of the heavily doped P-type gallium nitride region in Example 1 is changed (the range is 1e16 cm -3 ~3e17cm -3 ), the relationship between the reverse breakdown voltage and doping concentration of the obtained device is shown in the figure Figure 3 As shown in the figure, it can be seen intuitively that when the concentration is low, the depletion effect of the heavily doped P-type GaN region is weak and cannot provide good electric field shielding protection. When the concentration is too high, local electric field concentration will appear near the heavily doped P-type GaN region, causing the device to break down prematurely, and both will show poor reverse breakdown characteristics. Furthermore, the optimal magnesium ion doping concentration is 1e17 cm -3 .

[0099] Test Example 2

[0100] The relationship between the reverse breakdown voltage of the obtained device and the width of the Schottky contact anode electrode is shown in the figure below: Figure 4 The magnesium doping concentration of the heavily doped P-type GaN region is set to the optimal value of 1e17 cm -3 It can be seen that, regardless of whether there is a trench isolation layer or not, the increase in the width of the Schottky electrode will lead to a decrease in the reverse breakdown voltage; further, the structure with a trench isolation layer will show a smaller decrease in the reverse breakdown voltage; further, the presence of the trench isolation layer can effectively improve the reverse breakdown voltage of the device.

[0101] Test Example 3

[0102] The relationship between the reverse breakdown voltage of the obtained device and the lateral thickness of the isolation layer in Example 1 (varying range 50-300 nm), that is, the lateral thickness of each isolation layer, is shown in the figure below: Figure 5 The magnesium doping concentration of the heavily doped P-type GaN region is set to 1e17 cm -3 The greater the lateral thickness of the isolation layer, the worse the reverse breakdown characteristics of the device; further, when the material of the isolation layer is silicon dioxide, the lateral thickness of the isolation layer is preferably 50nm; further, the increase in the thickness of the isolation layer will lead to a weakening of the depletion effect of p-GaN on the trench channel carriers, reducing the effect of p-GaN.

Claims

1. A vertical III-nitride power semiconductor device structure with a trench isolation layer, characterized in that: The device includes, from bottom to top, a cathode electrode, a heavily doped N-type nitride substrate region, a lightly doped N-type nitride drift region, a heavily doped P-type nitride region, and an anode electrode, wherein an isolation layer is provided between vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region; The isolation layer is silicon dioxide, silicon nitride, hafnium oxide, aluminum nitride or aluminum oxide; an isolation layer is provided between two vertical contact surfaces of the heavily doped P-type nitride region and the lightly doped N-type nitride drift region, and the lateral thickness of each isolation layer is 50 nm - 150 nm; The doping element of the heavily doped P-type nitride region is magnesium ion, and the effective doping concentration is 1e17 cm -3 ; The lightly doped N-type nitride drift region is composed of a lightly doped N-type nitride drift layer and a lightly doped N-type nitride protrusion; the lightly doped N-type nitride protrusion is a rectangular parallelepiped structure, the lightly doped N-type nitride protrusion is arranged at a middle position above the lightly doped N-type nitride drift layer along the length direction of the lightly doped N-type nitride drift layer, and the lightly doped N-type nitride protrusion and the lightly doped N-type nitride drift layer form a "convex" shaped vertical cross section; the heavily doped P-type nitride region is arranged on both sides of the lightly doped N-type nitride protrusion and on the upper surface of the lightly doped N-type nitride drift layer, and the thickness of the heavily doped P-type nitride region is the same as the thickness of the lightly doped N-type nitride protrusion; The thickness of the lightly doped N-type nitride protrusion is 0.5 μm - 3.0 μm, and the width is 1 μm - 5 μm; the height of the isolation layer is the same as the thickness of the lightly doped N-type nitride protrusion; The anode electrode includes a Schottky contact anode electrode and an ohmic contact anode electrode; the Schottky contact anode electrode is arranged on the top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer; the ohmic contact anode electrode is arranged on the upper surface of the heavily doped P-type nitride region.

2. The vertical III-nitride power semiconductor device structure with a trench isolation layer according to claim 1, characterized in that: The lateral thickness of each isolation layer is 50 nm.

3. The vertical III-nitride power semiconductor device structure with a trench isolation layer according to claim 1, characterized in that: Includes one or more of the following conditions: i. The width of the lightly doped N-type nitride protrusion is 1 μm; ii. The sum of the width of one side of the heavily doped P-type nitride region, the thickness of a single isolation layer, and half the width of the lightly doped N-type nitride protrusion is equal to half the width of the lightly doped N-type nitride drift layer.

4. The vertical III-nitride power semiconductor device structure with a trench isolation layer according to claim 1, characterized in that: Includes one or more of the following conditions: i. The doping element of the lightly doped N-type nitride drift region is silicon, and the doping concentration is 5×10 14 ~3×10 16 cm -3 ; ii. The heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.

5. A method for preparing a vertical III-nitride power semiconductor device structure with a trench isolation layer according to any one of claims 1 to 4, comprising the steps of: (1) Using MOCVD method to prepare heavily doped N-type nitride substrate region; (2) homoepitaxially growing a lightly doped N-type nitride drift region on a heavily doped N-type nitride substrate region using a MOCVD method; (3) using a dry etching process to etch trench regions on both sides of the upper surface of the lightly doped N-type nitride drift region; and then performing damage treatment on the etched surface; (4) depositing an isolation layer at the bottom and sidewalls of the trench by plasma enhanced chemical vapor deposition (PECVD), and then removing the isolation layer at the bottom of the trench by anisotropic reactive ion etching (RIE); (5) epitaxially growing a heavily doped P-type nitride region at the bottom of the trench; (6) The cathode electrode and the anode electrode are prepared using an electron beam evaporator.

6. The method for preparing a vertical III-nitride power semiconductor device structure with a trench isolation layer according to claim 5, characterized in that: Includes one or more of the following conditions: i. In step (4), the chamber reaction gas of plasma enhanced chemical vapor deposition (PECVD) is silane (SiH4) and oxygen (O2) diluted with hydrogen; ii. In step (4), the reactants of anisotropic reactive ion etching (RIE) are boron trichloride (BCl3) and chlorine (Cl2).

7. The method for preparing a vertical III-nitride power semiconductor device structure with a trench isolation layer according to claim 5, characterized in that: In step (5), the heavily doped P-type nitride region is prepared by one of the following methods: i. The steps of growing a heavily doped P-type nitride region by MOCVD method include: ① Using silicon dioxide as a hard mask to cover the unetched top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer, ammonia is used as a nitrogen source, bismuth magnesium is used as a doping source, and H2 is used as a carrier gas. A layer of P-type nitride is homoepitaxially grown on both sides of the isolation layer and the upper surface of the lightly doped N-type nitride drift region by MOCVD method; ② Then, in-situ annealing is performed in a MOCVD furnace to activate the P-type doped magnesium ions and grow a heavily doped P-type nitride region; the in-situ annealing temperature is 400-1500° C. and the in-situ annealing time is 10-90 min; ii. The steps of growing a heavily doped P-type nitride region by multiple epitaxy and ion implantation processes include: ① Using silicon dioxide as a hard mask to cover the unetched top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer, ammonia gas was used as the nitrogen source, SiH3CH3 as the doping source, and H2 as the carrier gas. The MOCVD method was used to homogeneously epitaxially grow a layer of N-type nitride on both sides of the isolation layer and the upper surface of the lightly doped N-type nitride drift region. The doping concentration of silicon was 5×10 14 ~3×10 16 cm -3 ; ② Using an ion implanter to implant Mg ions into the N-type nitride region formed in step ①; ③ Performing rapid thermal annealing in a gas atmosphere of one or a mixture of two or more of nitrogen, ammonia, argon, and hydrogen; the rapid thermal annealing temperature is 400-1500° C., and the rapid thermal annealing time is 10-90 min; ④ Repeat steps ① to ③ until a heavily doped P-type nitride region of a specified thickness is generated; iii. The steps of growing a heavily doped P-type nitride region using a low temperature pulsed sputtering deposition (PSD) process include: ① Using silicon dioxide as a hard mask to shield the unetched top surface of the lightly doped N-type nitride drift region and the upper surface of the isolation layer, using ammonia as a nitrogen source, bismuth magnesium as a doping source, and H2 as a carrier gas, and using the low-temperature pulse sputtering deposition method to homoepitaxially grow a layer of P-type nitride on both sides of the isolation layer and the upper surface of the lightly doped N-type nitride drift region; ② Then, the P-type doped magnesium ions are activated by in-situ annealing in the furnace to grow and form a heavily doped P-type nitride region; the in-situ annealing temperature is 400-1500° C., and the in-situ annealing time is 10-90 minutes.

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