A semiconductor integrated circuit device and a method for manufacturing the same

Abstract

The present invention discloses a semiconductor integrated circuit device and a method for manufacturing the same. The structure adopted by the semiconductor integrated circuit device is that a first electrode is connected to the resistive switching layer at the side wall of the resistive switching layer, and is connected from the inner side of the resistive switching layer through a second electrode. Thus, a conductive filament is formed on the side wall of the resistive switching layer after voltage is applied. In this way, the resistive switching occurrence area can be reduced by reducing the height of the first electrode, which allows the electric field to be applied more concentratedly to the resistive switching layer during electrical operation, thereby improving the uniformity of the device. In addition, since the resistive switching area is located on the side wall of the resistive switching layer, it is formed by deposition and has not been etched, and there is no damage caused by etching; at the same time, the resistive switching area is located on the side wall of the resistive switching layer, which can also avoid the problem of unevenness of the resistive switching layer caused by depression of the through hole, so that the performance of the resistive switching layer can be better and the service life can be longer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a resistive random access memory (RRAM) and a manufacturing method thereof. Background Art

[0002] The basic structure of a resistive random access memory includes a top electrode, a resistive switching layer and a bottom electrode, and usually uses a sandwich structure stacked layer by layer from bottom to top. Usually, due to the large contact area between the electrode and the resistive switching layer, the distribution of the conductive filaments is more random, which is not conducive to the consistency of the device.

[0003] In addition, when the sandwich structure is etched, the side wall of the resistive switching layer will be damaged, thereby affecting the performance of the resistive switching layer.

[0004] If a sandwich-structured resistive random access memory is connected by vias, depressions may occur at the support of the via material, causing the resistive layer to be uneven, which may also affect the performance of the resistive layer. Summary of the invention

[0005] In view of the above technical problems, the inventors creatively provide a semiconductor integrated circuit device and a method for manufacturing the same.

[0006] According to a first aspect of an embodiment of the present invention, a semiconductor integrated circuit device is provided, comprising: a resistive layer, which is a groove-shaped structure opening upward; a first electrode located on the outside of the resistive layer, and a second electrode located on the inside of the resistive layer, the first electrode and the second electrode being opposite to each other on both sides of the side wall of the resistive layer; the resistive layer, the first electrode and the second electrode forming a first storage unit.

[0007] According to an implementation of an embodiment of the present invention, the semiconductor integrated circuit device further includes: a through hole located below the first electrode; a first metal layer connected to the first electrode through the through hole; and a second metal layer connected to the second electrode.

[0008] According to an embodiment of the present invention, the semiconductor integrated circuit device also includes: a second storage cell having the same structure as the first storage cell, the first electrode of the second storage cell is connected to the first metal layer through a through hole below, the second electrode of the second storage cell is connected to the second metal layer, and the first storage cell and the second storage cell are separated.

[0009] According to an implementation of an embodiment of the present invention, the semiconductor integrated circuit device further includes: a third memory cell having the same structure as the first memory cell, and a first electrode of the third memory cell is connected to the first metal layer through a through hole therebelow.

[0010] According to an implementation of an embodiment of the present invention, the second electrode of the third storage unit is connected to the third metal layer through the second metal layer above and the through hole, forming a 1T2R structure.

[0011] According to a second aspect of an embodiment of the present invention, a method for manufacturing a semiconductor integrated circuit device is provided, the method comprising: forming a first electrode on a substrate, the substrate comprising a first through hole connected to a first metal layer; engraving a groove on the first electrode at a position offset from the first through hole, forming a resistive layer in the groove, so that the resistive layer is a groove-shaped structure with an opening upward; forming a second electrode in the opening of the resistive layer to obtain a first storage unit.

[0012] According to an implementation manner of an embodiment of the present invention, the manufacturing method further includes: forming a second metal layer on the second electrode, so that the second metal layer is connected to the second electrode of the first storage unit.

[0013] According to an implementation of an embodiment of the present invention, the manufacturing method further includes: manufacturing a second storage unit at the same time as manufacturing the first storage unit, so that the first electrode of the second storage unit is connected to the first metal layer through the through hole below, and the second electrode of the second storage unit is connected to the second metal layer; and forming a partition between the first storage unit and the second storage unit.

[0014] According to an implementation manner of an embodiment of the present invention, the manufacturing method further includes: manufacturing a third storage unit while manufacturing the first storage unit, so that the first electrode of the third storage unit is connected to the first metal layer through the through hole below.

[0015] According to an implementation of an embodiment of the present invention, the manufacturing method further includes: forming a through hole and a third metal layer above the second electrode of the third storage unit, so that the second electrode of the third storage unit is connected to the third metal layer through the second metal layer above and the through hole, forming a 1T2R structure.

[0016] The present invention discloses a semiconductor integrated circuit device and a method for manufacturing the same. The structure adopted by the semiconductor integrated circuit device is that a first electrode is connected to the resistive switching layer at the side wall of the resistive switching layer, and is connected from the inner side of the resistive switching layer through a second electrode. Thus, a conductive filament is formed on the side wall of the resistive switching layer after voltage is applied. In this way, the resistive switching occurrence area can be reduced by reducing the height of the first electrode, which allows the electric field to be more concentratedly applied to the resistive switching layer during electrical operation, thereby improving the uniformity of the device. In addition, since the resistive switching area is located on the side wall of the resistive switching layer, it is formed by deposition and has not been etched, and there is no damage caused by etching; at the same time, the resistive switching area is located on the side wall of the resistive switching layer, which can also avoid the problem of unevenness of the resistive switching layer caused by depression of the through hole, so that the performance of the resistive switching layer can be better and the service life can be longer.

[0017] It should be understood that the implementation of the embodiments of the present invention does not need to achieve all of the above beneficial effects, but a specific technical solution can achieve a specific technical effect, and other implementations of the embodiments of the present invention can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0019] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0020] Figure 1 A schematic cross-sectional view of the structure of a semiconductor integrated circuit device according to an embodiment of the present invention is shown;

[0021] Figure 2 Shows Figure 1 A schematic top view of the embodiment shown;

[0022] Figure 3 A schematic cross-sectional view of the structure of another embodiment of a semiconductor integrated circuit device of the present invention is shown;

[0023] Figure 4 Shows Figure 3 A schematic top view of the embodiment shown;

[0024] Figure 5 A schematic cross-sectional view of the structure of another embodiment of a semiconductor integrated circuit device of the present invention is shown;

[0025] Figure 6 Shows Figure 5 A schematic top view of the embodiment shown;

[0026] Figure 7 A schematic flow chart showing a method for manufacturing a semiconductor integrated circuit device of the present invention is shown;

[0027] Figure 8 The present invention is shown Figure 1 A schematic diagram of the manufacturing process of the illustrated embodiment;

[0028] Fig. 9 The present invention is shown Figure 1 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0029] Fig.10 The present invention is shown Figure 1 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0030] Fig.11 The present invention is shown Figure 1 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0031] Fig.12 The present invention is shown Figure 1 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0032] Fig.13 The present invention is shown Figure 1 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0033] Fig.14 The present invention is shown Figure 1 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0034] Fig.15 The present invention is shown Figure 3 or Figure 5 A schematic diagram of the manufacturing process of the illustrated embodiment;

[0035] Fig.16 The present invention is shown Figure 3 or Figure 5 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0036] Fig.17 The present invention is shown Figure 3 or Figure 5 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0037] Fig.18 The present invention is shown Figure 3 or Figure 5 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0038] Fig.19 The present invention is shown Figure 3 or Figure 5 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment;

[0039] Fig. 20 The present invention is shown Figure 3 or Figure 5 A schematic cross-sectional view of the structure of a certain stage in the manufacturing process of the illustrated embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0041] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] Figure 1 FIG. 2 is a schematic diagram showing a cross-sectional structure of a semiconductor integrated circuit device according to an embodiment of the present invention. Figure 1 The semiconductor integrated circuit device includes: a resistive layer 110, which is a groove-shaped structure with an opening upward; a first electrode 106 located on the outside of the resistive layer, and a second electrode 112 located on the inside of the resistive layer, the first electrode 106 and the second electrode 112 are opposite to each other on both sides of the side wall of the resistive layer 110; the resistive layer 110, the first electrode 106 and the second electrode 112 form a first storage unit.

[0044] The resistive switching layer 110 may be made of one or more resistive switching materials. Commonly used resistive switching materials include: aluminum oxide (Al x O y ), copper oxide (Cu x O y ), Hafnium Oxide (Hf x O y ) and other transition metal oxides (TMO).

[0045] The first electrode 106 and the second electrode 112 may be made of one or more electrode materials. Commonly used electrode materials include aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and tungsten nitride (WN).

[0046] In the semiconductor integrated circuit device of this embodiment, an oxygen reservoir layer 111 (Oxygen Ion Reservoir, OIR) is also provided between the resistive layer 110 and the second electrode 112 to attract or store more oxygen when voltage is applied. The material of the oxygen reservoir layer 111 mainly includes titanium (Ti) and tantalum (Ta). The oxygen reservoir layer is a gain structure that makes the memory cell performance better, but it is not a necessary structure for the memory cell. The implementer can choose to set it or not according to the needs.

[0047] like Figure 1 As shown, the structure adopted by the semiconductor integrated circuit device in this embodiment is such that the first electrode 106 and the second electrode 112 are opposite to each other on both sides of the side wall of the resistive layer 110. As long as the first electrode 106 and the second electrode 112 are respectively connected to circuits of different electrodes, an electric field can be formed on the side wall of the resistive layer 110 after voltage is applied, and when the voltage reaches the formation voltage, a conductive filament is formed to obtain a resistive region.

[0048] In this way, the resistive switching region can be reduced by reducing the height of the first electrode 106 , which enables the electric field to be applied more concentratedly to the resistive switching layer during electrical operation, thereby improving the uniformity of the device.

[0049] In addition, since the resistive region is located on the side wall of the resistive layer 110 and is formed by deposition without being etched, there is no damage caused by etching; moreover, the resistive region is located on the side wall of the resistive layer 110, which can also avoid the problem of unevenness of the resistive layer caused by the depression of the through hole, thereby making the resistive layer 110 have better performance and longer service life.

[0050] The semiconductor integrated circuit device of this embodiment further includes: a through hole 105 located below the first electrode 106 , a first metal layer 101 connected to the first electrode 106 through the through hole 105 ; and a second metal layer 113 connected to the second electrode 112 .

[0051] The first metal layer 101 and the second metal layer 113 are respectively connected to the circuits in the semiconductor basic circuit device, so that a resistive switching region can be formed on the sidewall of the resistive switching layer 110 after a voltage is applied.

[0052] Theoretically, as long as the storage unit has the above structure, no matter which wiring method is used, it is sufficient to connect the first electrode and the second electrode to the circuits of different electrodes respectively. Figure 1 The wiring structure formed by the through hole 105, the first metal layer 101 and the second metal layer 113 can make the structure of the semiconductor integrated circuit device more compact and the plane area smaller.

[0053] Furthermore, the semiconductor integrated circuit device of this embodiment includes a plurality of memory cells. Figure 1 Only two of the memory cells are shown, wherein the memory cell shown on the left is the first memory cell R1, and the other memory cell shown on the right is the second memory cell R2. The second memory cell R2 has the same structure as the first memory cell R1, and its first electrode is also connected to the first metal layer 101 through the through hole below, and the second electrode is also connected to the second metal layer 113, but the first memory cell R1 and the second memory cell R2 are separated.

[0054] Figure 2 FIG. 2 shows a schematic top view of the first storage unit R1 and the second storage unit R2 in the semiconductor integrated circuit device of this embodiment. Figure 2 As shown, the second metal layer 113 is mainly disposed directly above the first storage unit R1 and the second storage unit R2, and is connected to the first storage unit R1 and the second storage unit R2, respectively.

[0055] In addition, the semiconductor integrated circuit device of this embodiment also includes some other commonly used components, such as an insulating layer 104, a dielectric layer 103 located on the substrate 102, etc. These parts are exemplary and are not limitations on the semiconductor integrated circuit device of this application. The implementer can use any applicable layout and design according to the implementation needs and implementation conditions.

[0056] Figure 3 A schematic cross-sectional view of the structure of another embodiment of a semiconductor integrated circuit device according to the present invention is shown.

[0057] exist Figure 3 The semiconductor integrated circuit device of the embodiment shown includes the following Figure 1 The structure is similar to the embodiment shown: a first storage unit R1 formed by a resistive layer 211 with a groove structure opening upward, a first electrode 206 located outside the resistive layer 211, a second electrode 213 located inside the resistive layer 211, and an oxygen storage layer 212, and a second unit R2 with the same structure as the first storage unit R1.

[0058] Among them, the first electrodes of the first storage unit R1 and the second storage unit R2 (for example, the first electrode 206) are connected to the first metal layer (for example, the first metal layer 201) through the lower through hole (for example, the through hole 205), and the second electrodes of the first storage unit R1 and the second storage unit R2 (for example, the second electrode 213) are connected to the second metal layer (for example, the second metal layer 214).

[0059] and Figure 1 Similar to the embodiment shown, Figure 3 In the illustrated embodiment, some other commonly used components are also included, such as insulating layer 204 and insulating layer 207 , dielectric layer 203 located on substrate 202 , and the like.

[0060] besides, Figure 3 The semiconductor integrated circuit device of the embodiment shown also includes: a third storage cell R3 having the same structure as the first storage cell R1, and the first electrode of the third storage cell R3 is connected to the first metal layer 201 through the through hole 205 below. Among them, although the third storage cell R3 located between the first storage cell R1 and the second storage cell R2 is also provided with a second metal layer 214, the second metal layer 214 on the third storage cell R3 is a metal block separated on all sides and is not connected to any circuit. Therefore, when a voltage is applied to the second metal layer 214 connected to the circuit, the third storage cell R3 is not energized.

[0061] Figure 4 Shows Figure 3 FIG. 1 is a schematic top view of a semiconductor integrated circuit device according to an embodiment of the present invention. Figure 4 As shown, the first memory cell R1, the second memory cell R2 and the third memory cell R3 are all connected to the second metal layer 214. The difference is that the second metal layers 214 of the first memory cell R1 and the second memory cell R2 are connected together, and the second metal layer 214 is the bit line of the first memory cell R1 and the second memory cell R2. The second metal 214 on the third memory cell R3 is a metal block isolated on all sides and will not be connected from the second metal layer.

[0062] exist Figure 3 The embodiment shown is Figure 1 Compared with the embodiment shown in the figure, the structure is more balanced, especially when grinding, the force is more uniform, so the quality of the manufactured semiconductor integrated circuit device is also higher. At the same time, the existence of R3 also makes it possible to make 1T1R and 1T2R on the same set of molds (masks) by only changing the mask 215 / 216, which is convenient for adjustment according to actual needs.

[0063] Figure 5 A schematic cross-sectional view of the structure of another embodiment of a semiconductor integrated circuit device according to the present invention is shown.

[0064] Figure 5 The semiconductor integrated circuit device of the embodiment shown in FIG. Figure 3 On the basis of the semiconductor integrated circuit device of the embodiment shown, the second electrode of the third storage cell R3 is connected to the third metal layer 216 through the upper through hole 215 to form a 1T2R structure.

[0065] Figure 6 Shows Figure 5 FIG. 1 is a schematic top view of a semiconductor integrated circuit device according to an embodiment of the present invention. Figure 6 As shown, the first storage unit R1 and the second storage unit R2 are both connected by the second metal layer 214, and the third storage unit R3 is not connected by the second metal layer 214, but uses the second metal layer as a connecting bracket (landing pad), forms a through hole on the second metal layer to connect to the third metal layer 216, and is connected by the third metal layer 216.

[0066] In this way, the first storage unit R1 and the third storage unit R3 are connected to the first metal layer 201 through the through hole 205 under the first electrode 206, and the first metal layer 201 can be connected to the same transistor through the same source line; and because the second electrode of the first storage unit R1 is connected to the second metal layer 214, the second metal layer 214 is connected to the first bit line; the second electrode of the third storage unit R3 is connected to the third metal layer 216, and the third metal layer 216 is connected to the second bit line. In this way, the first storage unit R1 and the third storage unit R3 form two independently controllable resistive memory. The first bit line can independently control the first storage unit R1, and the second bit line can independently control the third storage unit R3, thereby realizing a one-transistor-connected two resistive memory (1T2R) structure.

[0067] In addition, the 1T2R structure can further increase the storage capacity by stacking more resistive random access memories at different heights in the vertical direction without increasing the planar area, thereby meeting the increasing demand for miniaturization.

[0068] Furthermore, the present invention also provides a method for manufacturing a semiconductor integrated circuit device, such as Figure 7 As shown, the method includes: operation S710, forming a first electrode on a substrate, the substrate including a first through hole connected to a first metal layer; operation S720, cutting a groove on the first electrode at a position staggered from the first through hole, forming a resistive layer in the groove, so that the resistive layer is a groove-shaped structure with an opening facing upward; operation S730, forming a second electrode in the opening of the resistive layer to obtain a first storage unit.

[0069] In operation S710, the substrate refers to a dielectric layer including a through hole, and a circuit connected to the first metal layer. A first electrode is formed on the substrate, usually by depositing an electrode material, and then patterning to form a plurality of isolated memory cells. The electrode material may be any applicable electrode material, and the deposition process may be any applicable deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic deposition.

[0070] In operation S720, a groove is cut at a position staggered from the first through hole, and a resistive switching layer is formed in the groove, so that the first electrode is located outside the resistive switching layer, and a resistive switching layer material is deposited in the groove to form a groove structure with an opening facing upward. The resistive switching layer material can use any applicable existing material, and the deposition process can also use any applicable deposition process, such as physical vapor deposition, chemical vapor deposition, or atomic deposition.

[0071] Then, electrode material is deposited in the opening in operation S730 to obtain a second electrode located inside the resistive switching layer. In this way, a memory cell can be obtained in which the first electrode and the second electrode are located on both sides of the sidewall of the resistive switching layer.

[0072] It should be noted that the above steps are only the main steps for manufacturing the semiconductor integrated circuit device of the embodiment of the present invention, rather than all the steps. In the process of manufacturing the semiconductor integrated circuit device, it may also include steps such as depositing an oxygen barrier layer, depositing an oxygen storage layer, and forming other structures according to the product design of the semiconductor integrated circuit device. Among them, the deposition process can select any deposition process used according to the specific implementation situation, such as physical vapor deposition, chemical vapor deposition or atomic deposition.

[0073] According to an implementation manner of an embodiment of the present invention, the manufacturing method further includes: forming a second metal layer on the second electrode, so that the second metal layer is connected to the second electrode of the first storage unit.

[0074] According to an implementation of an embodiment of the present invention, the manufacturing method further includes: manufacturing a second storage unit at the same time as manufacturing the first storage unit, so that the first electrode of the second storage unit is connected to the first metal layer through the through hole below, and the second electrode of the second storage unit is connected to the second metal layer; and forming a partition between the first storage unit and the second storage unit.

[0075] According to an implementation manner of an embodiment of the present invention, the manufacturing method further includes: manufacturing a third storage unit while manufacturing the first storage unit, so that the first electrode of the third storage unit is connected to the first metal layer through the through hole below.

[0076] According to an implementation of an embodiment of the present invention, the manufacturing method further includes: forming a through hole and a third metal layer above the second electrode of the third storage unit, so that the second electrode of the third storage unit is connected to the third metal layer through the through hole above, forming a 1T2R structure.

[0077] Figure 8 Shows the manufacturing Figure 1 The main processes of the semiconductor integrated circuit device shown include:

[0078] Step S810, depositing a first electrode material on the substrate 102 to form a first electrode layer 106, Fig. 9 The structure shown;

[0079] The substrate 102 includes a dielectric layer 103 , a first metal layer 101 , an insulating layer 104 and a through hole 105 connected to the first metal layer 101 .

[0080] Step S820, patterning the first electrode layer 106 to obtain Fig.10 The structure shown;

[0081] The patterning process mainly refers to forming partitions 107 between storage units according to a designed layout or pattern.

[0082] The partition 107 may be formed by photolithography followed by etching.

[0083] Step S830, depositing insulating material on the first electrode layer and filling the partition 107 to obtain Fig.11 The structure shown;

[0084] Step S840, on the first electrode, grooves are cut at positions offset from the first through hole to form grooves 108 and 109 that open upward, so as to obtain Fig.12 The structure shown;

[0085] The groove engraving process is first photolithography and then etching.

[0086] Step S850, depositing the resistive switching layer material 110, the oxygen storage layer material 111 and the second electrode material 112 in the groove 108 and the groove 109 in sequence, and obtaining Fig.13 The structure shown;

[0087] The atomic deposition process can be used to deposit the resistive switching layer material, and the resistive switching layer material can be made of aluminum oxide (Al x O y ), copper oxide (Cu x O y ), Hafnium Oxide (Hf x O y ) and other transition metal oxides (TMO).

[0088] Step S860: Use a grinding process to remove the top portion of the resistive switching layer 110 in the horizontal direction, and obtain Fig.14 The structure shown;

[0089] The planarizing process may use a chemical mechanical polishing (CMP) process.

[0090] Step S870, depositing the second metal layer 113, and obtaining Figure 1 The semiconductor integrated circuit device shown.

[0091] Fig.15 Shows the manufacturing Figure 3 or Figure 5 The main processes of the semiconductor integrated circuit device shown include:

[0092] Step S1510, depositing a first electrode material on the substrate 202 to form a first electrode layer 206, Fig.16 The structure shown;

[0093] The substrate 202 includes a dielectric layer 203 , a first metal layer 201 , an insulating layer 204 and a through hole 205 connected to the first metal layer 201 .

[0094] Among them, the deposition process can use a vapor deposition process, and the first electrode material can use any suitable electrode material, for example, aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) and tungsten nitride (WN), etc.

[0095] Step S1520, depositing insulating material 207 on the first electrode layer 206 to obtain Fig.17 The structure shown;

[0096] Step S1530, on the first electrode, grooves are cut at positions staggered from the first through hole to form grooves 208, 209 and 210 that are open upwards, and the result is as follows: Fig.12 The structure shown;

[0097] Step S1540, depositing the resistive layer material 211, the oxygen storage layer material 212 and the second electrode material 213 in the groove 208, the groove 209 and the groove 210 in sequence, so as to obtain Fig.19 The structure shown;

[0098] Step S1550: Use a grinding process to remove the top portion of the resistive switching layer 211 in the horizontal direction, and obtain Fig. 20 The structure shown;

[0099] Step S1560, manufacturing the first storage unit R1, the second storage unit R2 and the third storage unit R3 as shown in FIG. Figure 4 The second metal layer 214 shown in FIG. Figure 3 The semiconductor integrated circuit device shown;

[0100] The method includes depositing an insulating layer material 207, Figure 4 A groove is cut at the position of the second metal layer 214 as shown, and the second metal layer material is deposited in the groove.

[0101] On this basis, if you continue with the following steps:

[0102] Step S1570, manufacturing a through hole 215 on the second metal layer on the third storage unit R3, and manufacturing a through hole 215 on the through hole. Figure 6 The third metal layer 216 shown in FIG. Figure 5 The semiconductor integrated circuit device shown.

[0103] The method comprises: depositing an insulating layer material 207, Figure 6 The through hole 215 shown in the figure is engraved; the through hole material is deposited to obtain the through hole 215; the insulating layer material 207 is continuously deposited, and the through hole 215 is obtained; Figure 6 A groove is cut at the position of the third metal layer 216 as shown, and the third metal layer material is deposited in the groove.

[0104] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0105] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another device, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0106] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor integrated circuit device, characterized in that: The semiconductor integrated circuit device comprises: The resistive switching layer is a groove-shaped structure with an opening upward; A first electrode located outside the resistive switching layer and a second electrode located inside the resistive switching layer, wherein the first electrode and the second electrode are opposite to each other at two sides of a side wall of the resistive switching layer; The resistive layer, the first electrode and the second electrode form a first storage unit; a through hole located below the first electrode; a first metal layer connected to the first electrode through the through hole; a second metal layer connected to the second electrode; A third memory cell having the same structure as the first memory cell, wherein a first electrode of the third memory cell is connected to the first metal layer through a through hole therebelow.

2. The semiconductor integrated circuit device according to claim 1, wherein: The semiconductor integrated circuit device further comprises: A second storage cell having the same structure as the first storage cell, wherein a first electrode of the second storage cell is connected to the first metal layer through a through hole below, a second electrode of the second storage cell is connected to the second metal layer, and the first storage cell is separated from the second storage cell.

3. The semiconductor integrated circuit device according to claim 1, wherein: The second electrode of the third storage unit is connected to the third metal layer through the second metal layer above and the through hole to form a 1T2R structure.

4. A method for manufacturing a semiconductor integrated circuit device, characterized in that: The method comprises: forming a first electrode on a substrate, the substrate comprising a first through hole connected to the first metal layer; On the first electrode, a groove is cut at a position staggered from the first through hole, and a resistive switching layer is formed in the groove, so that the resistive switching layer is a groove-shaped structure with an opening upward; Forming a second electrode in the opening of the resistive layer to obtain a first storage unit; While manufacturing the first memory cell, a third memory cell is manufactured, so that a first electrode of the third memory cell is connected to the first metal layer through a through hole therebelow.

5. The manufacturing method according to claim 4, characterized in that: The manufacturing method further comprises: A second metal layer is formed on the second electrode, so that the second metal layer is connected to the second electrode of the first memory cell.

6. The manufacturing method according to claim 5, characterized in that: The manufacturing method further comprises: While manufacturing the first memory cell, manufacturing a second memory cell, such that a first electrode of the second memory cell is connected to the first metal layer through a through hole below, and a second electrode of the second memory cell is connected to the second metal layer; A partition is formed between the first storage unit and the second storage unit.

7. The manufacturing method according to claim 6, characterized in that: The manufacturing method further comprises: A second metal layer, a through hole and a third metal layer are formed above the second electrode of the third storage unit, so that the second electrode of the third storage unit is connected to the third metal layer through the second metal layer and the through hole to form a 1T2R structure.

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