Information transmission method and device, electronic equipment and readable storage medium

Abstract

The application provides an information transmission method, comprising the following steps: determining a specification parameter of a target buffer according to read-write information of a chip; configuring the target buffer according to the specification parameter to obtain a current target buffer; and transmitting the read-write information through the current target buffer. The application determines the specification parameter of the buffer according to the read-write information actually required by the buffer, and configures the buffer according to the actual requirement, so that the buffer can meet the actual requirement while the buffer with a suitable size is selected, and the chip area and power consumption are balanced.

Description

Technical Field

[0001] This application relates to the field of chip design, and more specifically, to an information transmission method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] Ping-pong caching is a common technique used in information storage. It's a dual-caching mechanism designed to accelerate devices that simultaneously handle I / O and data processing operations. One cache stores older versions of data for read devices, while the other stores newer versions generated by write devices. When new data is ready, the read and write devices swap the two caches. This dual-caching mechanism improves throughput, but current ping-pong caching methods struggle to balance area and power consumption. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide an information transmission method to solve the problem of balancing area and power using a dual buffering mechanism.

[0004] In a first aspect, embodiments of this application provide an information transmission method, comprising: determining the specification parameters of a target cache based on the read / write information of a chip; configuring the target cache according to the specification parameters to obtain a current target cache; and transmitting the read / write information through the current target cache.

[0005] In the above implementation process, the parameters of the target cache are determined by the actual read and write information of the chip, and the target cache is configured according to the parameters. This ensures that the target cache can meet the actual information transmission requirements while also configuring the corresponding cache module according to the actual read and write access information, keeping the area of ​​the target cache within a relatively small range and balancing the chip area and power consumption.

[0006] In conjunction with the first aspect, this application provides a first possible implementation of the first aspect, wherein: the specification parameters include a cache type, and determining the specification parameters of the target cache based on the chip's read / write information includes: determining the cache type of the target cache based on the read / write information.

[0007] In the above implementation process, since the target cache can be configured with various types of caches, and different types of caches have different characteristics, the cache type of the target cache is determined according to the chip's read and write information. This on-demand specification can better enable the target cache to meet actual needs, and at the same time, it can prevent problems such as setting the target cache too large, resulting in excessive chip area or excessive power, which would lead to resource waste.

[0008] In conjunction with the first possible implementation of the first aspect, this application provides a second possible implementation of the first aspect, wherein: the cache type includes SRAM and LATCH; determining the cache type of the target cache based on the read / write information includes: determining the cache type of the target cache to be SRAM and LATCH based on the read / write information; configuring the target cache according to the specification parameters to obtain the current target cache includes: configuring the SRAM and LATCH according to the cache type of the target cache to obtain the current target cache.

[0009] In the above implementation process, the target cache type can be set to SRAM and LATCH based on the actual read and write information. This combination of two cache types avoids the problems of low transfer efficiency that might result from using two SRAMs and excessive chip area that might result from using two LATCHs. This combination leverages the advantages of SRAM's small size and LATCH's parallel access capability, balancing area and efficiency.

[0010] In conjunction with the second possible implementation of the first aspect, this application provides a third possible implementation of the first aspect, wherein the transmission of the read / write information through the current target buffer includes: outputting the read / write information through a front-end module and storing it in the SRAM; loading the read / write information into the LATCH through the SRAM; and outputting the read / write information to a back-end module through the LATCH.

[0011] In the above implementation process, by setting the target cache as a combination of two different types of caches and realizing information transfer through the connection between the two types of caches, read and write operations can be separated, thereby improving the efficiency of information processing and transfer.

[0012] In conjunction with the third possible implementation of the first aspect, this application provides a fourth possible implementation of the first aspect, wherein the cache type includes: SRAM and REGISTER; determining the cache type of the target cache based on the read / write information includes: determining the cache type of the target cache to be SRAM and REGISTER based on the read / write information; configuring the target cache according to the specification parameters to obtain the current target cache includes: configuring the SRAM and REGISTER according to the cache type of the target cache to obtain the current target cache.

[0013] In the above implementation process, the target cache type can be set to SRAM and REGISTER based on the actual read and write information. This combination avoids the problems of low transfer efficiency that might result from using two SRAMs and excessive chip area that might result from using two REGISTERs. This combination leverages the advantages of SRAM's small size and REGISTER's parallel access capabilities, balancing area and efficiency.

[0014] In conjunction with the fourth possible implementation of the first aspect, this application provides a fifth possible implementation of the first aspect, wherein the transmission of the read / write information through the current target buffer includes: outputting the read / write information through a front-end module and storing it in the SRAM; loading the read / write information into the REGISTER through the SRAM; and outputting the read / write information to a back-end module through the REGISTER.

[0015] In the above implementation process, by setting the target cache as a combination of two different types of caches and realizing information transfer through the connection between the two types of caches, read and write operations can be separated, thereby improving the efficiency of information processing and transfer.

[0016] In conjunction with the fifth possible implementation of the first aspect, this application provides a sixth possible implementation of the first aspect, wherein the specification parameters include the number of caches, and the step of determining the specification parameters of the target cache based on the chip's read / write information includes: determining the number of read / write operations required for the target cache based on the read / write information; and determining the number of caches based on the number of read / write operations.

[0017] In the above implementation process, by determining the number of target registers based on the number of read and write operations, it can be ensured that the number of target memories is controlled within a reasonable range while the target cache meets the actual read and write operations, so as to balance area and transfer efficiency.

[0018] Secondly, embodiments of this application also provide an information transmission device, comprising: a determining module for determining the specification parameters of a target cache based on the read / write information of a chip; a configuring module for configuring the target cache based on the specification parameters to obtain a current target cache; and a transmission module for transmitting the read / write information through the current target cache.

[0019] Thirdly, embodiments of this application also provide an electronic device, including: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the machine-readable instructions are executed by the processor to perform the steps of the method described in the first aspect above, or any possible implementation of the first aspect.

[0020] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the information transmission method described in the first aspect or any possible implementation of the first aspect.

[0021] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A block diagram illustrating an electronic device provided in an embodiment of this application;

[0024] Figure 2 A block diagram illustrating one possible configuration of an electronic device provided in this application embodiment;

[0025] Figure 3 A block diagram illustrating another configuration of the electronic device provided in this application embodiment;

[0026] Figure 4 A flowchart illustrating the information transmission method provided in the embodiments of this application;

[0027] Figure 5 This is a schematic diagram of the functional modules of the information transmission device provided in the embodiments of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] In ping-pong caching technology, common cache combinations include SRAM-to-SRAM and Register-to-Register. Based on the characteristics of SRAM and Register, for the same storage space, SRAM-to-SRAM has a smaller area than Register-to-Register, but due to the limitations of SRAM, it cannot support multi-address parallel access. For the same access frequency, Register-to-Register consumes less power than SRAM-to-SRAM and supports multi-address parallel access, but it has a larger area.

[0031] The inventors discovered during their research on caches that, by determining the cache combination type based on read / write information, SRAM and REGISTER can be combined according to actual read / write information, combining the advantages of both and balancing area and power consumption. Based on this, this application proposes an information transfer method, apparatus, electronic device, and readable storage medium. The information transfer method provided in this application is described below through some embodiments.

[0032] To facilitate understanding of this embodiment, an electronic device that performs an information transmission method disclosed in this application will first be described in detail.

[0033] like Figure 1 The diagram shown is a block diagram of an electronic device. The electronic device 100 may include a front-end module 111, a buffer 112, and a back-end module 113. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device 100. For example, the electronic device 100 may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0034] The aforementioned memory front-end module 111, buffer 112, and back-end module 113 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0035] The front-end module 111 can be a frequency domain transformation module. The front-end module 111 is used to perform DCT (Discrete Cosine Transform) and DWT (Discrete Wavelet Transform) transformations. After receiving access information, the front-end module 111 transforms the access information and transmits the transformed information to the buffer 112. The method executed by the electronic device 100 according to the process definition disclosed in any embodiment of this application can be applied to the buffer 112, or implemented by the buffer 112.

[0036] The aforementioned buffer 112 may be an integrated circuit chip with signal processing capabilities. The buffer 112 can be a general-purpose buffer, including Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.; it can also be Read Only Memory (ROM), Flash Memory (FLASH), a register, a latch, or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0037] Alternatively, the cache 112 may be one or more combinations of the various types of caches described above.

[0038] Alternatively, the buffer 112 can be SRAM TO SRAM, REGISTER TO REGISTER, SRAM TO REGISTER, SRAM TO LATCH, etc.

[0039] For example, such as Figure 2 As shown, the cache 112 can be a combination of SRAM and LATCH. Figure 2 The information interaction process between the buffer 112, the front-end module 111, and the back-end module 113 is as follows: the front-end module 111 transmits the read and write information to the SRAM, the SRAM loads the read and write information into the idle space of the LATCH, and the back-end module 113 receives the read and write information in the LATCH.

[0040] This system can consist of one or more SRAMs, which can be accessed in parallel. Each SRAM can be connected to a different space in the LATCH, enabling parallel transfer of read and write information between the SRAMs and the LATCH.

[0041] The LATCH address can be updated based on the actual read and write information transfer. Some data in the SRAM can be used as preparation data to wait for the LATCH address to be updated. Once the LATCH address is updated, the preparation data is immediately loaded into the updated free address.

[0042] Alternatively, for multiple read / write tasks, the above example can be repeated until all tasks are completed.

[0043] LATCH is level-triggered, essentially having an enable pin. When activated, it acts like a wire, changing with the output. In the deactivated state, it retains the original signal. Therefore, LATCH cannot be replaced in certain situations. However, because LATCH is prone to glitches and cannot filter them, these glitches can significantly impact the next stage of the circuit. Therefore, REGISTER is now more commonly used.

[0044] For example, such as Figure 3 As shown, the cache 112 can be a combination of SRAM and REGISTER. Figure 2 The information interaction process between the buffer 112, the front-end module 111, and the back-end module 113 is as follows: the front-end module 111 transmits the read and write information to the SRAM, the SRAM loads the read and write information into the idle space of the REGISTER, and the back-end module 113 receives the read and write information in the REGISTER.

[0045] This system can consist of one or more SRAM chips, which can be accessed in parallel. These multiple SRAM chips can each interface with different spaces of the recorder, enabling parallel transfer of read and write information between the SRAM and the recorder.

[0046] The REGISTER address can be updated based on the actual read and write information transmission. Some data in the SRAM can be used as preparation data, waiting for the REGISTER address to be updated. Once the REGISTER address is updated, the preparation data is immediately loaded into the updated free address.

[0047] Alternatively, for multiple read / write tasks, the above example can be repeated until all tasks are completed.

[0048] The aforementioned post-module 113 can be an entropy code, such as jpeg, jpeg2000, EVC, etc.

[0049] The electronic device 100 in this embodiment can be used to execute various steps in the various methods provided in the embodiments of this application. The implementation process of information transmission is described in detail below through several embodiments.

[0050] Ping-Pong Buffering: Ping-Pong buffering uses two identical objects as buffers (the object type can be any), which are alternately read from and written to. In the scroll example, moving to the visible area is a read operation, and generating and drawing is a write operation. The read and write process alternates between the two buffers: initially, both buffer contents are invalid and cannot be read; then 0 is written, making 0 readable; then 1 is written, making 1 readable, while 0 can be read at the same time; after reading, 0 becomes writable; after 1 is written, it becomes readable... Thus, for each buffer, there are four possible states that cycle repeatedly in the following order: readable => Reading => Writable => Writing => Readable => ...

[0051] Please see Figure 4 This is a flowchart of the information transmission method provided in the embodiments of this application. The following will describe... Figure 4 The specific process shown will be explained in detail.

[0052] Step 201: Determine the specifications of the target cache based on the chip's read / write information.

[0053] Specifically, the specification parameters of the target cache can be determined based on the chip's read and write information according to preset rules. These preset rules can include the specifications of the cache corresponding to each piece of read and write information. By matching each piece of read and write information with the cache specifications, the specification parameters of the target cache can be determined.

[0054] Optionally, the read / write information of the chip can be determined based on the chip type and the chip's usage scenario. When the chip has multiple read / write information, one type of read / write information can be selected to determine the target cache's specifications based on actual needs.

[0055] For example, when the chip may support multiple read / write information, the read / write information with the largest amount of read / write information and the most data can be selected to determine the specification parameters of the target cache.

[0056] For example, when the chip may support multiple read / write information, the most frequently transmitted read / write information among the multiple read / write information can be selected to determine the specification parameters of the target cache.

[0057] Optionally, the chip's read / write information may include read / write data, the amount of read / write information, read / write type, the number of accesses required, access clock cycles, etc.

[0058] Optionally, the target cache specifications may include the target cache type, the number of target caches, the characteristics of the target cache, the read / write cycle of the target cache, the target cache interface, etc.

[0059] Step 202: Configure the target cache according to the specification parameters to obtain the current target cache.

[0060] Step 203: Pass the read / write information through the current target cache.

[0061] Optionally, the current target buffer may temporarily store the read / write information when passing it.

[0062] For example, the current target buffer receives read and write information from the preceding module, performs read and write operations on the read and write information and temporarily stores the read and write information, and then passes the read and write information to the following module to complete the transfer of read and write information.

[0063] In the above technical solution, step 201 includes: determining the cache type of the target cache based on the read / write information.

[0064] The cache type can include, but is not limited to: SRAM, LATCH, REGISTER.

[0065] In the above technical solution, step 201 can be implemented as follows: determining the cache type of the target cache as SRAM and LATCH based on the read and write information.

[0066] Of the three types of memory, SRAM has the smallest area for the same storage capacity, but it does not support multi-address parallel access. For the same storage capacity, LATCH consumes the least power at the same access frequency as SRAM, and it also supports multi-address parallel access. When activated, LATCH acts like a wire, changing with the output; when disabled, it retains its original signal. Therefore, LATCH cannot be replaced in certain situations.

[0067] Optionally, the specific cache type of the target cache can be selected according to the read and write frequency of the read and write information and the preset frequency range, with different read and write frequencies matching different cache types.

[0068] For example, if the preset frequency range is set to less than A, between A and B, or greater than B, and assuming the read / write frequency is X, then the rule for determining the cache type of the target cache can be set as follows: when the read / write frequency X is less than A, the corresponding cache type can be set to "SRAM TO SRAM"; when the read / write frequency X is between A and B, the corresponding cache type can be set to "SRAM and LATCH"; when the read / write frequency X is greater than B, the corresponding cache type can be set to REGISTER TO REGISTER.

[0069] Optionally, the specific cache type of the target cache can be selected based on the number of accesses to read and write information and a preset range of accesses, with different accesses matching different cache types.

[0070] For example, if the preset range of access counts is set to less than M, between M and N, or greater than N, and assuming the access count is Y, then the rule for determining the cache type of the target cache can be set as follows: when the access count Y is less than M, the corresponding cache type can be set to "SRAM TO SRAM"; when the access count Y is between M and N, the corresponding cache type can be set to "SRAM and LATCH"; when the access count Y is greater than N, the corresponding cache type can be set to REGISTER TO REGISTER.

[0071] If the target cache type is SRAM and LATCH, then step 202 can be implemented as: configuring SRAM and LATCH according to the target cache type to obtain the current target cache.

[0072] In the above technical solution, step 201 specifically includes: determining the cache type of the target cache as SRAM and REGISTER based on the read / write information.

[0073] Of the three types of memory, SRAM has the smallest area for the same storage capacity, but it does not support multi-address parallel access. For the same storage capacity, REGISTER consumes the least power at the same access frequency as SRAM, and it also supports multi-address parallel access. Compared to REGISTER, LATCH is more prone to glitches and cannot filter them. These glitches can significantly impact subsequent circuitry; therefore, REGISTER is used more frequently and is applicable to a wider range of scenarios compared to LATCH.

[0074] Optionally, the specific cache type of the target cache can be selected according to the read and write frequency of the read and write information and the preset frequency range, with different read and write frequencies matching different cache types.

[0075] For example, if the preset frequency range is set to less than A, between A and B, or greater than B, and assuming the read / write frequency is X, the rule for determining the cache type of the target cache can be set as follows: when the read / write frequency X is less than A, the corresponding cache type can be set to "SRAM TO SRAM"; when the read / write frequency X is between A and B, the corresponding cache type can be set to "SRAM and REGISTER"; when the read / write frequency X is greater than B, the corresponding cache type can be set to REGISTER TO REGISTER. When the read / write frequency X is between A and B, it is also necessary to determine the chip type and decide whether to set the cache type to "SRAM and LATCH" or "SRAM and REGISTER" based on the chip type.

[0076] Optionally, the specific cache type of the target cache can be selected based on the number of accesses to read and write information and a preset range of accesses, with different accesses matching different cache types.

[0077] For example, if the preset range of access counts is set to less than M, between M and N, or greater than N, and assuming the access count is Y, then the rule for determining the cache type of the target cache can be set as follows: when the access count Y is less than M, the corresponding cache type can be set to "SRAM TO SRAM"; when the access count Y is between M and N, the corresponding cache type can be set to "SRAM and REGISTER"; when the access count Y is greater than N, the corresponding cache type can be set to REGISTER TO REGISTER.

[0078] Optionally, when the number of accesses Y is between M and N, it is also necessary to determine the chip type and decide whether to set the cache type to "SRAM and LATCH" or "SRAM and REGISTER" based on the chip type.

[0079] The specific choice of cache type for the target cache mentioned above is merely illustrative; of course, different rules can be specified according to the actual situation.

[0080] Step 202 includes: configuring SRAM and REGISTER according to the cache type of the target cache to obtain the current target cache.

[0081] Optionally, the target cache may include one or more SRAMs.

[0082] In the above technical solution, step 201 includes: determining the number of reads and writes required for the target cache based on the read and write information; and determining the number of caches based on the number of reads and writes.

[0083] Optionally, determining the number of caches based on the number of reads and writes can be done by determining the target number of caches based on the number of reads and writes, or by determining the number of each cache type in the target cache based on the number of reads and writes.

[0084] Optionally, the number of caches can be determined based on the access frequency of read and write information, the access requirements of the front-end module and the back-end module, and different rules can be set according to the actual situation.

[0085] In the above technical solution, determining the number of caches based on the number of reads and writes includes determining the number of SRAMs based on the number of reads and writes.

[0086] Due to the small size of SRAM, when the number of read / write operations is within a certain range, using combinations of "SRAM and LATCH" or "SRAM and REGISTER" to form a cache can effectively control the cache area within a suitable range. However, given the limitation of SRAM not being able to be accessed in parallel, in order to balance the power consumption of the cache and improve the information transfer efficiency, the number of SRAMs can be set according to the actual number of read / write operations. Each SRAM can receive read / write information access simultaneously and can interact with LATCH or REGISTER in parallel.

[0087] In the above technical solution, step 203 includes: outputting read / write information through the front-end module and storing it in SRAM; loading the read / write information into LATCH or REGISTER through SRAM; and outputting the read / write information to the back-end module through LATCH or REGISTER.

[0088] For example, the read and write information output by the front-end module is stored in SRAM. The target buffer may include one or more SRAMs (multiple SRAMs can store multiple read and write information from the front-end module at the same time). When some or all of the addresses of LATCH or REGISTER are no longer used by the back-end module in the current task, and the corresponding data in SRAM is ready (it may be all ready or not all ready), the read and write information in the corresponding SRAM is loaded into the idle space of LATCH or REGISTER. When all the read and write information in SRAM has been loaded into LATCH or REGISTER, the back-end module starts working, and the front-end module can continue to output read and write information and store it in SRAM. This cycle continues until all the read and write information of the front-end module has been output to the back-end module.

[0089] This application embodiment formulates corresponding cache configuration rules based on actual read and write information, and configures the corresponding cache type and quantity for the target cache. While ensuring that the target cache is kept within an appropriate area, the power of the target cache is also controlled within an appropriate range. This not only balances the area and power of the cache, but also improves the efficiency of information transmission.

[0090] Based on the same application concept, this application also provides an information transmission device corresponding to the information transmission method. Since the principle of the device in this application is similar to that of the aforementioned information transmission method embodiment, the implementation of the device in this application can refer to the description in the above method embodiment, and the repeated parts will not be repeated.

[0091] Please see Figure 5 This is a functional module diagram of the information transmission device provided in this application embodiment. Each module in the information transmission device in this embodiment is used to execute the steps in the above method embodiments. The information transmission device / system includes a determining module 301, a configuring module 302, and a transmission module 303; wherein,

[0092] The determination module 301 is used to determine the specifications of the target cache based on the chip's read and write information.

[0093] The configuration module 302 is used to configure the target cache according to the specification parameters to obtain the current target cache.

[0094] The transmission module 303 is used to transmit the read / write information through the current target buffer.

[0095] In one possible implementation, the determining module 301 is further configured to: determine the cache type of the target cache based on the read / write information.

[0096] In one possible implementation, the determining module 301 is specifically used to: determine, based on the read / write information, that the cache type of the target cache is the SRAM and the LATCH.

[0097] In one possible implementation, the configuration module 302 is specifically used to: configure the SRAM and the LATCH according to the cache type of the target cache to obtain the current target cache.

[0098] In one possible implementation, the determining module 301 is specifically used to: determine, based on the read / write information, that the cache type of the target cache is the SRAM and the REGISTER.

[0099] In one possible implementation, the configuration module 302 is specifically used to: configure the SRAM and the REGISTER according to the cache type of the target cache to obtain the current target cache.

[0100] In one possible implementation, the determining module 301 is further configured to: determine the number of reads and writes required for the target cache based on the read / write information; and determine the number of caches based on the number of reads and writes.

[0101] In one possible implementation, the determining module 301 is specifically used to: determine the number of SRAMs based on the number of reads and writes.

[0102] In one possible implementation, the transmission module 303 is further configured to: output the read / write information through the front-end module and store it in the SRAM; load the read / write information into the LATCH or REGISTER through the SRAM; and output the read / write information to the back-end module through the LATCH or REGISTER.

[0103] Furthermore, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the information transmission method described in the above method embodiments.

[0104] The computer program product of the information transmission method provided in this application includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the steps of the information transmission method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0106] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0107] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. It should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0109] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An information delivery method, characterized by, include: Determine the specifications of the target cache based on the chip's read / write information; Configure the target buffer according to the specified parameters to obtain the current target buffer; The read / write information is transmitted through the current target buffer; The specifications include the cache type, and determining the specifications of the target cache based on the chip's read / write information includes: The cache type of the target cache is determined based on the read / write information; The cache types include SRAM and REGISTER. Determining the cache type of the target cache based on the read / write information includes: Based on the read / write information, the cache type of the target cache is determined to be SRAM and REGISTER; The step of configuring the target buffer according to the specification parameters to obtain the current target buffer includes: Configure the SRAM and REGISTER according to the cache type of the target cache to obtain the current target cache; The step of transmitting the read / write information through the current target cache includes: The read / write information is output through the front-end module and stored in the SRAM; The read / write information is loaded into the REGISTER via the SRAM; The REGISTER module outputs the read / write information to the subsequent module.

2. The method of claim 1, wherein, The cache types include SRAM and LATCH. Determining the cache type of the target cache based on the read / write information includes: Based on the read / write information, the cache type of the target cache is determined to be SRAM and LATCH; The step of configuring the target buffer according to the specification parameters to obtain the current target buffer includes: Configure the SRAM and LATCH according to the cache type of the target cache to obtain the current target cache.

3. The method according to claim 2, characterized in that, The step of transmitting the read / write information through the current target cache includes: The read / write information is output through the front-end module and stored in the SRAM; The read / write information is loaded into the LATCH via the SRAM; The read / write information is output to the subsequent module via the LATCH.

4. The method according to claim 2 or 3, characterized in that, The specifications include the number of caches. Determining the specifications of the target cache based on the chip's read / write information includes: The number of reads and writes required for the target cache is determined based on the read and write information; The number of caches is determined based on the number of reads and writes.

5. An information transmission device, characterized in that, The information transmission method applied to any one of claims 1-4 includes: Determining module: Used to determine the specifications of the target cache based on the chip's read / write information; Configuration module: used to configure the target buffer according to the specified parameters to obtain the current target buffer; Transmission module: Used to transmit the read / write information through the current target buffer.

6. An electronic device, characterized in that, include: The processor and memory, wherein the memory stores machine-readable instructions executable by the processor, wherein when the electronic device is running, the machine-readable instructions are executed by the processor to perform the steps of the method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the method as described in any one of claims 1 to 4.

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