Storage device and system for adjusting delay on data clock path and operating method thereof

Abstract

A storage system includes a storage device configured to monitor a first oscillator count value of a write data strobe signal used to sample a data signal at a first temperature and a second oscillator count value of the write data strobe signal used to sample the data signal at a second temperature, and a storage controller configured to determine a weight based on the first oscillator count value and the second oscillator count value, wherein the storage device is configured to sample the data signal by adjusting a delay on a transmission path of the write data strobe signal based on the weight according to a temperature change of the storage device.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0115516 filed on September 9, 2020, and Korean Patent Application No. 10-2021-0004928 filed on January 13, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and more specifically, to a storage device configured to adjust the delay on a data clock path, a storage system including the storage device, and a method of operating the storage system. Background Technology

[0004] Electronic devices, including smartphones, graphics accelerators, and artificial intelligence (AI) accelerators, can process data using storage devices such as dynamic random access memory (DRAM). These electronic devices can control internal or external storage devices via a storage controller. The storage controller can send various signals to the storage device to control it.

[0005] Storage devices and storage controllers can send and receive data via data signals. Storage devices can sample these data signals using a data clock signal (or write strobe signal) provided by the storage controller. For example, a storage device can sample the data signal based on the edge timing of the data clock signal. To sample the data signal based on the data clock signal, the storage device can transmit the data clock signal to circuitry used for sampling the data signal. The storage controller can perform training on the data clock signal to compensate for delays on the path used to transmit the data clock signal (hereinafter referred to as the data clock path).

[0006] The latency on the data clock path can vary depending on the temperature of the storage device. When the sampling timing changes due to variations in latency on the data clock path, the setup / hold (S / H) margin may decrease. The storage controller can perform retraining to compensate for the latency variations caused by temperature changes. Therefore, the storage controller can adjust the latency on the data clock path. However, when retraining is performed, the resources used for training may increase. Summary of the Invention

[0007] The present invention provides a storage device configured to adjust the latency on the data clock path without retraining by the storage controller, a storage system including the storage device, and a method of operating the storage system.

[0008] According to one aspect of the present invention, a storage system is provided, comprising a storage device and a storage controller, wherein the storage device is configured to monitor a first oscillator count value of a write data strobe signal for sampling a data signal at a first temperature and a second oscillator count value of a write data strobe signal for sampling a data signal at a second temperature, the storage controller being configured to determine weights based on the first and second oscillator count values, wherein the storage device is configured to sample the data signal by adjusting the delay on the transmission path of the write data strobe signal according to a temperature change of the storage device based on the weights.

[0009] According to another aspect of the present invention, a method of operating a storage system is provided, wherein the storage system includes a storage controller and a storage device, the storage device being configured to sample a data signal provided from the storage controller based on a write data strobe signal provided from the storage controller, wherein the method includes: the storage controller requesting a first oscillator count value of the write data strobe signal at a first temperature from the storage device; the storage device sending the first oscillator count value to the storage controller; the storage controller requesting a second oscillator count value of the write data strobe signal at a second temperature from the storage device; the storage device sending the second oscillator count value to the storage controller; the storage controller setting a weight determined based on the first oscillator count value and the second oscillator count value to the storage device; and the storage device sampling the data signal by adjusting the delay on the transmission path of the write data strobe signal according to a temperature change of the storage device based on the weight.

[0010] According to another aspect of the present invention, a storage device is provided, comprising: a data sampler configured to sample a data signal based on a write data strobe signal; a storage circuit configured to store weights representing the amount of change in delay along the transmission path of the write data strobe signal according to temperature; a temperature sensor configured to sense a temperature; a temperature compensator configured to generate a delay code based on the sensed temperature and the weights; a reference voltage generator configured to generate a reference voltage from a power supply voltage based on the delay code; a voltage regulator configured to generate an regulated voltage based on the reference voltage; and a write data strobe signal transmission circuit configured to transmit the write data strobe signal to the data sampler using the regulated voltage. Attached Figure Description

[0011] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating a storage system according to an embodiment;

[0013] Figure 2It is a diagram. Figure 1 A flowchart illustrating an exemplary operation of a storage system;

[0014] Figure 3 The illustration is configured to set weights according to an embodiment. Figure 2 A block diagram of the storage system;

[0015] Figure 4 It is a diagram. Figure 3 An exemplary flowchart of the weight setting operation of the storage system;

[0016] Figure 5 It shows the basis Figure 3 A diagram illustrating the delay variation along the write data strobe (WDQS) path of a storage device's component characteristics;

[0017] Figure 6 The diagram illustrates the following: Figure 5 The example indicated in the document is by Figure 3 An example of how a storage controller determines weights;

[0018] Figure 7 This is a block diagram illustrating a storage device configured to adjust latency on a WDQS path according to an embodiment;

[0019] Figure 8 The diagram shows Figure 7 Exemplary operation of a temperature compensator;

[0020] Figure 9 The diagram shows Figure 7 Exemplary operation of the reference voltage generator and voltage regulator;

[0021] Figure 10 yes Figure 7 Illustrative circuit diagram of the voltage regulator and WDQS transmission circuit;

[0022] Figure 11 It is a diagram. Figure 7 An exemplary flowchart of latency adjustment operations for storage devices;

[0023] Figure 12 This is a block diagram illustrating a storage device configured to adjust latency on a WDQS path according to an embodiment;

[0024] Figure 13A and Figure 13B yes Figure 12 Illustrative circuit diagram of the WDQS transmission circuit;

[0025] Figure 14 It is a diagram. Figure 12 An exemplary flowchart of latency adjustment operations for storage devices;

[0026] Figure 15 This is a block diagram illustrating a stacked storage device according to some embodiments.

[0027] Figure 16 It is a diagram. Figure 15 A block diagram of the buffer chip;

[0028] Figure 17 This is a diagram illustrating a semiconductor package according to an embodiment;

[0029] Figure 18 It is a diagram illustrating an implementation example of a semiconductor package according to an embodiment; and

[0030] Figure 19 This is a diagram illustrating a semiconductor package according to another embodiment. Detailed Implementation

[0031] In the following description, embodiments of the inventive concept will be clearly and sufficiently detailed to the extent that those skilled in the art will be able to implement the inventive concept.

[0032] Figure 1 This is a block diagram illustrating a storage system 10 according to an embodiment. (See reference) Figure 1 The storage system 10 may include a storage controller 100 and a storage device 200. The storage controller 100 can control the overall operation of the storage device 200. For example, the storage controller 100 can control the storage device 200 so that data DATA is output from or stored in the storage device 200.

[0033] The storage controller 100 can send various signals to and receive various signals from the storage device 200. For example, the storage controller 100 can send a command / address signal CA, a clock signal CK, a write data strobe signal WDQS, and a data signal DQ to the storage device 200, and receive the data signal DQ from the storage device 200. For example, the data signal DQ is a multi-bit signal. The command / address signal CA may include a command CMD and / or an address ADD, and the data signal DQ may include data DATA.

[0034] The storage controller 100 may be implemented in a host (not explicitly shown in the figures) and access the storage device 200 upon request from the host's internal processor (not explicitly shown in the figures). For example, the storage controller 100 may access the storage device 200 via direct memory access (DMA). For example, the storage controller 100 may be implemented as part of a system-on-a-chip (SoC), but the implementation is not limited to this.

[0035] Storage device 200 can operate as a buffer memory, working memory, or main memory for a host including storage controller 100. Storage device 200 can operate under the control of storage controller 100. For example, storage device 200 can output stored data DATA or store data DATA provided from storage controller 100, depending on the control of storage controller 100.

[0036] Storage device 200 can receive various signals from storage controller 100 and send various signals to storage controller 100. For example, storage device 200 can receive command / address signal CA, clock signal CK, write data strobe signal WDQS and data signal DQ from storage controller 100, and send data signal DQ to storage controller 100.

[0037] The storage controller 100 may include a phase-locked loop 110, a clock divider 120, a first transmitter 130, a second transmitter 140, a phase controller 150, a third transmitter 160, and a fourth transmitter 170. The phase-locked loop 110 can generate a first internal clock signal ICS1. For example, the first internal clock signal ICS1 may have a specific frequency and switch between high and low levels. The clock divider 120 can divide the first internal clock signal ICS1 to generate a divided internal clock signal dICS. For example, the frequency of the divided internal clock signal dICS may be half the frequency of the first internal clock signal ICS1. Ordinal numbers such as “first,” “second,” “third,” etc., can simply be used as labels for specific elements, steps, etc., to distinguish them from each other. Terms described using “first,” “second,” etc., not used in the specification may still be referred to as “first” or “second” in the claims. Furthermore, terms referenced with a specific ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim).

[0038] The first transmitter 130 can send a command / address signal CA to the storage device 200 based on a partitioned internal clock signal dICS. For example, the first transmitter 130 can send a command CMD and / or an address ADD to the storage device 200 via the command / address signal CA at the rising and / or falling edge timing of the partitioned internal clock signal dICS. The command / address signal CA can be sent to the storage device 200 via the command / address pin CA_P'.

[0039] The second transmitter 140 can send a partitioned internal clock signal dICS to the storage device 200 as a clock signal CK. For example, the partitioned internal clock signal dICS and the clock signal CK can have the same frequency and phase. The clock signal CK can be sent to the storage device 200 via the clock pin CK_P'.

[0040] The phase controller 150 can generate a second internal clock signal ICS2 with a phase different from that of the first internal clock signal ICS1 based on the first internal clock signal ICS1. For example, the phase difference between the first internal clock signal ICS1 and the second internal clock signal ICS2 can be 90 degrees.

[0041] The third transmitter 160 can send the first internal clock signal ICS1 to the storage device 200 as a write data strobe signal WDQS. For example, the first internal clock signal ICS1 and the write data strobe signal WDQS can have the same frequency and phase. For example, when the frequency of the first internal clock signal ICS1 is twice the frequency of the divided internal clock signal dICS, the frequency of the write data strobe signal WDQS can be twice the frequency of the clock signal CK. The write data strobe signal WDQS can be sent to the storage device 200 through the write data strobe pin W_P'.

[0042] The fourth transmitter 170 can send the data signal DQ to the storage device 200 based on the second internal clock signal ICS2. For example, the fourth transmitter 170 can send the data DATA to the storage device 200 via the data signal DQ at the rising and / or falling edge timing of the second internal clock signal ICS2. The data signal DQ can be sent to the storage device 200 via the data pin D_P'.

[0043] As described above, the clock signal CK and the write data strobe signal WDQS can be generated by a single phase-locked loop 110. Therefore, the operating current of the memory controller 100 can be reduced. However, the inventive concept is not limited to this, and each of the clock signal CK and the write data strobe signal WDQS can be generated by a separate phase-locked loop.

[0044] Storage device 200 may include a command / address sampler 210, a clock receiver 220, a write data strobe (WDQS) transmission circuit 230, and a data sampler 240. Clock receiver 220 can receive a clock signal CK from storage controller 100 via the clock pin CK_P. The clock signal CK received by clock receiver 220 can be sent to command / address sampler 210.

[0045] Command / address sampler 210 can receive command / address signals CA from memory controller 100 via command / address pin CA_P. Command / address sampler 210 can sample command / address signals CA based on clock signal CK. For example, command / address sampler 210 can sample command / address signals CA at the rising and / or falling edges of clock signal CK. Therefore, memory device 200 can obtain commands and / or addresses CMD / ADD.

[0046] The WDQS transmission circuit 230 can receive the write data strobe signal WDQS from the memory controller 100 via the write data strobe pin W_P. The WDQS transmission circuit 230 can transmit the write data strobe signal WDQS to the data sampler 240. In an example embodiment, the WDQS transmission circuit 230 may include a write data strobe signal WDQS receiver and a write data strobe signal WDQS tree circuit. For example, the write data strobe signal WDQS receiver may receive the write data strobe signal WDQS provided via the write data strobe pin W_P. The write data strobe signal WDQS tree circuit may include multiple repeaters configured to transmit the write data strobe signal WDQS output from the write data strobe signal WDQS receiver to the data sampler 240. For example, each of the multiple repeaters may be implemented by at least one buffer or inverter.

[0047] Data sampler 240 can receive data signal DQ from memory controller 100 via data pin D_P. Data sampler 240 can sample data signal DQ based on write data strobe signal WDQS. For example, data sampler 240 can sample data signal DQ at the rising and / or falling edge timing of write data strobe signal WDQS. Therefore, memory device 200 can obtain data DATA.

[0048] As described above, storage device 200 can sample data signal DQ based on a write data strobe signal WDQS that is different from the clock signal CK. For example, the write data strobe signal WDQS can be a clock signal used for data communication (i.e., a data clock signal).

[0049] In an example embodiment, training can be performed on the write data strobe signal WDQS to compensate for delays in the path of transmitting the write data strobe signal WDQS to the data sampler 240 during the initialization of the storage device 200. Therefore, the transmission timing (i.e., sampling timing) of the write data strobe signal WDQS can be determined to increase the S / H margin of the data sampler 240.

[0050] In an example embodiment, the path through which the write data strobe signal WDQS is transmitted from the write data strobe pin W_P to the data sampler 240 (hereinafter referred to as the WDQS path WDQS_P) may not match the path through which the data signal DQ is transmitted from the data pin D_P to the data sampler 240 (hereinafter referred to as the DQ path DQ_P). For example, the circuitry on the WDQS path WDQS_P and the DQ path DQ_P may be arranged asymmetrically. For example, the number of transistors included in the WDQS path WDQS_P may differ from the number of transistors included in each DQ path DQ_P. In this case, even if training is performed on the write data strobe signal WDQS during the initialization of the storage device 200, the change in delay on the WDQS path WDQS_P will differ from the change in delay on the DQ path DQ_P due to temperature changes that may occur after the training. Therefore, the arrival timing (i.e., sampling timing) of the write data strobe signal WDQS transmitted to the data sampler 240 can be altered. Specifically, the delay on the WDQS path WDQS_P can vary with temperature changes, which may be based on the characteristics of the components on the WDQS path WDQS_P. Therefore, the S / H margin of the data sampler 240 may decrease.

[0051] According to some embodiments, the delay on the WDQS path WDQS_P can be compensated for temperature variations without performing retraining associated with the write data strobe signal WDQS. Storage device 200 can adjust the delay on the WDQS path WDQS_P according to temperature changes, detecting temperature changes in real time while taking into account the characteristics of the circuitry on the WDQS path WDQS_P. Therefore, the delay on the WDQS path WDQS_P based on training performed during the initialization process of storage device 200 can be maintained. Thus, the S / H margin of the data sampler 240 can be increased regardless of temperature changes, and data errors can also be reduced.

[0052] Figure 2 It is a diagram. Figure 1 A flowchart illustrating an operational example of a storage system. Specifically, refer to... Figure 2 This explains the operation by which storage system 10 adjusts the latency on the WDQS path based on temperature changes. (Reference) Figure 1 and Figure 2 In operation S11, the storage system 10 can determine weights. Weights can represent the amount of change in latency along the WDQS path due to temperature variations. For example, the storage controller 100 can determine weights during the initialization of the storage device 200 or during testing of the storage device 200. The determined weights are stored in registers or fuses of the storage device 200 and can be set by the storage device 200. (See reference...) Figures 3 to 6An embodiment in which weights are set by storage system 10 is described in further detail.

[0053] In operation S12, the storage system 10 can adjust the delay on the WDQS path based on the real-time temperature and a set weight. For example, the storage device 200 can sense the temperature in real time. The storage device 200 can adjust the delay on the WDQS path based on the sensed temperature. For example, the storage device 200 can adjust the voltage applied to the WDQS transmission circuit 230 to adjust the delay, or control the delay units of the WDQS transmission circuit 230. The scale of the delay to be adjusted can vary according to the set weight. Therefore, even if the temperature of the storage device 200 changes in real time, the delay on the WDQS path can remain stable. For example, the delay in the initial state of the storage device 200 or the delay at the reference temperature can remain consistent. Figures 7 to 14 An embodiment of adjusting latency on the WDQS path by storage device 200 is described in further detail.

[0054] In operation S13, the storage system 10 can sample the data signal DQ based on a write data strobe signal WDQS with an adjusted delay. For example, the write data strobe signal WDQS can be transmitted to the data sampler 240 via the WDQS transmission circuit 230. In this case, the arrival timing of the write data strobe signal WDQS to the data sampler 240 can remain constant regardless of temperature changes in the storage device 200. The data sampler 240 can sample the data signal DQ based on the write data strobe signal WDQS.

[0055] The storage system 10 and storage device 200 according to the present invention can compensate for latency variations on the WDQS path based on weights set during initialization or testing, according to real-time temperature changes. For example, the latency on the WDQS path can remain constant without retraining by the storage controller 100. Therefore, retraining to compensate for temperature-dependent latency variations on the WDQS path can be avoided, thus reducing the resources used for retraining.

[0056] In the following text, reference will be made to Figures 3 to 6 An embodiment of the operation of setting weights by storage system 10 is described in further detail.

[0057] Figure 3 It is configured to set weights according to the embodiment. Figure 2 A block diagram of the storage system. (Reference) Figure 3 The storage system 20 may include a storage controller 300 and a storage device 400. The storage controller 300 and the storage device 400 may respectively correspond to... Figure 1The storage controller 100 and the storage device 200. Therefore, their repeated descriptions are omitted below.

[0058] The storage controller 300 may include a weight determination circuit 310. The weight determination circuit 310 can control the initialization or testing operations of the storage device 400. The weight determination circuit 310 can determine weights during the initialization or testing operations of the storage device 400 and set the determined weights to the storage device 400. For example, the weight determination circuit 310 can be implemented by a processor such as the CPU of the storage controller 300, but the inventive concept is not limited thereto.

[0059] In an example embodiment, the weight determination circuit 310 may request oscillation information of the write data strobe signal WDQS at each of two predetermined temperatures from the storage device 400. The weight determination circuit 310 may receive the oscillation information of the write data strobe signal WDQS from the storage device 400. The weight determination circuit 310 may determine weights based on the oscillation information of the write data strobe signal WDQS at the two temperatures. The weight determination circuit 310 may send the determined weights to the storage device 400. For example, the storage controller 300 may further include a temperature sensor configured to sense the temperature.

[0060] Storage device 400 may include a WDQS transmission circuit 410, a data sampler 420, a WDQS oscillator 430, a counter 440, and a storage circuit 450. The WDQS transmission circuit 410 can transmit the write data strobe signal WDQS provided from the storage controller 300 to the data sampler 420. The data sampler 420 can sample the data signal DQ provided from the storage controller 300 based on the write data strobe signal WDQS.

[0061] WDQS oscillator 430 may be a replica of WDQS transmission circuit 410. WDQS oscillator 430 may be configured to match WDQS transmission circuit 410. Therefore, the delay in the signal output from WDQS oscillator 430 may be substantially the same as the delay in the write data strobe signal output from WDQS transmission circuit 410. For example, the delay on the WDQS path may be substantially the same as the delay on the replica path. Terms such as “same,” “identical,” “equivalent,” “plane,” or “coplanar” as used herein, when referring to orientation, layout, location, shape, size, composition, quantity, or other measure, do not necessarily mean exactly the same orientation, layout, location, shape, size, composition, quantity, or other measure, but are intended to cover substantially the same orientation, layout, location, shape, size, composition, quantity, or other measure, for example, that may be due to acceptable variations in the manufacturing process. The term “substantially” may be used herein to emphasize the meaning unless the context or other statement otherwise indicates otherwise.

[0062] The WDQS oscillator 430 can generate a copy signal corresponding to the write data strobe signal WDQS. For example, the WDQS oscillator 430 can operate in response to a command or control signal from the memory controller 300. Because the WDQS oscillator 430 is a copy of the WDQS transfer circuit 410, the oscillation value (e.g., number of oscillations) of the copy signal can be substantially the same as the oscillation value (e.g., number of oscillations) of the write data strobe signal WDQS. For example, the WDQS oscillator 430 can be implemented by a ring oscillator, but the inventive concept is not limited thereto.

[0063] Counter 440 can calculate the oscillator count value of the copy signal output from WDQS oscillator 430. For example, counter 440 can count the number of oscillations of the copy signal. The oscillator count value of the copy signal calculated by counter 440 can be substantially the same as the number of oscillations of the write data strobe signal WDQS. Therefore, the oscillator count value calculated by counter 440 can correspond to the delay on the WDQS path. The oscillator count value calculated by counter 440 can be sent to storage controller 300 as oscillation information about the write data strobe signal WDQS (i.e., delay information on the WDQS path).

[0064] The storage circuit 450 can store weights provided from the storage controller 300. In an example embodiment, the storage circuit 450 can be implemented as a register or a fuse. For example, when weights are set during the initialization process of the storage device 400, the storage circuit 450 can be a mode register. For example, when weights are set during the testing process of the storage device 400, the storage circuit 450 can be a test mode register or a fuse.

[0065] Figure 4 The diagram is drawn by Figure 3 An exemplary flowchart illustrating the operation of setting weights in a storage system. (See reference...) Figure 3 and Figure 4 In operation S301, the storage controller 300 may determine whether the temperature of the storage system 20 (i.e., the storage controller 300 or the storage device 400) is a first temperature. For example, the storage controller 300 may determine whether the temperature of the storage system 20 is equal to the first temperature using an internal temperature sensor. As another example, the storage device 400 may include an internal temperature sensor, and the storage controller 300 may request temperature information from and receive temperature information about the storage system 20 from the storage device 400. In some embodiments, in operation S301, the storage controller 300 may determine whether the temperature of the storage system 20 is equal to or higher than the first temperature. In some embodiments, in operation S301, the storage controller 300 may determine whether the temperature of the storage system 20 exceeds the first temperature.

[0066] When the temperature of the storage system 20 is equal to a first temperature, the storage controller 300 may send a WDQS oscillator enable command to the storage device 400 in operation S303. For example, the storage controller 300 may send the WDQS oscillator enable command to the storage device 400 via a command / address signal CA. However, the inventive concept is not limited thereto, and the storage controller 300 may send the WDQS oscillator enable command to the storage device 400 via a separate control signal. In some embodiments, when the temperature of the storage system 20 is equal to or higher than the first temperature, the storage controller 300 may send the WDQS oscillator enable command to the storage device 400 in operation S303. In some embodiments, when the temperature of the storage system 20 exceeds the first temperature, the storage controller 300 may send the WDQS oscillator enable command to the storage device 400 in operation S303.

[0067] In operation S305, the storage device 400 can count the number of oscillations of the write data strobe signal WDQS in response to a WDQS oscillator enable command. For example, the storage device 400 can enable the WDQS oscillator 430 and the counter 440 in response to the WDQS oscillator enable command. Therefore, the storage device 400 can count the number of oscillations of the write data strobe signal WDQS by counting the number of oscillations of the copy signal.

[0068] In operation S307, the storage controller 300 may request an oscillator count value from the storage device 400. For example, the storage controller 300 may send a command to request the oscillator count value to the storage device 400 via a command / address signal CA. However, the inventive concept is not limited thereto, and the storage controller 300 may request the oscillator count value from the storage device 400 via a separate control signal.

[0069] In operation S309, the storage device 400 may send a first oscillator count value CNT1 to the storage controller 300 in response to a request from the storage controller 300. For example, the first oscillator count value CNT1 may be the oscillator count value of the write data strobe signal WDQS at a first temperature. For example, the storage device 400 may send the first oscillator count value CNT1 to the storage controller 300 via the data signal DQ, but the inventive concept is not limited thereto.

[0070] In operation S311, the storage controller 300 may determine whether the temperature of the storage system 20 is equal to a second temperature. For example, the first temperature may be room temperature (e.g., approximately 20 degrees Celsius), and the second temperature may be a temperature hotter than room temperature. In some embodiments, in operation S311, the storage controller 300 may determine whether the temperature of the storage system 20 is equal to or higher than the second temperature. In some embodiments, in operation S311, the storage controller 300 may determine whether the temperature of the storage system 20 exceeds the second temperature. When the temperature of the storage system 20 is equal to the second temperature, the storage controller 300 may send a WDQS oscillator enable command to the storage device 400 in operation S313. In some embodiments, when the temperature of the storage system 20 is equal to or higher than the second temperature, the storage controller 300 may send a WDQS oscillator enable command to the storage device 400 in operation S313. In some embodiments, when the temperature of the storage system 20 exceeds the second temperature, the storage controller 300 may send a WDQS oscillator enable command to the storage device 400 in operation S313. In operation S315, storage device 400 may count the number of oscillations of the write data strobe signal WDQS in response to a WDQS oscillator enable command. For example, storage device 400 may count the number of oscillations of the write data strobe signal WDQS by counting the number of oscillations of the copy signal. Terms such as “approximately” or “around” may reflect quantities, sizes, orientations, or layouts that vary only in a small relative manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, a range of “approximately 0.1 to approximately 1” may include ranges such as 0%–5% deviation around 0.1 and 0%–5% deviation around 1, particularly if such deviations maintain the same effect as the listed ranges.

[0071] In operation S317, the storage controller 300 may request an oscillator count value from the storage device 400. In operation S319, the storage device 400 may send a second oscillator count value CNT2 to the storage controller 300 in response to the request from the storage controller 300. For example, the second oscillator count value CNT2 may be the oscillator count value of the write data strobe signal WDQS at the second temperature.

[0072] In operation S321, the storage controller 300 can determine the weights based on the first oscillator count value CNT1 and the second oscillator count value CNT2. For example, the storage controller 300 can calculate the weights assuming that the oscillator count value of the write data strobe signal WDQS changes linearly from the first temperature to the second temperature. The calculated weights can represent the amount of change in delay along the WDQS path according to the temperature change of the storage system 20.

[0073] In operation S323, the storage controller 300 can send weights to the storage device 400. For example, the storage controller 300 can send weights along with a weight setting command to the storage device 400 via the command / address signal CA. For example, the storage controller 300 can send weights to the storage device 400 based on a Mode Register Setting (MRS) command. As another example, the storage controller 300 can send weights to the storage device 400 based on a Test Mode Register Setting (TMRS) command.

[0074] In operation S325, storage device 400 can store weights provided from storage controller 300. For example, storage device 400 can store weights in response to a weight setting command (e.g., an MRS command or a TMRS command) from storage controller 300. The weights can be stored in storage circuitry 450.

[0075] Figure 5 It shows the basis Figure 3 A graph illustrating the latency variations along the WDQS path of the component characteristics of a storage device. Figure 5 In the graph, the horizontal axis represents temperature, and the vertical axis represents the delay along the WDQS path. (Reference) Figure 3 and Figure 5 The amount by which the delay on the WDQS path changes with temperature can vary depending on the component characteristics of the WDQS transfer circuit 410. Component characteristics can be categorized by the process corner of the components (e.g., transistors) on the WDQS path. For example, component characteristics can be classified as slow process corner, typical process corner, and fast process corner.

[0076] like Figure 5 As shown, when the components of the WDQS transfer circuit 410 have a first component characteristic (e.g., when the components of the WDQS transfer circuit 410 correspond to a slow process corner) and when the temperature of the storage system 20 increases, a reduction in delay on the WDQS path occurs.

[0077] For example Figure 5 As shown, a reduction in delay on the WDQS path occurs when the components of the WDQS transfer circuit 410 have second component characteristics (e.g., when the components of the WDQS transfer circuit 410 correspond to a typical process corner) and when the temperature of the storage system 20 increases. Figure 5 As shown, the amount of delay reduction corresponding to the characteristics of the second element can be less than the amount of delay reduction corresponding to the characteristics of the first element.

[0078] like Figure 5As further shown, when the elements of the WDQS transfer circuit 410 have third element characteristics (e.g., when the elements of the WDQS transfer circuit 410 correspond to a fast process corner) and when the temperature of the storage system 20 increases, an increase in delay on the WDQS path occurs.

[0079] like Figure 5 As described, the delay on the WDQS path, based on the component characteristics of the WDQS transmission circuit 410, can vary linearly (or approximately linearly) depending on temperature changes. Therefore, a weight reflecting the component characteristics can be calculated based on the delay values ​​on the WDQS path corresponding to two temperatures. For example, the weight can be calculated based on the slope of the delay change with temperature. Therefore, when the storage device 400 compensates for delay changes by using weights calculated based on delay values ​​at two temperatures, temperature compensation reflecting the component characteristics can be performed.

[0080] Figure 6 The diagram is based on Figure 5 The example indicated in the document is by Figure 3 An example of how a storage controller determines weights. Specifically, Figure 6 The illustration shows an example of how the storage controller 300 determines each of a plurality of different weights based on the characteristics of the components.

[0081] refer to Figure 3 , Figure 5 and Figure 6 The storage controller 300 can calculate weights based on the delay corresponding to each of the first temperature T1 and the second temperature T2. For example, as referenced... Figure 4 As explained, the storage controller 300 can receive the oscillator count values ​​of the write data strobe signal WDQS at the first temperature T1 and the second temperature T2 from the storage device 400, respectively. In this case, the oscillator count value corresponding to each of the first temperature T1 and the second temperature T2 can respectively correspond to the delay value corresponding to the first temperature T1 and the second temperature T2.

[0082] When the components of the WDQS transmission circuit 410 have the first component characteristics, the storage controller 300 can calculate the first weight WT1 based on the first delay D1 corresponding to the first temperature T1 and the second delay D2 corresponding to the second temperature T2. For example, the first weight WT1 can represent the slope of the delay change according to the temperature under the first component characteristics.

[0083] When the components of the WDQS transfer circuit 410 have the second component characteristics, the storage controller 300 can calculate the second weight WT2 based on the third delay D3 corresponding to the first temperature T1 and the fourth delay D4 corresponding to the second temperature T2. For example, the second weight WT2 can represent the slope of the delay change according to the temperature under the second component characteristics.

[0084] When the components of the WDQS transfer circuit 410 have a third component characteristic, the storage controller 300 can calculate a third weight WT3 based on a fifth delay D5 corresponding to the first temperature T1 and a sixth delay D6 corresponding to the second temperature T2. For example, the third weight WT3 can represent the slope of the delay change according to temperature under the third component characteristic.

[0085] As described above, the storage controller 300 can determine the weights reflecting the component characteristics of the WDQS transfer circuit 410 based on the oscillator count values ​​of the write data strobe signal WDQS at two temperatures. The storage controller 300 can store the weights reflecting the component characteristics in the storage device 400. Therefore, the storage device 400 can adjust the delay on the WDQS path according to temperature changes by reflecting the component characteristics.

[0086] In the following text, reference will be made to Figures 7 to 14 Further explanation describes an embodiment where the storage system 10 adjusts the latency on the WDQS path. Specifically, refer to... Figures 7 to 11 as well as Figures 12 to 14 The document describes an embodiment of adjusting the delay by changing the voltage applied to the delay unit on the WDQS path using a voltage regulator, and an embodiment of adjusting the delay by controlling the delay unit on the WDQS path.

[0087] Figure 7 This is a block diagram illustrating a storage device configured to adjust latency on a WDQS path according to an embodiment. Reference Figure 7 Storage device 500 can be compared with reference Figures 1 to 6 The storage devices 200 and 400 are described accordingly. Therefore, their repeated descriptions are omitted below.

[0088] Storage device 500 may include storage circuitry 510, temperature sensor 520, temperature compensator 530, reference voltage generator 540, voltage regulator 550, WDQS transmission circuitry 560, and data sampler 570. Storage circuitry 510 can be connected to... Figure 3 Corresponding to the storage circuit 450, and the WDQS transmission circuit 560 and data sampler 570 can be respectively connected to... Figure 1 The WDQS transmission circuit 230 and the data sampler 240 correspond to each other.

[0089] Storage circuit 510 can store weight WT. (See reference...) Figures 1 to 6 As described, the weight WT can be determined by the memory controllers 100 and 300 during the initialization or testing process. For example, the memory circuit 510 can be implemented by one of a mode register, a test mode register, and a fuse.

[0090] Temperature sensor 520 can sense the temperature of storage device 500. Temperature sensor 520 can provide the sensed current temperature TP to temperature compensator 530.

[0091] Temperature compensator 530 can generate a delay code DCODE based on the current temperature TP and weight WT. The delay code DCODE can correspond to the delay adjustment amount used to adjust the delay on the WDQS path. For example, temperature compensator 530 can calculate the temperature change based on a predetermined reference temperature and the current temperature TP, and generate a delay code DCODE for adjusting the delay based on the weight WT. For example, when adjusting the delay on the WDQS path according to the delay code DCODE, the delay on the WDQS path can remain constant regardless of the temperature change.

[0092] The reference voltage generator 540 can generate a reference voltage VREF from the supply voltage VDDQ based on the delay code DCODE. The reference voltage generator 540 can generate a reference voltage VREF having a level corresponding to the delay code DCOD. For example, the reference voltage generator 540 can generate a reference voltage VREF having a different level corresponding to each different delay code DCODE.

[0093] Voltage regulator 550 can generate an regulated voltage VLDO based on a reference voltage VREF. For example, voltage regulator 550 can generate an regulated voltage VLDO with a level lower than the reference voltage VREF. The regulated voltage VLDO output from voltage regulator 550 can be provided to WDQS transmission circuit 560.

[0094] The WDQS transmission circuit 560 can transmit the write data strobe signal WDQS to the data sampler 570. The WDQS transmission circuit 560 can transmit the write data strobe signal WDQS to the data sampler 570 using a power supply voltage VDDQ and a regulating voltage VLDO. For example, some of the repeaters (or inverters) in the WDQS transmission circuit 560 can operate using the power supply voltage VDDQ, and other repeaters (or inverters) can operate using the regulating voltage VLDO. In this case, the delay of the write data strobe signal WDQS transmitted by the repeater operating using the regulating voltage VLDO can be controlled according to the level of the regulating voltage VLDO.

[0095] Data sampler 570 can sample the data signal DQ based on the write data strobe signal WDQS. When the delay on the WDQS path is adjusted based on the regulating voltage VLDO, the S / H margin of data sampler 570 can be increased regardless of temperature. Therefore, the error rate of the data output from data sampler 570 is reduced.

[0096] As described above, storage device 500 can control the level of the regulated voltage VLDO applied to the WDQS transmission circuit 560 via voltage regulator 550 based on the pre-stored weight WT and the current temperature TP. Therefore, storage device 500 can adjust the delay on the WDQS path according to the temperature sensed in real time without needing to be retrained by storage controllers 100 and 300.

[0097] Figure 8 The diagram shows Figure 7 Example operation of the temperature compensator. (See reference) Figure 7 and Figure 8 The temperature compensator 530 can calculate the temperature change by comparing the current temperature TP with the reference temperature TREF. For example, the reference temperature TREF can be pre-stored in the temperature compensator 530.

[0098] The temperature compensator 530 can generate a delay code DCODE corresponding to the weight WT based on a temperature change. For example, different delay codes DCODEs can be generated based on the same temperature change that depends on the weight WT. Figure 8 As shown, the temperature compensator 530 can generate a first delay code DCODE1 corresponding to the first weight WT1, a second delay code DCODE2 corresponding to the second weight WT2, and a third delay code DCODE3 corresponding to the third weight WT3. (See reference...) Figure 6 As explained, the weights reflect the component characteristics of the WDQS transmission circuit 560, and therefore, the delay code DCODE generated by the temperature compensator 530 can reflect the component characteristics.

[0099] Figure 9 The diagram shows Figure 7 Example operation of the reference voltage generator and voltage regulator. Reference Figure 7 and Figure 9 The reference voltage generator 540 can generate a reference voltage VREF corresponding to the delay code DCODE. For example, as... Figure 9 As shown, the reference voltage generator 540 can generate a first reference voltage VREF1 to a third reference voltage VREF3 corresponding to the first delay code DCODE1 to the third delay code DCODE3, respectively.

[0100] Voltage regulator 550 can generate a regulated voltage VLDO corresponding to the reference voltage VREF. For example, as Figure 9 As shown, the voltage regulator 550 can generate a first regulated voltage VLDO1 to a third regulated voltage VLDO3 corresponding to the first reference voltage VREF1 to the third reference voltage VREF3, respectively.

[0101] As described above, the delay code DCODE reflects the component characteristics of the WDQS transmission circuit 560, and therefore, the regulating voltage VLDO generated by the voltage regulator 550 can also reflect these component characteristics. Thus, the storage device 500 can adjust the delay on the WDQS path based on the regulating voltage VLDO, which has a level reflecting the component characteristics.

[0102] Figure 10 yes Figure 7 An exemplary circuit diagram of the voltage regulator and WDQS transmission circuit. (Refer to...) Figure 7 and Figure 10 The voltage regulator 550 may include an amplifier AMP, a transistor TR, a first resistor R1, and a second resistor R2. A reference voltage VREF can be input to the first input terminal of the amplifier AMP, and a feedback voltage VFDB can be input to its second input terminal. The amplifier AMP can output the comparison result between the reference voltage VREF and the feedback voltage VFDB to the gate terminal of the transistor TR. For example, based on the comparison result, the transistor TR can be turned on or off. Depending on the on / off state of the transistor TR, the voltage of the output node nd (i.e., the regulated voltage VLDO) can be controlled based on the power supply voltage VDDQ and the ground voltage VSS. When the transistor TR is on, the voltage of the output node nd can be increased by the power supply voltage VDDQ. Therefore, when controlling the voltage of the output node nd, the level of the regulated voltage VLDO output from the output node nd can remain constant.

[0103] The WDQS transmission circuit 560 may include an inverter INV. The inverter INV can output a delayed write data strobe signal rWDQS by delaying the write data strobe signal WDQS. The delay of the inverter INV on the write data strobe signal WDQS can be controlled according to the adjustment voltage VLDO. For example, when the adjustment voltage VLDO increases, the delay of the write data strobe signal WDQS can be reduced. Therefore, the delay on the WDQS path can be adjusted based on the adjustment voltage VLDO.

[0104] exist Figure 10In this work, the WDQS transmission circuit 560 is described as including a single inverter INV for transmitting the write data strobe signal WDQS to the data sampler 570; however, the inventive concept is not limited thereto. For example, the WDQS transmission circuit 560 may include multiple inverters operating based on the regulated voltage VLDO. Alternatively, the WDQS transmission circuit 560 may further include at least one inverter operating based on the power supply voltage VDDQ.

[0105] Figure 11 The diagram is drawn by Figure 7 An exemplary flowchart illustrating the latency adjustment operation of a storage device. (See reference...) Figure 7 and Figure 11 In operation S501, the storage device 500 can sense temperature. For example, the storage device 500 can sense the temperature of the storage device 500 in real time via a temperature sensor 520.

[0106] In operation S502, the storage device 500 can generate a delay code based on the sensed temperature and a weight. For example, the storage device 500 can calculate a temperature change by comparing a predetermined reference temperature with the sensed temperature. The storage device 500 can generate a delay code corresponding to the weight based on the temperature change. For example, the delay code can be generated differently depending on the temperature change and the weight.

[0107] In operation S503, the storage device 500 can control the regulated voltage applied to the WDQS transmission circuit 560 based on a delay code. The storage device 500 can adjust the delay on the WDQS path by controlling the regulated voltage. For example, the storage device 500 can generate a reference voltage corresponding to the delay code from the power supply voltage. The storage device 500 can generate a regulated voltage corresponding to the reference voltage. The WDQS transmission circuit 560 can transmit the write data strobe signal WDQS to the data sampler 570 based on the regulated voltage. The transmission timing of the write data strobe signal WDQS can vary depending on the regulated voltage. Therefore, the delay on the WDQS path can be adjusted.

[0108] As described above, the storage device 500 according to the embodiment can adjust the delay on the WDQS path by controlling the level of the regulating voltage applied to the circuit on the WDQS path via the voltage regulator 550.

[0109] Figure 12 This is a block diagram illustrating a storage device configured to adjust the delay on a WDQS circuit according to an embodiment. Reference Figure 12 Storage device 600 can be compared with reference Figures 1 to 6 The storage devices 200 and 400 are described accordingly. Therefore, their repeated descriptions are omitted below.

[0110] Storage device 600 may include storage circuitry 610, temperature sensor 620, temperature compensator 630, WDQS transmission circuitry 640, and data sampler 650. Storage circuitry 610, temperature sensor 620, and temperature compensator 630 can be respectively connected to… Figure 7 The storage circuit 510, temperature sensor 520, and temperature compensator 530 correspond to each other. The WDQS transmission circuit 640 and data sampler 650 can be respectively connected to... Figure 1 The WDQS transmission circuit 230 and the data sampler 240 correspond to each other. Therefore, their repeated descriptions are omitted below.

[0111] Temperature compensator 630 can generate a delayed code DCODE based on the weight WT from storage circuit 610 and the current temperature TP from temperature sensor 620. For example, as referenced... Figure 8 As described, the temperature compensator 630 can generate a delay code DCODE corresponding to the weight WT based on temperature changes. The temperature compensator 630 can control the delay unit of the WDQS transmission circuit 640 based on the delay code DCODE.

[0112] The WDQS transmission circuit 640 can transmit the write data strobe signal WDQS to the data sampler 650. For example, the WDQS transmission circuit 640 may include a delay unit (e.g., a repeater or inverter) for transmitting the write data strobe signal WDQS. The delay unit of the WDQS transmission circuit 640 can be operated using the power supply voltage VDDQ.

[0113] At least one delay unit of the WDQS transmission circuit 640 can be controlled based on the delay code DCODE. For example, the on / off state of the transistor in the delay unit can be controlled based on the delay code DCODE. The delay of the delay unit can be adjusted based on the on / off state of the transistor. Therefore, the delay of the write data strobe signal WDQS output by the WDQS transmission circuit 640 can be adjusted according to the delay code DCODE.

[0114] The data sampler 650 can sample the data signal DQ based on the write data strobe signal WDQS. When the delay on the WDQS path is adjusted by controlling the delay unit, the S / H margin of the data sampler 650 can be increased regardless of temperature changes. Therefore, the error rate of the data output from the data sampler 650 is reduced.

[0115] As described, storage device 600 does not include Figure 7The voltage regulator 550 of the storage device 500 can therefore adjust the delay of the write data strobe signal WDQS by directly controlling the delay unit of the WDQS transfer circuit 640. Thus, the storage device 600 can adjust the delay on the WDQS path based on the real-time sensed temperature without requiring retraining by the storage controllers 100 and 300.

[0116] Figure 13A and Figure 13B yes Figure 12 An illustrative circuit diagram of the WDQS transmission circuit. Specifically, Figure 13A and Figure 13B Each of the figures illustrates a delay unit of the WDQS transmission circuit 640. However, the inventive concept is not limited thereto, and the WDQS transmission circuit 640 may include multiple delay units.

[0117] refer to Figure 13A The WDQS transmission circuit 640a may include an inverter INVa, PMOS transistors PM1 to PMn, and NMOS transistors NM1 to NMn. For example, the dimensions of each PMOS transistor PM1 to PMn may be different, and the dimensions of each NMOS transistor NM1 to NMn may also be different. However, the inventive concept is not limited thereto.

[0118] The inverter INVa can output a delayed write data strobe signal rWDQS by delaying the write data strobe signal WDQS. The delay of the inverter INVa on the write data strobe signal WDQS can be adjusted according to the first enable voltage VEN1 and the second enable voltage VEN2. For example, when the voltage difference between the first enable voltage VEN1 and the second enable voltage VEN2 increases, the delay of the write data strobe signal WDQS can be reduced.

[0119] The first enable voltage VEN1 can be controlled based on enable signals ES11 to ES1n that control the on / off states of PMOS transistors PM1 to PMn. The second enable voltage VEN2 can be controlled based on enable signals ES21 to ES2n that control the on / off states of NMOS transistors NM1 to NMn. For example, enable signals ES11 to ES1n and enable signals ES21 to ES2n can be complementary. In this case, PMOS transistors PM1 to PMn and NMOS transistors NM1 to NMn can operate symmetrically. For example, when the first PMOS transistor PM1 is turned on, the first NMOS transistor NM1 can also be turned on.

[0120] Enable signals ES11 to ES1n can be generated based on the delay code DCODE. In an example embodiment, the delay code DCODE can be used as either enable signals ES11 to ES1n or enable signals ES21 to ES2n. For example, when the delay code DCODE is used as enable signals ES11 to ES1n, the on / off states of PMOS transistors PM1 to PMn can be controlled by bits of the delay code DCODE. In this case, the on / off states of NMOS transistors NM1 to NMn can be controlled based on the complementary bits of the delay code DCODE.

[0121] For example, when the number of PMOS transistors PM1 to PMn and NMOS transistors NM1 to NMn in the on state increases based on the delay code DCODE, the first enable voltage VEN1 can increase the supply voltage VDDQ, and the second enable voltage VEN2 can decrease the ground voltage VSS. Therefore, the delay of the inverter INVa on the write data strobe signal WDQS can be reduced.

[0122] refer to Figure 13B The WDQS transmission circuit 640b may include an inverter INVb and transistors MO1 to MOn. For example, each of transistors MO1 to MOn may be an NMOS transistor.

[0123] The inverter INVb can operate based on the supply voltage VDDQ and the ground voltage VSS. The inverter INVb can output a delayed write data strobe signal rWDQS by delaying the write data strobe signal WDQS. The delay of the write data strobe signal WDQS by the inverter INVb can be adjusted according to the load of the capacitors CP1 to CPn connected to the output terminals of the inverter INVb. For example, when the load of capacitors CP1 to CPn increases, the delay of the write data strobe signal WDQS can also be increased.

[0124] The load on capacitors CP1 to CPn can be controlled based on enable signals ES31 to ES3n, which in turn control the on / off states of transistors MO1 to MOn. For example, as the number of transistors MO1 to MOn in the on state increases, the load on capacitors CP1 to CPn can also increase. Therefore, the delay of inverter INVb on the write data strobe signal WDQS can be increased.

[0125] Enable signals ES31 to ES3n can be generated based on the delay code DCODE. In the example embodiment, the delay code DCODE can be used as the enable signals ES31 to ES3n. For example, when the delay code DCODE is used as the enable signals ES31 to ES3n, the on / off state of transistors MO1 to MOn can be controlled by the bits of the delay code DCODE.

[0126] As described above, the transistors of the delay unit in the WDQS transmission circuit 640 can be controlled based on the delay code DCODE. Therefore, the delay on the WDQS path can be adjusted based on the on / off state of the transistors in the delay unit.

[0127] Figure 14 The diagram is drawn by Figure 12 An exemplary flowchart illustrating the latency adjustment operation of a storage device. (See reference...) Figure 12 and Figure 14 In operation S601, the storage device 600 can sense temperature. For example, the storage device 600 can sense the temperature of the storage device 600 in real time via a temperature sensor 620.

[0128] In operation S602, storage device 600 can generate a delay code based on the sensed temperature and a weight. For example, storage device 600 can calculate a temperature change by comparing a predetermined reference temperature with the sensed temperature. Storage device 600 can then generate a delay code corresponding to the weight based on the temperature change.

[0129] In operation S603, the storage device 600 can control the delay unit of the WDQS transmission circuit 640 based on the delay code. For example, as referenced... Figure 13A and Figure 13B As explained, the storage device 600 can control the on / off state of the transistor in the delay cell based on a delay code. The storage device 600 can control the enable voltage applied to the inverter of the delay cell by controlling the on / off state of the transistor. Alternatively, the storage device 600 can control the load of the capacitor in the delay cell by controlling the on / off state of the transistor. Therefore, the delay of the write data strobe signal WDQS through the delay cell can be adjusted, and the delay on the WDQS path can be adjusted.

[0130] As described above, the storage device 600 according to the embodiment can adjust the delay on the WDQS path without a voltage regulator by controlling the transistors of the delay unit of the WDQS transmission circuit 640.

[0131] Figure 15 This is a block diagram of a stacked storage device according to an embodiment. (Reference) Figure 15 The stacked storage device 700 can be compared with the reference. Figures 1 to 14 The described storage devices 200, 400, 500, and 600 correspond to each other. The stacked storage device 700 may include a buffer chip 710 and multiple core chips 720 to 750. For example, the buffer chip 710 may be referred to as an interface chip, a substrate chip, a logic chip, a master chip, etc., and each of the core chips 720 to 750 may be referred to as a storage chip, a slave chip, etc. Figure 15In this context, the stacked storage device 700 is described as comprising four core chips 720 to 750; however, the number of core chips can vary. For example, the stacked storage device 700 may include eight, twelve, or sixteen core chips.

[0132] Buffer wafer 710 and core wafers 720 to 750 can be stacked and electrically connected via through-silicon vias (TSVs). Therefore, the stacked memory device 700 can have a three-dimensional memory structure in which multiple wafers 710 to 750 are stacked. For example, the stacked memory device 700 can be implemented based on the High Bandwidth Memory (HBM) or Hybrid Memory Cube (HMC) standard.

[0133] The stacked storage device 700 can support multiple functionally independent channels (or libraries). For example, such as Figure 15 As shown, the stacked storage device 700 can support sixteen channels CH0 to CH15. When each of the channels CH0 to CH15 supports 64 data transfer paths (i.e., when there are 64 data signal DQ pins corresponding to each of the channels CH0 to CH15), the stacked storage device 700 including 16 channels CH0 to CH15 can support 1,024 data transfer paths. However, the inventive concept is not limited thereto. The stacked storage device 700 can support 1,024 or more data transfer paths and various numbers of channels (e.g., eight channels). For example, when the stacked storage device 700 supports eight channels and each of the channels supports 128 data transfer paths, the stacked storage device 700 can support 1,024 data transfer paths.

[0134] Each of the core chips 720 to 750 can support at least one channel. For example, such as Figure 15 As shown, each of the core chips 720 to 750 can support four channels CH0 to CH3, CH4 to CH7, CH8 to CH11, and CH12 to CH15. In this case, core chips 720 to 750 can each support different channels. However, the inventive concept is not limited to this, and at least two of the core chips can support the same channel. For example, when the stacked storage device 700 includes eight core chips, one of the four core chips constituting one stack and one of the other four core chips constituting another stack can support the same channel. In this case, the core chips supporting the same channel can be distinguished by the stack ID (SID).

[0135] Each channel can be configured with independent command and data interfaces. For example, each channel can be timed independently based on independent timing requirements, or it can be out of sync with each other.

[0136] Each of the channels may include multiple banks or multiple memory banks 701. Each of the memory banks 701 may include memory cells, sense amplifiers, etc., connected to word lines and bit lines. For example, each of the channels CH0 to CH15 may include 32 memory banks 701. However, the inventive concept is not limited thereto, and each of the channels CH0 to CH15 may include eight or more memory banks 701. Figure 15 The text describes a memory bank 701 included in a single channel within a single core chip; however, the memory bank 701 included in a single channel can be distributed across multiple core chips. For example, when two core chips support the first channel CH0, the memory bank 701 of the first channel CH0 can be distributed across the two core chips.

[0137] In an example embodiment, a channel can be divided into two pseudo-channels that operate independently. For example, pseudo-channels can share the channel's command and clock inputs (e.g., clock signal CK and / or clock enable signal CKE), but they can also decode and execute commands independently. For example, when a channel supports 64 data transmission paths, each of the pseudo-channels can support 32 data transmission paths. For example, when a channel includes 32 memory banks 701, each pseudo-channel can include 16 memory banks 701.

[0138] Buffer chip 710 and core chips 720 to 750 may include TSV regions 702. TSVs configured to penetrate chips 710 to 750 may be located in TSV regions 702. Buffer chip 710 can transmit and receive various signals with core chips 720 to 750 via TSVs. Each of the core chips 720 to 750 can transmit and receive signals with buffer chip 710 and other core chips via TSVs. In this case, signals can be transmitted and received independently via the TSV corresponding to each channel. For example, when an external host device (e.g., Figure 1 When the storage controller 100 sends a data signal to the first channel CH0 to store data in the storage cell of the first channel CH0, the buffer chip 710 can send a data signal to the first core chip 720 via the TSV corresponding to the first channel CH0. In this way, data can be stored in the storage cell of the first channel CH0.

[0139] In the example embodiment, the power supply voltage VDDQL can be used to transmit signals via TSV. The power supply voltage VDDQL can be less than the power supply voltage VDDQ used for the overall operation of the buffer chip 710. For example, when the power supply voltage VDDQL is 0.4V, the power supply voltage VDDQ can be 1.1V.

[0140] The buffer chip 710 may include a physical layer PHY 711. Physical layer 711 may include interface circuitry for communicating with an external host device. In an example embodiment, physical layer 711 may include interface circuitry corresponding to each of channels CH0 to CH15. For example, the interface circuitry corresponding to one channel may include… Figure 1 The storage device 200 comprises components 210 to 240. Signals received from the host device via the physical layer 711 can be transmitted to the core chip 720 to 750 via TSV.

[0141] In an example embodiment, buffer chip 710 may include a channel controller corresponding to each of the channels. The channel controller may manage memory reference operations for the corresponding channel and determine the timing requirements for the corresponding channel.

[0142] In an example embodiment, buffer chip 710 may include multiple pins configured to receive signals from an external host device. (See reference...) Figure 1 As described, the buffer chip 710 can receive clock signal CK, command / address signal CA, write data strobe signal WDQS and data signal DQ, and send data signal DQ through multiple pins.

[0143] In an example embodiment, the stacked storage device 700 may further include error-correcting code (ECC) circuitry for detecting and correcting data errors. For example, during a write operation, the ECC circuitry may generate parity bits for data transmitted from the host device. During a read operation, the ECC circuitry may use the parity bits to detect and correct errors in data transmitted from one of the core chips 720 to 750, and send the error-corrected data to the host device.

[0144] In the example embodiment, as referenced Figures 1 to 14 As described, the stacked storage device 700 can store weights to compensate for latency variations on the WDQS path due to temperature changes. For example, the weights can be determined during the initialization or testing process of the stacked storage device 700. The stacked storage device 700 can adjust the latency on the WDQS path based on the stored weights and the real-time temperature. Therefore, even if the temperature of the stacked storage device 700 changes, it can maintain a constant latency on the WDQS path without requiring the host device to be retrained. Thus, the S / H margin used for sampling the data signal DQ can be increased regardless of temperature changes.

[0145] Figure 16 yes Figure 15 A block diagram of the buffer chip. (Reference) Figure 16The buffer chip 710 can support a first channel CHa and a second channel CHb. The buffer chip 710 may include a first storage circuit 712a corresponding to the first channel CHa, a first temperature sensor 713a, a first temperature compensator 714a, a first reference voltage generator 715a, a first voltage regulator 716a, a first WDQS divider 717a, a first WDQS tree circuit 718a, and a first receiver 719a. The buffer chip 710 may include a first write data strobe pin W_P1 and a first data pin D_P1 to receive a first write data strobe signal WDQS1 and a first data signal DQ1 provided to the first channel CHa.

[0146] The buffer chip 710 may include a second storage circuit 712b corresponding to the second channel CHb, a second temperature sensor 713b, a second temperature compensator 714b, a second reference voltage generator 715b, a second voltage regulator 716b, a second WDQS divider 717b, a second WDQS tree circuit 718b, and a second receiver 719b. The buffer chip 710 may include a second write data strobe pin W_P2 and a second data pin D_P2 to receive the second write data strobe signal WDQS2 and the second data signal DQ2 provided to the second channel CHb.

[0147] The components 712b to 719b and pins W_P2 and D_P2 corresponding to the second channel CHb can respectively correspond to the components 712a to 719a and pins W_P1 and D_P1 corresponding to the first channel Cha. Therefore, for ease of explanation, the buffer chip 710 will be described below focusing on the components 712a to 719a and pins W_P1 and D_P1 of the first channel CHa.

[0148] The first storage circuit 712a, the first temperature sensor 713a, the first temperature compensator 714a, the first reference voltage generator 715a, and the first voltage regulator 716a can be respectively connected to... Figure 7 The storage circuit 510, temperature sensor 520, temperature compensator 530, reference voltage generator 540, and voltage regulator 550 correspond to each other. The first WDQS divider 717a and the first WDQS tree circuit 18a can be connected to... Figure 7 Corresponding to the WDQS transmission circuit 560, and the first receiver 719a can be connected to... Figure 7 This corresponds to the data sampler 570. Therefore, its repeated description is omitted below.

[0149] The first storage circuit 712a can store a first weight WT1 corresponding to the first channel CHa. The first weight WT1 can be determined during the initialization or testing process of the first channel CHa. The first temperature sensor 713a can be a temperature sensor located adjacent to the interface circuit (e.g., the first WDQS divider 717a, the first WDQS tree circuit 718a, and the first receiver 719a) corresponding to the first channel CHa. The first current temperature TP1 sensed by the first temperature sensor 713a can be provided to the first temperature compensator 714a.

[0150] The first temperature compensator 714a can generate a first delay code DCODE1 based on the first weight WT1 and the first current temperature TP1. The first reference voltage generator 715a can generate a first reference voltage VREF1 based on the first delay code DCODE1, and the first voltage regulator 716a can generate a first regulated voltage VLDO1 based on the first reference voltage VREF1.

[0151] The first WDQS divider 717a can generate a first internal write data strobe signal dWDQS1 based on the first write data strobe signal WDQS1. For example, the first WDQS divider 717a can divide the first write data strobe signal WDQS1 and generate first internal write data strobe signals dWDQS1 with different phases. In this case, the frequency of each first internal write data strobe signal dWDQS1 can be less than the frequency of the first write data strobe signal WDQS1. In an example embodiment, a separate receiver (or buffer) configured to receive the first write data strobe signal WDQS1 can be arranged between the first WDQS divider 717a and the first write data strobe pin W_P1.

[0152] The first WDQS tree circuit 718a can transmit the first internal write data strobe signal dWDQS1 to the first receiver 719a via multiple repeaters (or inverters). In an example embodiment, the first WDQS tree circuit 718a can transmit the first internal write data strobe signal dWDQS1 based on a first adjustment voltage VLDO1. For example, the first WDQS tree circuit 718a may include an inverter operating based on the first adjustment voltage VLDO1. When the first adjustment voltage VLDO1 is controlled according to the first delay code DCODE1, the delay of each first internal write data strobe signal dWDQS1 transmitted through the first WDQS tree circuit 718a can be adjusted. Therefore, the first WDQS tree circuit 718a can transmit the first internal write data strobe signal dWDQS1 with the adjusted delay to the first receiver 719a.

[0153] The first receiver 719a can sample the first data signal DQ1 based on the first internal write data strobe signal rWDQS1. For example, the first receiver 719a can sample the first data signal DQ1 at the rising or falling edge timing of each of the first internal write data strobe signals rWDQS1.

[0154] As described above, the first adjustment voltage VLDO1 can be controlled based on the first weight WT1 and the first current temperature TP1, and the delay on the path through which the first write data strobe signal WDQS1 is transmitted to the first receiver 719a can be adjusted based on the first adjustment voltage VLDO1.

[0155] Similarly, the second adjustment voltage VLDO2 can be controlled based on the second weight WT2 and the second current temperature TP2, and the delay on the path through which the second write data strobe signal WDQS2 is transmitted to the second receiver 719b can be adjusted based on the second adjustment voltage VLDO2.

[0156] A second weight WT2 for controlling the second regulation voltage VLDO2 can be determined during the initialization or testing process of the second channel CHb. For example, the second weight WT2 can be different from the first weight WT1. A second current temperature TP2 for controlling the second regulation voltage VLDO2 can be sensed by a second temperature sensor 713b located adjacent to the interface circuitry corresponding to the second channel CHb (e.g., the second WDQS divider 717b, the second WDQS tree circuit system 718b, and the second receiver 719b). For example, the second current temperature TP2 can be different from the first current temperature TP1. Therefore, the second regulation voltage VLDO2 can be different from the first regulation voltage VLDO1, and the delay on the WDQS path adjusted based on the second regulation voltage VLDO2 can be different from the delay on the WDQS path adjusted based on the first regulation voltage VLDO1.

[0157] As described above, when the buffer chip 710 supports multiple channels CHa and CHb, the buffer chip 710 can independently adjust the delay on the WDQS path corresponding to each of the channels CHa and CHb. Therefore, even if the characteristics of the components on the WDQS path corresponding to the first channel CHa are different from the characteristics of the components on the WDQS path corresponding to the second channel CHb, the change in delay on the WDQS path corresponding to each of the channels CHa and CHb can be compensated. Therefore, the S / H margin for sampling the data signal in each channel can be increased.

[0158] Figure 16 The illustration shows the buffer chip 710 as shown in the reference diagram. Figures 7 to 11The embodiments described herein involve adjusting the delay on the WDQS path via voltage regulators 716a and 716b; however, the inventive concept is not limited thereto. For example, the buffer chip 710 may be as described in reference... Figures 12 to 14 As described, the delay is adjusted by controlling the transistors of the delay cells in the WDQS tree circuits 718a and 718b.

[0159] Figure 17 This is an illustrative diagram of a semiconductor package according to an embodiment. Reference Figure 17 The semiconductor package 1000 may include a stacked memory device 1100, a system-on-a-chip 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer chip 1110 and core chips 1120 to 1150. The stacked memory device 1100 may be related to a reference... Figure 15 The described stacked storage device corresponds to 700.

[0160] Each of the core chips 1120 to 1150 may include a storage cell for storing data. Buffer chip 1110 may include a physical layer 1111 and a direct access area (DAB) 1112. Physical layer 1111 may be electrically connected to the physical layer 1210 of system-on-chip 1200 via an interposer layer 1300. Stacked storage device 1100 may receive signals from or send signals to system-on-chip 1200 via physical layer 1111. Physical layer 1111 may include a reference... Figure 15 and 16 The components of the buffer chip 710 are described.

[0161] Direct access region 1112 provides an access path that enables testing of stacked memory device 1100 without requiring processing by system-on-chip 1200. Direct access region 1112 may include conductive devices (e.g., ports or pins) capable of direct communication with external test equipment. Test signals received through direct access region 1112 can be transmitted to core wafers 1120 to 1150 via TSV. Data read from core wafers 1120 to 1150 can be transmitted to test equipment via TSV and direct access region 1112 for testing core wafers 1120 to 1150. In this way, direct access testing can be performed on core wafers 1120 to 1150.

[0162] Buffer chip 1110 and core chips 1120 to 1150 can be electrically connected to each other via TSV 1101 and bump 1102. Buffer chip 1110 can receive signals provided to each channel from system-on-chip 1200 via bump 1102 assigned to each channel, or send signals to system-on-chip 1200 via bump 1102. For example, bump 1102 can be a microbump.

[0163] The system-on-chip 1200 can execute applications supported by the semiconductor package 1000 by using the stacked storage device 1100. For example, the system-on-chip 1200 may include at least one of a central processing unit (CPU), an application processor (AU), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP) to perform specialized operations.

[0164] The system-on-chip 1200 can control the overall operation of the stacked storage device 1100. The system-on-chip 1200 may correspond to the storage controllers 100 and 300 described above. The system-on-chip 1200 may include a physical layer 1210. The physical layer 1210 may include interface circuitry for sending and receiving signals with the physical layer 1111 of the stacked storage device 1100. For example, the physical layer 1210 may include… Figure 1 The memory controller 100 is a component. The system-on-chip 1200 can provide various signals to the physical layer 1111 through the physical layer 1210. The signals provided to the physical layer 1111 can be transmitted to the core chips 1120 to 1150 through the interface circuit of the physical layer 1111 and the TSV 1101.

[0165] Intermediate layer 1300 can connect stacked memory device 1100 and system-on-chip 1200. Intermediate layer 1300 can connect physical layer 1111 of stacked memory device 1100 and physical layer 1210 of system-on-chip 1200, and provide physical paths formed by using conductive materials. Therefore, stacked memory device 1100 and system-on-chip 1200 can be stacked on top of intermediate layer 1300 to send and receive signals to each other.

[0166] Bump 1103 can be attached to the top of package substrate 1400, and solder ball 1104 can be attached to the bottom of package substrate 1400. For example, bump 1103 can be a flip chip bump. Interposer 1300 can be stacked on package substrate 1400 via bump 1103. Semiconductor package 1000 can send and receive signals with other external packages or semiconductor devices via solder ball 1104. For example, package substrate 1400 can be a printed circuit board (PCB).

[0167] In an example embodiment, the physical layer 1111 of buffer chip 1110 can receive the write data strobe signal WDQS and the data signal DQ from the system-on-chip 1200 via bumps 1102. (See reference...) Figures 1 to 16 As described, physical layer 1111 can sample the data signal DQ based on a write data strobe signal WDQS with adjusted delay.

[0168] Figure 18 This is a diagram illustrating an implementation example of a semiconductor package according to an embodiment. (Reference) Figure 18 The semiconductor package 2000 may include multiple stacked memory devices 2100 and a system-on-a-chip 2200. Each stacked memory device 2100 can be connected to... Figure 17 Corresponding to the stacked storage device 1100, and the system-on-chip 2200 can be with Figure 17 Corresponding to the system-on-chip 1200. Stacked memory device 2100 and system-on-chip 2200 can be stacked on interposer 2300, and interposer 2300 can be stacked on package substrate 2400. Semiconductor package 2000 can send and receive signals with other external packages or semiconductor devices through solder balls 2001 attached to the bottom of package substrate 2400.

[0169] Each stacked storage device 2100 may be implemented based on the HBM standard. However, the inventive concept is not limited thereto, and each stacked storage device 2100 may be implemented based on the Graphics Double Data Rate (GDDR), HMC, or Wide Input / Output (I / O) standard.

[0170] The system-on-a-chip 2200 may include at least one processor such as a CPU, AP, GPU, NPU, etc., and multiple memory controllers for controlling multiple stacked memory devices 2100. The system-on-a-chip 2200 can send and receive signals with the corresponding stacked memory devices through the memory controllers.

[0171] Figure 19 This is a diagram illustrating a semiconductor package according to another embodiment. Reference Figure 19 The semiconductor package 3000 may include a stacked memory device 3100, a host chip 3200, and a package substrate 3300. The stacked memory device 3100 may include a buffer chip 3110 and core chips 3120 to 3150. The buffer chip 3110 may include a physical layer 3111 configured to communicate with the host chip 3200, and each of the core chips 3120 to 3150 may include a memory cell for storing data. The stacked memory device 3100 may be referenced in... Figure 15 and Figure 16 The described stacked storage device 700 corresponds to this.

[0172] The host chip 3200 may include a physical layer 3210 configured to communicate with the stacked storage device 3100. Physical layers 3111 and 3210 may communicate via TSV 3001. The host chip 3200 may correspond to the aforementioned storage controllers 100 and 300. Physical layer 3111 may include a reference... Figures 1 to 16The components of the described storage device. The host chip 3200 may include a processor configured to control the overall operation of the semiconductor package 3000 and execute applications supported by the semiconductor package 3000. For example, the host chip 3200 may include at least one processor, such as a CPU, AP, GPU, NPU, etc.

[0173] The stacked storage device 3100 can be located above the host chip 3200 based on a TSV 3001 vertically stacked on the host chip 3200. Therefore, the buffer chip 3110, core chips 3120 to 3150, and host chip 3200 can be electrically connected to each other via the TSV 3001 and bumps 3002 without an interposer layer. For example, the bumps 3002 can be microbumps.

[0174] Bump 3003 can be attached to the top of package substrate 3300, and solder ball 3004 can be attached to the bottom of package substrate 3300. For example, bump 3003 can be a flip chip bump. Host die 3200 can be stacked on package substrate 3300 via bump 3003. Semiconductor package 3000 can send and receive signals with other external packages or semiconductor devices via solder ball 3004.

[0175] In the example embodiment, the physical layer 3111 of the buffer chip 3110 can receive the write data strobe signal WDQS and the data signal DQ from the host chip 3200 via the TSV 3001. (See reference...) Figures 1 to 16 As described, physical layer 3111 can sample data signal DQ based on write data strobe signal WDQS with adjusted delay.

[0176] In another embodiment, the stacked storage device 3100 may be implemented solely by core chips 3120 to 3150 without the need for a buffer chip 3110. In this case, each of the core chips 3120 to 3150 may further include interface circuitry configured to communicate with the host chip 3200. In this case, each of the core chips 3120 to 3150 may send and receive signals with the physical layer 3210 of the host chip 3200 via the TSV 3001.

[0177] While the inventive concept has been specifically shown and described with reference to its embodiments, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage system, comprising: The storage device is configured to monitor a first oscillator count value of a write data strobe signal used to sample a data signal at a first temperature, and to monitor a second oscillator count value of a write data strobe signal used to sample a data signal at a second temperature. as well as The storage controller is configured to determine weights based on a first oscillator count value and a second oscillator count value during the initialization process of the storage device or during the testing process of the storage device. The storage device includes a temperature sensor configured to sense the temperature of the storage device. The storage device is configured to sample a data signal by adjusting the delay on the transmission path of the write data strobe signal based on the temperature and weight sensed by the storage device.

2. The storage system as claimed in claim 1, wherein, The weight represents the amount of delay in the write data strobe signal based on the temperature sensed by the storage device, and The temperature sensed is in real time.

3. The storage system as described in claim 1, wherein, The storage device is configured to store weights in a mode register in response to a mode register setting command provided from the storage controller.

4. The storage system as claimed in claim 1, wherein, The storage device is configured to store weights in a test mode register or fuse in response to a test mode register setting command provided from the storage controller.

5. The storage system as claimed in claim 1, wherein, The storage device includes: The data sampler is configured to sample the data signal based on the write data strobe signal; and The write data strobe signal transmission circuit is configured to transmit the write data strobe signal to the data sampler.

6. The storage system as claimed in claim 5, wherein, The storage device also includes: A write data strobe oscillator is configured to match the write data strobe signal transmission circuit; and The counter is configured to calculate a first oscillator count value by counting a first number of oscillations of the write data strobe oscillator at a first temperature, and to calculate a second oscillator count value by counting a second number of oscillations of the write data strobe oscillator at a second temperature.

7. The storage system of claim 6, wherein, The write data strobe oscillator and the counter are configured to operate in response to a write data strobe oscillator enable command provided from the storage controller at each of the first and second temperatures.

8. The storage system as claimed in claim 5, wherein, The storage device also includes: A temperature compensator is configured to generate a delay code based on the sensed temperature and weights. The write data strobe signal transmission circuit is configured to transmit the write data strobe signal to the data sampler based on a delay corresponding to the delay code.

9. The storage system of claim 8, wherein, The storage device also includes: A reference voltage generator is configured to generate a reference voltage from the supply voltage based on a delay code; and The voltage regulator is configured to generate a regulated voltage based on a reference voltage, and The write data strobe signal transmission circuit is configured to transmit the write data strobe signal to the data sampler by using the adjusted voltage.

10. The storage system of claim 8, wherein, The write data strobe signal transmission circuit includes a plurality of transistors configured to operate in an on or off state according to a delay code.

11. The storage system of claim 1, wherein, The storage controller is configured to determine weights during the initialization of the storage device or during testing of the storage device.

12. A method of operating a storage system, the storage system comprising a storage controller and a storage device, the storage device being configured to sample a data signal provided by the storage controller based on a write data strobe signal provided by the storage controller, the method comprising: The storage controller requests the first oscillator count value of the write data strobe signal at the first temperature from the storage device; The storage device sends the first oscillator count value to the storage controller; The storage controller requests the second oscillator count value of the write data strobe signal at the second temperature from the storage device; The storage device sends the second oscillator count value to the storage controller. The storage controller sets the weights determined based on the first oscillator count value and the second oscillator count value to the storage device during the initialization process or during the testing process of the storage device; as well as The storage device samples the data signal by adjusting the delay on the transmission path of the write data strobe signal based on the temperature and weight sensed by the storage device.

13. The operating method as described in claim 12, wherein, The weight represents the amount of delay in the write data strobe signal based on the temperature sensed by the storage device, and The temperature sensed is in real time.

14. The operating method as described in claim 12, further comprising: Before requesting the first oscillator count value, the storage controller sends a first write data strobe signal oscillator enable command to the storage device at the first temperature; The storage device counts the number of oscillations of the write data strobe signal in response to a first write data strobe signal oscillator enable command; Before requesting the second oscillator count value, the storage controller sends a second write data strobe signal oscillator enable command to the storage device at the second temperature; as well as The storage device counts the number of oscillations of the write data strobe signal in response to the second write data strobe signal oscillator enable command.

15. The operating method as described in claim 12, wherein, Setting weights to the storage device by the storage controller includes sending a mode register setting command to the storage device.

16. The operating method as described in claim 12, wherein, The process of setting weights to the storage device by the storage controller also includes sending a test mode register setting command to the storage device.

17. The operating method as described in claim 12, wherein, The sampling of data signals by the storage device includes: Delay codes are generated based on the sensed temperature and weights; and The delay on the transmission path of the write data strobe signal is adjusted according to the delay code.

18. A storage device, comprising: The data sampler is configured to sample the data signal based on the write data strobe signal; The storage circuit is configured to store weights, the weights representing the amount by which the delay on the transmission path of the write data strobe changes with temperature. A temperature sensor, configured to sense temperature; A temperature compensator is configured to generate a delay code based on the sensed temperature and weights. A reference voltage generator is configured to generate a reference voltage from the supply voltage based on a delay code. The voltage regulator is configured to generate a regulated voltage based on a reference voltage; as well as The write data strobe signal transmission circuit is configured to transmit the write data strobe signal to the data sampler by using an regulated voltage.

19. The storage device of claim 18, further comprising: The first pin is configured to receive data signals; as well as The second pin is configured to receive a write data strobe signal, and Specifically, the data signal path corresponding to the first path from the first pin to the data sampler and the transmission path of the write data strobe signal corresponding to the second path from the second pin to the data sampler do not match.

20. The storage device of claim 18, wherein, The write data strobe signal transmission circuit includes: The write data strobe frequency divider is configured to generate an internal write data strobe signal by dividing the write data strobe signal; and The write data strobe signal tree circuit is configured to transmit the internal write data strobe signal to the data sampler by using an regulated voltage.

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