Semiconductor memory device, method of testing semiconductor memory device, and test system

Abstract

A semiconductor memory device included in each of a plurality of chips divided by scribe lanes and formed on an upper surface of a wafer includes a memory core and a built-in self-test (BIST) circuit. The memory core includes an array of memory cells storing data and a data input / output circuit connected to a data input / output pad. The BIST circuit is connected to a test pad separate from the data input / output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer-level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data through the data input / output circuit to the array of memory cells.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Korean Patent Application No. 10-2020-0115129, filed on September 9, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This disclosure generally relates to semiconductor integrated circuits, and more specifically to semiconductor memory devices, methods for testing semiconductor memory devices, and test systems.

[0004] Semiconductor memory devices used for storing data can be broadly classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. In volatile semiconductor memory devices, such as dynamic random access memory (DRAM), data is stored by charging or discharging cell capacitors, and the stored data is retained when powered. However, the stored data is lost when power is off. In contrast, non-volatile memory devices retain the stored data even when power is off.

[0005] In the manufacturing process of semiconductor memory devices, wafer-level processes, package-level processes, and post-package-level processes can be performed. Wafer-level processes correspond to the processes that produce wafers containing semiconductor memory devices. Built-in Self-Test (BIST) can be performed during wafer-level processes to test the semiconductor memory devices. However, when BIST is performed by directly connecting external Automated Test Equipment (ATE) to the data input / output pads of the semiconductor memory device, the execution speed and application scope of BIST may be limited due to the load effect generated by BIST. Summary of the Invention

[0006] Embodiments of the present invention can provide semiconductor memory devices capable of efficiently performing built-in self-test (BIST) during wafer-level processing of semiconductor memory devices, methods for testing semiconductor memory devices, and test systems.

[0007] Embodiments of this invention provide a semiconductor memory device including a memory core and a BIST circuit. The memory core includes an array of memory cells for storing data and data input / output circuitry connected to data input / output pads. The BIST circuitry is connected to test pads separately from the data input / output pads. The BIST circuitry generates test pattern data, including first parallel bits, based on commands and addresses received from an external automated test equipment (ATE) during a wafer-level testing process performed on the semiconductor memory device. The BIST circuitry tests the memory core by applying the test pattern data to the memory cell array via the data input / output circuitry. The semiconductor memory device is disposed on a chip among multiple chips located on the surface of a wafer and separated from each other by scribe lines.

[0008] Embodiments of the present invention also provide a method for testing a semiconductor memory device, the method comprising: receiving commands and addresses from an external source via test pads separate from data input / output pads connected to data input / output circuitry of the semiconductor memory device; generating test pattern data including parallel bits based on the commands and addresses; and testing the memory core by applying the test pattern data to a memory cell array of the memory core of the semiconductor memory device via data input / output circuitry. The semiconductor memory device is comprised in each of a plurality of chips located on the surface of a wafer and separated from each other by scribe lines.

[0009] Embodiments of the present invention also provide a test system comprising an ATE (Automatic Test Equipment) and a semiconductor memory device. The ATE generates commands and addresses in a first test mode of wafer-level testing, which is performed on the semiconductor memory device, which is included in a chip among a plurality of chips located on the upper surface of a wafer. The ATE generates commands, addresses, and external test mode data in a second test mode of wafer-level testing. The semiconductor memory device includes a memory core and a BIST (Best-In-Size) circuit. The memory core includes a memory cell array for storing data and data input / output circuitry connected to data input / output pads. The BIST circuitry is connected to test pads separate from the data input / output pads. In the first test mode, the BIST circuitry generates test mode data including first parallel bits in response to commands and addresses from the ATE. In the second test mode, the BIST circuitry receives commands, addresses, and external test mode data and tests the memory core by applying one of the test mode data and the external test mode data to the memory cell array via the data input / output circuitry.

[0010] Embodiments of the present invention also provide a method for manufacturing a semiconductor memory device, the method comprising: forming a semiconductor memory device in each of a plurality of chips located on the upper surface of a wafer and separated from each other by scribe lines; and testing the semiconductor memory device. The testing includes: receiving commands and addresses from outside the semiconductor memory device via test pads separate from data input / output pads connected to data input / output circuitry of the semiconductor memory device; generating test pattern data including parallel bits based on the commands and addresses; and testing the memory core of the semiconductor memory device by applying the test pattern data to a memory cell array of the memory core via data input / output circuitry.

[0011] The semiconductor memory devices, methods for testing semiconductor memory devices, and test systems of embodiments of the present invention perform wafer-level testing via test pads that are separate from the data input / output pads connected to the data input / output circuitry. As a result, wafer-level testing can be performed at high speed because the load effects generated by the automated test equipment do not affect input buffers and output drivers that can be targets of wafer-level testing. Furthermore, the semiconductor memory devices and test systems include serializers / deserializers (SERDES) connected to the test pads. SERDES performs serialization-parallelization of data input / output via the test pads, thereby enabling wafer-level testing to be performed using a single test pad. Attached Figure Description

[0012] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description of the embodiments in conjunction with the accompanying drawings.

[0013] Figure 1 A block diagram of a test system according to an embodiment of the present invention is shown.

[0014] Figure 2 It shows Figure 1 A plan view of the wafer and test structure.

[0015] Figure 3 It shows that it includes Figure 2 A block diagram of a semiconductor memory device in one of a plurality of chips.

[0016] Figure 4 Semiconductor memory devices included in a portion of multiple chips are shown. Figure 2 A block diagram showing the connection relationships between common chip pads.

[0017] Figure 5 An embodiment of the invention is shown. Figure 3 A block diagram of a semiconductor memory device.

[0018] Figure 6An embodiment of the invention is shown. Figure 3 and Figure 5 A block diagram of a semiconductor memory device.

[0019] Figure 7 It shows the description of input to Figure 6 A diagram showing the commands and addresses of the sampling circuit in the diagram.

[0020] Figure 8 An embodiment of the invention is shown. Figure 3 and Figure 6 A block diagram of a semiconductor memory device.

[0021] Figure 9 It shows Figure 8 The block diagram of the serializer is shown.

[0022] Figure 10 It shows Figure 9 The timing diagram for the operation of the serializer is shown.

[0023] Figure 11 The description is shown through Figure 8 The diagram shows the data rate of the serializer or parallelizer.

[0024] Figure 12A and Figure 12B The test was shown Figure 8 An example of a method for a semiconductor memory device is shown.

[0025] Figure 13 An embodiment of the invention is shown. Figure 3 and Figure 5 A block diagram of a semiconductor memory device.

[0026] Figure 14A and Figure 14B The test was shown Figure 13 An example of a method for a semiconductor memory device is shown.

[0027] Figure 15 A diagram illustrating an example of the connection relationship between a built-in self-test (BIST) circuit and test pads in a semiconductor memory device, according to an embodiment of the present invention.

[0028] Figure 16 A flowchart illustrating a method for testing semiconductor memory devices according to an embodiment of the present invention is shown.

[0029] Figure 17 It shows Figure 16 The flowchart shows an example of testing the memory core.

[0030] Figure 18A diagram of a test system according to an embodiment of the present invention is shown. Detailed Implementation

[0031] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings. In the drawings, similar reference numerals always denote similar elements. Repeated descriptions may be omitted.

[0032] As is common in the field of inventive conception, embodiments can be described and illustrated based on blocks that perform one or more described functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may optionally be driven by firmware and / or software. For example, the circuitry may be specifically implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Without departing from the scope of the inventive conception, each block of an embodiment may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of the inventive conception, the blocks of an embodiment may be physically combined into more complex blocks.

[0033] Figure 1 A block diagram of a test system according to an embodiment of the present invention is shown. Figure 2 It shows Figure 1 A plan view of the wafer and test structure.

[0034] Reference Figure 1 and Figure 2 The test system 100 includes an automated test equipment (ATE) 110, a wafer 150, a test structure 190 formed on the wafer 150, probes 151, and common chip pads 157. The test structure 190 includes a plurality of chips 300, and the plurality of chips 300 include semiconductor memory devices.

[0035] The ATE 110 performs various tests on semiconductor memory devices during wafer-level processing or between wafer-level and package-level processing, hereinafter referred to as "wafer-level testing".

[0036] In some embodiments, the tests performed by the ATE 110 may include DC testing, AC testing, and functional testing. DC testing, for example, tests the DC characteristics of a semiconductor memory device by applying a DC voltage to the semiconductor memory device. DC characteristics may include whether the semiconductor memory device is open-circuited or short-circuited, and the magnitude of input / output current and voltage. AC testing, for example, tests the AC characteristics of a semiconductor memory device by applying an AC voltage to the semiconductor memory device. AC characteristics may include the input / output start time, end time, and delay time of the semiconductor memory device. Functional testing, for example, tests the functional characteristics of a semiconductor memory device by applying test mode data, etc. Functional characteristics may include the write and read performance of the semiconductor memory device, and the data transfer performance of the paths formed during the test of write and read performance.

[0037] In some embodiments, ATE 110 can generate commands and addresses to perform DC tests, AC tests, and functional tests. Additionally, ATE 110 can generate test mode data to perform DC tests and AC tests.

[0038] In some embodiments, ATE 110 can provide command, address, and test mode data to the semiconductor memory device via probe 151 and common chip pad 157.

[0039] However, unlike in DC and AC testing, ATE 110 does not generate test mode data during the functional testing process. In some embodiments, the test mode data required during the functional testing process may be generated by a built-in self-test (BIST) circuitry included in the semiconductor memory device instead of ATE 110, as will be referred to later. Figure 3 As described. Therefore, functional testing can be distinguished from DC testing and AC testing. The operating mode used to perform functional testing can be called the first test mode, and the operating modes used to perform DC testing and AC testing can be called the second test mode.

[0040] ATE 110 can perform tests on multiple test items in each of a plurality of test modes, including a first test mode and a second test mode. In some embodiments, a portion of the plurality of tests may be performed by [the system described later]. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 8 or Figure 13 The described BIST circuit is used to perform this.

[0041] As a result of the tests performed by ATE 110, it is determined whether the semiconductor memory device is defective. Based on the determination results, all or a portion of multiple chips 300, including the semiconductor memory device, are selected. The selected chips 300 are scribed by scribe lines SL and can be manufactured as individual unit chips or packages using packaging-level processes.

[0042] Figure 2 The image shows a total of twelve chips 300, but the number of chips 300 is merely exemplary. In various embodiments, the wafer may include any number of chips 300. See later... Figure 5 This describes a portion of the 300 chips (400).

[0043] Figure 3 It shows that it includes Figure 2 A block diagram of a semiconductor memory device in one of a plurality of chips.

[0044] exist Figure 3 In this embodiment, the semiconductor memory device is shown as a non-volatile memory device. However, this is merely exemplary, and in other embodiments, the semiconductor memory device may be a volatile memory device.

[0045] Reference Figures 1 to 3 The semiconductor memory device 500 includes a control circuit (CC) 510, a voltage generator (VG) 530, a line decoder (RD) 550, a built-in self-test (BIST) circuit (BC) 570, test pads 560, data input / output pads 580, and a memory core 590. The memory core 590 includes a memory cell array (MCA) 591, a page buffer circuit (PBC) 593, and a data input / output circuit (DIOC) 595.

[0046] The memory cell array 591 is coupled to the row decoder 550 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. The memory cell array 591 is also coupled to the page buffer circuit 593 via multiple bit lines BL. In some embodiments, more than one serial select line and / or more than one ground select line GSL may be included.

[0047] In some embodiments, the memory cell array 591 may include a plurality of memory blocks, and each memory block may include a plurality of non-volatile memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL.

[0048] In some embodiments, the memory cell array 591 may be a two-dimensional memory cell array formed on a substrate as a two-dimensional structure (or horizontal structure). For example, the memory cell array 591 may include a string select transistor, a ground select transistor, and memory cells. The string select transistor may be coupled to a bit line, and the ground select transistor may be coupled to a common source line. Memory cells in the same string may be arranged in series between a corresponding bit line and the common source line. Memory cells in the same row may be coupled to a corresponding word line. Therefore, memory cells may be coupled in series between the string select transistor and the ground select transistor, and, for example, 16, 32, or 64 word lines may be provided between the string select line SSL and the ground select line GSL. The string select transistor may be coupled to the string select line SSL and may be controlled according to the voltage level applied to the string select line SSL. The ground select transistor may be coupled to the ground select line GSL and may be controlled according to the voltage level applied to the ground select line GSL. Memory cells may be controlled according to the voltage level applied to the word line WL. The first non-volatile memory, including the storage cell array 591, can perform write (or program) and read operations on a page basis, and can perform erase operations on a block basis.

[0049] In other example embodiments, the memory cell array 591 may be a three-dimensional memory cell array formed on a substrate as a three-dimensional structure (or vertical structure). The following patent documents (incorporated herein by reference in their entirety) describe suitable memory cell array constructions including a 3D vertical array structure, wherein the 3D memory array is configured as multiple levels and shares word lines and / or bit lines between levels: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0050] Although the example of semiconductor memory device 500 according to the exemplary embodiment is described based on NAND flash memory, semiconductor memory device 500 can be any non-volatile memory device, such as phase random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), and various other types of non-volatile memory.

[0051] BIST circuit 570 performs a portion of the functions executed by control circuit 510 during wafer-level testing after the semiconductor memory device 500 has been executed at the wafer-level, package-level, and post-package-level processes and after the semiconductor memory device has been installed in the electronic device.

[0052] More specifically, the BIST circuit 570 from Figure 1 The ATE shown receives the command CMD, address ADDR, and test mode data, and provides the command CMD and address ADDR to the control circuit 510. (Refer to the above...) Figure 1 and Figure 2 The ATE 110 can perform DC tests, AC tests, and functional tests, and can also generate test mode data during the execution of DC and AC tests.

[0053] Specifically, during DC and AC testing, the BIST circuit 570 receives command CMD, address ADDR, and test mode data from ATE 110, provides command CMD and address ADDR to the control circuit 510, and provides test mode data to the data input / output circuit 595. During functional testing, the BIST circuit 570 receives command CMD and address ADDR from ATE 110, generates test mode data internally, provides command CMD and address ADDR to the control circuit 510, and provides test mode data to the data input / output circuit 595.

[0054] BIST circuit 570 is connected to test pad 560. BIST circuit 570 receives command CMD, address ADDR and test mode data through test pad 560, which is separate from data input / output pad 580.

[0055] The control circuit 510 receives the command CMD and address ADDR from the BIST circuit 570, and controls the row decoder 550, page buffer circuit 593, data input / output circuit 595 and voltage generator 530 based on the command CMD and address ADDR to perform write (or program), read and erase operations for the memory cell array 591.

[0056] In some embodiments, control circuitry 510 may provide row address RADDR to row decoder 550 and column address CADDR to data input / output circuitry 595. Row decoder 550 may be connected to memory cell array 591 via serial select line, multiple word lines, and ground select line. Based on row address RADDR, row decoder 550 may determine at least one of the multiple word lines as the selected word line and the remaining word lines as the unselected word lines.

[0057] Voltage generator 530 can generate word line voltages required for the operation of semiconductor memory device 500 based on control signal CON. The word line voltage VWL can be applied to multiple word lines via row decoder 550. For example, during an erase operation, voltage generator 530 can provide erase voltages to be applied to the well or common source line of the memory block, and can provide ground voltages to be applied to all word lines of the memory block. During an erase verification operation, voltage generator 530 can provide erase verification voltages to be applied to all word lines of the memory block, or can provide erase verification voltages to be applied sequentially to the word lines of the memory block on a word-line-by-word basis. During a programming operation (or write operation), voltage generator 530 can provide programming voltages to be applied to selected word lines, and can provide programming pass voltages to be applied to unselected word lines. During a programming verification operation, voltage generator 530 can provide programming verification voltages to be applied to selected word lines, and can provide verification pass voltages to be applied to unselected word lines. During a read operation, voltage generator 530 can provide a read voltage to be applied to the selected word line and can provide a read pass voltage to be applied to the unselected word line.

[0058] Page buffer circuitry 593 can be connected to memory cell array 591 via multiple bit lines BL. Page buffer circuitry 593 may include multiple page buffers. In some example embodiments, each page buffer may be connected to one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines. Page buffer circuitry 593 can store data to be programmed into memory cell array 591 or can read data sensed from memory cell array 591. In other words, page buffer circuitry 593 can operate as a write driver or a sense amplifier depending on the operating mode of semiconductor memory device 500.

[0059] Data I / O circuit 595 can be connected to page buffer circuit 593 via data line DL. Data I / O circuit 595 can provide data from outside semiconductor memory device 500 to memory cell array 591 via page buffer circuit 593 based on column address CADDR, or it can provide data from memory cell array 591 to outside semiconductor memory device 500.

[0060] Figure 4 Semiconductor memory devices included in a portion of multiple chips are shown. Figure 2 A block diagram showing the connection relationships between common chip pads.

[0061] exist Figure 4The diagram shows a portion 400a of multiple chips. This portion 400a may include four chips, a probe 151a, and a common chip pad 157a. The first of the four chips includes a memory core (MC1) 590-1, a built-in self-test (BIST) circuit (BC1) 570-1, a test pad 560-1, and a data input / output pad 580-1. The second of the four chips includes a memory core (MC2) 590-2, a BIST circuit (BC2) 570-2, a test pad 560-2, and a data input / output pad 580-2. The third of the four chips includes a memory core (MC3) 590-3, a BIST circuit (BC3) 570-3, a test pad 560-3, and a data input / output pad 580-3. The fourth of the four chips includes a memory core (MC4) 590-4, a BIST circuit (BC4) 570-4, a test pad 560-4, and a data input / output pad 580-4. Each of the first through fourth chips may include, for example, a reference... Figure 3 The described additional circuit (not shown).

[0062] As shown above (refer to the reference) Figures 1 to 3 The BIST circuits 570-1, 570-2, 570-3, and 570-4 can be derived from... Figure 1 The ATE 110 shown receives command CMD, address ADDR, and test mode data. Each of the BIST circuits 570-1, 570-2, 570-3, and 570-4 can be connected to probe 151a and common chip pad 157a formed in the scribe line SL to receive command CMD, address ADDR, and test mode data.

[0063] at the same time, Figure 4 Each of the memory cores 590-1, 590-2, 590-3, and 590-4 shown is connected to one of the data input / output pads 580-1, 580-2, 580-3, and 580-4. However, the data input / output pads 580-1, 580-2, 580-3, and 580-4 are not used during wafer-level testing and may only be used to provide / receive commands, addresses, and data to / from an external memory controller during the installation and use of semiconductor memory devices in electronic devices.

[0064] exist Figure 4 In the figure, a portion 400a of multiple chips includes four chips, a probe 151a and a common chip pad 157a, but the number of chips, probe 151a and common chip pad 157a is merely exemplary.

[0065] Figure 5illustrates an embodiment according to the inventive concept of Figure 3 semiconductor memory device is a block diagram.

[0066] In Figure 5 , for convenience of description, the semiconductor memory device is shown as including only Figure 3 the memory cell array 591, the page buffer circuit 593, the data input / output circuit 595, the built-in self-test (BIST) circuit 570, the test pad 560, and the data input / output pad 580 among the components included in the illustrated semiconductor memory device 500. Components having the same reference numerals as the components included in the semiconductor memory device 500 shown in Figure 3 perform the same or similar functions, and thus repeated description may be omitted hereinafter.

[0067] Referring to Figures 1 to 5 , the semiconductor memory device according to the example embodiment includes a separate test pad 560 for performing a wafer level test. The test pad 560 is connected to the BIST circuit 570 included in the semiconductor memory device, and is used to mediate data input / output between the ATE 110 and the BIST circuit 570.

[0068] When performing a wafer level test, not only the memory cell array 591 but also components included in the data input / output circuit 595 can be included as targets of the wafer level test. For example, the input buffer 5115 and the output driver 5111 included in the data input / output circuit 595 can be included as targets of the wafer level test.

[0069] According to the example embodiment, since the semiconductor memory device is connected to the ATE 110 through the test pad 560 instead of the data input / output pad 580, the load effect generated by the ATE 110 does not affect the input buffer 5115 and the output driver 5111 that can be targets of the wafer level test.

[0070] When performing a wafer level test, a functional test is performed based on the test mode data TP generated by the BIST circuit 570. When the test mode data TP passes through various components included in the data input / output circuit 595, the data rate exceeds a maximum value of 1000 Mbps. Therefore, when the semiconductor memory device is formed in a structure that transmits data to and receives data from the ATE 110 through the separately provided test pad 560 as described above, the input buffer 5115 and the output driver 5111 can be included as targets of the functional test. Hereinafter, various examples of the semiconductor memory device according to example embodiments will be described.

[0071] Figure 6 illustrates an embodiment according to the inventive concept of Figure 3 and Figure 5 A block diagram of a semiconductor memory device.

[0072] exist Figure 6 In, with Figure 5 The components included in the semiconductor memory devices shown have the same reference numerals and perform the same or similar functions, and therefore repeated descriptions may be omitted below.

[0073] Reference Figure 6 The semiconductor memory device includes a memory cell array 591, a BIST circuit 570a, an input buffer 5115, an output driver 5111, a test pad 560, and a data input / output pad 580. The BIST circuit 570a includes a sampling circuit (CASC) 5010, a clock generator (CG) 5030a, a pattern generator (PG) 5050a, a comparator circuit (CP) 5070, and a determination logic (DL) 5090.

[0074] Figure 6 The semiconductor memory device shown can perform functional tests in wafer-level testing. (Refer to the above...) Figure 5 As described above, test pad 560 is connected to ATE 110, but data input / output pad 580 is not connected and does not perform specific functions when performing functional tests.

[0075] Reference Figure 1 , Figure 5 and Figure 6 The sampling circuit 5010 receives the command CMD and address ADDR from the ATE 110, and generates control signals PCTL and CCTL by sampling at least one of the command CMD and address ADDR. The command CMD and address ADDR will be described in more detail.

[0076] Figure 7 It shows the description of input to Figure 6 A diagram showing the commands and addresses of the sampling circuit in the diagram.

[0077] Reference Figure 7 Each of the command CMD and address ADDR can include serial bits received through the test pad. For example, the command CMD can include a first command CMD1, a second command CMD2, and a third command CMD3, and the address ADDR can include a first address ADDR1, a second address ADDR2, and a third address ADDR3.

[0078] In one embodiment, the command CMD may include a write command, a read command, and an erase command. However, in other embodiments, the command CMD may also include, for example, a chip enable signal, a command latch enable signal, an address latch enable signal, a write enable signal, a read enable signal, a data strobe signal, a data signal, and a ready / busy signal.

[0079] In some embodiments, the control signal PCTL can be a signal that controls the mode generator 5050a, and the control signal CCTL can be a signal that controls the clock generator 5030a.

[0080] Clock generator 5030a receives control signal CCTL from sampling circuit 5010 and generates multiple clock signals CLK1, CLK2, CLK4 and CLK8 with different frequencies relative to each other based on control signal CCTL.

[0081] In some embodiments, clock generator 5030a may provide one of a plurality of clock signals CLK1, CLK2, CLK4 and CLK8, namely CLK1, to pattern generator 5050a, comparator circuit 5070 and determination logic 5090.

[0082] Pattern generator 5050a generates test pattern data TP in response to command CMD and address ADDR. In some embodiments, pattern generator 5050a may receive control signal PCTL from sampling circuit 5010 and clock signal CLK1 from clock generator 5030a, and may generate test pattern data TP based on control signal PCTL and clock signal CLK1. Test pattern data TP may include parallel bits. Test pattern data TP can be transmitted via data input / output circuitry (e.g., ...). Figure 5 The 595) is applied to the memory cell array 591 and can be used to test the memory core including the memory cell array 591. After the test mode data TP is written to the memory cell array 591, the data read from the memory cell array 591 can be called the test result data TR.

[0083] The comparator circuit 5070 compares the test result data TR output from the memory cell array 591 in response to the test mode data TP with the test mode data TP to generate a comparison signal CR.

[0084] The determination logic 5090 determines whether the test on the memory core passes or fails based on the comparison signal CR. In an embodiment, the determination logic 5090 may be a circuit including, for example, logic gates.

[0085] exist Figure 6The diagram illustrates multiple paths 5201 and 5203. Path 5201 represents the path where test pattern data TP is generated from the pattern generator 5050a and written to the memory cell array 591. Path 5203 represents the path where test result data TR is read from the memory cell array 591 and sent to the comparator circuit 5070. In some embodiments, the output driver 5111 and the input buffer 5115 may be included on path 5203.

[0086] Figure 8 An embodiment of the invention is shown. Figure 3 and Figure 6 A block diagram of a semiconductor memory device.

[0087] exist Figure 8 In, with Figure 3 and Figure 6 The components included in the semiconductor memory devices shown have the same reference numerals and perform the same or similar functions, and therefore repeated descriptions will be omitted below.

[0088] Reference Figure 8 The semiconductor memory device includes a memory cell array 591, a BIST circuit 570b, a multiplexer 5151, a serializer 5131, an output driver 5111, an input buffer 5115, a parallelizer 5135, a test pad 560, and a data input / output pad 580.

[0089] The BIST circuit 570b includes a sampling circuit 5010, a clock generator 5030b, a pattern generator 5050a, a comparator circuit 5070, a determination logic 5090, and a parallelizer 5100b.

[0090] Figure 8 The semiconductor memory device shown can perform functional tests in wafer-level testing. (See reference above.) Figure 6 As described above, test pad 560 is connected to ATE 110, but data input / output pad 580 is not connected and does not perform specific functions when performing functional tests.

[0091] Reference Figure 1 , Figure 6 and Figure 8 The sampling circuit 5010 receives the command CMD and address ADDR from the ATE 110, and generates control signals PCTL and CCTL by sampling at least one of the command CMD and address ADDR. The sampling circuit 5010 provides the command CMD and address ADDR to the parallel processor 5100b.

[0092] Parallelizer 5100b receives command CMD and address ADDR, and receives multiple clock signals CLK2, CLK4, and CLK8 from clock generator 5030b. Parallelizer 5100b parallelizes (i.e., deserializes) command CMD and address ADDR based on the multiple clock signals CLK2, CLK4, and CLK8 to provide command CMD and address ADDR to control circuit 510 in parallel. The detailed configuration and operation of parallelizer 5100b will be described later.

[0093] Clock generator 5030b receives a control signal CCTL from sampling circuit 5010 and generates multiple clock signals CLK1, CLK2, CLK4, and CLK8 with different frequencies relative to each other based on the control signal CCTL. In some embodiments, clock generator 5030b may provide one of the multiple clock signals CLK1, CLK2, CLK4, and CLK8, CLK1, to pattern generator 5050a, comparator circuit 5070, and determination logic 5090. Clock generator 5030b may provide clock signals CLK2, CLK4, and CLK8 from the multiple clock signals CLK1, CLK2, CLK4, and CLK8 to parallelizer 5100b included in BIST circuit 570b and serializer 5131 and parallelizer 5135 included in data input / output circuit. That is, some of the multiple clock signals CLK1, CLK2, CLK4, and CLK8 may be provided to parallelizer 5100b, serializer 5131, and parallelizer 5135.

[0094] The pattern generator 5050a generates test pattern data TP in response to the command CMD and the address ADDR. In some embodiments, the pattern generator 5050a may receive a control signal PCTL from the sampling circuit 5010 and a clock signal CLK1 from the clock generator 5030b, and generate the test pattern data TP based on the control signal PCTL and the clock signal CLK1. The test pattern data TP may include parallel bits.

[0095] The comparator circuit 5070 compares the test result data TR output from the memory cell array 591 in response to the test mode data TP with the test mode data TP to generate a comparison signal CR.

[0096] The Logic 5090 determines whether the test on the memory core passes or fails based on the comparison signal CR.

[0097] exist Figure 8 In the middle, the multiplexer 5151, the serializer 5131, and the parallelizer 5135 are located in the same position as... Figure 7 The paths corresponding to paths 5201 and 5203 are shown.

[0098] The multiplexer 5151 responds to the first selection signal sel1 to select one of the test mode data TP and the test result data TR. It can be selected from... Figure 3 The control circuit 510 shown provides a selection signal sel1 as a command.

[0099] Serializer 5131 receives one of test mode data TP and test result data TR from multiplexer 5151, and multiple clock signals CLK2, CLK4, and CLK8 from BIST circuit 570b. Serializer 5131 serializes one of the first parallel bits PA in the test mode data TP and test result data TR based on the multiple clock signals CLK2, CLK4, and CLK8 to output a first serial bit SA with a first data rate.

[0100] Parallelizer 5135 receives a first serial bit SA from serializer 5131 via output driver 5111 and input buffer 5115, and receives multiple clock signals CLK2, CLK4, and CLK8 from BIST circuit 570b. Parallelizer 5135 parallelizes the first serial bit SA based on the multiple clock signals CLK2, CLK4, and CLK8 to output a second parallel bit PB with a second data rate. Serializer 5131 will be described in more detail below.

[0101] Figure 9 It shows Figure 8 The block diagram of the serializer is shown. Figure 10 It shows Figure 8 The timing diagram for the operation of the serializer.

[0102] Reference Figure 9 and Figure 10 The serializer 5131 includes multiple stages (STG11, STG12, and STG13) 5131-1, 5131-2, and 5131-3. The multiple stages 5131-1, 5131-2, and 5131-3 operate based on multiple clock signals CLK2, CLK4, and CLK8, respectively. In some embodiments, the frequency of clock signal CLK2 can be twice the frequency of clock signal CLK1, the frequency of clock signal CLK4 can be twice the frequency of clock signal CLK2, and the frequency of clock signal CLK8 can be twice the frequency of clock signal CLK4.

[0103] The first stage 5131-1 receives parallel bits PA10, PA11, PA12, ..., PA17 and combines them based on the clock signal CLK2 to generate the first intermediate parallel bits PA20, PA21, PA22 and PA23.

[0104] The second stage 5131-2 receives the first intermediate parallel bits PA20, PA21, PA22 and PA23, and combines the first intermediate parallel bits PA20, PA21, PA22 and PA23 based on the clock signal CLK4 to generate the second intermediate parallel bits PA30 and PA31.

[0105] The third stage 5131-3 receives the second intermediate parallel bits PA30 and PA31, and combines them based on the clock signal CLK8 to generate the serial bit SA. Therefore, the serializer 5131 sequentially combines parallel bits PA10, PA11, PA12, ..., PA17, and can ultimately output the serial bit SA synchronized with the clock signal CLK8, which has a frequency eight times that of the clock signal CLK1. For example, the first set of parallel bits PA10, PA11, PA12, PA13, PA14, PA15, PA16, and PA17 received at the first stage 5131-1 are provided from the third stage 5131-3 as the final output serial bits 0, 1, 0, 1, 1, 0, 1, and 0.

[0106] Reference Figure 8 , Figure 9 and Figure 10 Multiple stages 5131-1, 5131-2, and 5131-3 can receive multiple clock signals CLK2, CLK4, and CLK8, and sequentially serialize the parallel bits PA according to the method described above to output the serial bits SA. In some embodiments, the parallel bits PA can be one of the test mode data TP and the test result data TR. Figure 9 The parallel bits PA10, PA11, PA12, PA13, PA14, PA15, PA16 and PA17 described herein can be examples of parallel bits PA.

[0107] Figure 8 The parallel processors 5100b and 5135 shown perform the same operation as referenced above. Figure 9 The serializer 5131 described has the opposite function. The parallelizers 5100b and 5135 also include multiple stages, similar to the serializer 5131, and operate based on multiple clock signals. Since the configuration and operation of the parallelizers 5100b and 5135 are similar to those of the serializer 5131, detailed descriptions will be omitted.

[0108] Figure 11 The description is shown through Figure 8 The diagram shows the data rate of the serializer or parallelizer.

[0109] exist Figure 11 In, it is shown Figure 8The data rate of the serial bits PA10, PA11, PA12, ..., PA17 received by the serializer 5131, the first intermediate parallel bits PA20, PA21, PA22 and PA23, the second intermediate parallel bits PA30 and PA31, and the serial bits SA generated by the serializer 5131.

[0110] As shown above (refer to the reference) Figure 6 When the semiconductor memory device according to the example embodiment is subjected to wafer-level testing, in the case of functional testing, the data rate of the data through the various components included in the data input / output circuit 595 exceeds a maximum value of 1000 Mbps.

[0111] Reference Figure 11 The data rate of parallel bits PA10, PA11, PA12, ..., PA17 can be 150 Mbps, the data rate of the first intermediate parallel bits PA20, PA21, PA22, and PA23 can be 300 Mbps, the data rate of the second intermediate parallel bits PA30 and PA31 can be 600 Mbps, and the data rate of serial bit SA can be 1200 Mbps. However, each data rate is merely exemplary, and the scope of the example embodiments is not limited thereto.

[0112] Figure 12A and Figure 12B Tests illustrating embodiments of the present invention are shown. Figure 8 Examples of methods for semiconductor memory devices.

[0113] exist Figure 12A In this configuration, the memory cell array 591 includes a plurality of memory blocks MB1, MB2, MB3, and MB4. In some embodiments, each of the plurality of memory blocks MB1, MB2, MB3, and MB4 may include at least one cell string comprising a plurality of memory cells sequentially stacked on a substrate. This can be determined according to... Figure 12A The test method shown performs functional tests in wafer-level testing for semiconductor memory devices. The number of memory blocks MB1, MB2, MB3, and MB4 included in the memory cell array 591 is merely exemplary.

[0114] Reference Figure 12A As time goes by, functional tests can be performed sequentially for each of the first storage block MB1, the second storage block MB2, the third storage block MB3, and the fourth storage block MB4.

[0115] When performing functional tests on the first storage block MB1, the pattern generator 5050a can generate first test pattern data (e.g., Figure 8The first test mode data can be provided to the first memory block MB1 through the output driver 5111 and the input buffer 5115, and the first test result data generated from the first memory block MB1 (e.g., ...) Figure 8 The TR in the output buffer (MB2) can be provided to the comparator circuit 5070. When performing a functional test on the second memory block MB2, the pattern generator 5050a can generate second test pattern data, which can be provided to the second memory block MB2 through the output driver 5111 and the input buffer 5115. The second test result data generated from the second memory block MB2 can be provided to the comparator circuit 5070. When performing a functional test on the third memory block MB3, the pattern generator 5050a can generate third test pattern data, which can be provided to the third memory block MB3 through the output driver 5111 and the input buffer 5115. The third test result data generated from the third memory block MB3 can be provided to the comparator circuit 5070. When performing a functional test on the fourth memory block MB4, the pattern generator 5050a can generate fourth test pattern data, which can be provided to the fourth memory block MB4 through the output driver 5111 and the input buffer 5115. The fourth test result data generated from the fourth memory block MB4 can be provided to the comparator circuit 5070.

[0116] In some embodiments, when performing functional tests on each of the first to fourth storage blocks MB1, MB2, MB3, and MB4, Figure 8 The multiplexer shown can select one of the first test mode data, the second test mode data, the third test mode data, and the fourth test mode data based on the selection signal sel1 (for example, the selection signal sel1 is "0").

[0117] In this embodiment, each of the first test mode data, the second test mode data, the third test mode data, and the fourth test mode data may be the same. However, the scope of this example embodiment is not limited thereto. In other embodiments, each of the first test mode data, the second test mode data, the third test mode data, and the fourth test mode data may be different from each other. As another example, the first test mode data and the third test mode data may be the same test mode data, and the second test mode data and the fourth test mode data may be the same test mode data, but different from the first and third test mode data.

[0118] exist Figure 12BIn this configuration, the memory cell array 591 includes a plurality of memory blocks MB1, MB2, MB3, and MB4. In some embodiments, each of the plurality of memory blocks MB1, MB2, MB3, and MB4 may include at least one cell string comprising a plurality of memory cells sequentially stacked on a substrate. This can be determined according to... Figure 12B The test method shown performs functional tests in wafer-level testing for semiconductor memory devices. The number of memory blocks MB1, MB2, MB3, and MB4 included in the memory cell array 591 is merely exemplary.

[0119] Reference Figure 12B As time goes by, functional tests can be performed sequentially for each of the first storage block MB1, the second storage block MB2, the third storage block MB3, and the fourth storage block MB4.

[0120] When performing functional tests on the first storage block MB1, the pattern generator 5050a can generate first test pattern data (e.g., Figure 8 The first test mode data can be provided to the first memory block MB1 through the output driver 5111 and the input buffer 5115, and the first test result data generated from the first memory block MB1 can be provided to the comparator circuit 5070.

[0121] When a functional test is performed on the second memory block MB2, the first test result data can be provided to the second memory block MB2 through the output driver 5111 and the input buffer 5115, and the second test result data generated from the second memory block MB2 (e.g., Figure 8 The TR in the circuit can be provided to the comparator circuit 5070.

[0122] When performing functional tests on the third memory block MB3, the second test result data can be provided to the third memory block MB3 through the output driver 5111 and the input buffer 5115, and the third test result data generated from the third memory block MB3 can be provided to the comparator circuit 5070.

[0123] When the fourth memory block MB4 is functionally tested, the third test result data can be provided to the fourth memory block MB4 through the output driver 5111 and the input buffer 5115, and the fourth test result data generated from the fourth memory block MB4 can be provided to the comparator circuit 5070.

[0124] In some embodiments, when performing functional tests on each of the first to fourth storage blocks MB1, MB2, MB3, and MB4, Figure 8The multiplexer 5151 shown can select one of the first test mode data, the first test result data, the second test result data, and the third test result data based on the selection signal sel1 (which is “0” when a functional test is performed on the first memory block MB1, and “1” when a functional test is performed on the second to fourth memory blocks MB2 to MB4).

[0125] Figure 13 An embodiment of the invention is shown. Figure 3 and Figure 5 A block diagram of a semiconductor memory device.

[0126] exist Figure 13 In the semiconductor memory device shown, with Figure 3 and Figure 5 The components included in the semiconductor memory devices shown have the same reference numerals and perform the same or similar functions, and therefore repeated descriptions may be omitted below.

[0127] Reference Figure 13 The semiconductor memory device includes a memory cell array 591, a BIST circuit 570c, a first multiplexer 5151, a second multiplexer 5155, a serializer 5131, an output driver 5111, an input buffer 5115, a parallelizer 5135, a test pad 560, and a data input / output pad 580.

[0128] The BIST circuit 570b includes a clock generator 5030c, a pattern generator 5050, a comparator circuit 5070, a determination logic 5090, a serializer / deserializer (SERDES) 5100c, and a sampling circuit 5010c.

[0129] Figure 13 The semiconductor memory device shown can perform DC testing, AC testing, and functional testing in wafer-level testing. (Referring to the above...) Figure 8 The process of performing functional tests on semiconductor memory devices has been described. The following will describe the execution... Figure 13 The procedure for one of the DC and AC tests of the semiconductor memory device is shown above. Figure 6 As described above, test pad 560 is connected to ATE 110, but data input / output pad 580 is not connected and does not perform specific functions when performing wafer-level testing.

[0130] Reference Figure 1 , Figure 5 , Figure 6 , Figure 8 and Figure 13The sampling circuit 5010c receives command CMD, address ADDR, and test mode data from ATE 110 via test pad 560. Unlike when the semiconductor memory device is performing functional tests, when performing either DC or AC tests, the semiconductor memory device also receives test mode data from ATE 110.

[0131] The sampling circuit 5010c samples at least one of the command CMD and the address ADDR to generate control signals PCTL and CCTL. The sampling circuit 5010c can provide the command CMD and the address ADDR to the serializer / deserializer 5100c.

[0132] The serializer / deserializer 5100c receives command CMD, address ADDR, and test mode data, and receives multiple clock signals CLKL from the clock generator 5030c. The serializer / deserializer 5100c parallelizes command CMD, address ADDR, and test mode data based on the multiple clock signals CLKL.

[0133] Sampling circuit 5010c directs to control circuit 510 (see...) Figure 3 It provides the command CMD and address ADDR, and provides test mode data to the second multiplexer 5155.

[0134] Clock generator 5030c receives control signal CCTL from sampling circuit 5010 and generates multiple clock signals CLKH and CLKL with different frequencies relative to each other based on control signal CCTL. In some embodiments, clock signal CLKH may include the above-mentioned reference. Figure 9 The description includes multiple clock signals CLK1, CLK2, CLK4, and CLK8, and clock signal CLKL may include multiple clock signals having a frequency lower than that of clock signal CLKH, to perform one of DC tests and AC tests.

[0135] exist Figure 13 The diagram illustrates multiple paths 5205 and 5207. Path 5205 represents the path from which test mode data is provided from ATE 110 and written to memory cell array 591, and path 5207 represents the path from which test result data is read from memory cell array 591 and provided to ATE 110. In some embodiments, output driver 5111 and input buffer 5115 may be included on path 5207.

[0136] Figure 14A and Figure 14B The test was shown Figure 13 Examples of methods for semiconductor memory devices.

[0137] exist Figure 14AIn the memory cell array 591, multiple memory blocks MB1, MB2, MB3, and MB4 are included. This can be determined according to... Figure 14A The test method shown performs one of the DC and AC tests in wafer-level testing for semiconductor memory devices. The number of memory blocks MB1, MB2, MB3, and MB4 included in the memory cell array 591 is merely exemplary.

[0138] Reference Figure 14A As time goes by, one of the DC test and AC test for each of the first storage block MB1, the second storage block MB2, the third storage block MB3 and the fourth storage block MB4 can be performed sequentially, referred to below as the "DC / AC test".

[0139] When performing DC / AC tests on the first to fourth storage blocks MB1 to MB4, ATE 110 can generate first to fourth test mode data to provide the first to fourth test mode data to the first to fourth storage blocks MB1 to MB4 respectively. ATE 110 can receive first to fourth test result data from each of the first to fourth storage blocks MB1 to MB4.

[0140] In some embodiments, when performing a DC / AC test on each of the first to fourth storage blocks MB1, MB2, MB3, and MB4, Figure 13 The first multiplexer 5151 shown can select one of the first to fourth test result data based on the selection signal sel1 (e.g., the selection signal sel1 is "1"). The second multiplexer 5155 can select one of the first to fourth test mode data based on the selection signal sel2 (e.g., the selection signal sel2 is "0").

[0141] exist Figure 14B In the memory cell array 591, multiple memory blocks MB1, MB2, MB3, and MB4 are included. This can be determined according to... Figure 14B The test method shown performs DC / AC testing in wafer-level testing for semiconductor memory devices. The number of memory blocks MB1, MB2, MB3, and MB4 included in the memory cell array 591 is merely exemplary.

[0142] Reference Figure 14B As time goes by, DC / AC tests can be performed sequentially on each of the first storage block MB1, the second storage block MB2, the third storage block MB3, and the fourth storage block MB4.

[0143] When performing DC / AC tests on the first to fourth storage blocks MB1 to MB4, ATE 110 can generate only the first test mode data to provide the first mode data to the first storage block MB1. ATE 110 can receive the first test result data from the first storage block MB1.

[0144] When performing DC / AC tests on the second to fourth storage blocks MB2 to MB4, refer to the above. Figure 12B The test result data from previously tested storage blocks can be used as test pattern data for new storage blocks.

[0145] In some embodiments, when performing a DC / AC test on the first storage block MB1, Figure 13 The second multiplexer 5155 shown can select first test mode data based on the selection signal sel2 (e.g., the selection signal sel2 is "0"). However, when performing DC / AC tests on the second to fourth memory blocks MB2 to MB4, Figure 13 The first multiplexer 5151 and the second multiplexer 5155 shown can select test result data for a previously tested memory block based on selection signals sel1 and sel2 (e.g., selection signals sel1 and sel2 are "1").

[0146] Figure 15 A diagram illustrating the connection relationship between a BIST circuit and test pads in a semiconductor memory device 700, according to an embodiment of the present invention, is shown.

[0147] Reference Figure 15 Semiconductor memory devices include those referenced above. Figure 3 The described components include a control circuit (CC) 510, a voltage generator (VG) 530, a line decoder (RD) 550, a test pad 560, a BIST circuit (BC) 570, a data input / output pad 580, and a memory core 590 including a memory cell array (MCA) 591, a page buffer circuit (PBC) 593, and a data input / output circuit (DIOC) 595.

[0148] In some embodiments, the data input / output pad 580 may be Figure 15 The data input / output pads shown are DQ0 to DQ7, and test pad 560 can be... Figure 15 A portion of the non-connected pads (NC) shown (e.g., 710 and 730).

[0149] exist Figure 15 The image shows two test pads (e.g., 710 and 730), but the number of test pads is merely exemplary. That is, the number of test pads can be limited to a few. Figure 15One of the non-connection pads shown. In some embodiments, the BIST circuit BC can provide the control circuit CC with the command CMD and address ADDR received through the test pad via the data strobe pad (DQS) 750.

[0150] Figure 16 A flowchart illustrating a method for testing semiconductor memory devices according to an embodiment of the present invention is shown.

[0151] Reference Figure 16 In a method for testing semiconductor memory devices, the semiconductor memory device is tested in each of a plurality of chips that are scribed and formed on the upper surface of a wafer.

[0152] In a method for testing semiconductor memory devices, commands and addresses are received from the outside via test pads that are separate from the data input / output pads connected to the data input / output circuit (S1000). Test pattern data, including parallel bits, is generated based on the commands and addresses (S2000). Then, the test pattern data is applied to the memory cell array via the data input / output circuit to test the memory core (S3000).

[0153] Figure 17 An embodiment of the invention is shown. Figure 16 A flowchart of the test memory core (S3000).

[0154] Reference Figure 17 In response to the test mode data, a comparison signal is generated by comparing the test result data output from the memory cell array with the test mode data (S3100). Based on the comparison signal, it is determined whether the test on the memory core passes or fails (S3500).

[0155] Figure 18 A diagram of a test system according to an embodiment of the present invention is shown.

[0156] Reference Figure 18 The test system 7000 includes a probe card 7040, a test chamber 7050, an ATE 7010, and a loading chamber 7090. The ATE 7010 includes a test head 7030 and a test body 7020, and the test head 7030 and the test body 7020 are electrically connected via wires or the like (not shown). The probe card 7040 may include a substrate 7041 and a probe unit 7043.

[0157] The test chamber 7050 provides space for testing the electrical characteristics of the chip, and the wafer support chuck 7070 can perform vertical movement while supporting the wafer 150.

[0158] The test head 7030 may include a test head plate 7031 and a base 7033. The base 7033 is disposed on the lower surface of the test head plate 7031 and may have an annular shape with a hollow central portion, and the probe card 7040 may be coupled to the lower surface of the base 7033.

[0159] The test body 7020 can generate electrical signals for testing the chips and can send these signals to the chips in the wafer 150 via the test head 7030 and the probe card 7040. Furthermore, the test body 7020 can receive output signals from each chip in response to the electrical signals sent to each chip via the probe card 7040 and the test head 7030, thereby determining whether each chip is faulty.

[0160] Loading chamber 7090 is a space for storing the wafer 150 to be tested. For testing purposes, the wafers 150 stored in loading chamber 7090 can be transferred one by one to the wafer support chuck 7070 of test chamber 7050 by a mobile device (not shown).

[0161] In other embodiments of the inventive concept, such as Figure 3 Semiconductor memory devices such as the semiconductor memory device 500 shown can be formed on, for example, Figure 2 In each of the plurality of chips 300 on the upper surface of the wafer 150 shown. Then a reference can be used. Figures 1 to 18 The described test is used to test semiconductor memory devices.

[0162] As described above, the semiconductor memory device, the method for testing the semiconductor memory device, and the test system of the present invention perform wafer-level testing via test pads that are separate from the data input / output pads connected to the data input / output circuitry. As a result, wafer-level testing can be performed at high speed because the load effect generated by the automated test equipment does not affect the input buffers and output drivers that can be targets of wafer-level testing. Furthermore, the semiconductor memory device and the test system include a serializer / deserializer connected to the test pads. The serializer / deserializer performs serial-to-parallelization of the data input / output through the test pads, thereby enabling wafer-level testing to be performed using a single test pad.

[0163] Semiconductor memory devices, methods for testing semiconductor memory devices, and test systems can be used to test general semiconductor memory devices. The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although exemplary embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A semiconductor memory device, comprising: The memory core includes an array of memory cells configured to store data and data input / output circuitry connected to data input / output pads; as well as A built-in self-test (BIST) circuit is connected to test pads that are separate from the data input / output pads. The BIST circuit is configured to generate test pattern data, including a first parallel bit, based on commands and addresses received from an external automated test equipment (ATE) during a wafer-level test process performed on the semiconductor memory device. It is also configured to test the memory core by applying the test pattern data to the memory cell array via the data input / output circuit. The semiconductor memory device is disposed in a chip among a plurality of chips located on the surface of a wafer and separated from each other by scribe lines. The data input / output circuit includes: The output driver is connected to the BIST circuit and the data input / output pads; and An input buffer is connected to the data input / output pads, the output driver, and the memory cell array, and The test pad is connected to the input buffer via the BIST circuit.

2. The semiconductor memory device according to claim 1, in, The BIST circuit is also configured to test the output driver and the input buffer by applying the test mode data to the memory cell array through the output driver and the input buffer, and the memory cell array outputs test result data in response to the test mode data.

3. The semiconductor memory device according to claim 1, wherein, The BIST circuit includes: A pattern generator is configured to generate the test pattern data in response to the command and the address; A comparison circuit is configured to generate a comparison signal by comparing test result data with test mode data, the test result data being output from the memory array in response to the test mode data; and The determination logic is configured to determine whether the test on the memory core passes or fails based on the comparison signal.

4. The semiconductor memory device according to claim 3, wherein, The BIST circuit also includes: A clock generator is configured to generate multiple clock signals, each with a different frequency; and A sampling circuit is configured to receive the command and the address, and to output a first control signal associated with controlling the pattern generator and a second control signal associated with controlling the clock generator by sampling at least one of the command and the address.

5. The semiconductor memory device according to claim 4, wherein, Each of the command and the address includes serial bits received through the test pad, and The BIST circuit further includes a parallelizer configured to parallelize the serial bits of each of the command and the address to output a second parallel bit.

6. The semiconductor memory device according to claim 3, wherein, The data input / output circuit also includes: A multiplexer is configured to select one of the test mode data and the test result data in response to a first selection signal; A serializer, configured to serialize the first parallel bits of the test mode data based on a plurality of clock signals provided from the BIST circuit, to provide a first serial bit having a first data rate; and The parallelizer is configured to output a second parallel bit with a second data rate by parallelizing the first serial bit based on the plurality of clock signals.

7. The semiconductor memory device according to claim 6, wherein, The parallelizer is configured to provide the second parallel bit to the memory cell array.

8. The semiconductor memory device according to claim 6, wherein, The first data rate is greater than the second data rate.

9. The semiconductor memory device according to claim 6, wherein, The serializer includes multiple stages. The plurality of stages are configured to receive the plurality of clock signals and sequentially serialize the test mode data to output the first serial bit, and Each clock signal has a different frequency.

10. The semiconductor memory device according to claim 6, wherein, The serializer includes: The first stage is configured to generate a first intermediate parallel bit by merging the first parallel bit based on a first clock signal among the plurality of clock signals; The second stage is configured to generate a second intermediate parallel bit by combining the first intermediate parallel bit based on a second clock signal from the plurality of clock signals; and The third level is configured to generate the first serial bit by combining the second intermediate parallel bit based on a third clock signal among the plurality of clock signals.

11. The semiconductor memory device according to claim 10, wherein, The frequency of the second clock signal is twice the frequency of the first clock signal, and the frequency of the third clock signal is twice the frequency of the second clock signal.

12. The semiconductor memory device according to claim 1, wherein, The memory cell array includes multiple memory blocks, and each memory block includes at least one cell string, the cell string comprising multiple memory cells sequentially stacked on a substrate. The BIST circuit is configured to sequentially test each of the plurality of memory blocks.

13. The semiconductor memory device according to claim 12, wherein, The data input / output circuitry includes a multiplexer configured to select one of the test mode data and test result data in response to a first selection signal, the test result data being output from the storage cell array in response to the test mode data. Specifically, when the BIST circuit initially tests the first memory block among the plurality of memory blocks, the multiplexer is configured to select the test mode data, and When the BIST circuit tests a second memory block that is different from the first memory block after testing the first memory block, the multiplexer is configured to select the test result data.

14. The semiconductor memory device according to claim 1, wherein, The BIST circuit is configured to test the memory core for multiple test items in each of multiple test modes, to receive the command and the address from an external ATE in a first test mode of the multiple test modes, and to receive the command, the address and external test mode data from an external ATE in a second test mode of the multiple test modes.

15. The semiconductor memory device according to claim 14, wherein, The data input / output circuitry further includes a multiplexer configured to select, in the second test mode, one of the external test mode data and test result data output from the storage cell array in response to the external test mode data.

16. The semiconductor memory device according to claim 15, wherein, The first test mode specifies functional testing in wafer-level testing of the semiconductor memory device, and the second test mode specifies DC testing and AC testing in wafer-level testing of the semiconductor memory device.

17. The semiconductor memory device according to claim 16, wherein, The BIST circuit also includes a serializer / deserializer SERDES, which is configured to receive and parallelize the command, the address, and the external test mode data in the second test mode, and to serialize the test result data output from the memory cell array.

18. A method for testing semiconductor memory devices, comprising: The built-in self-test BIST circuit included in the semiconductor memory device receives commands and addresses from the outside through test pads that are separate from the data input / output pads connected to the data input / output circuitry of the semiconductor memory device; The BIST circuit generates test mode data including parallel bits based on the command and the address; as well as The BIST circuit tests the memory core by applying the test mode data to the memory cell array of the memory core of the semiconductor memory device through the data input / output circuit. The semiconductor memory device is included in each of a plurality of chips located on the upper surface of the wafer and separated from each other by scribe lines. The data input / output circuit includes: The output driver is connected to the BIST circuit and the data input / output pads; and An input buffer is connected to the data input / output pads, the output driver, and the memory cell array, and The test pad is connected to the input buffer via the BIST circuit.

19. The method according to claim 18, wherein, The test of the storage core includes: A comparison signal is generated by comparing test result data with test mode data, the test result data being output from the storage cell array in response to the test mode data; and The comparison signal determines whether the test on the memory core passes or fails.

20. A testing system, comprising: An automated test equipment (ATE) is configured to generate commands and addresses in a first test mode for performing wafer-level testing on a semiconductor memory device, which is included in a chip among a plurality of chips located on the upper surface of a wafer. And in the second test mode of the wafer-level test, the command, the address, and the external test mode data are generated. The semiconductor memory device includes: The memory core includes an array of memory cells configured to store data and data input / output circuitry connected to data input / output pads, and A built-in self-test (BIST) circuit is connected to a test pad separate from the data input / output pads. The BIST circuit is configured to generate test mode data including parallel bits in response to the command and address from the ATE in the first test mode, and The BIST circuit is configured to receive the command, the address, and the external test mode data in the second test mode, and to test the memory core by applying one of the test mode data and the external test mode data to the memory cell array through the data input / output circuit. The data input / output circuit includes: The output driver is connected to the BIST circuit and the data input / output pads; and An input buffer is connected to the data input / output pads, the output driver, and the memory cell array, and The test pad is connected to the input buffer via the BIST circuit.

Images