An Improved QFN Product Packaging Process

Abstract

This invention discloses an improved QFN product packaging process, which includes a film application step, wherein a film is applied to the back of a lead frame on which a chip is mounted, and the terminals on the back of the lead frame protrude outward from the plane of the back of the lead frame, and the terminals on the back of the lead frame are embedded in the film; a molding process, wherein the molding process includes molding the lead frame on which the chip is mounted after film application; a film removal process, wherein the film is removed from the back of the molded lead frame, exposing the protruding terminals on the back of the lead frame; and an electroplating process, wherein the electroplating process includes electroplating the terminals on the back of the lead frame after film removal. The improved QFN product packaging process provided by this invention can increase the solder area of ​​the terminals of the QFN product, achieving a reliable soldering to the PCB board.

Description

Technical Field

[0001] This invention relates to the field of chip packaging and testing technology, and in particular to an improved packaging process for QFN products. Background Technology

[0002] The chip industry chain can be divided into three main areas: circuit design, wafer manufacturing, and chip packaging and testing. Chip packaging and testing belongs to the back-end process of the industry chain. Semiconductor packaging and testing refers to the process of processing tested wafers into individual chips according to product models and functional requirements. Based on the assembly method of packaged chips by electronic product end-product manufacturers, chip packaging forms can be divided into through-hole packaging and surface-mount packaging. Among surface-mount packaging types, one packaging form is particularly popular in the market: QFN packaging (Quad Flat No-leads Package).

[0003] The QFN package is a leadless package, square or rectangular in shape, with a large exposed pad at the center of the bottom for heat dissipation. Electrically connected pads surround the large pad. Unlike traditional SOIC (Small Outline Integrated Circuit Package) and TSOP (Thin Small Outline Package) packages, the QFN package has short conductive paths between the internal leads and pads, resulting in low self-inductance and low wiring resistance within the package, thus providing excellent electrical performance. Furthermore, it offers excellent thermal performance through the exposed leadframe pads, which provide direct heat dissipation channels to release heat within the package. Typically, the thermal pads are directly soldered onto the PCB (Printed Circuit Board), and thermal vias in the PCB help dissipate excess power to the copper ground plane, absorbing excess heat and thus contributing to good heat dissipation.

[0004] The packaging process for QFN products mainly includes processes such as die grinding, die mounting, dicing, die assembly, baking, wire bonding, film application, molding, electroplating, and cutting. The film application process before molding involves applying a film to the back of the leadframe. This prevents the pre-molding processes from scratching the leadframe terminals (pins) and avoids the molding resin overflowing onto the terminals during molding. Existing QFN products use parallel terminals. Due to the limited film thickness, after film removal and electroplating, the QFN product terminals only protrude slightly, with a thickness of approximately 7 to 20 micrometers. This results in a small soldering area, which can easily lead to weak soldering and product peeling when soldering on certain special PCBs. Summary of the Invention

[0005] The purpose of this invention is to provide an improved packaging process for QFN products, which can increase the solder area of ​​the terminals of QFN products and achieve a reliable soldering with the PCB board.

[0006] To achieve the above objectives, the technical solution proposed by this invention is as follows:

[0007] An improved QFN product packaging process includes a film application step, wherein the film application step includes applying a film to the back of a lead frame on which a chip is mounted, wherein the terminals on the back of the lead frame protrude outward from the plane on which the back of the lead frame is located, and the terminals on the back of the lead frame are embedded in the film; a molding process, wherein the molding process includes molding the lead frame on which the chip is mounted after film application; a film peeling process, wherein the film peeling process includes peeling off the film on the back of the molded lead frame, thereby exposing the protruding terminals on the back of the lead frame; and an electroplating process, wherein the electroplating process includes electroplating the terminals on the back of the lead frame after film peeling.

[0008] Compared to existing technologies, the improved QFN product packaging process provided by this invention increases the exposed terminal area after molding and film removal. This results in a larger solder paste area, reduces the failure rate during PCB soldering, and improves the product's stability on the PCB. Furthermore, compared to current manufacturing processes, the packaging is simpler and does not increase production efficiency or energy consumption. Therefore, the improved QFN product packaging process provided by this invention increases the solder area of ​​the QFN product terminals, achieving a reliable soldering to the PCB.

[0009] In addition, according to the above embodiments of the present invention, the following additional technical solutions may also be provided:

[0010] Preferably, in the film application process, the terminals on the back of the lead frame are embedded in the film to a depth of 40-60 micrometers.

[0011] Preferably, in the film application process, the terminals on the back of the lead frame are embedded in the film to a depth of 50 micrometers.

[0012] Preferably, the terminals on the back of the lead frame protrude from the back of the lead frame by a length of 80-150 micrometers.

[0013] Preferably, the terminals on the back of the lead frame protrude 100 micrometers beyond the back of the lead frame.

[0014] Preferably, in the film application process, the thickness of the film is greater than or equal to 200 micrometers.

[0015] Preferably, the film is a UV film.

[0016] Preferably, the terminals on the back of the lead frame protrude from the back of the lead frame through a semi-corrosion process.

[0017] Preferably, in the electroplating process, the outer surface of the terminals is electroplated with tin.

[0018] Preferably, in the electroplating process, the terminals on the back of the lead frame are cleaned before electroplating.

[0019] The advantages of the above-mentioned additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] Figure 1 This is a flowchart of the improved QFN product packaging process according to a preferred embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the protruding terminals on the back of the lead frame; only some terminals are shown in the diagram.

[0022] Figure 3 yes Figure 2 The diagram shows the structure of the lead frame after the back film has been applied.

[0023] Figure 4 This is a schematic diagram of the structure of a product after it has been sealed with plastic film;

[0024] Figure 5 This is a schematic diagram of the structure of a plastic-sealed product after the film has been removed.

[0025] Figure 6 This is a schematic diagram of the structure of the product after tin plating following the removal of the protective film;

[0026] Figure 7 This is a schematic diagram of the solder shape of the QFN product obtained by the improved QFN product packaging process provided by the present invention when it is soldered on a PCB board;

[0027] Figure 8 This is a schematic diagram of the solder shape when existing QFN products are soldered on a PCB board. Detailed Implementation

[0028] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0029] Existing QFN product packaging processes include wafer grinding, die mounting, dicing, die assembling, baking, wire bonding, film application, molding, electroplating, and dicing. These processes are all existing QFN product packaging steps. For example, wafer grinding is a process of thinning the wafer at the wafer fab to allow for packaging within a limited space; dicing is a process of cutting and separating the wafer into thousands of independent functional chips; die assembling involves removing the separated chips from the diced wafer and placing them into the lead frame, where the chips and lead frames are connected using silver paste or adhesive film; and wire bonding uses automated wire bonding equipment to connect the chip's functional pads to the terminals (pins) of the lead frame, enabling the chip's designed functions to be implemented through the lead frame terminals. The process involves several steps: connecting to the PCB board to ensure proper operation after power-on; applying a film to the back of the leadframe using a film application device; encapsulation using automated injection molding equipment to cover and cure the soldered chip and leadframe with epoxy resin under high temperature and pressure, forming physical protection on the chip; tin plating on the terminals of the encapsulated product using an electroplating device to facilitate SMT soldering onto the PCB board; printing information on the QFN product surface using laser printing equipment for traceability; and cutting the QFN product into individual units using mechanical cutting.

[0030] The improved QFN product packaging process provided by this invention is an improvement made to some of its processes.

[0031] like Figure 1 As shown, the improved QFN product packaging process provided by this invention includes:

[0032] The film application process includes applying a protective film to the back of the leadframe (formed after die mounting, baking, and wire bonding processes) on which the chip is mounted. This protective film facilitates subsequent injection molding and encapsulation processes. Existing leadframe film application equipment can be used for this process.

[0033] like Figure 2 As shown, in this process, the terminal 1 on the back of the lead frame protrudes outward from the plane 4 on the back of the lead frame. The length of the terminal protruding from the back of the lead frame is 80-150 micrometers, preferably 100 micrometers.

[0034] The terminal 1 on the back of the lead frame can protrude from the back of the lead frame in various suitable ways. In a preferred embodiment of the invention, the terminal 1 on the back of the lead frame protrudes from the back of the lead frame by a semi-etching process. The semi-etching process refers to a semi-etching process, which etches a lower-level surface on the product surface.

[0035] like Figure 3 As shown, after the film is applied, the terminals 1 on the back of the lead frame are embedded in the film 2. The depth to which the terminals on the back of the lead frame are embedded in the film 2 is 40-60 micrometers, preferably 50 micrometers.

[0036] In this invention, the film 2 attached to the back of the lead frame can be any of the existing suitable films, preferably a UV film.

[0037] The molding process includes molding the lead frame containing the chip after it has been laminated. The molded product is as follows: Figure 4 As shown in the figure. The molding compound used for molding is selected with small filler particles and high flowability.

[0038] The film peeling process includes peeling off the film from the back of the plastic-sealed lead frame, exposing the protruding terminals 1 on the back of the lead frame; the product after film peeling is as follows: Figure 5 As shown, the terminals embedded in membrane 2 are exposed outside the plastic seal after the membrane is peeled off.

[0039] The electroplating process includes electroplating the terminals on the back of the lead frame after the film has been removed. For example... Figure 6 As shown, after electroplating, the outer surface of terminal 1 is plated with tin 3. That is, the five exposed surfaces of terminal 1—front, back, left, right, and bottom—are all plated with tin 3. After removing the film, it is preferable to clean the terminals on the back of the lead frame before electroplating, for example, by using an immersion desmearing process to ensure the cleanliness of terminal 1.

[0040] Figure 7 This is a schematic diagram showing the shape of solder 5 when the QFN product obtained using the process of this invention is soldered on a PCB board. Figure 8 This is a schematic diagram of the solder 6 shape structure when soldering QFN products obtained using existing processes on a PCB board, for comparison. Figure 7 , Figure 8 As can be seen, after the above-mentioned process of the present invention, the amount of solder on the terminals of the QFN product when soldering on the PCB board is significantly increased.

[0041] The following describes the improved QFN product packaging process provided by the present invention using a preferred embodiment.

[0042] In the film application process, a film is applied to the back of the lead frame after wire bonding. Terminal 1 on the back of the lead frame protrudes outward by 100 micrometers, and the length and width of the terminal are both 200 micrometers. After film application, the thickness of the portion of terminal 1 embedded in film 2 is 50 micrometers.

[0043] The molding process involves molding the lead frame containing the chip after the film has been applied.

[0044] In the film peeling process, the film on the back of the plastic-sealed lead frame is peeled off, exposing the protruding terminals on the back of the lead frame. The height of the exposed terminal 1 is 50 micrometers, which is 50 micrometers higher than the terminals of existing QFN products.

[0045] In the electroplating process, the terminals on the back of the lead frame after the film is removed are electroplated. Existing QFN products only have a planar tin-plated area (the length and width of the terminal are both 200 micrometers), with a tin plating area of ​​40,000 square micrometers. The QFN product of this invention has terminals with a height of 50 micrometers and tin-plated areas on the front, back, left, right, and bottom surfaces, with a tin plating area of ​​80,000 square micrometers. This tin plating area is twice that of existing QFN products. Therefore, the improved process provided by this invention significantly increases the solder area of ​​the QFN product terminals compared to existing processes, enabling reliable soldering to the PCB board.

[0046] In the description of this invention, it should be understood that the terms "inner" and "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as a limitation of this invention.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, an integral part, or even components located in the middle. Those skilled in the art can understand the specific meaning of these terms in this invention according to the specific circumstances.

[0049] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An improved QFN product packaging process, characterized in that... ,include: The film application process includes applying a film to the back of the lead frame on which the chip is mounted. The terminals on the back of the lead frame are pre-designed to protrude outward from the plane on the back of the lead frame through a semi-corrosion process, with a protrusion length of 80-150 micrometers. The terminals on the back of the lead frame are embedded in the film to a depth of 40-60 micrometers. The thickness of the film is greater than or equal to 200 micrometers, so as to increase the exposed area of ​​the terminals after the molding process and the film peeling process. The molding process includes molding the lead frame on which the chip is mounted after the film is applied. The film peeling process includes peeling off the film on the back of the plastic-sealed lead frame, so that the protruding terminals on the back of the lead frame are exposed; The electroplating process includes electroplating the terminals on the back of the lead frame after the film is removed. Before electroplating, the terminals on the back of the lead frame are cleaned. In the electroplating process, the outer surface of the terminals is electroplated with tin.

2. The improved QFN product packaging process according to claim 1, characterized in that, In the film application process, the terminals on the back of the lead frame are embedded in the film to a depth of 50 micrometers.

3. The improved QFN product packaging process according to claim 2, characterized in that, The terminals on the back of the lead frame protrude 100 micrometers from the back of the lead frame.

4. The improved QFN product packaging process according to claim 3, characterized in that, The membrane is a UV membrane.

5. The improved QFN product packaging process according to claim 4, characterized in that, The terminals on the back of the lead frame protrude from the back of the lead frame through a semi-corrosion process.

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