Defect extraction methods and defect extraction systems

Abstract

This invention provides a defect extraction method and a defect extraction system. The defect extraction method includes: providing a sample to be tested, in which gate oxide defects caused by stress are present; applying different discharge voltages to the gate of the sample to be tested, obtaining the threshold voltage drift under each discharge voltage, wherein the threshold voltage drift corresponds one-to-one with the discharge voltage, and obtaining the threshold voltage drift versus discharge voltage curve based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage; converting the discharge voltage of the sample to be tested into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface; converting the threshold voltage drift of the sample to be tested into the equivalent gate oxide defect density; and converting the curve of the threshold voltage drift versus discharge voltage of the sample to the curve of the equivalent gate oxide defect density versus the position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample to be tested, thereby obtaining the defect level distribution information of the sample to be tested.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a defect extraction method and a defect extraction system. Background Technology

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices face various reliability issues caused by stress during operation. After prolonged exposure to electrical and thermal stress, devices exhibit various degradation effects, such as NBTI (Negative Bias Temperature Instability), PBTI (Positive Bias Temperature Instability), HCI (Hot Carrier Injection), and TID (Total Ionizing Dose). In particular, as semiconductor process nodes scale down proportionally, the reliability problems faced by MOSFET devices become increasingly severe. For example, at advanced process nodes, the gate oxide thickness of the device becomes thinner. Although the operating voltage also decreases proportionally, the rate of voltage reduction is less than the rate of gate oxide thickness reduction, leading to a continuous increase in the equivalent electric field within the gate oxide. Furthermore, for devices operating in special environments such as those with radiation, long-term ionizing radiation can also cause performance degradation. These defects accumulate with increasing stress time, ultimately leading to permanent degradation of key parameters such as threshold voltage, saturation current, carrier mobility, and transconductance. Therefore, measuring stress-induced oxide layer defects and accurately obtaining their energy level distribution information is crucial for understanding stress degradation in MOSFET devices and can provide a basis for optimizing device reliability. However, existing methods for obtaining defect energy level distribution information rely on high-precision temperature control, which places high demands on the testing system and is not very convenient to use. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a defect extraction method and a defect extraction system, wherein the defect extraction method includes:

[0004] Provide a test sample, wherein the test sample contains gate oxide layer defects caused by stress;

[0005] Different discharge voltages are applied to the gate of the sample to be tested, and the threshold voltage drift under each discharge voltage is obtained. The threshold voltage drift corresponds one-to-one with the discharge voltage. The change curve of the threshold voltage drift with the discharge voltage is obtained based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage.

[0006] The discharge voltage of the sample under test is converted into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface;

[0007] The threshold voltage drift of the sample under test is converted into the equivalent defect density of gate oxide.

[0008] The threshold voltage drift curve of the sample under test as a function of the discharge voltage is converted into the gate oxide equivalent defect density curve of the sample under test as a function of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test, thus obtaining the defect level distribution information of the sample under test.

[0009] In one embodiment, applying different discharge voltages to the gate of the sample to be tested to obtain a threshold voltage drift at each discharge voltage, wherein the threshold voltage drift corresponds one-to-one with the discharge voltage, and obtaining the threshold voltage drift versus discharge voltage curve based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage includes:

[0010] Different discharge voltages are applied to the gate of the sample under test and maintained for a preset time; within the preset time, the defects of the sample under test are fully discharged.

[0011] Multiple threshold voltages of the gate of the sample under test are collected for each of the preset time periods during which the discharge voltage is maintained, and the threshold voltage drift under each discharge voltage is obtained.

[0012] A coordinate system is established with each discharge voltage as the abscissa and the threshold voltage drift as the ordinate, to obtain the curve of the threshold voltage drift changing with the discharge voltage.

[0013] In one embodiment, the step of acquiring multiple threshold voltages of the gate of the sample under test during a preset time period for each of the discharge voltages, and obtaining the threshold voltage drift under each discharge voltage, includes:

[0014] Different time points are selected within the preset time period;

[0015] The threshold voltage at different time points under each discharge voltage is measured using a dynamic initialization measurement method.

[0016] Record the threshold voltage drift at the end of each discharge voltage.

[0017] In one embodiment, the sample under test includes a P-type MOS device, the initial discharge voltage applied to the gate of the sample under test is a negative voltage, the discharge voltage gradually decreases over different preset time periods, the maximum discharge voltage applied to the gate of the sample under test is less than the breakdown voltage of the gate of the sample under test, and the Fermi level at the gate oxide / silicon interface of the sample under test enters the conduction band.

[0018] In one embodiment, the sample under test includes an N-type MOS device, the initial discharge voltage applied to the gate of the sample under test is a positive voltage, the discharge voltage gradually increases over different preset time periods, the initial discharge voltage applied to the gate of the sample under test is less than the breakdown voltage of the gate of the sample under test, and the Fermi level at the gate oxide / silicon interface of the sample under test enters the conduction band.

[0019] In one embodiment, converting the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface includes:

[0020] The relative position of the Fermi level at the gate oxide / silicon interface of the sample under test is obtained by solving the surface potential equation at each discharge voltage before stress.

[0021] The relative valence band position of the Fermi level at the gate oxide / silicon interface at each discharge voltage before stress is calibrated based on the threshold voltage after stress on the sample under test, so as to obtain the relative valence band position of the Fermi level at the gate oxide / silicon interface at each discharge voltage of the sample under test.

[0022] In one embodiment, converting the threshold voltage drift of the test sample into the equivalent gate oxide defect density includes: converting the threshold voltage drift of the test sample into the corresponding equivalent gate oxide defect density based on the following formula:

[0023]

[0024] Where, ΔN ox ΔV represents the equivalent defect density of the gate oxide. th For threshold voltage drift; ε ox t is the gate oxide dielectric constant; q is the elementary charge; t ox The gate oxide thickness.

[0025] In one embodiment, converting the threshold voltage drift curve of the sample under test as a function of the discharge voltage into a curve showing the gate oxide equivalent defect density of the sample under test as a function of the relative position of the Fermi level at the gate oxide / silicon interface of the sample under test includes:

[0026] In the curve of the threshold voltage drift versus the discharge voltage, the threshold voltage drift is replaced by the gate oxide equivalent defect density, and the discharge voltage is replaced by the position of the Fermi level relative to the valence band at the gate oxide / silicon interface.

[0027] The present invention also designs a defect extraction system, wherein the defect extraction system employs the defect extraction method described in any of the above-mentioned schemes, and the defect extraction system includes:

[0028] The acquisition module is used to apply different discharge voltages to the gate of the sample to be tested, acquire the threshold voltage drift under each discharge voltage, the threshold voltage drift corresponds one-to-one with the discharge voltage, and establish the change curve of the threshold voltage drift with the discharge voltage based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage;

[0029] The first conversion module is used to convert the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface;

[0030] The second conversion module is used to convert the threshold voltage drift of the sample under test into the equivalent defect density of gate oxide.

[0031] The processing module is used to convert the threshold voltage drift curve of the sample under test as a function of the discharge voltage into the gate oxide equivalent defect density curve of the sample under test as a function of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test, so as to obtain the defect level distribution information of the sample under test.

[0032] In one embodiment, the defect extraction system further includes an update module connected to the processing module, which is used to perform real-time automatic updates based on the defect energy level distribution information of the sample to be tested obtained by the processing module.

[0033] The defect extraction method and system of the present invention have the following beneficial effects: The present invention designs a defect extraction method and system that, by applying different discharge voltages to the gate of the sample under test, obtains the threshold voltage drift under each discharge voltage, and can quickly and accurately obtain the relationship curve between the threshold voltage drift and the discharge voltage; by converting the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface and converting the threshold voltage drift of the sample under test into the equivalent gate oxide defect density, and converting the curve of the threshold voltage drift of the sample under test as a function of the discharge voltage into the curve of the equivalent gate oxide defect density of the sample under test as a function of the discharge voltage, the present invention provides a method and system for extracting defects by applying different discharge voltages to the gate of the sample under test and obtaining the threshold voltage drift as a function of the discharge voltage. The curve showing the change in the position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test can accurately obtain the defect energy level distribution information of the sample under test. The defect extraction method of the present invention is applicable to both P-type MOS and N-type MOS. For P-type MOS devices, the initial discharge voltage applied to the gate is a negative voltage, and the discharge voltage gradually decreases over different preset time periods. For N-type MOS devices, the initial discharge voltage applied to the gate is a positive voltage, and the discharge voltage gradually increases over different preset time periods. In addition, the defect extraction system of the present invention is based on the defect extraction method, is convenient to use, and does not require high-precision temperature control. The defect extraction method and defect extraction system of the present invention are applicable to the acquisition of defect energy level distribution information under various stress conditions, and can quickly and accurately obtain the defect energy level distribution information of the sample under test. Attached Figure Description

[0034] Figure 1 This is a flowchart of a defect extraction method in one embodiment of the present invention.

[0035] Figure 2 This is a flowchart illustrating the curve of threshold voltage drift versus discharge voltage in one embodiment of the present invention.

[0036] Figure 3 This is a curve showing the change of threshold voltage drift with discharge voltage in one embodiment of the present invention.

[0037] Figure 4 This is a flowchart of obtaining the threshold voltage drift under each discharge voltage in one embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram of the test waveforms for obtaining each discharge voltage in one embodiment of the present invention.

[0039] Figure 6 This is a curve showing the change of threshold voltage drift over time during the discharge process in one embodiment of the present invention.

[0040] Figure 7This is a flowchart in one embodiment of the present invention that converts the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface.

[0041] Figure 8 This is a curve showing the position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test as a function of discharge voltage in one embodiment of the present invention.

[0042] Figure 9 In one embodiment of the present invention, the curve showing the variation of the equivalent gate oxide defect density of the sample under test with the position of the Fermi level relative to the valence band at the gate oxide / silicon interface is provided.

[0043] Figure 10 This is a schematic diagram of the defect extraction system in one embodiment of the present invention.

[0044] Figure 11 This is a schematic diagram of the defect extraction system in another embodiment of the present invention.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1. Acquisition module; 2. First conversion module; 3. Second conversion module; 4. Processing module; 5. Update module. Detailed Implementation

[0047] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0048] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0050] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0051] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0052] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0054] With the development of CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit technology, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices face various reliability issues caused by stress during operation. After long-term electrical and thermal stress, the devices exhibit various degradation effects, such as NBTI (Negative-bias temperature instability), PBTI (Positive-bias temperature instability), HCI (Hot Carrier Injection), and TID (Total Ionization Dose).

[0055] In particular, as semiconductor process nodes shrink proportionally, the reliability issues faced by MOSFET devices become increasingly severe. For example, at advanced process nodes, the gate oxide thickness of devices becomes thinner. Although the operating voltage of the device also decreases proportionally, the rate of decrease in the operating voltage is less than the rate of decrease in the gate oxide thickness, resulting in a continuous increase in the equivalent electric field in the gate oxide. Furthermore, for devices operating in special environments such as radiation, long-term ionizing radiation can also lead to performance degradation. These defects accumulate with increasing stress over time, eventually causing permanent degradation of key parameters such as threshold voltage, saturation current, carrier mobility, and transconductance. Therefore, measuring stress-induced oxide layer defects and accurately obtaining the energy level distribution information of these defects is crucial for understanding the stress degradation phenomenon in MOSFET devices and can provide a basis for optimizing device reliability design. However, existing methods for obtaining defect energy level distribution information rely on high-precision temperature control, which places high demands on the testing system and is not very convenient to use.

[0056] To address the aforementioned technical problems, this invention designs a defect extraction method and a defect extraction system. The defect extraction method and system can quickly and accurately obtain energy level distribution information of defects, and are applicable to obtaining energy level distribution information of defects in the oxygen layer under various stress conditions.

[0057] This invention designs a defect extraction method. Figure 1 This is a flowchart of a defect extraction method in one embodiment. Figure 1 As shown, the defect extraction methods include:

[0058] S1: Provide a sample to be tested, which contains gate oxide layer defects caused by stress;

[0059] S2: Apply different discharge voltages to the gate of the sample to be tested, and obtain the threshold voltage drift under each discharge voltage. The threshold voltage drift corresponds one-to-one with the discharge voltage. Based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage, obtain the curve of the threshold voltage drift changing with the discharge voltage.

[0060] S3: Convert the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface;

[0061] S4: Convert the threshold voltage drift of the sample under test into the equivalent defect density of gate oxide;

[0062] S5: The threshold voltage drift curve of the sample under test is converted into the gate oxide equivalent defect density curve of the sample under test as a function of the Fermi level at the gate oxide / silicon interface relative to the valence band, thus obtaining the defect level distribution information of the sample under test.

[0063] The defect extraction method of the present invention obtains the threshold voltage drift under different discharge voltages by applying different discharge voltages to the gate of the sample under test, and can quickly and accurately obtain the relationship between the threshold voltage drift and the discharge voltage. By converting the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface and converting the threshold voltage drift of the sample under test into the gate oxide equivalent defect density, and converting the curve of the threshold voltage drift of the sample under test with the discharge voltage into the curve of the gate oxide equivalent defect density of the sample under test with the position of the Fermi level relative to the valence band at the gate oxide / silicon interface, the defect level distribution information of the sample under test can be accurately obtained.

[0064] It should be noted that the order of S3 and S4 is not subject to the order described above. Figure 1 The order in which the drawing is performed is limited; for example, in other embodiments, the defect extraction method may include:

[0065] S1: Provide a sample to be tested, which contains gate oxide layer defects caused by stress;

[0066] S2: Apply different discharge voltages to the gate of the sample to be tested, and obtain the threshold voltage drift under each discharge voltage. The threshold voltage drift corresponds one-to-one with the discharge voltage. Based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage, obtain the curve of the threshold voltage drift changing with the discharge voltage.

[0067] S3: Convert the threshold voltage drift of the sample under test into the equivalent defect density of gate oxide;

[0068] S4: Convert the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface;

[0069] S5: The threshold voltage drift curve of the sample under test is converted into the gate oxide equivalent defect density curve of the sample under test as a function of the Fermi level at the gate oxide / silicon interface relative to the valence band, thus obtaining the defect level distribution information of the sample under test.

[0070] Combination Figure 2 and participate Figure 3 , Figure 2 This is a flowchart illustrating the threshold voltage drift versus discharge voltage curve in one embodiment. Figure 3 Here is a curve showing the threshold voltage drift versus discharge voltage in one embodiment; see reference. Figure 2 In one embodiment, different discharge voltages are applied to the gate of the sample to be tested to obtain the threshold voltage drift at each discharge voltage. The threshold voltage drift corresponds one-to-one with the discharge voltage. Based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage, the curve of the threshold voltage drift changing with the discharge voltage is obtained, including:

[0071] S21: Apply different discharge voltages to the gate of the sample under test and maintain them for a preset time; within the preset time, the defects of the sample under test are fully discharged;

[0072] S21: Multiple threshold voltages of the gate of the sample under test are collected for each discharge voltage for a preset time, and the threshold voltage drift under each discharge voltage is obtained.

[0073] S23: Establish a coordinate system with each discharge voltage as the abscissa and the threshold voltage drift as the ordinate to obtain the curve of threshold voltage drift as a function of discharge voltage.

[0074] Combination Figure 2 and participate Figure 4 In one embodiment, multiple threshold voltages of the gate of the sample under test are acquired during a preset time period for each discharge voltage, and the threshold voltage drift under each discharge voltage may include:

[0075] S221: Select different time points within a preset time period;

[0076] S222: The threshold voltage at different time points under each discharge voltage is measured using a dynamic initialization measurement method;

[0077] S223: Record the threshold voltage drift at the end of each discharge voltage.

[0078] In one embodiment, the sample under test includes a P-type MOS (P-type metal-oxide-semiconductor field-effect transistor) device. The initial discharge voltage applied to the gate of the sample under test is a negative voltage. The discharge voltage gradually decreases over different preset time periods. The maximum discharge voltage applied to the gate of the sample under test is less than the breakdown voltage of the gate of the sample under test, and the Fermi level at the gate oxide / silicon interface of the sample under test enters the conduction band.

[0079] In one embodiment, the sample under test includes an N-type MOS device (N-type metal-oxide-semiconductor field-effect transistor). The initial discharge voltage applied to the gate of the sample under test is a positive voltage. The discharge voltage gradually increases over different preset time periods. The initial discharge voltage applied to the gate of the sample under test is less than the breakdown voltage of the gate of the sample under test, and the Fermi level at the gate oxide / silicon interface of the sample under test enters the conduction band.

[0080] Specifically, such as Figure 5 As shown, taking a P-type MOS device as an example, for a stressed device, a discharge voltage Vdis(1) is applied to the gate terminal of the device under test. At this time, the discharge voltage Vdis(1) is a negative voltage, which will cause the defect charge to discharge. The selection of Vdis(1) should ensure that the Fermi level near the device channel enters the valence band without causing gate breakdown. The preset time for maintaining the discharge voltage Vdis(1) is set to t. During the discharge process, k time points are selected, and k can include but is not limited to 6s, 10s, 16s, 25s, 40s, 63s, 100s, 160s..., 10 0.2n+0.6 s、… (where n=1,2,3,…), the threshold voltage of the test device; the threshold voltage is measured using OTF (on-the-fly, dynamic initialization) rapid testing. The selection of the preset time t varies depending on the device, but the basic principle is to ensure that the defect is fully discharged, which is manifested by the threshold voltage drift becoming stable over time. After full discharge, the negative gate discharge voltage is gradually increased in steps of Vdis, and the above test is repeated until the last discharge voltage Vdis(n). The selection of Vdis(n) should ensure that the Fermi level near the device channel enters the conduction band without causing gate breakdown. During the test, the discharge voltage is selected to satisfy Vdis(n)>Vdis(n-1)>…>Vdis(2)>Vdis(1)>Vgst, where Vgst is the gate breakdown voltage of the sample under test. The selection of Vdis(1) should ensure that the Fermi level at the gate oxide / silicon interface of the device under test rises above the conduction band, and the selection of Vdis(n) should ensure that the Fermi level at the gate oxide / silicon interface of the device under test falls below the valence band.

[0081] It should be noted that for N-type MOS devices, the above method also applies. However, the selection of the discharge voltage during the test should satisfy Vdis(n) < Vdis(n - 1) < … < Vdis(2) < Vdis(1), where Vdis(1) is a positive voltage.

[0082] As an example, as Figure 6 shown, taking the defects introduced by NBTI stress in P-type MOS devices as an example, the positive trap charges generated in the gate oxide layer after stress will cause the threshold voltage of the device to drift negatively. Figure 6 Fig. is the result of the change of the threshold voltage drift |ΔVth| with time when a P-type MOS device undergoes stepwise discharge testing after NBTI stress in an embodiment. First, at room temperature, a discharge voltage Vdis of -6.3V is applied to the device, and the threshold voltage ΔVth caused by NBTI stress reaches -109.4mV after the -6.3V stress ends; then, the discharge voltage Vdis gradually increases from -6V to 3V, and the step voltage ΔVg = 0.3V; when the discharge voltage Vdis is -6V, the threshold voltage drift |ΔVth| starts to decrease due to the discharge of some defects; as the discharge time increases, the threshold voltage drift |ΔVth| gradually stabilizes and reaches a flat region after 25 seconds, indicating that all recoverable defects have been discharged, and similar discharge phenomena are observed in the discharge stages at each discharge voltage. <>

[0083] It should be noted that for the convenience of experiments in the above embodiments, defects are introduced into the gate oxide layer of the待测样品 by applying stress to the待测样品. In actual applications, the待测样品 itself may already include defects, and there is no need to artificially introduce defects by applying stress.

[0084] Specifically, the defects caused by stress in the待测样品 may include, but are not limited to, positive bias temperature instability, negative bias temperature instability, hot carrier injection, or total dose effect.

[0085] Combined with Figure 1 and referring to Figure 7 , in one of the embodiments, the conversion of the discharge voltage of the待测样品 to the position of the Fermi level relative to the valence band at the gate oxide / silicon interface includes:

[0086] S31: Solve based on the surface potential equation to obtain the position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the待测样品 at each discharge voltage corresponding to the待测样品 before being stressed;

[0087] S32: Calibrate the position of the Fermi level relative to the valence band at the gate oxide / silicon interface at each discharge voltage corresponding to the stress-free state of the待测样品 based on the threshold voltage of the待测样品 after being stressed, so as to obtain the position of the Fermi level relative to the valence band at the gate oxide / silicon interface corresponding to each discharge voltage of the待测样品.

[0088] Specifically, the position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test at each discharge voltage before stress is calculated according to the following surface potential equation:

[0089] (E F -E V ) 界面 =(E F -E V ) 体内 -φ s

[0090]

[0091]

[0092] Among them, E F For the Fermi level position, E V Here, Eg represents the valence band level, and Eg represents the band gap of silicon. F -E V ) 界面 The relative position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test; (E F -E V ) 体内 The relative valence band position of the Fermi level inside the substrate of the sample under test; φs is the surface potential; n is the substrate electron concentration; N C V represents the effective density of states in the conduction band. g V is the gate voltage; fb It is a flat band voltage; C ox ε is the gate oxide surface capacitance; Si q is the dielectric constant of silicon; q is the elementary charge; N D The substrate doping concentration of the sample under test is denoted as . It should be noted that the gate voltage here can be the same as the discharge voltage applied to the gate after the sample under test is subjected to stress and defects are generated.

[0093] Specifically, the position of the relative valence band of the Fermi level at the gate oxide / silicon interface at each discharge voltage before stress is calibrated based on the threshold voltage after stress on the sample under test, so as to obtain the position of the relative valence band of the Fermi level at the gate oxide / silicon interface at each discharge voltage of the sample under test. This includes: using the TCAD (Technology Computer Aided Design, a numerical simulation tool based on semiconductor physics) simulation method to calibrate the position of the relative valence band of the Fermi level at the gate oxide / silicon interface at each discharge voltage before stress based on the threshold voltage after stress on the sample under test.

[0094] As an example, for a MOSFET device, the position of the Fermi level relative to the valence band at the gate oxide / silicon interface satisfies the following relationship:

[0095]

[0096] Among them, E F For the Fermi level position, E V For valence band energy levels, E F -E V The Fermi level at the gate oxide / silicon interface represents the position of the relative valence band, Eg is the band gap of silicon, and φ is the relative position of the Fermi level. B V is the energy difference between the band level and the Fermi level in the bulk region. g V is the gate voltage, which is the same as the discharge voltage applied to the gate of the sample under test; th Let be the threshold voltage of the sample under test. According to the above formula, based on the threshold voltage value obtained from the actual test of the sample under stress, the (EF-EV)~Vg curve of the device before stress calculated by TCAD simulation is calibrated. That is, the actual (EF-EV)~Vg curve should pass through a fixed point (Vth, Eg / 2-φB). The (EF-EV)~Vg curve of the device before stress calculated by simulation is shifted along the X-axis to pass through the fixed point (Vth, Eg / 2-φB), thus obtaining the curve (EF-EV)~Vg, which shows the change in the position of the Fermi level relative to the valence band at the gate oxide / silicon interface after stress as a function of the gate voltage. Since the gate voltage can be the same as the discharge voltage applied to the gate after the sample under stress develops a defect, the position EF-EV of the Fermi level relative to the valence band at the gate oxide / Si interface before stress is obtained. For a clearer illustration of this embodiment, please refer to [reference needed]. Figure 8 , Figure 8 This is a curve showing the position of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test in this example as a function of discharge voltage.

[0097] In one embodiment, converting the threshold voltage drift of the sample under test into the equivalent gate oxide defect density includes: converting the threshold voltage drift of the sample under test into the corresponding equivalent gate oxide defect density based on the following formula:

[0098]

[0099] Where, ΔN ox ΔV represents the equivalent defect density of the gate oxide. th For threshold voltage drift; ε ox t is the gate oxide dielectric constant; q is the elementary charge; t ox The gate oxide thickness.

[0100] In one embodiment, converting the threshold voltage drift curve of the sample under test as a function of discharge voltage into a curve showing the equivalent gate oxide defect density of the sample under test as a function of the Fermi level relative to the valence band at the gate oxide / silicon interface of the sample under test includes:

[0101] In the threshold voltage drift versus discharge voltage curve, the threshold voltage drift is replaced by the gate oxide equivalent defect density, and the discharge voltage is replaced by the position of the Fermi level relative to the valence band at the gate oxide / silicon interface.

[0102] Specifically, to facilitate observation of the curve showing the change in the equivalent gate oxide defect density of the sample under test as a function of the relative position of the Fermi level to the valence band at the gate oxide / silicon interface, one can... Figure 9 The curve shown illustrates the variation of the equivalent gate oxide defect density of the sample under test with the position of the Fermi level relative to the valence band at the gate oxide / silicon interface.

[0103] like Figure 10 As shown, the present invention also designs a defect extraction system, which employs the defect extraction method described in any of the above-mentioned schemes. The defect extraction system includes:

[0104] The acquisition module 1 is used to apply different discharge voltages to the gate of the sample to be tested and acquire the threshold voltage drift under each discharge voltage. The threshold voltage drift corresponds one-to-one with the discharge voltage. Based on the one-to-one correspondence between the threshold voltage drift and the discharge voltage, a curve of the threshold voltage drift changing with the discharge voltage is established.

[0105] The first conversion module 2 is used to convert the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface;

[0106] The second conversion module 3 is used to convert the threshold voltage drift of the sample under test into the equivalent defect density of the gate oxide.

[0107] Processing module 4 is used to convert the threshold voltage drift curve of the sample under test into the gate oxide equivalent defect density curve of the sample under test as a function of the Fermi level at the gate oxide / silicon interface relative to the valence band, so as to obtain the defect level distribution information of the sample under test.

[0108] Combination Figure 10 And see Figure 11 In another embodiment, the defect extraction system further includes an update module 5; the update module 5 is connected to the processing module 4 and is used to automatically update the defect energy level distribution information of the sample under test in real time based on the defect energy level distribution information of the sample under test obtained by the processing module 4, based on the threshold voltage, threshold voltage drift and discharge voltage.

[0109] The defect extraction method and system of the present invention have the following beneficial effects: The present invention designs a defect extraction method and system that, by applying different discharge voltages to the gate of the sample under test, obtains the threshold voltage drift under each discharge voltage, and can quickly and accurately obtain the relationship curve between the threshold voltage drift and the discharge voltage; by converting the discharge voltage of the sample under test into the position of the Fermi level relative to the valence band at the gate oxide / silicon interface and converting the threshold voltage drift of the sample under test into the gate oxide equivalent defect density, and converting the curve of the threshold voltage drift of the sample under test with the discharge voltage into the curve of the gate oxide equivalent defect density of the sample under test with the position of the Fermi level relative to the valence band at the gate oxide / silicon interface, the defect level distribution information of the sample under test can be accurately obtained. The defect extraction method of this invention is applicable to both P-type MOS and N-type MOS. For P-type MOS devices, the initial discharge voltage applied to the gate is negative, and the discharge voltage gradually decreases over different preset time periods. For N-type MOS devices, the initial discharge voltage applied to the gate is positive, and the discharge voltage gradually increases over different preset time periods. Furthermore, the defect extraction system of this invention is based on the defect extraction method, making it convenient to use and eliminating the need for high-precision temperature control. The defect extraction method and system of this invention are applicable to acquiring energy level distribution information of defects under various stress conditions and can quickly and accurately obtain the defect energy level distribution information of the sample under test.

[0110] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A defect extraction method characterized by, The method comprises: providing a sample to be tested, wherein gate oxide layer defects generated due to stress exist in the sample to be tested; applying different discharge voltages to the gate of the sample to be tested to obtain threshold voltage drifts under each discharge voltage, wherein the threshold voltage drifts correspond to the discharge voltages one by one, and a curve of the threshold voltage drifts changing with the discharge voltages is obtained according to the one-to-one correspondence between the threshold voltage drifts and the discharge voltages; calculating the position of the Fermi level at the gate oxide / silicon interface of the sample to be tested before being stressed relative to the valence band according to the following surface potential equation: wherein E F is the Fermi level position, E V is the valence band level, Eg is the band gap of silicon; (E F -E V ) 界面 is the Fermi level position relative to the valence band at the gate oxide / silicon interface of the sample to be measured; (E F -E V ) 体内 is the Fermi level position relative to the valence band inside the substrate of the sample to be measured; φs is the surface potential; n is the substrate electron concentration; N C is the conduction band effective state density; V g is the gate voltage; V fb is the flat band voltage; C ox is the gate oxide capacitance; ε Si is the silicon dielectric constant; q is the basic charge quantity; N D is the substrate doping concentration of the sample to be measured; here, the gate voltage is the same as the discharge voltage applied to the gate after the sample to be measured generates defects under stress; calibrating the position of the Fermi level at the gate oxide / silicon interface of the sample to be tested before being stressed relative to the valence band based on the threshold voltage of the sample to be tested after being stressed by using a TCAD (Technology Computer Aided Design, a numerical simulation tool based on semiconductor physics) simulation method; converting the threshold voltage drifts of the sample to be tested into gate oxide equivalent defect densities; converting the curve of the threshold voltage drifts of the sample to be tested changing with the discharge voltages into a curve of the gate oxide equivalent defect densities of the sample to be tested changing with the position of the Fermi level at the gate oxide / silicon interface of the sample to be tested, i.e. obtaining the defect energy level distribution information of the sample to be tested.

2. The defect extraction method of claim 1, wherein, The method comprises: applying different discharge voltages to the gate of the sample to be tested to obtain threshold voltage drifts under each discharge voltage, wherein the threshold voltage drifts correspond to the discharge voltages one by one, and a curve of the threshold voltage drifts changing with the discharge voltages is obtained according to the one-to-one correspondence between the threshold voltage drifts and the discharge voltages; applying different discharge voltages to the gate of the sample to be tested and maintaining for a preset time; the defects of the sample to be tested are fully discharged within the preset time; collecting multiple threshold voltages of the gate of the sample to be tested within the preset time maintained under each discharge voltage to obtain threshold voltage drifts under each discharge voltage; 3. The defect extraction method of claim 2, wherein, establishing a coordinate system with each discharge voltage as the abscissa and the threshold voltage drift as the ordinate to obtain the curve of the threshold voltage drift changing with the discharge voltage. The method comprises: selecting different time points within the preset time; measuring the threshold voltages at each discharge voltage and each different time point by using a dynamic initialization measurement method; 4. The defect extraction method according to claim 3, wherein recording the threshold voltage drift at the end of each discharge voltage. The sample to be tested comprises a P-type MOS device, the initial discharge voltage applied to the gate of the sample to be tested is a negative voltage, the discharge voltages within different preset times gradually decrease, the maximum discharge voltage applied to the gate of the sample to be tested is less than the breakdown voltage of the gate of the sample to be tested, and the Fermi level at the gate oxide / silicon interface of the sample to be tested enters the conduction band.

5. The defect extraction method of claim 3, wherein, The to-be-tested sample comprises an N-type MOS device, the initial discharge voltage applied on the gate of the to-be-tested sample is a positive voltage, the discharge voltage gradually increases in the preset time, the initial discharge voltage applied on the gate of the to-be-tested sample is less than the breakdown voltage of the gate of the to-be-tested sample, and the Fermi level at the gate oxide / silicon interface of the to-be-tested sample enters the conduction band.

6. The defect extraction method of claim 1, wherein, The converting the threshold voltage shift of the to-be-tested sample into the gate oxide equivalent defect density comprises: converting the threshold voltage shift of the to-be-tested sample into the corresponding gate oxide equivalent defect density based on the following formula: ； where ΔN ox is the gate oxide equivalent defect density, ΔV th is the threshold voltage shift; ε ox is the gate oxide dielectric constant; q is the elementary charge; t ox is the gate oxide thickness.

7. The defect extraction method of claim 1, wherein, The converting the curve of the threshold voltage shift of the to-be-tested sample with the change of the discharge voltage into the curve of the gate oxide equivalent defect density of the to-be-tested sample with the change of the position of the Fermi level at the gate oxide / silicon interface of the to-be-tested sample relative to the valence band comprises: In the curve of the threshold voltage shift with the change of the discharge voltage, the threshold voltage shift is replaced by the gate oxide equivalent defect density, and the discharge voltage is replaced by the position of the Fermi level at the gate oxide / silicon interface relative to the valence band.

8. A defect extraction system employing the defect extraction method according to any one of claims 1 to 7, characterized by, The defect extraction system comprises: The acquisition module is configured to apply different discharge voltages to the gate of the to-be-tested sample, acquire threshold voltage shifts under each discharge voltage, the threshold voltage shifts correspond to the discharge voltages one by one, and establish a curve of the threshold voltage shift with the change of the discharge voltage according to the one-to-one correspondence between the threshold voltage shifts and the discharge voltages. The first conversion module is configured to calculate the position of the Fermi level at the gate oxide / silicon interface of the to-be-tested sample corresponding to each discharge voltage before stress according to the following surface potential equation: wherein E F is the Fermi level position, E V is the valence band level, Eg is the band gap of silicon; (E F -E V ) 界面 is the Fermi level position relative to the valence band at the gate oxide / silicon interface of the sample to be measured; (E F -E V ) 体内 is the Fermi level position relative to the valence band inside the substrate of the sample to be measured; φs is the surface potential; n is the substrate electron concentration; N C is the conduction band effective state density; V g is the gate voltage; V fb is the flat band voltage; C ox is the gate oxide capacitance; ε Si is the silicon dielectric constant; q is the elementary charge; N D is the substrate doping concentration of the sample to be measured; here, the gate voltage is the same as the discharge voltage applied to the gate after the sample to be measured generates defects under stress; The first conversion module is further configured to calibrate the position of the Fermi level at the gate oxide / silicon interface of the to-be-tested sample corresponding to each discharge voltage before stress based on the threshold voltage of the to-be-tested sample after stress by using a TCAD (Technology Computer Aided Design, a numerical simulation tool based on semiconductor physics) simulation method. The second conversion module is configured to convert the threshold voltage shift of the to-be-tested sample into a gate oxide equivalent defect density. The processing module is configured to convert the curve of the threshold voltage shift of the to-be-tested sample with the change of the discharge voltage into a curve of the gate oxide equivalent defect density of the to-be-tested sample with the change of the position of the Fermi level at the gate oxide / silicon interface of the to-be-tested sample relative to the valence band, to obtain defect energy level distribution information of the to-be-tested sample.

9. The defect extraction system of claim 8, wherein, The defect extraction system further comprises an updating module connected to the processing module, configured to automatically update in real time based on the defect energy level distribution information of the to-be-tested sample obtained by the processing module.

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