Parallel access to memory subarrays

Abstract

This application relates to parallel access of subarrays of memory. A row of a subarray in a bank of a memory device can be activated before a precharge operation of a previously open memory cell row in the same bank is completed. Each subarray within the bank can be associated with a respective local latch circuit that can be used to maintain a phase at the subarray independent of subsequent commands for the same bank. The latch circuit can internalize a timing signal triggered by a precharge command for a first row. If an activate command for a different subarray in the same bank is received before the precharge operation of the first row is completed, the precharge operation can continue until the first row is closed because the timing signal triggered by the precharge command can be locally maintained at the subarray using the latch circuit.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 037221, entitled "Parallel Access for Memory Subarrays," filed June 11, 2020, by Mirichigni et al., which claims priority to U.S. Patent Application No. 16 / 515,629, entitled "Parallel Access for Memory Subarrays," filed July 18, 2019, by Mirichigni et al., each of which has been assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to parallel access to memory subarrays. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most typically store one of two states, usually represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power supply.

[0006] Memory devices can be organized into a memory bank, and the memory bank can then be organized into subarrays, each containing rows of memory cells. Access operations can be used to access data stored in the memory cells, which may involve activation commands to open memory cell rows within the subarray of the memory bank, access commands (e.g., read or write commands) to access data in the opened rows, and precharge commands to close the opened rows. Summary of the Invention

[0007] A method is described. The method includes: receiving at a memory device a first activation command to enable a first memory cell row in a first subarray of memory; after receiving the first activation command, receiving at the memory device a precharge command to disable the first memory cell row; and before disabling the first memory cell row in the first subarray of memory, receiving at the memory device a second activation command to enable a second memory cell row in a second subarray of memory.

[0008] A device is described. The device includes: a memory bank of a memory device, the memory bank including a first subarray and a second subarray; a command component of the memory device, the command component configured to receive commands from the first subarray and commands from the second subarray, wherein the command from the first subarray triggers timing signals of the first subarray, and wherein the command from the second subarray triggers timing signals of the second subarray. The device further includes a first latch circuit configured to maintain the timing signals of the first subarray independently of the commands from the second subarray.

[0009] Another method is described. The method includes: transmitting a first activation command to a first memory cell row in a first subarray of a memory bank to the memory device; transmitting a first precharge command to disable the first memory cell row to the memory device after transmitting the first activation command for the first row; determining a second memory cell row in a second subarray of the memory bank for access; determining a time for transmitting a second activation command to enable the second row, based at least in part on the fact that the second row is in the second subarray and the first row is in the first subarray; and transmitting the second activation command to the memory device at the determined time. Attached Figure Description

[0010] Figure 1 This describes an example of a system that supports parallel access to memory subarrays, based on examples disclosed herein.

[0011] Figure 2This describes an example of a memory die that supports parallel access to memory subarrays, based on examples disclosed herein.

[0012] Figure 3 This describes an example of a memory storage system that supports parallel access to memory subarrays, based on examples disclosed herein.

[0013] Figures 4 to 7 This describes an example of a command timeline that supports parallel access to memory subarrays, based on examples disclosed herein.

[0014] Figure 8 A block diagram illustrating a memory device supporting parallel access to memory subarrays according to aspects of this disclosure.

[0015] Figure 9 A block diagram illustrating a host device supporting parallel access to a memory subarray according to aspects of this disclosure.

[0016] Figures 10 to 13 The flowchart illustrates one or more methods for supporting parallel access to memory subarrays according to examples disclosed herein. Detailed Implementation

[0017] To access a memory cell within a row of a subarray within the memory bank of a memory device (e.g., a random access memory (RAM) device), a separate operation can be performed, triggered by a separate corresponding command for the memory device (e.g., sent by a host device or its controller). For example, the memory device may receive an activation command for a row of memory cells, which triggers an activation operation. The activation operation opens a row of memory cells within a given subarray of a given memory bank. Following the activation command, the memory device may receive an access command (e.g., read, write, program, rewrite, etc.) for the opened row. Based on the access command, the memory device may read data from or write data to one or more memory cells in the opened row. Next, the memory device may receive a precharge command for the opened row. Based on the precharge command, the memory device may close the opened row, which can lead to the completion of the access operation.

[0018] Subarrays within a memory bank can utilize local row buffers to access data stored in their respective memory subarrays (e.g., each subarray within the memory bank may have a corresponding local row buffer). However, some memory devices may support only a single set of active phases per memory bank, where phase may refer to timing signals or other control signals that control internal operations (e.g., within the memory bank) associated with commands such as activation, access, and precharge commands. In some cases, if phases are maintained on a per-memory basis, access to subsequent rows in the same memory bank may only occur after the precharge operation of a previously accessed row in the memory bank has been completed, regardless of whether the previously accessed row and the subsequent row are in the same subarray or different subarrays within the memory bank. For example, it may not be possible to simultaneously maintain the phase associated with enabling a subsequent row and the phase associated with disabling a previously accessed row (e.g., a newly generated phase may overwrite or otherwise corrupt a previously generated phase in the memory bank). The delay between the completion of a precharge operation (e.g., closing one or more memory cell rows) and the activation command for a subsequent memory cell row can cause a delay, which can increase the amount of time required to access memory cells within the memory device.

[0019] According to aspects described herein, rows of subarrays within the same memory bank can be accessed before the pre-charge operation of previously opened memory cell rows in the memory bank is completed, provided that the two rows are in different subarrays within the memory bank. This allows for parallel access to different subarrays within the same memory bank (e.g., access to one subarray within the memory bank may at least partially overlap with access to another subarray within the memory bank in time), which can provide reduced latency and other performance benefits as will be apparent to those skilled in the art.

[0020] For example, in addition to each subarray within the memory having its own row buffer, each subarray within the memory may also (e.g., may include or be coupled) be associated with a corresponding local latch circuit, which may maintain (retain, store) the phase associated with the command of the subarray (e.g., the phase of an activation command, access command, or precharge command) independently of any phase associated with commands of other subarrays or even other subarrays within the same memory. In some cases, latching can be viewed as a copy of the phase of the subarray, which may be generated outside the subarray or memory (e.g., by the memory controller or other components not specific to the subarray). The latch circuit may then maintain a copy of the externally generated phase, and the local copy can be used to execute the associated command, even if the memory device receives a new command for another subarray (which may corrupt the phase other than that maintained by the latch circuit, e.g., the original phase generated outside the subarray or memory).

[0021] For example, if the activation signal for the same memory bank (e.g., a different subarray) is received before the precharge operation for the first row is completed (e.g., using a shortened row precharge time (tRP_S)), then the precharge operation can continue until the first row is turned off regardless, because latching circuitry can be used to locally maintain the precharge phase at the subarray. However, in some cases, because each subarray can be associated with a corresponding latching circuitry, the latching circuitry system cannot simultaneously maintain the phase associated with two rows in the same subarray. In such examples, the activation signal for the second row in the same subarray can be received after the precharge operation for the first row in the same subarray is completed (e.g., using a default row precharge time (tRP), which may be longer than tRP_S). In some cases, tRP (whether the default tRP or tRP_S) may represent the number of clock cycles that occur (e.g., as observed by the host device) between issuing the precharge command for a previously opened row and issuing the activation command for a subsequently (e.g., immediately consecutively) opened row, which may be the minimum number of clock cycles.

[0022] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the memory system and memory die described herein. (See references...) Figures 3 to 7 The features of this disclosure are described within the context of the command timeline. See references as follows. Figures 8 to 13 The device diagrams and flowcharts described in relation to parallel access to the memory subarrays further illustrate and describe these and other features of this disclosure.

[0023] Figure 1 This describes an example of a system 100 utilizing one or more memory devices, as disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and multiple channels 115 coupling the external memory controller 105 and the memory device 110. System 100 may include one or more memory devices, but for ease of description, one or more memory devices may be described as a single memory device 110.

[0024] System 100 may include portions of an electronic device, such as a computing device, mobile computing device, wireless device, or graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, or the like. Memory device 110 may be a component of the system, configured to store data from one or more other components of system 100.

[0025] At least a portion of system 100 may be an example of a host device. This host device may be an example of a device that uses memory to perform processes, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, some other fixed or portable electronic device, or the like. In some cases, host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some instances, system 100 is a graphics card.

[0026] In some instances, the host device may transmit multiple activation commands to the memory device 110 (e.g., via an external memory controller 105). For example, the host device may determine access to one or more rows of memory cells within the memory device 110 (e.g., within the same or different subarrays of the memory device 110, or within the same or different memory banks of the memory device 110) and may transmit an activation command for accessing a first row of memory cells and a second activation command for accessing a second row of memory cells. The first and second rows may be in the same memory bank, and the host device may determine the timing of transmitting the second activation command based on whether the first and second rows of memory cells are also in the same or different subarrays of the memory bank. According to some aspects, when determining the timing of transmitting the second activation command, the host device may select between a default tRP or tRP_S. Selecting the default tRP or tRP_S may indicate (specify) a delay between transmitting a precharge command from the host device and turning off the first row of memory cells, which may occur after transmitting the first activation command. The host device may transmit a second activation command after transmitting the precharge command to the first line with a delay corresponding to the selected default tRP or tRP_S (the duration between the two commands).

[0027] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses / space that may be used or referenced by system 100. In some instances, memory device 110 may be configured to work with at least one or more different types of system 100. Signaling between components of system 100 and memory device 110 is operable to support modulation schemes used to modulate signals, different pin designs used to transmit signals, dissimilar packages of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions and / or other factors.

[0028] Memory device 110 may be configured to store data of components of system 100. In some cases, memory device 110 may act as a slave device to system 100 (e.g., responding to and executing commands provided by system 100 via an external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified data storage capacity. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0029] System 100 may further include processor 120, basic input / output system (BIOS) component 125, one or more peripheral components 130, and input / output (I / O) controller 135. The components of system 100 may communicate electronically with each other via bus 140.

[0030] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these types of components. In such cases, processor 120 may be an example of a central processing unit (CPU), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), or system-on-a-chip (SoC), and other examples.

[0031] BIOS component 125 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100. BIOS component 125 may also manage data flow between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O controller 135, etc.). BIOS component 125 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0032] Peripheral component 130 may be any input or output device or interface for such device that can be integrated into or is integrated with system 100. Examples may include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, universal serial bus (USB) controllers, serial or parallel ports, or peripheral card slots such as peripheral component interconnects (PCI) or dedicated graphics ports. Peripheral component 130 may be other components that a person skilled in the art would understand as peripheral devices.

[0033] I / O controller 135 manages data communication between processor 120 and peripheral components 130, input devices 145, or output devices 150. I / O controller 135 can manage peripheral devices that are not integrated into system 100 or are not integrated with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0034] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or interface with other devices or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or can be managed by I / O controller 135.

[0035] Output 150 may represent a device or signal external to system 100, configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, audio speaker, printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or can be managed by I / O controller 135.

[0036] The components of system 100 may consist of general-purpose or special-purpose circuit systems designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components.

[0037] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., a grid), wherein each memory cell is configured to store at least one digital data bit. Reference Figure 2 The characteristics of memory array 170 and / or memory cells are described in more detail.

[0038] In some instances, memory array 170 may comprise multiple memory banks, and each memory bank may comprise multiple subarrays. In some cases, each subarray comprises multiple rows of memory cells that can be accessed by external devices (e.g., host devices, external memory controller 105). A given subarray may include or utilize corresponding latching circuitry that allows memory device 110 to maintain the phase of the memory cells in a given subarray (e.g., timing signals associated with access operations such as precharge commands) independently of the phase of memory cells in other subarrays or even other subarrays within the same memory bank.

[0039] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array. For example, a 2D memory device may comprise a single memory die 160. A 3D memory device may comprise two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or adjacent to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a layer, a layer, a stack, or a die. A 3D memory device may comprise any number of stacked memory dies 160-N (e.g., up to two, up to three, up to four, up to five, up to six, up to seven, up to eight). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce manufacturing costs or increase the performance of the memory array, or both. In a 3D memory device, different layers may share at least one common access line such that some layers may share at least one of word lines, digital lines, and / or board lines.

[0040] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Therefore, device memory controller 155 may include hardware, firmware, and software enabling memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information associated with memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command instructing memory device 110 to store specific data on behalf of a component of system 100 (e.g., processor 120) or a read command instructing memory device 110 to provide specific data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with a local memory controller 165 of memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, a decoder, an amplifier, a filter, or the like.

[0041] A local memory controller 165 (e.g., local to memory die 160) may be configured to control the operation of memory die 160. Furthermore, the local memory controller 165 may be configured to communicate with device memory controller 155 (e.g., to receive and transmit data and / or commands). The local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110 as described herein. In some cases, memory device 110 may not include device memory controller 155, and local memory controller 165 or external memory controller 105 may perform the various functions described herein. Therefore, the local memory controller 165 may be configured to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 105 or processor 120.

[0042] External memory controller 105 can be configured to enable information, data, and / or command communication between components of system 100 (e.g., processor 120) and memory device 110. External memory controller 105 can act as a liaison between components of system 100 and memory device 110, allowing components of system 100 to operate without needing to know the details of memory device operation. Components of system 100 can present requests (e.g., access commands, including read or write commands) to external memory controller 105. External memory controller 105 can translate or interpret the communication exchanged between components of system 100 and memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0043] External memory controller 105 may be part of or associated with a host device and may send one or more commands to memory device 110. In some instances, the external memory controller may send an activation command to enable a row of memory cells in a subarray to memory device 110, followed by an access command to access the row of memory cells in the subarray. External memory controller 105 may determine access to a second row of memory cells (e.g., in the same or a different subarray) and may select the time to send the second activation command to memory device 110 based on tRP or tRP_S, each of tRP or tRP_S corresponding to a delay (e.g., a wait duration) between the precharge command of the first row and the second activation command. For example, if the second row of memory cells is in a subarray different from the first row of memory cells, then external memory controller 105 may determine, based on tRP_S, to send the second activation command to enable the second row of memory cells after the precharge command of the first row. In other cases, if the second memory cell row is in the same subarray, the external memory controller 105 may send a second activation command to enable the second memory cell row after determining the precharge command for the first memory cell row based on tRP.

[0044] In some cases, the external memory controller 105 or other components of system 100, or the functions described herein, may be implemented by processor 120. For example, external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by processor 120 or other components of system 100. Although external memory controller 105 is depicted as being external to memory device 110, in some cases, external memory controller 105, or the functions described herein, may be implemented by memory device 110. For example, external memory controller 105 may be hardware, firmware, or software, or a combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165. In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110 such that portions of external memory controller 105 are implemented by processor 120 and other portions by device memory controller 155 or local memory controller 165. Similarly, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may be performed by the external memory controller 105 (separate from or included in the processor 120).

[0045] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some instances, channel 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal having one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins may be conductive input or output points of devices of system 100, and pins may be configured to act as portions of a channel.

[0046] In some cases, the pins or pads of the termination may be part of the signal path of channel 115. Additional signal paths may be coupled to the termination of the channel to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths within memory device 110 or its components, such as within memory die 160) that route signals from the termination of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0047] Channel 115 (and associated signal paths and terminations) can be dedicated to conveying a specific type of information. In some cases, channel 115 can be a summary channel and therefore can contain multiple individual channels. For example, data channel 190 can be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), and so on. Signals conveyed through the channel can use a double data rate (DDR) timing scheme. For example, some symbols of the signal can be registered on the rising edge of the clock signal and other symbols of the signal can be registered on the falling edge of the clock signal. Signals conveyed through the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be registered for each clock cycle.

[0048] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to communicate commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the command. For example, CA channel 186 may contain a read command with an address containing desired data. In some cases, CA channel 186 may be registered on rising and / or falling clock edges. In some cases, CA channel 186 may contain any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0049] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between high and low states and coordinate the operation of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK_t and CK_c signals), and the signal paths of CK channel 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channel 188 may contain any number of signal paths. In some cases, the clock signals CK (e.g., CK_t and CK_c signals) may provide timing references for commands and provide addressing operations for memory device 110 or other system-wide operations for memory device 110. Therefore, the clock signal CK may be referred to differently as the control clock signal CK, the command clock signal CK, or the system clock signal CK. The system clock signal CK can be generated by the system clock and may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor or the like).

[0050] In some cases, channel 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may communicate information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110.

[0051] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may contain any number of signal paths.

[0052] Channel 115 can couple external memory controller 105 to memory device 110 using a variety of different architectures. Examples of various architectures may include buses, point-to-point connections, crossbar switches, high-density interposers (e.g., silicon interposers), or channels formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0053] Various modulation schemes can be used to modulate signals transmitted through channel 115. In some cases, binary symbol (or binary level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals 2. Each symbol of a binary symbol modulation scheme can be configured to represent a digital data bit (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include (but are not limited to) non-return-to-zero (NRZ), unipolar coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0054] In some cases, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one digital data bit (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include (but are not limited to) PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0055] Figure 2 This describes an example of a memory die 200 as disclosed herein. The memory die 200 may be used as a reference. Figure 1 An example of the described memory die 160. In some cases, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205 programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one digital logic bit at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multilevel memory cell) may be configured to store more than one digital logic bit at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0056] Memory cell 205 can store charge representing programmable states in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing programmable states. In other memory architectures, other memory devices and components are possible. For example, nonlinear dielectric materials (e.g., ferroelectric materials) may be used.

[0057] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting access lines, such as word line 210 and / or digital line 215. In some cases, digital line 215 may also be referred to as a bit line. References to access lines, word lines, and bit lines or the like are interchangeable without loss of understanding or operation. Activating or selecting word line 210 or digital line 215 may involve applying a voltage to the corresponding line.

[0058] The memory die 200 may include access lines (e.g., word lines 210 and digital lines 215) arranged in a grid pattern. Memory cells 205 may be located at the intersections of word lines 210 and digital lines 215. Individual memory cells 205 can be accessed at their intersections by applying a bias voltage to word lines 210 and digital lines 215 (e.g., applying a voltage to word lines 210 or digital lines 215).

[0059] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 may receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 260 and activate digital line 215 based on the received column address. For example, memory die 200 may include multiple word lines 210 (labeled WL_1 to WL_M) and multiple digital lines 215 (labeled DL_1 to DL_N), where M and N depend on the size of the memory array. Therefore, by activating word line 210 and digital line 215 (e.g., WL_1 and DL_3), memory cell 205 at their intersection can be accessed. The intersection of word line 210 and digital line 215 (in a two-dimensional or three-dimensional configuration) may be referred to as the address of memory cell 205.

[0060] Memory cell 205 may contain logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell board reference voltage (e.g., Vpl) or may be grounded (e.g., Vss). In some cases, voltage source 240 may be an example of a board line coupled to a board line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0061] In some instances, a portion of memory cell 205 may be a row of memory cells 205 within a subarray of memory. A row of memory cells 205 can be accessed (e.g., by a host device) via one or more commands. For example, a row of memory cells 205 can be opened based on an activation command, an access command (e.g., a read command or a write command) can access data stored in or write data to a row of memory cells 205, and a row of memory cells 205 can be closed based on a precharge command. After a first delay following the precharge command (e.g., corresponding to tRP), access to a second row of memory cells 205 within the same subarray can be performed via an activation command. After a second, shorter delay following the precharge command (e.g., corresponding to tRP_S), access to a second row of memory cells 205 within a different subarray can be performed via an activation command.

[0062] Selecting or deselecting memory cell 205 can be accomplished by activating or deactivating activation switch assembly 235. Capacitor 230 can communicate electronically with digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when activation switch assembly 235 is deactivated, and capacitor 230 can be coupled to digital line 215 when activation switch assembly 235 is activated. In some cases, switch assembly 235 is a transistor and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the transistor's threshold voltage. In some cases, switch assembly 235 can be a p-type transistor or an n-type transistor. Word line 210 can communicate electronically with the gate of switch assembly 235 and can activate / deactivate switch assembly 235 based on the voltage applied to word line 210.

[0063] Word line 210 may be a conductive line for electronic communication with memory cell 205, used to perform access operations on memory cell 205. In some architectures, word line 210 may be electronically communication with the gate of switching component 235 of memory cell 205 and may be configured to control the switching component 235 of memory cell. In some architectures, word line 210 may be electronically communication with the node of capacitor in memory cell 205 and memory cell 205 may not include a switching component.

[0064] Digital line 215 may be a conductive line connecting memory cell 205 and sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 235 of memory cell 205 may be configured to couple and / or isolate capacitor 230 of memory cell 205 from digital line 215. In some architectures, memory cell 205 may communicate electronically (e.g., constantly) with digital line 215.

[0065] Sensing component 245 may be configured to detect a state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be extremely small. Therefore, sensing component 245 may include one or more sensing amplifiers to amplify the signal output of memory cell 205. The sensing amplifier may detect small changes in charge on digital line 215 during a read operation and may generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, capacitor 230 of memory cell 205 may output a signal (e.g., discharge charge) to its corresponding digital line 215. The signal may cause a voltage change on digital line 215. Sensing component 245 may be configured to compare the signal received from memory cell 205 across digital line 215 with a reference signal 250 (e.g., a reference voltage). Sensing component 245 may determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digital line 215 has a voltage higher than reference signal 250, then sensing component 245 can determine that the stored state of memory cell 205 is logic 1, and if digital line 215 has a voltage lower than reference signal 250, then sensing component 245 can determine that the stored state of memory cell 205 is logic 0. Sensing component 245 may include various transistors or amplifiers to detect and amplify differences in signals. The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., to input / output component 255), and may (e.g., directly or using local memory controller 260) indicate the detected logic state to another component of memory device 110 containing memory die 200 (e.g., device memory controller 155).

[0066] The local memory controller 260 can control the operation of the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, and sensing component 245). The local memory controller 260 may be used as a reference. Figure 1 An example of the described local memory controller 165. In some cases, one or more of the row decoder 220, column decoder 225, and sensing component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to: receive data from an external memory controller 105 (or refer to...) Figure 1The described device memory controller 155 receives commands and / or data; translates the commands and / or data into information usable by the memory die 200; performs one or more operations on the memory die 200; and transmits data from the memory die 200 to an external memory controller 105 (or device memory controller 155) in response to performing one or more operations. The local memory controller 260 can generate row and column address signals to activate target word lines 210 and target digital lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current described herein can be adjusted or changed and may vary for various operations discussed during operation of the memory die 200.

[0067] In some cases, the local memory controller 260 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 on which the write operation is performed. The local memory controller 260 may identify the target word line 210 and target digital line 215 (e.g., the address of the target memory cell 205) that are electronically communicating with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and target digital line 215 (e.g., apply voltage to the word line 210 or digital line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., voltage) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205, the specific state (e.g., charge) indicating a desired logic state.

[0068] In some cases, the local memory controller 260 may be configured to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During a read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 on which the read operation is performed. The local memory controller 260 may identify the target word line 210 and target digital line 215 (e.g., the address of the target memory cell 205) that are electronically communicating with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 245 in response to a bias applied to the access line. The sensing component 245 may amplify the signal. The local memory controller 260 can trigger a sensing component 245 (e.g., a latching sensing component 245) and thereby compare a signal received from memory cell 205 with a reference signal 250. Based on the comparison, the sensing component 245 can determine a logical state stored in memory cell 205. As part of a read operation, the local memory controller 260 can transmit the logical state stored in memory cell 205 to external memory controller 105 (or device memory controller 155).

[0069] In some memory architectures, accessing memory cell 205 can degrade or corrupt the logic state stored in memory cell 205. For example, a read operation performed in a DRAM architecture can partially or completely discharge the capacitors of the target memory cell. Local memory controller 260 can perform a rewrite or refresh operation to return the memory cell to its original logic state. Local memory controller 260 can rewrite the logic state to the target memory cell after a read operation. In some cases, a rewrite operation can be considered part of a read operation. Additionally, activating a single access line (e.g., word line 210) can interfere with the state stored in some memory cells that are in electronic communication with said access line. Therefore, a rewrite or refresh operation can be performed on one or more memory cells that have not yet been accessed.

[0070] Figure 3 This describes an example of a memory storage system 300 that supports parallel access to memory subarrays, as disclosed herein. The memory storage system 300 may include a host device 305 and a memory device 310. The host device 305 may include a memory controller 315 (which may be as described in the references...) Figure 1(An example of the described external memory controller), the memory controller 315 can communicate with the memory device 310 via CA bus 320 and / or data bus 325 (which may be as described in the reference). Figure 1 (Example of the described memory device 110). The memory device 310 may utilize DRAM, FeRAM, or other types of memory to store data at the memory device 310. The process by which the data stored in the memory device 310 can be accessed by the memory controller 315 and the memory controller 315 accesses the data stored at the memory device 310 is referred to as an access operation.

[0071] Access operations, such as read or write operations, may be communicated (e.g., sent by host device 305) to memory device 310 as a series of commands (e.g., as a sequence of commands). These commands may be communicated to memory device 310 by memory controller 315 via CA bus 320 (an example of CA bus 186). The commands may be received by memory device 310 and may trigger corresponding operations at memory device 310 to read, write, or otherwise access data stored by memory device 310 (e.g., at one or more memory cells of memory device 310). Data stored at or written to memory device 310 may be communicated between host device 305 and memory device 310 via data bus 325 (an example of DQ bus 190).

[0072] Memory device 310 may include multiple subarrays 335. Subarrays 335 may store data contained in memory device 310. First memory bank 330-a and second memory bank 330-b may be instances of memory bank 330. Subarrays 335 may be grouped into memory banks 330. In some instances, memory device 310 may include thirty-two memory banks 330, each of which may include multiple subarrays 335 of memory cells. For example, one or more memory banks 330 may contain sixteen subarrays 335. First subarray 335-a and second subarray 335-b may be instances of subarray 335 and, as shown in this example, are located in two different memory banks 330 of memory device 310. Subarrays 335 may each contain data that can be stored associated with memory device 310 or data that can be written to individual memory cell rows of memory device 310, such as row 340.

[0073] In some cases, commands received by memory device 310 may cause memory device 310 to generate one or more associated phases (e.g., using phase generator 350). For example, for each activation, access, or precharge command received by memory device 310, phase generator 350 of memory device 310 may generate an associated set of phases. The associated set of phases may refer to or may include timing signals that commonly trigger or otherwise control a sequence of internal operations within subarray 335. Executing a command operation may involve performing a set of such internal operations (e.g., performing an activation operation at subarray 335 may involve a first set of phased internal operations, performing an access operation such as a read or write operation at subarray 335 may involve a second set of phased internal operations, and performing a precharge operation at subarray 335 may involve a third set of phased internal operations). Therefore, the phases can control the internal timing of access operations for a given row of a given subarray 335 to which the command is targeted. In some instances, the phase may be an internal timing signal that triggers an electrical operation (e.g., a physical electrical operation) corresponding to a command operation on an individual row basis to access a memory cell of a given row 340.

[0074] Memory device 310 may include any number of phase generators 350 (e.g., one per subarray 335, one per bank 330, one per memory die, or one per memory device 310). As an example, a phase generator 350 may be included in or incorporated into an aspect of a device memory controller 155 or a local memory controller 165 included in memory device 310. As another example, a phase generator 350 may include logic or other special-purpose circuitry that may be included in, coupled to, or otherwise associated with the bank 330 targeted by the corresponding command (e.g., each bank 330 may include a corresponding phase generator 350, coupled to, or otherwise associated with it), i.e., phases may be generated on a per-bank 330 basis. Phases and other signals generated within memory device 310 but outside the corresponding subarray 335 may be referred to as global phases or signals. As another example, each subarray 335 may include a corresponding phase generator 350, coupled to or otherwise associated with it, and may locally generate the phase of each subarray 335.

[0075] A global phase can be generated for each memory bank 330. This can support simultaneous (parallel) access to different memory banks 330, with at least partial temporal overlap between rows in different memory banks 330. In some instances, activation and / or precharge operations can occur on rows 340 in different memory banks 330 when activation and / or precharge operations occur on rows 340 in memory banks 330 in memory device 310.

[0076] In some instances, each subarray 335 may include, use, or otherwise associate with a corresponding (e.g., a corresponding) row buffer to access data stored in the subarray 335. Alternatively, each subarray 335 within the memory bank 330 may include, use, or otherwise associate with a corresponding latch circuit 345 that can replicate the phase associated with the subarray 335 and maintain (store, retain) the phase independently of the phase associated with the remaining subarrays 335 in the memory bank 330 or memory device 310. For example, the latch circuit 345 may store a copy of the global phase or other signals associated with the corresponding subarray 335 (for performing operations on the corresponding subarray 335). The latch circuit 345 allows the memory storage system 300 to be optimized according to the examples described herein. For example, this can support simultaneous (parallel) access to different subarrays 335 of the same memory bank 330, where access to rows in different subarrays 335 of the same memory bank 330 at least partially overlaps in time. In some instances, when an activation and / or precharge operation occurs on a row 340 of a first subarray 335 of the memory bank 330 in the memory device 310, an activation and / or precharge operation can also occur on a row 340 of a second subarray of the memory bank 330.

[0077] Accessing row 340 may involve one or more operations, each of which may result in a total latency for accessing the row. Such operations may be based on (in response to) a corresponding command, which may be communicated from memory controller 315 to memory device 310. Commands for accessing row 340 within subarray 335 of memory bank 330 may include activation commands (corresponding to activation operations), access commands (corresponding to, for example, read operations, write operations, programming operations, reset operations, and rewrite operations), and precharge commands (corresponding to precharge operations). The activation operation may open memory cell row 340. The access operation may access data contained in the opened (e.g., activated) row 340 (e.g., in the case of a read operation) or write data into the opened row 340 (e.g., in the case of a write operation). The precharge operation may close the opened row 340.

[0078] All three operations can be performed to access a row of memory cells 340 within a subarray 335 of the memory bank 330 of the memory device 310. In some instances, an activation operation can be performed before the access operation to enable row 340. Additionally, a precharge operation can be performed after the access operation to disable the activated row 340. In some cases, a precharge operation can be performed before subsequent access operations to row 340 within the same memory bank 330. Corresponding commands can be communicated from the memory controller 315 to the memory device 310 as a series of commands (e.g., as a command sequence). The commands may include an activation command, an access command, and a precharge command, and can be received in the order in which the corresponding operations are performed.

[0079] Figure 4 This describes an example of a command timeline 400 that supports parallel access to memory subarrays, as disclosed herein. Figure 4 This describes the instance access of two rows in two different subarrays within different memory banks of a memory device, where the memory banks may be as follows: Figure 3 Examples of the corresponding devices described. For example, the first memory bank 405 and the second memory bank 435 may be two separate memory banks within a memory device.

[0080] The memory device including the first memory bank 405 and the second memory bank 435 can, for example, Figure 3 The host device of the memory controller 315 receives commands. The host device can transmit commands to the memory device via the CA bus 320-a. Commands associated with the first memory bank 405 and the second memory bank 435 can be received via the same CA bus 320-a, but for the sake of clarity, separate commands associated with the two memory banks 405 and 435 are not specified here. Figure 4 Two examples of CA bus 320-a may appear in the text.

[0081] The memory device may receive a first activation command 415 for a row of memory cells in the first memory bank 405 (e.g., in a subarray) via CA bus 320-a. The first activation command 415 may trigger an activation phase, which may include timing or other signals for initiating internal operations of the row in the first memory bank 405.

[0082] The memory device may subsequently receive a first access command 420 of one or more memory cells in a row of the first memory bank 405 via CA bus 320-a. The first access command 420 may trigger an additional phase (not shown) that may include timing or other signals for reading, writing or otherwise accessing internal operations of memory cells in an open row of the first memory bank 405.

[0083] The memory device may subsequently receive a first precharge command 425 for a row in the first memory bank 405 via CA bus 320-a. The first precharge command 425 may trigger a precharge phase (not shown), which may include timing or other signals for disabling internal operations of the row in the first memory bank 405.

[0084] The memory device can also receive a second activation command 445 for a row of memory cells in the second memory bank 435 (e.g., in a subarray) via CA bus 320-a. The second activation command 445 may trigger an activation phase (not shown), which may include timing or other signals for initiating internal operations of the row in the second memory bank 435.

[0085] The memory device may subsequently receive a second access command 450 for one or more memory cells in a row of the second memory bank 435 via the CA bus 320-a. The second access command 450 may trigger an additional phase (not shown) that may include timing or other signals for reading, writing or otherwise accessing internal operations of memory cells in an open row of the second memory bank 435.

[0086] The memory device may subsequently receive a second precharge command 455 for a row in the second memory bank 435 via CA bus 320-a. The second precharge command 455 may trigger a precharge phase (not shown), which may include timing or other signals for disabling internal operations of the row in the second memory bank 435.

[0087] However, in some instances as described herein, the memory device including the first memory bank 405 and the second memory bank 435 may use subarray-specific structures or processes that operate at the subarray granularity level (e.g., subarray-specific latch circuitry 345, as referenced). Figure 3 (As described) to maintain phase. For example, the memory device may use a structure or process specific to the first memory bank 405 (e.g., dedicated to the first memory bank 405, included in the first memory bank 405) to maintain phase.

[0088] The time tRRD 430 (e.g., row-to-row access time delay) can be the time elapsed between the memory device receiving a first activation command 415 for a row of a subarray in the first memory bank 405 and the memory device receiving a second activation command 445 for a row of a subarray in the second memory bank 435 (e.g., the number of clock cycles, which can be the minimum number of clock cycles).

[0089] In some cases, tRRD 430 may be less than the time it takes for the internal operation controlled by the phase triggered by the first activation command 415 to access the open row within the first memory bank 405. Because the first memory bank 405 and the second memory bank 435 have corresponding row buffers for accessing data stored in rows contained in separate memory banks, it is possible to activate rows in the second memory bank 435 prior to subsequent accesses and precharge operations of rows in the first memory bank 405. In some instances, for the memory device described herein, subarrays within the first memory bank 405 and the second memory bank 435 may have corresponding latching circuitry configured to maintain the phase within the memory device triggered by a command sent via the CA bus 320-a (e.g., ...). Figure 3 The latch circuit 345 allows the host device to access the row based on different time delays (e.g., tRP or tRP_S) and whether the memory cell row in a memory bank (e.g., one of the first memory bank 405 or the second memory bank 435) is in the same or different subarrays within the same memory bank (e.g., one of the first memory bank 405 or the second memory bank 435).

[0090] Figure 5 This describes an example of a command timeline 500 that supports parallel access to memory subarrays, as disclosed in this document. Figure 5 This describes an instance access to two rows in two different subarrays within the same memory cell of a memory device, the subarrays being as follows: Figure 3 and 4 Examples of the corresponding devices described. For example, the first subarray 505 and the second subarray 580 may be two separate subarrays within the same memory cell of a memory device.

[0091] The memory device including the first subarray 505 and the second subarray 580 can, for example, Figure 3 The host device of the memory controller 315 receives commands. The host device can transmit commands to the memory device via the CA bus 320-b. Commands associated with the first subarray 505 and the second subarray 580 can be received via the same CA bus 320-b, but for clarity, separate commands associated with the two subarrays 505 and 580 are not specified. Figure 5 Two examples of CA bus 320-b may appear. A command associated with the first subarray 505 can trigger phase 545, and a command associated with the second subarray 580 can trigger phase 590.

[0092] The memory device can receive a first activation command 515 for a row of memory cells in the first subarray 505 via the CA bus 320-b. The first activation command 515 can trigger a first activation phase 550, which may include timing or other signals for initiating internal operations of the rows in the first subarray 505.

[0093] The memory device may subsequently receive a first access command 520 for one or more memory cells in a row of the first subarray 505 via CA bus 320-b. The first access command 520 may trigger an additional phase (not shown) that may include timing or other signals for reading, writing or otherwise accessing internal operations of memory cells in an open row of the first subarray 505.

[0094] The memory device may subsequently receive a first precharge command 525-a for a row in the first subarray 505 via CA bus 320-b. The first precharge command 525-a may trigger a precharge phase 555, which may include timing or other signals for disabling internal operations of the rows in the first subarray 505.

[0095] The memory device can also receive a second activation command 595-a for a row of memory cells in the second subarray 580 via CA bus 320-b. The second activation command 595-a can trigger a second activation phase 599, which may include timing or other signals for initiating internal operations of the rows in the second subarray 580.

[0096] The memory device may subsequently receive additional commands (not shown) via CA bus 320-b (e.g., access commands to open rows in the second subarray 580, precharge commands to close rows in the second subarray 580).

[0097] The latency for accessing rows on a memory device can be based on various global operation timings, examples of which are... Figure 5 As explained below. For example, time tRCD 530 (e.g., row address to column address delay) can be the time elapsed between the memory device receiving the first activation command 515 and the memory device receiving the first access command 520 (e.g., the number of clock cycles, which can be the minimum number of clock cycles). Therefore, tRCD 530 can be or includes the time for the internal operation controlled by the first activation phase 550 to activate rows within the first subarray 505.

[0098] The time tRTP 535 (e.g., read-precharge delay) can be the time elapsed between the memory device receiving the first access command 520 and the memory device receiving the precharge command 525-a (e.g., the number of clock cycles, which can be the minimum number of clock cycles). Therefore, tRTP 535 can be or include the time for an internal operation controlled by the phase triggered by the first access command 520 to access an open row within the first subarray 505.

[0099] The time tRAS 540 (e.g., row validity time) can be the time elapsed between the memory device receiving the first activation command 515 and the memory device receiving the precharge command 525-a (e.g., the number of clock cycles, which can be the minimum number of clock cycles). Therefore, tRAS 540 can be or include the sum of time tRCD 530 and time tRTP 535.

[0100] The time tRP 570 (e.g., row precharge time) can be the time elapsed between the memory device receiving the precharge command 525-a and completing the precharge operation to open rows within the first subarray 505 (e.g., the number of clock cycles, which can be the minimum number of clock cycles). Therefore, tRP 570 can be or include the time for the internal operation controlled by the precharge phase 555 to close rows within the first subarray 505.

[0101] The time tRC 560 (e.g., row cycle time) may be the time elapsed between the memory device receiving the first activation command 515 and completing the precharge operation of the open row within the first subarray 505. Therefore, tRC 560 may be or include the total time for performing access operations on the row (e.g., may be or include the sum of times tRAS 540 and tRP 570).

[0102] For some memory devices, the memory controller 315 may have to wait at least tRP 570 duration before issuing a subsequent activation command to the memory device for another row within the same memory cell as the row associated with the precharge command 525-a, regardless of whether the row associated with the precharge command 525-a and the row to be activated subsequently are in the same subarray or in different subarrays of the memory cell. For example, some memory devices may generate and maintain phase only at the memory cell level (e.g., using memory cell-specific structures or processes that operate at the memory cell granular level, rather than subarray-specific structures or processes that operate at the subarray granular level). In such instances, if the memory device receives a second activation command 595-a (for the second row in the same memory bank) before the end of tRP 570 (which may also be the end of tRC 560), then the phase 545 associated with the first subarray 505 (e.g., precharge phase 555) may be overwritten, replaced, or otherwise damaged or lost, and thus one or more aspects of the access operation to the first row (e.g., the precharge operation triggered by precharge command 525-a) may be improperly performed or completed. Additionally or alternatively, if the memory device receives a second activation command 595-a (for the second row in the same memory bank) before the end of tRP 570, then the activation (e.g., enabling) of the second row in the same memory bank may be improperly performed or completed, or some other error condition may occur.

[0103] However, in some instances as described herein, a memory device including a first subarray 505 and a second subarray 580 (both may be within the same memory cell of the memory device) may use subarray-specific structures or processes that operate at the subarray granularity level (e.g., subarray-specific latch circuitry 345, as referenced). Figure 3 (As described) Maintaining phase (e.g., phase 545 or phase 590). For example, the memory device may maintain phase 545 using a structure or process specific to the first subarray 505 (e.g., dedicated to the first subarray 505, contained within the first subarray 505). Thus, even if a second activation command 595-a is received before the end of tRP 570 (e.g., before closing the first row in the first subarray 505), the precharge phase 555 or other phase 545 may continue (persist, be maintained) until other aspects of the precharge operation or access operation of the first row are performed and completed. That is, even within the same memory cell as the first subarray 505, phase 545 may be maintained until any phase or associated command independent of other subarrays completes the associated operation.

[0104] In some cases, phase 545 may be generated globally (e.g., within a memory device but outside the first subarray 505, such as through a device memory controller 155, a local memory controller 165, a phase generator 350, or some other logic or other circuitry system shared (configured to generate their phases) by multiple subarrays within the same memory), but may be replicated and maintained by components specific to the first subarray 505. In other cases, phase 545 may be generated and also maintained locally (e.g., within the first subarray 505).

[0105] Therefore, for a memory device as described herein, the memory controller 315 may be able to wait for a duration (e.g., the number of clock cycles, which may be the minimum number of clock cycles) corresponding to tRP_S (e.g., a shortened row precharge time) between sending the precharge command 525-a and sending the second activation command 595-a. Thus, tRP_S 575 may be the time (e.g., the number of clock cycles, which may be the minimum number of clock cycles) between the memory device receiving the precharge command 525-a and the memory device receiving the second activation command 595-a. Figure 5 As shown, tRP_S 575 can be shorter than tRP570. Thus, for example, tRP 570 can be, in some cases, the minimum time (e.g., minimum number of clock cycles) that the memory controller 315 must wait between sending a precharge command and sending an immediate consecutive activation command for rows in the same subarray, while tRP_S 575 can be the minimum time (e.g., minimum number of clock cycles) that the memory controller 315 must wait between sending a precharge command and sending an immediate consecutive activation command for rows in different subarrays of the same memory bank.

[0106] Alternatively, for a memory device as described herein, the memory controller 315 may be able to wait for a duration (e.g., the number of clock cycles, which may be the minimum number of clock cycles) corresponding to tRC_S (e.g., a shortened row cycle time) between sending the first activation command 515 and sending the second activation command 595-a. Therefore, tRC_S 565 may be the time (e.g., the number of clock cycles, which may be the minimum number of clock cycles) between the memory device receiving the first activation command 515 and the memory device receiving the second activation command 595-a. Figure 5As shown, tRC_S565 can be shorter than tRC560. Thus, for example, tRC 560 can be, in some cases, the minimum time (e.g., minimum number of clock cycles) that the memory controller 315 must wait between sending consecutive activation commands for rows in the same subarray, while tRC_S 565 can be the minimum time (e.g., minimum number of clock cycles) that the memory controller 315 must wait between sending consecutive activation commands for rows in different subarrays of the same memory bank.

[0107] As described with reference to phase 545 of the first subarray 505, phase 590 of the second subarray 580 (including the second active phase 599) can be maintained using a structure or process specific to the second subarray (e.g., latch circuitry 345). Similarly, phase 590 may be generated globally and locally replicated or otherwise maintained, or in some cases may be generated locally.

[0108] In some cases, for memory devices supporting tRP_S as described herein, the memory controller 315 may determine the timing for issuing the second activation command 595-a based on whether the row associated with the precharge command 525-a and the row associated with the second activation command 595-a are in the same subarray or different subarrays within the same memory cell. For example, the memory controller 315 may determine the delay between issuing the precharge command 525-a and issuing the second activation command 595-a based on whether the row associated with the precharge command 525-a and the row associated with the second activation command 595-a are in the same subarray or different subarrays. This may include, for example, selecting between tRP 570 and tRP_S 575. Figure 5 In the example described, the row associated with precharge command 525-a is in the first subarray 505, and the row associated with the second activation command 595-a is in the second subarray 580, and therefore the memory controller 315 can select tRP_S 575. In other examples, the row associated with the precharge command and the row associated with the subsequent activation command may be in the same subarray, and the memory controller 315 can select tRP 570, which in some cases may be referred to as the default tRP.

[0109] Figure 6 This describes an example of a command timeline 600 that supports parallel access to memory subarrays, as disclosed in this document. Figure 6 This describes instanced command signaling and instanced local and global signaling during access operations of two rows in two different subarrays within the same memory cell of a memory device, including phase and associated delays (e.g., the triggering of an internal operation relative to an associated command).

[0110] The memory device can receive commands from the memory controller. For example, regarding... Figure 4 and 5 The commands discussed can be examples of access operation commands, which may include activation commands, access commands, and precharge commands. These commands can be transmitted to the memory device via the CA bus 320-c.

[0111] The command may trigger (e.g., cause) the memory device to generate a global signal 605, which may indicate which subarray of a set of subarrays within the memory is active (e.g., any currently active global phase corresponds to that subarray). Thus, for example, when the memory device receives a precharge command 525-b, the memory device may have previously generated a global signal 610-a based on a previous activation command for the subarray targeted by the precharge command 525-b. When the global signal 610-a is high, this may indicate or otherwise correspond to the first activated subarray (targeted by the precharge command 525-b). The precharge command 525-b may represent a reference... Figure 5 The precharge command 525-a is described, and therefore the first subarray can be the first subarray 505.

[0112] As another example, when the memory device receives the second activation command 595-b, the memory device may generate a global signal 615-a. When the global signal 615-a is high, this may indicate or otherwise correspond to the activated subarray (the subarray for which the second activation command 595-b is directed). The second activation command 595-b may represent a reference... Figure 5 The second activation command 595 is described, and therefore the second subarray can be the second subarray 580.

[0113] In some cases, the memory device may maintain a global signal 605 (e.g., a global phase) on a per-bank basis (e.g., at the bank-level). Therefore, when global signal 615-a is triggered (e.g., goes high), global signal 610-a may be corrupted or otherwise prematurely interrupted (e.g., goes low). For example, a precharge command 525-b may be associated with a set of corresponding precharge phases (e.g., precharge phase 555) whose duration may correspond to a precharge signal delay 660-a, which may correspond to, as referenced... Figure 5 The described tRP 570. When the memory device receives the second activation command 595-b, if the second activation command 595-b is received based on tRP_S 575, then the global signal 610-a may go low before the precharge signal delay 660-a ends, as... Figure 5 and 6 As illustrated in the examples.

[0114] However, the memory device may use any number of first subarray local signals 620 to locally (e.g., using subarray-specific structures or processes, such as latch circuitry 345) copy and maintain the global signal 60 and any associated phase. For example, when or after generating the global signal 610-a of the first subarray, the memory device may also generate (e.g., by copying, latching) a localized global signal 625, which may be a copy of the globally generated global signal 610-a. The memory device may also generate (e.g., by copying, latching) a localized version of any global phase (not shown) associated with the global signal 610-a, which may be represented by instances of first phase 630-a, second phase 635, and third phase 640. The first phase 630-a may be an instance of a phase whose rising edge triggers a corresponding internal operation (e.g., a first internal operation included in a broader precharge operation) relative to a first phase delay 645-a of receiving the precharge command 525-b. The second phase 635 may be an instance of a phase signal whose falling edge triggers a corresponding internal operation (e.g., a second internal operation included in a broader precharge operation) with a second phase delay 650 relative to the received precharge command 525-b. The third phase 640 may be an instance of a phase signal whose pulse (e.g., a combination of rising and falling edges) triggers a corresponding internal operation (e.g., a third internal operation included in a broader precharge operation) with a third phase delay 655 relative to the received precharge command 525-b.

[0115] As in Figure 6 As illustrated in the example, even after the memory device receives the second activation command 595-b, the first subarray local signal 620 can still be maintained (e.g., it can continue to evolve and otherwise persist until completion). For example, even if the global signal 610-a drops prematurely (e.g., before the end of the precharge signal delay 660-a, before the duration of tRP 570) due to the receipt of the second activation command 595-b (e.g., at a time based on tRP_S 575), the localized global signal 625 does not drop until the end of the precharge signal delay 660-a, and even after the second activation command 595-b has been received, internal operations associated with the corresponding phases (e.g., phases 630-a, 635, 640) can still be triggered at an appropriate time (e.g., with an appropriate delay relative to the precharge command 525-b) (e.g., by one or more changes in the associated phase signals).

[0116] Figure 7 This describes an example of a command timeline 700 that supports parallel access to memory subarrays, as disclosed herein. Figure 7This describes instanced command signaling and instanced local and global signaling during access operations of three rows in three different subarrays within the same memory cell of a memory device, including phase and associated delays (e.g., the triggering of an internal operation relative to an associated command).

[0117] CA bus 320-d, precharge command 525-c, second activation command 595-c, ​​global signal 705 (e.g., first subarray global signal 610-b, second subarray global signal 615-b, and third subarray global signal 745), and first subarray local signal 710 may be similar to or the same as those referenced. Figure 6 The described CA bus 320-c, precharge command 525-b, second activation command 595-b, global signal 605 (e.g., global signal 610-a and global signal 615-a), and first subarray local signal 620. In some instances, when or after generating the global signal 610-b for the first subarray, the memory device may also have generated (e.g., by copying or latching) a first localized global signal 625-b, which may be a copy (replica) of the globally generated global signal 610-b.

[0118] Figure 7 An example can be illustrated where the memory device receives the second precharge command 715 after the second activation command 595-c and before the first precharge signal delay 660-b ends (e.g., before the tRP 570 time associated with the precharge command 525-c).

[0119] like Figure 7As shown, when the memory device receives the second activation command 595-c, ​​the second subarray global signal 615-b can be triggered (e.g., go high), and the global signal 610-b can be corrupted or otherwise prematurely interrupted (e.g., go low). However, the first subarray local signal 710 persists (e.g., maintained within or locally for the first subarray). Similarly, when the second precharge command 715 is received, the first subarray local signal 710 persists (e.g., maintained within or locally for the first subarray). Therefore, even if both the second activation command 595-c and the second precharge command 715 of the second subarray in the same memory bank are received before the associated precharge operation is completed (e.g., before closing rows in the first subarray), the first subarray local signal 710 will persist for the entire first precharge signal delay 660-b. For example, even if the global signal 610-b drops prematurely due to the receipt of the second activation command 595-c (e.g., before the precharge signal delay 660-b ends), the localized global signal 625-b does not drop until the precharge signal delay 660-b ends, and even after the receipt of the second activation command 595-c, ​​the internal operation associated with the corresponding phase (e.g., the first phase 630-b) can be triggered at an appropriate time (e.g., by one or more changes in the associated phase signal) (e.g., with an appropriate delay relative to the precharge command 525-c). For example, the first phase 630-b may be an instance of a phase for which the rising edge of the phase signal triggers the corresponding internal operation (e.g., a first internal operation included in a broader precharge operation), having a first phase delay 645-b relative to the receipt of the precharge command 525-c.

[0120] Furthermore, during or after the generation of the second subarray global signal 615-b, the memory device may also generate (e.g., by copying, latching) a second localized global signal 717, which may be a copy of the globally generated second subarray global signal 615-b. The memory device may also generate (e.g., by copying, latching) a localized version of any global phase (not shown) associated with the second subarray global signal 615-b, which may be represented by an instance of a second phase 720, which may be one of any number of phases included in the second subarray local signal 735. The second phase 720 may be an instance of a phase signal whose rising edge triggers a corresponding internal operation (e.g., an internal operation included in a broader precharge operation) relative to a second phase delay 725 of receiving the second precharge command 715.

[0121] As in Figure 7As illustrated in the example, even after the memory device receives the third activation command 740, the second subarray local signal 735 can be maintained (e.g., it can continue to evolve and otherwise persist until completion). For example, even if the second subarray global signal 615-b drops prematurely (e.g., before the end of the second precharge signal delay 730, before the duration of tRP570 relative to the second precharge command 715) due to the receipt of the third activation command 740 (e.g., at a time based on tRP_S 575), the second localized global signal 717 does not drop until the end of the second precharge signal delay 730, and even after the third activation command 740 has been received, internal operations associated with the corresponding phase (e.g., the second phase 720) can be triggered at an appropriate time (e.g., with an appropriate delay relative to the second precharge command 715).

[0122] Therefore, typically, by replicating or otherwise maintaining the phase associated with a specific operation of a subarray on a per-subarray basis (e.g., locally within the respective subarray), any number of commands can be received and the corresponding phases of other subarrays (even other subarrays within the same memory) can be triggered without adversely affecting the ongoing operations (e.g., phases and associated internal operations) of previously activated subarrays in the memory.

[0123] Figure 8 A block diagram 800 illustrates a memory device 805 supporting parallel access to a memory subarray according to an example disclosed herein. The memory device 805 may be as described in the references... Figures 3 to 7 Examples of aspects of the described memory device. Memory device 805 may include command component 810, precharge manager 815, row close module 820, row open module 825, timing signal generator 830, timing signal manager 835, latch component 840, and phase signal manager 845. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0124] Command component 810 may receive at the memory device a first activation command to enable a first memory cell row in a first subarray of the memory bank. In some instances, command component 810 may receive at the memory device a second activation command to enable a second memory cell row in a second subarray of the memory bank before disabling the first memory cell row in the first subarray of the memory bank. In some cases, command component 810 may receive at the memory device a third activation command to enable a third memory cell row in a third subarray of the memory bank. In some aspects, command component 810 may receive at the memory device a fourth activation command to enable a fourth memory cell row in a third subarray of the memory bank, wherein the fourth activation command is received within a second time period after receiving the third precharge command, the second time period being longer than the first time period. In some examples, the first time period includes tRP_S and the second time period includes default tRP.

[0125] The precharge manager 815 may receive a precharge command to close a first memory cell row at the memory device after receiving a first activation command. In some instances, the precharge manager 815 may receive a second precharge command to close a second memory cell row at the memory device after receiving a second activation command. In some aspects, the precharge manager 815 may receive a third precharge command to close a third memory cell row at the memory device.

[0126] The row shutdown module 820 may shut down the first memory cell row after receiving a second activation command, based on the receipt of a precharge command. In some instances, the row shutdown module 820 may shut down the first memory cell row after receiving the second activation command, based on maintaining the set of timing signals. In some aspects, the row shutdown module 820 may shut down the first memory cell row after a second delay following the receipt of the precharge command, the second delay being based on a second set of phase signals.

[0127] The row opening module 825 can open a first memory cell row based on a first activation command, wherein a second activation command is received when the first memory cell row is opened. In some instances, the row opening module 825 can open the first memory cell row after a first delay following the receipt of the first activation command, the first delay being based on a first set of phase signals. In some aspects, the row opening module 825 can open a second memory cell row after a third delay following the receipt of the second activation command, the third delay being based on a third set of phase signals.

[0128] The timing signal generator 830 can generate a set of timing signals to shut down the first memory cell row based on the received precharge command.

[0129] The timing signal manager 835 can maintain the set of timing signals after receiving a second activation command. In some instances, the timing signal manager 835 can maintain the set of timing signals after receiving a second precharge command.

[0130] The latching component 840 can latch the set of timing signals into the first subarray after receiving a precharge command.

[0131] The phase signal manager 845 can trigger a first set of phase signals at the memory device based on receiving a first activation command, the first set of phase signals being used to enable a first memory cell row. In some instances, the phase signal manager 845 can trigger a second set of phase signals at the memory device based on receiving a precharge command, the second set of phase signals being used to disable the first memory cell row. In some instances, the phase signal manager 845 can trigger a third set of phase signals at the memory device based on receiving a second activation command, the third set of phase signals being used to enable a second memory cell row.

[0132] Figure 9 A block diagram 900 illustrates a host device 905 supporting parallel access to a memory subarray according to an example disclosed herein. The host device 905 may be as described in the references... Figures 3 to 7 Examples of aspects of the described host device. Host device 905 may include command transmitter 910, precharge transmitter 915, access component 920, timing component 925, and selection manager 930. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0133] Command transmitter 910 can transmit a first activation command to the memory device in a first memory cell row of a first subarray of the memory bank. In some instances, command transmitter 910 can transmit a second activation command to the memory device after a predetermined time.

[0134] The precharge transmitter 915 can transmit a first precharge command to close the first memory cell row to the memory device after transmitting the first activation command of the first row.

[0135] Access component 920 can determine a second memory cell row in a second subarray of the memory bank.

[0136] Timing component 925 can determine the timing for transmitting a second activation command to enable the second row based on the fact that the second row is in the second subarray and the first row is in the first subarray. In some instances, timing component 925 can determine the timing for transmitting the second activation command based on a first time delay associated with consecutive access to rows within the same subarray and a second time delay for consecutive access to rows within different subarrays of the memory, where the first time delay is longer than the second time delay. In some cases, when the first and second subarrays are the same, the determined time corresponds to a default precharge time. In some examples, when the first and second subarrays are different, the determined time corresponds to tRP_S.

[0137] The selection manager 930 can select a row tRP for a second activation command, wherein the selection is between a first tRP for continuous access to rows within the same subarray and a second tRP for continuous access to rows within different subarrays of the memory, the second tRP being shorter than the first tRP.

[0138] Figure 10 A flowchart illustrating one or more methods 1000 supporting parallel access to a memory subarray according to aspects of this disclosure is provided. Operation of method 1000 may be implemented by a memory device or its components as described herein. For example, operation of method 1000 may be performed by, as referenced... Figure 8 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0139] At 1005, the memory device may receive a first activation command to open a first memory cell row in a first subarray of the memory bank. Operation 1005 may be performed according to the method described herein. In some instances, aspects of operation 1005 may be provided by reference to [reference needed]. Figure 8 The command component described is used to execute it.

[0140] At 1010, the memory device may receive a precharge command to close the first memory cell row after receiving a first activation command. Operation 1010 may be performed according to the method described herein. In some instances, aspects of operation 1010 may be provided by reference to [reference needed]. Figure 8 The precharge manager described is used to perform this.

[0141] At point 1015, the memory device may receive a second activation command to enable a second memory cell row in a second subarray of the memory bank before closing a first memory cell row in a first subarray of the memory bank. Operation 1015 may be performed according to the methods described herein. In some instances, aspects of operation 1015 may be provided by reference to [reference needed]. Figure 8The command component described is used to execute it.

[0142] In some instances, the device as described herein may perform a method or methods, such as method 1000. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving at a memory device a first activation command to enable a first memory cell row in a first subarray of the memory bank; receiving at a memory device a precharge command to disable the first memory cell row after receiving the first activation command; and receiving at a memory device a second activation command to enable a second memory cell row in a second subarray of the memory bank before disabling the first memory cell row in the first subarray of the memory bank.

[0143] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for shutting down a first memory cell row based on a received precharge command after receiving a second activation command.

[0144] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for opening a first memory cell row based on a first activation command (where a second activation command may be received when the first memory cell row is openable).

[0145] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: generating a set of timing signals to shut down a first memory cell row based on receiving a precharge command; maintaining the set of timing signals after receiving a second activation command; and shutting down the first memory cell row based on maintaining the set of timing signals after receiving the second activation command.

[0146] In some instances of the method 1000 and apparatus described herein, maintaining the set of timing signals may include operations, features, components, or instructions for latching the set of timing signals into a first subarray after receiving a precharge command.

[0147] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for receiving a second precharge command to close a second memory cell row at a memory device after receiving a second activation command and for maintaining the set of timing signals after receiving the second precharge command.

[0148] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: receiving at a memory device a third activation command to enable a third memory cell row in a third subarray of the memory bank; receiving at a memory device a third precharge command to disable the third memory cell row; and receiving at a memory device a fourth activation command to enable a fourth memory cell row in a third subarray of the memory bank, wherein the fourth activation command may be received within a second time period after the third precharge command can be received, the second time period being longer than the first time period.

[0149] In some instances of the method 1000 and device described herein, the first time quantity includes tRP_S and the second time quantity includes the default tRP.

[0150] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: triggering a first set of phase signals at the memory device based on receiving a first activation command, the first set of phase signals being used to open a first memory cell row; triggering a second set of phase signals at the memory device based on receiving a precharge command, the second set of phase signals being used to close the first memory cell row; and triggering a third set of phase signals at the memory device based on receiving a second activation command, the third set of phase signals being used to open a second memory cell row.

[0151] Some examples of the method 1000 and apparatus described herein may further include operations, features, components, or instructions for: opening a first memory cell row after a first delay following the receipt of a first activation command, the first delay being based on a first set of phase signals; closing the first memory cell row after a second delay following the receipt of a precharge command, the second delay being based on a second set of phase signals; and opening a second memory cell row after a third delay following the receipt of a second activation command, the third delay being based on a third set of phase signals.

[0152] Figure 11 The illustration shows a flowchart of one or more methods 1100 supporting parallel access to a memory subarray according to aspects of this disclosure. Operation of method 1100 may be implemented by a memory device or its components as described herein. For example, operation of method 1100 may be performed as described in reference... Figure 8 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0153] At 1105, the memory device may receive a first activation command at the memory device to open a first memory cell row in a first subarray of the memory bank. Operation 1105 may be performed according to the method described herein. In some instances, aspects of operation 1105 may be provided by reference to [reference needed]. Figure 8 The command component described is used to execute it.

[0154] At 1110, the memory device can open the first memory cell row based on a first activation command. Operation 1110 can be performed according to the methods described herein. In some instances, aspects of operation 1110 can be derived from, as referenced... Figure 8 The described line enables the module to be executed.

[0155] At 1115, the memory device may receive a precharge command to close the first memory cell row after receiving the first activation command. Operation 1115 may be performed according to the method described herein. In some instances, aspects of operation 1115 may be provided by reference to [reference needed]. Figure 8 The precharge manager described is used to perform this.

[0156] At 1120, the memory device may receive a second activation command at the memory device to enable a second memory cell row in a second subarray of the memory bank when the first memory cell row is enabled. Operation 1120 may be performed according to the methods described herein. In some instances, aspects of operation 1120 may be provided by reference to [reference needed]. Figure 8 The command component described is used to execute it.

[0157] At 1125, the memory device may shut down the first memory cell row based on the receipt of a precharge command after receiving a second activation command. Operation 1125 may be performed according to the method described herein. In some instances, aspects of operation 1125 may be provided by reference to [reference needed]. Figure 8 The described line closes the module to execute.

[0158] Figure 12 The illustration shows a flowchart of one or more methods 1200 supporting parallel access to a memory subarray according to aspects of this disclosure. Operation of method 1200 can be implemented by a memory device or its components as described herein. For example, operation of method 1200 can be performed as described in reference... Figure 8 The described memory device is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0159] At 1205, the memory device may receive a first activation command at the memory device to open a first memory cell row in a first subarray of the memory bank. Operation 1205 may be performed according to the method described herein. In some instances, aspects of operation 1205 may be provided by reference to [reference needed]. Figure 8 The command component described is used to execute it.

[0160] At 1210, the memory device may receive a precharge command to close the first memory cell row after receiving the first activation command. Operation 1210 may be performed according to the method described herein. In some instances, aspects of operation 1210 may be provided by reference to [reference needed]. Figure 8 The precharge manager described is used to perform this.

[0161] At 1215, the memory device may generate a set of timing signals to shut down the first memory cell row based on the receipt of a precharge command. Operation 1215 may be performed according to the method described herein. In some instances, aspects of operation 1215 may be derived from, as referenced... Figure 8 The timing signal generator described is used to perform this.

[0162] At 1220, the memory device may receive a second activation command at the memory device to enable a second memory cell row in a second subarray of the memory bank before closing a first memory cell row in a first subarray of the memory bank. Operation 1220 may be performed according to the methods described herein. In some instances, aspects of operation 1220 may be provided by reference to [reference needed]. Figure 8 The command component described is used to execute it.

[0163] At 1225, the memory device may maintain the set of timing signals after receiving a second activation command. Operation 1225 may be performed according to the methods described herein. In some instances, aspects of operation 1225 may be provided by reference to [reference needed]. Figure 8 The timing signal manager described is used to execute this.

[0164] At 1230, the memory device may shut down the first memory cell row based on maintaining the set of timing signals after receiving the second activation command. Operation 1230 may be performed according to the methods described herein. In some instances, aspects of operation 1230 may be provided by reference to [reference needed]. Figure 8 The described line closes the module to execute.

[0165] Figure 13 The illustration shows a flowchart of one or more methods 1300 supporting parallel access to a memory subarray according to aspects of this disclosure. Operation of method 1300 can be implemented by a host device or its components as described herein. For example, operation of method 1300 can be performed by, as referenced... Figure 9The described host device is used to execute the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0166] At 1305, the host device may transmit a first activation command to the memory device to enable a first memory cell row in a first subarray of the memory bank. Operation 1305 may be performed according to the method described herein. In some instances, aspects of operation 1305 may be provided by reference to [reference needed]. Figure 9 The command transmitter described is used to execute the command.

[0167] At 1310, the host device may transmit a first precharge command to close the first memory cell row to the memory device after transmitting the first activation command for the first row. Operation 1310 may be performed according to the method described herein. In some instances, aspects of operation 1310 may be provided by reference to [reference needed]. Figure 9 The precharge transmitter described is used to perform this.

[0168] At 1315, the host device may determine a second memory cell row in a second subarray of the memory bank. Operation 1315 may be performed according to the method described herein. In some instances, aspects of operation 1315 may be provided by, as referenced Figure 9 The described access components are used to execute this.

[0169] At 1320, the host device can determine the timing of transmitting the second activation command to open the second row based on the fact that the second row is in the second subarray and the first row is in the first subarray. Operation 1320 can be performed according to the method described herein. In some instances, aspects of operation 1320 can be derived from, as referenced... Figure 9 The described timing components are used for execution.

[0170] At 1325, the host device may transmit a second activation command to the memory device at a predetermined time. Operation 1325 may be performed according to the method described herein. In some instances, aspects of operation 1325 may be provided by reference to [reference needed]. Figure 9 The command transmitter described is used to execute the command.

[0171] In some instances, the device as described herein may perform a method or methods, such as method 1300. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting a first activation command to a memory device for enabling a first memory cell row in a first subarray of a memory bank; transmitting a first precharge command to a memory device for disabling the first memory cell row after transmitting the first activation command for the first row; determining access to a second memory cell row in a second subarray of the memory bank; determining a time for transmitting a second activation command to enable a second row based on the second row being in the second subarray and the first row being in the first subarray; and transmitting the second activation command to the memory device at the determined time.

[0172] In some instances of the method 1300 and apparatus described herein, determining the timing of transmitting the second activation command may include operations, features, components, or instructions for selecting a tRP for the second activation command (wherein the selection may be between a first tRP for consecutive access to rows within the same subarray and a second tRP for consecutive access to rows within different subarrays of the memory, the second tRP being shorter than the first tRP).

[0173] Some examples of the method 1300 and apparatus described herein may further include operations, features, components, or instructions for determining the time of transmitting a second activation command (the first time delay being longer than the second time delay) based on a first time delay associated with consecutive access to rows within the same subarray and a second time delay associated with consecutive access to rows within different subarrays of the memory.

[0174] In some instances of the method 1300 and device described herein, when the first subarray and the second subarray may be the same, the determined time corresponds to a default precharge time (e.g., tRP), and when the first subarray and the second subarray may be different, the determined time corresponds to a shortened precharge time (e.g., tRP_S).

[0175] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, parts from two or more methods can be combined.

[0176] Describe an apparatus. The apparatus may include: a memory bank of a memory device, the memory bank including a first subarray and a second subarray; a command component of the memory device, the command component being configured to receive commands from the first subarray and commands from the second subarray, wherein the command from the first subarray triggers timing signals of the first subarray, and wherein the command from the second subarray triggers timing signals of the second subarray; and a first latch circuit configured to maintain the timing signals of the first subarray independently of the commands from the second subarray.

[0177] In some instances, the memory device supports a first tRP for continuous access to different memory cell rows within the same subarray and a second tRP for continuous access to memory cell rows within different subarrays of the memory bank.

[0178] In some instances, the second tRP may be shorter than the first tRP.

[0179] Some instances of the device may include timing components that are used in the memory device and configured to generate timing signals for the first subarray and timing signals for the second subarray.

[0180] In some instances, the first subarray includes the first latch circuit.

[0181] Some instances of the device may include a second latch circuit configured to maintain the timing signals of the second subarray independently of the commands of the first subarray.

[0182] In some instances, the second subarray includes the second latch circuit.

[0183] Some instances of the device may include a set of latching circuits, the set of latching circuits including a first latching circuit and a second latching circuit for the second subarray, wherein each of the set of latching circuits is configured to maintain the timing signals of the respective subarray independently of commands from other subarrays.

[0184] Some instances of the device may include a set of storage units, each of which may be coupled to the command component and include multiple subarrays, the command component being configured to receive commands from each of the storage units.

[0185] In some instances, the memory device includes the set of memory cells, and each of the plurality of subarrays includes a corresponding latch circuit.

[0186] In some instances, the command includes activation commands, access commands (e.g., read commands, write commands), precharge commands, or any combination thereof.

[0187] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have multiple bit widths.

[0188] Furthermore, while DRAM architecture and terminology may be used in this document to describe specific aspects, these are merely illustrative examples, and the teachings herein can be applied to any type of memory device, including (but not limited to) FeRAM memory devices.

[0189] The terms "electronic communication," "conductive contact," "connected," and "coupled" refer to a relationship between components that supports signal flow between them. Components are considered to be in electronic communication (or electrically connected, connected, or coupled) with each other if any conductive path exists between them to support signal flow at any given time. At any given time, the conductive path between components that are in electronic communication (or electrically connected, connected, or coupled) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, signal flow between connected components may be interrupted for a period of time using one or more intermediate components (e.g., switches or transistors).

[0190] The term "coupling" refers to the condition of moving from an open-circuit relationship between components (where signals cannot currently travel between components via a conductive path) to a closed-circuit relationship between components (where signals can travel between components via a conductive path). When a component (e.g., a controller) is coupled to other components, the component initiates a change to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0191] The term "isolated" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it creates a change that prevents signals from flowing between the components using a previously permitted conductive path.

[0192] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0193] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0194] The descriptions presented herein, in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and not "preferred" or "superior to other examples." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described examples.

[0195] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second reference numeral to differentiate similar components. When only the first reference label is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference label.

[0196] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0197] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Moreover, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one" or "one or more") indicates a list of items, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0198] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method implemented by a memory device, comprising: The memory device receives a first activation command to enable a first memory cell row in a first subarray of the memory bank; After receiving the first activation command, a precharge command to close the first memory cell row is received at the memory device; At the first subarray and at least in part based on receiving the precharge command, a first set of timing signals is generated to shut down the first memory cell row; Before closing the first memory cell row in the first subarray of the memory bank, a second activation command is received at the memory device to open the second memory cell row in the second subarray of the memory bank; At the second subarray, and at least in part based on receiving the second activation command, a second set of timing signals is generated to enable the second memory cell row; and After receiving the second activation command, the first set of timing signals is maintained at the first subarray.

2. The method according to claim 1, further comprising: Upon receiving the second activation command, the first memory cell row is shut down at least in part based on the receipt of the precharge command.

3. The method according to claim 1, further comprising: The first memory cell row is opened at least in part based on the first activation command, wherein the second activation command is received when the first memory cell row is opened.

4. The method of claim 1, further comprising: Upon receiving the second activation command, the first memory cell row is turned off at least in part based on maintaining the first set of timing signals at the first subarray.

5. The method of claim 4, wherein maintaining the first set of timing signals at the first subarray after receiving the second activation command comprises: After receiving the precharge command, the first set of timing signals is latched into the first subarray.

6. The method of claim 5, further comprising: After receiving the second activation command, a second precharge command to close the second memory cell row is received at the memory device; and The first set of timing signals is maintained after receiving the second precharge command.

7. A method implemented by a memory device, comprising: The memory device receives a first activation command to enable a first memory cell row in a first subarray of the memory bank; After receiving the first activation command, a precharge command to close the first memory cell row is received at the memory device; Before closing the first memory cell row in the first subarray of the memory bank, a second activation command is received at the memory device to open the second memory cell row in the second subarray of the memory bank. The second activation command is received within a first time period after the pre-charge command is received; A third activation command is received at the memory device to enable the third memory cell row in the third subarray of the memory bank; A third precharge command to close the third memory cell row is received at the memory device; and A fourth activation command is received at the memory device to activate a fourth memory cell row in the third subarray of the memory bank, wherein the fourth activation command is received within a second time period after the third precharge command is received, the second time period being longer than the first time period.

8. The method of claim 7, wherein the first time quantity includes a shortened row precharge time tRP_S and the second time quantity includes a default row precharge time tRP.

9. A method implemented by a memory device, comprising: The memory device receives a first activation command to enable a first memory cell row in a first subarray of the memory bank; After receiving the first activation command, a precharge command to close the first memory cell row is received at the memory device; Before closing the first memory cell row in the first subarray of the memory bank, a second activation command is received at the memory device to open the second memory cell row in the second subarray of the memory bank; At least in part based on receiving the first activation command, a first set of phase signals is triggered at the memory device to open the first memory cell row; At the memory device, a second set of phase signals is triggered at least in part based on the receipt of the precharge command, the second set of phase signals being used to shut down the first memory cell row; and At the memory device, a third set of phase signals is triggered at least in part based on the receipt of the second activation command, the third set of phase signals being used to activate the second memory cell row.

10. The method of claim 9, further comprising: The first memory cell row is opened after a first delay following the receipt of the first activation command, the first delay being at least partially based on the first set of phase signals; The first memory cell row is shut down after a second delay following the receipt of the precharge command, the second delay being at least partially based on the second set of phase signals; and The second memory cell row is activated after a third delay following the receipt of the second activation command, the third delay being at least partially based on the third set of phase signals.

11. A memory device comprising: A memory device having a storage body, the storage body comprising a first subarray and a second subarray; The command component of the memory device is configured to receive commands from the first subarray and commands from the second subarray, wherein the command of the first subarray triggers a first set of timing signals of the first subarray based at least in part on an activation command to enable a first memory cell row and a precharge command to disable a first memory cell row, wherein the command of the second subarray triggers a second set of timing signals of the second subarray, and wherein the first set of timing signals is used to disable the first memory cell row and the second set of timing signals is used to enable the second memory cell row; and A first latch circuit is configured to maintain the first set of timing signals of the first subarray independently of the commands of the second subarray.

12. The memory device of claim 11, wherein the memory device supports a first row precharge time tRP for continuous access to different memory cell rows within the same subarray and a second tRP for continuous access to memory cell rows within different subarrays of the memory bank.

13. The memory device of claim 12, wherein the second tRP is shorter than the first tRP.

14. The memory device of claim 11, further comprising: A timing component for the memory device and configured to generate the first set of timing signals for the first subarray and the second set of timing signals for the second subarray.

15. The memory device of claim 11, wherein the first subarray includes the first latch circuit.

16. The memory device of claim 11, further comprising: A second latch circuit is configured to maintain the second set of timing signals for the second subarray independently of the commands of the first subarray.

17. The memory device of claim 16, wherein the second subarray includes the second latch circuit.

18. The memory device of claim 11, further comprising: A set of latching circuits, comprising a first latching circuit and a second latching circuit for a second subarray, wherein each of the set of latching circuits is configured to maintain the timing signals of the respective subarray independently of commands from other subarrays.

19. The memory device of claim 11, further comprising: A set of storage units comprising the storage units, wherein each of the storage units is coupled to the command component and includes a plurality of subarrays, the command component being configured to receive commands from each of the storage units.

20. The memory device of claim 19, wherein the memory device includes the set of memory cells, and each of the plurality of subarrays includes a corresponding latch circuit.

21. The memory device of claim 11, wherein the command of the first subarray or the command of the second subarray includes an activation command, a read command, a write command, a precharge command, or any combination thereof.

22. A method implemented by a host device, comprising: A first activation command is transmitted to the memory device to enable the first memory cell row in the first subarray of the memory bank of the memory device. After transmitting the first activation command of the first memory cell row, a first precharge command to close the first memory cell row is transmitted to the memory device. Determine the second memory cell row in the second subarray of the memory bank; The timing for transmitting the second activation command to enable the second memory cell row is determined at least in part based on the fact that the second memory cell row is in the second subarray and the first memory cell row is in the first subarray; and The second activation command is transmitted to the memory device at a predetermined time, wherein determining the time for transmitting the second activation command includes selecting a row precharge time tRP for the second activation command, wherein the selection is between a first tRP for continuous access to rows within the same subarray and a second tRP for continuous access to rows within different subarrays of the memory, the second tRP being shorter than the first tRP.

23. The method of claim 22, further comprising: The time for transmitting the second activation command is determined at least in part based on a first time delay associated with consecutive access to rows within the same subarray and a second time delay for consecutive access to rows within different subarrays of the memory, wherein the first time delay is longer than the second time delay.

24. The method of claim 22, wherein: When the first subarray and the second subarray are the same, the determined time corresponds to the default precharge time; and When the first subarray and the second subarray are different, the determined time corresponds to the shortened precharge time.

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