Display device and its operation method

Abstract

A display device and a method of operating the display device are provided. The display device may include: a first transistor controlled by a first control signal to connect an input terminal to which an input voltage is applied and a first node; a second transistor controlled by a second control signal to output a power supply voltage thereto and connected to the first node; an overcharge identification circuit configured to receive a first reference voltage, a feedback voltage, and a second reference voltage to determine whether the circuit is overcharged and to output an overcharge identification signal; and a discharge circuit configured to provide a first discharge path for discharging the power supply voltage based on an enable signal generated according to the overcharge identification signal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0123186, filed with the Korean Intellectual Property Office on September 23, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to display devices and methods of operating display devices. More specifically, this disclosure relates to display devices capable of improving visual recognition of changes in screen brightness. Background Technology

[0003] Flat panel displays such as liquid crystal displays, plasma displays, and electroluminescent displays are under development. Specifically, electroluminescent displays can be driven by light-emitting diodes (LEDs) or organic light-emitting diodes (OLEDs) that generate light through the recombination of electrons and holes, offering fast response times and low power consumption.

[0004] Organic light-emitting diodes (OLEDs) include an anode, a cathode, and an emitting layer between the anode and cathode, and emit light based on a current flowing from the anode to the cathode. In electroluminescent displays, the emission brightness is determined based on the driving current flowing through the OLED of each pixel, and high-brightness images require a larger driving current than low-brightness images.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background of the described technology, and therefore, the above information may contain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The described technology aims to provide a display device and a method of operating the display device that can improve visual recognition of screen brightness changes caused by voltage variations when the power supply voltage ELVSS is discharged.

[0007] The described technology aims to provide a display device capable of changing the discharge rate of the power supply voltage ELVSS and a method of operating the display device.

[0008] An example embodiment provides a display device, including: a first transistor controlled by a first control signal, wherein the first transistor is configured to connect an input terminal to which an input voltage is applied and a first node; a second transistor controlled by a second control signal, wherein the second transistor is configured to connect a second node to which a power supply voltage is output; an overcharge identification circuit configured to receive a first reference voltage, a feedback voltage, and a second reference voltage to determine whether the circuit is overcharged and to output an overcharge identification signal; and a discharge circuit configured to provide a first discharge path for discharging the power supply voltage based on an enable signal generated according to the overcharge identification signal.

[0009] The display device may further include an enable signal generating circuit configured to generate an enable signal by performing logic operations on an overcharge identification signal and an ELVSS high signal.

[0010] The overcharge identification circuit may include: an error amplifier configured to amplify the difference between a first reference voltage and a feedback voltage to output an error amplification output signal; and a comparator configured to output an overcharge identification signal by comparing the voltage level of the error amplification output signal with the voltage level of a second reference voltage.

[0011] When the feedback voltage level is higher than the first reference voltage level, the circuit can be identified as being in an overcharge state, thereby reducing the voltage level of the error amplification output signal. The comparator can also output an overcharge identification signal when the voltage level of the error amplification output signal is lower than the voltage level of the second reference voltage.

[0012] The display device may further include an inductor connected to the first node, wherein the discharge rate of the power supply voltage can be controlled by the operation of the discharge circuit when the panel load is within a predetermined range, and can be controlled by adjusting the number of charging and discharging cycles of the inductor when the panel load is outside the predetermined range.

[0013] Multiple intermediate target voltage levels can be set between the current voltage level of the power supply voltage and the target voltage level of the power supply voltage, and the discharge of the power supply voltage can be repeatedly performed according to the intermediate target voltage level.

[0014] The intermediate target voltage level can be set using the up-level code and the down-level code.

[0015] The display device may further include: a third transistor controlled by a third control signal, wherein the third transistor is used to connect the second node to a ground terminal; and a resistor configured to provide a second discharge path via the third transistor based on an enable signal.

[0016] An example embodiment provides a display device, including: a first transistor controlled by a first control signal, wherein the first transistor is configured to connect an input terminal to which an input voltage is applied and a first node; a second transistor controlled by a second control signal, wherein the second transistor is configured to connect a second node to which a power supply voltage is output; an overcharge identification circuit configured to receive a reference voltage and a feedback voltage to determine whether the circuit is overcharged and to output an overcharge identification signal; and a discharge circuit configured to provide a first discharge path for discharging the power supply voltage based on an enable signal generated according to the overcharge identification signal.

[0017] The overcharge detection circuit may include a comparator configured to output an overcharge detection signal by comparing the voltage level of a reference voltage with the voltage level of a feedback voltage.

[0018] When the feedback voltage level is lower than the reference voltage level, the circuit can be identified as being in an overcharge state, and the comparator can output an overcharge identification signal.

[0019] The display device may further include an inductor connected to the first node, wherein the discharge rate of the power supply voltage can be controlled by the operation of the discharge circuit when the panel load is within a predetermined range, and can be controlled by adjusting the number of charging and discharging cycles of the inductor when the panel load is outside the predetermined range.

[0020] Multiple intermediate target voltage levels can be set between the current voltage level of the power supply voltage and the target voltage level of the power supply voltage, and the power supply voltage can be discharged repeatedly according to the intermediate target voltage levels.

[0021] The intermediate target voltage level can be set using the up-level code and the down-level code.

[0022] The display device may further include: a third transistor controlled by a third control signal, wherein the third transistor is used to connect the second node to a ground terminal; and a resistor configured to provide a second discharge path via the third transistor based on an enable signal.

[0023] An example embodiment provides an operation method for a display device, including: receiving a value of a panel load; determining a value of the panel load; when the value of the panel load exceeds a threshold, charging an inductor of a power management integrated circuit (PMIC) and adjusting the number of charging and discharging cycles of the PMIC's inductor by controlling the discharge rate of the power supply voltage; and when the value of the panel load is less than or equal to the threshold, charging the inductor of the PMIC and adjusting the number of charging and discharging cycles of the PMIC's inductor by controlling the discharge rate of the power supply voltage through the PMIC's discharge circuit.

[0024] The discharge circuit can provide a first discharge path for discharging the power supply voltage based on an enable signal generated according to the overcharge identification signal.

[0025] The discharge circuit can be enabled by an enable signal generated by performing logic operations on the overcharge identification signal and the ELVSS high signal.

[0026] Controlling the discharge rate of the power supply voltage through a discharge circuit may include the step of controlling the discharge rate of the power supply voltage through a resistor in the PMIC.

[0027] Controlling the discharge rate of the power supply voltage through a discharge circuit can include setting multiple intermediate target voltage levels between the current voltage level of the power supply voltage and the target voltage level of the power supply voltage; and repeatedly discharging the power supply voltage based on the intermediate target voltage levels.

[0028] According to some example embodiments, when the power supply voltage ELVSS is discharged, it is possible not only to improve the phenomenon that the brightness change of the screen is visually identifiable due to the voltage change, but also to achieve discharge control of the power supply voltage ELVSS suitable for various frequencies such as 60Hz and 120Hz. Attached Figure Description

[0029] Figure 1 A block diagram illustrating a display device according to an example embodiment is shown.

[0030] Figure 2 This is a circuit diagram used to describe a power management integrated circuit (PMIC) of a display device according to an example embodiment.

[0031] Figure 3 The figure illustrates a timing diagram for describing the variation of the power supply voltage ELVSS in a display device according to an example embodiment.

[0032] Figure 4 The figure illustrates a timing diagram for describing the variation of the power supply voltage ELVSS in a display device according to an example embodiment.

[0033] Figure 5 The figure illustrates a timing diagram of an example implementation for changing the power supply voltage ELVSS in a display device according to an example embodiment.

[0034] Figure 6 The figure illustrates a timing diagram of an example implementation for changing the power supply voltage ELVSS in a display device according to an example embodiment.

[0035] Figure 7 The figure illustrates a timing diagram of an example implementation for changing the power supply voltage ELVSS in a display device according to an example embodiment.

[0036] Figure 8 , Figure 9 and Figure 10 The illustration shows an example view for describing specifications that can be set in a display device according to an example embodiment.

[0037] Figure 11 The illustration shows a flowchart illustrating an operation method of a display device according to an example embodiment.

[0038] Figure 12The figure illustrates a circuit diagram of a power management integrated circuit for a display device according to an example embodiment.

[0039] Figure 13 The figure illustrates a circuit diagram of a power management integrated circuit for a display device according to an example embodiment.

[0040] Figure 14 The figure illustrates a circuit diagram of a power management integrated circuit for a display device according to an example embodiment. Detailed Implementation

[0041] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0042] For the sake of clarity in describing this disclosure, parts irrelevant to the description have been omitted, and throughout the specification, the same numbers refer to the same or similar constituent elements.

[0043] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses illustrated. In the drawings, the thicknesses of layers, films, panels, areas, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and areas are exaggerated for better understanding and ease of description.

[0044] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or an intervening element may be present. Conversely, when an element is referred to as being "directly" on another element, no intervening element is present. Furthermore, in the specification, the terms "on" or "above" mean placed on or below the object portion, and not necessarily placed on the upper side of the object portion based on the direction of gravity.

[0045] In addition, unless explicitly stated otherwise, the words “including” and variations shall be understood to mean including the stated elements, but not excluding any other elements.

[0046] Furthermore, in the instruction manual, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a cross-sectional view" means when viewing a section taken by vertically cutting through a portion of the object from the side.

[0047] Figure 1 A block diagram illustrating a display device according to an example embodiment is shown.

[0048] refer to Figure 1The display device according to the example embodiment may be an organic light-emitting display, but the scope of this disclosure is not limited thereto. In this example embodiment, the display device may include a power management integrated circuit 100, a pixel unit 120, a scan driver 130, a data driver 140, and a controller 150.

[0049] Pixel unit 120 may include one or more pixels 110 connected to one or more scan lines S1 to Sn and one or more data lines D1 to Dm.

[0050] Each pixel 110 includes a pixel circuit (not shown) connected to an organic light-emitting diode (OLED), a data line Dm, and a scan line Sn to control the OLED. The anode of the OLED is connected to the pixel circuit, and the cathode is connected to a power supply voltage ELVSS. Such an OLED produces light of a predetermined brightness in response to a current supplied from the pixel circuit. The pixel circuit includes elements, such as transistors and capacitors, for controlling the amount of current supplied to the OLED in response to a data signal supplied to the data line Dm when a scan signal is supplied to the scan line Sn.

[0051] The scan driver 130 can supply scan signals to each pixel 110 through one or more scan lines S1 to Sn. The data driver 140 can supply data signals to each pixel 110 through one or more data lines D1 to Dm.

[0052] The power management integrated circuit 100 can supply power supply voltages ELVDD and ELVSS to each pixel 110. Specifically, the power management integrated circuit 100 receives an input voltage Vin, converts the received input voltage Vin, and generates power supply voltages ELVDD and ELVSS to be supplied to each pixel 110. The power supply voltage ELVDD can be a positive voltage, the power supply voltage ELVSS can be a negative voltage, and the input voltage Vin can be supplied by a battery 160 charged with a predetermined amount of power.

[0053] Each pixel 110 of the pixels 110 that has received power supply voltages ELVDD and ELVSS from the power management integrated circuit 100 can generate light corresponding to the data signal based on the current flowing from power supply voltage ELVDD to power supply voltage ELVSS via an organic light-emitting diode.

[0054] The controller 150 can control the scan driver 130 and the data driver 140. The scan driver 130, under the control of the controller 150, can generate scan signals and supply the generated scan signals to one or more scan lines S1 to Sn. The data driver 140, under the control of the controller 150, can generate data signals and supply the generated data signals to one or more data lines D1 to Dm. When scan signals are sequentially supplied to one or more scan lines S1 to Sn, pixels 110 can be sequentially selected for each line, and the selected pixels 110 can receive data signals transmitted from one or more data lines D1 to Dm.

[0055] In the following description, an example embodiment will be described by focusing on the power management integrated circuit 100 and the power supply voltage ELVSS supplied from the power management integrated circuit 100 to the pixel 110.

[0056] Figure 2 The figure illustrates a circuit diagram of a power management integrated circuit for a display device according to an example embodiment. The power management integrated circuit 1 of the display device according to the example embodiment can correspond to... Figure 1 100 power management integrated circuits.

[0057] refer to Figure 2 The power management integrated circuit 1 includes transistors M1, M2 and M3, inductor L, discharge circuit 10, enable signal generation circuit 20, overcharge identification circuit 30 and control circuit 40.

[0058] Transistor M1 can be arranged between the input terminal to which the input voltage Vin is applied and node N1. That is, the first electrode of transistor M1 can be connected to the input terminal to which the input voltage Vin is applied, and the second electrode of transistor M1 can be connected to node N1. Transistor M1 can be controlled by a control signal O1 supplied from control circuit 40 to connect the input terminal to which the input voltage Vin is applied and node N1.

[0059] Transistor M2 can be positioned between node N1 and node N2 (or a second node) to which the power supply voltage ELVSS is output. That is, the first electrode of transistor M2 can be connected to node N1, and the second electrode of transistor M2 can be connected to node N2 to which the power supply voltage ELVSS is output. Transistor M2 can be controlled by a control signal O2 supplied from control circuit 40 to connect nodes N1 and N2.

[0060] Transistor M3 can be positioned between node N2 and the ground terminal. Specifically, the first electrode of transistor M3 can be connected to node N2 via resistor R_FD, and the second electrode of transistor M3 can be connected to the ground terminal. Transistor M3 can be controlled by a control signal O3 supplied from control circuit 40 to connect node N2 and the ground terminal.

[0061] The first terminal of inductor L can be connected to node N1, and the second terminal of inductor L can be connected to the ground terminal. When transistor M1 is turned on by control signal O1 and transistor M2 is turned off by control signal O2, the voltage applied to node N1 becomes the input voltage Vin, and inductor L is charged with a predetermined amount of energy. Conversely, when transistor M1 is turned off by control signal O1 and transistor M2 is turned on by control signal O2, the energy charged in inductor L can be transferred to the output terminal through which the power supply voltage ELVSS is output.

[0062] The control circuit 40 can compare the input voltage Vin and the power supply voltage ELVSS to selectively select one of a boost mode, a buck mode, and a buck-boost mode, and can control the on and off states of transistors M1, M2, and M3 based on the selected mode. That is, the control circuit 40 can control the on and off states of transistors M1, M2, and M3 by supplying control signals O1, O2, and O3, each with a pulse width adjusted based on each mode, to the gate electrodes of transistors M1, M2, and M3 respectively.

[0063] The discharge circuit 10 can provide a discharge path for discharging the power supply voltage ELVSS. That is, the discharge circuit 10 can provide a discharge path through which the power supply voltage ELVSS can be discharged via node N2, the discharge circuit 10, and the ground terminal. Depending on the operating conditions of the display device, the discharge circuit 10 can be implemented to operate by being activated or enabled when needed. For example, the discharge circuit 10 can provide a discharge path for discharging the power supply voltage ELVSS based on an enable signal EN. In this document, the enable signal EN can be generated based on the overcharge detection signal PSM_EN.

[0064] The discharge circuit 10 can be implemented using any electronic device capable of providing the aforementioned discharge path. For example, the discharge circuit 10 can be implemented as a circuit with any configuration including any electronic device such as resistors, transistors, and current sources, and has the function of activating operation upon receiving the enable signal EN.

[0065] The enable signal generation circuit 20 can supply an enable signal EN to the discharge circuit 10. That is, the enable signal generation circuit 20 can generate the enable signal EN by performing a logic operation on the overcharge identification signal PSM_EN and the ELVSS high signal ELVSS_High, and can supply the generated enable signal EN to the discharge circuit 10. In this document, the ELVSS high signal ELVSS_High can be a signal supplied from the driver IC of the display device to the power management integrated circuit 1, and the logic operation can include an AND logic operation, but the scope of this disclosure is not limited thereto. When the logic operation is an AND logic operation, that is, when both the overcharge identification signal PSM_EN and the ELVSS high signal ELVSS_High are logic high, the enable signal EN can be supplied to the discharge circuit 10 to operate the discharge circuit 10.

[0066] Figure 2 The internal structure of the enable signal generation circuit 20 shown is merely an example and may vary depending on the specific implementation purpose of this disclosure.

[0067] The overcharge detection circuit 30 can supply the overcharge detection signal PSM_EN to the enable signal generation circuit 20. That is, the overcharge detection circuit 30 can receive the first reference voltage ELVSS_Vref, the feedback voltage ELVSS_FB, and the second reference voltage PSM_Vref, determine whether the circuit is overcharged, and output the overcharge detection signal PSM_EN. Furthermore, it can supply the output overcharge detection signal PSM_EN to the enable signal generation circuit 20. In other words, when the overcharge detection circuit 30 detects that overcharging has occurred, it can operate the discharge circuit 10 through the enable signal generation circuit 20 to promote the discharge of the power supply voltage ELVSS.

[0068] In this example embodiment, the overcharge detection circuit 30 may include an error amplifier 32 and a comparator 34. The error amplifier 32 may amplify the difference between the first reference voltage ELVSS_Vref and the feedback voltage ELVSS_FB to output an error amplification output signal EAO. For example, when the voltage level of the feedback voltage ELVSS_FB is higher than the voltage level of the first reference voltage ELVSS_Vref, the circuit is determined to be in an overcharged state (e.g., where the target voltage is -4 V but the circuit is overcharged to -4.01 V), and the voltage level of the error amplification output signal EAO may be reduced. Conversely, when the voltage level of the feedback voltage ELVSS_FB is lower than the voltage level of the first reference voltage ELVSS_Vref, insufficient charge is determined (e.g., the target voltage is -4 V, but insufficient charge is found at -3.99 V), and the voltage level of the error amplification output signal EAO may be increased.

[0069] In the case of overcharge, comparator 34 can compare the voltage level of the error amplification output signal EAO with the voltage level of the second reference voltage PSM_Vref to output the overcharge identification signal PSM_EN. That is, when the voltage level of the error amplification output signal EAO is lower than the voltage level of the second reference voltage PSM_Vref, comparator 34 can output the overcharge identification signal PSM_EN.

[0070] As described above, if necessary, the discharge rate of the power supply voltage ELVSS can be adjusted and changed accordingly when the discharge circuit 10 configured to be activated or enabled for operation is used in the power management integrated circuit 1, based on the operating status of the display device.

[0071] exist Figure 2 In this context, "Vreg", "COUT", and "ILOAD" represent voltage, output terminal, and output terminal current, respectively.

[0072] Figure 3 The figure illustrates a timing diagram for describing the variation of the power supply voltage ELVSS in a display device according to an example embodiment.

[0073] refer to Figure 3 The tearing effect (TE) signal can be used to set the data voltage. When the voltage change of the power supply voltage ELVSS is not completed during the period when the TE signal is logic high, the brightness change is recognized by the user of the display panel.

[0074] In this example embodiment, when the display device is driven at 60 Hz, Figure 2 The power management integrated circuit 1 can provide multiple options, such as four voltage change time (VCT) options. That is, the power management integrated circuit 1 can support multiple options for discharging the power supply voltage ELVSS at different rates during the period when the TE signal is logic high by using the discharge circuit 10. In addition, in the power management integrated circuit 1, the power supply voltage ELVSS will not be discharged faster or slower depending on the size of the panel load; instead, the power supply voltage ELVSS can be discharged at a constant rate, independent of changes in the panel load and unaffected by the panel load.

[0075] exist Figure 3In the diagram, during the period when the TE signal is logic high, after the Vsync signal is changed to logic low and the I2C / SWIRE signal is applied, the power management integrated circuit 1 illustrates four options—Option 1, Option 2, Option 3, and Option 4—for raising the starting supply voltage ELVSS@Start to the target supply voltage ELVSS@Target. Option 1 provides the fastest discharge of the supply voltage ELVSS, and Option 4 provides the slowest discharge. However, it can be seen that even in the case of Option 4, the discharge of the supply voltage ELVSS can be completed before the end of the period when the TE signal is still logic high.

[0076] Figure 4 The figure illustrates a timing diagram for describing the variation of the power supply voltage ELVSS in a display device according to an example embodiment.

[0077] refer to Figure 4 In this example embodiment, the display device is driven at 120 Hz. In this case, Figure 2 The power management integrated circuit 1 can provide multiple options: Option 1, Option 2, Option 3, and Option 4. This is because when the drive rate of the display device increases from 60 Hz to 120 Hz, the length of the logic high period of the TE signal becomes shorter. Therefore, Option 1 provides the fastest discharge of the power supply voltage ELVSS, Options 1 and 2 correspond to areas where the user does not perceive changes in brightness, and Options 3 and 4 leave the discharge of the power supply voltage ELVSS outside the logic high period of the TE signal, and Options 3 and 4 correspond to areas where the user perceives changes in brightness.

[0078] exist Figure 3 and Figure 4 In this context, "data" relates to a specific grayscale level of the display, and "normal image" is used to display a specific grayscale level, while "black" is data used only for black. This implies a variation in the data related to screen visibility.

[0079] Figure 5 The figure illustrates a timing diagram of an example implementation for changing the power supply voltage ELVSS in a display device according to an example embodiment.

[0080] refer to Figure 5The voltage level of the feedback voltage ELVSS_FB, which is below the voltage level of the first reference voltage ELVSS_Vref, can correspond to the overcharged condition, and the voltage level of the feedback voltage ELVSS_FB, which is above the voltage level of the first reference voltage ELVSS_Vref, can correspond to the undercharged condition.

[0081] In this case, where the panel load exceeds a predetermined range, the discharge rate of the power supply voltage ELVSS can be controlled by adjusting the number of charge and discharge cycles of inductor L. For example, in loads with discontinuous conduction mode (DCM) operation or higher, the discharge rate of the power supply voltage ELVSS can be changed by adjusting the number of charge and discharge cycles of inductor L. In this example embodiment, when the panel load is 20 mA or higher (where the panel load exceeds a predetermined range), the power supply voltage ELVSS can be changed by adjusting the number of charge and discharge cycles of inductor L.

[0082] exist Figure 5 In the middle, "T" vct "LX" refers to the duration of the change, "LX" refers to the control signal used for charging / amplification, and "ELVSS_High" refers to the ELVSS high level in the ELVSS signal.

[0083] Figure 6 The figure illustrates a timing diagram of an example implementation for changing the power supply voltage ELVSS in a display device according to an example embodiment.

[0084] refer to Figure 6 In the display device according to this example embodiment, in order to change the power supply voltage ELVSS, a plurality of intermediate target voltage levels are set between the current voltage level of the power supply voltage ELVSS and the target voltage level of the power supply voltage ELVSS, and the discharge of the power supply voltage ELVSS can be repeatedly performed multiple times based on the intermediate target voltage levels.

[0085] For example, when the current voltage level is -4.05 V and the target voltage level is -4.00 V, that is, when the command applied by the driver IC to the power management integrated circuit 1 instructs the power supply voltage ELVSS to change in 50 mV increments, overshoot or undershoot may occur when the power supply voltage ELVSS changes immediately from -4.05 V to -4.00 V. In this case, the display device according to the example embodiment can repeatedly perform multiple discharges by setting, for example, three intermediate target voltage levels between the current voltage level of the power supply voltage ELVSS and the target voltage level of the power supply voltage ELVSS, with each discharge changing the power supply voltage ELVSS by 12.5 mV.

[0086] Therefore, the intermediate target voltage level can be set using up-level and down-level codes. Figure 6 In the middle, the upper level code is displayed as "ELVSS_Ref digital code", the lower level code is displayed as "sub DAC", and the intermediate target voltage level is indicated as "ELVSS value".

[0087] For example, when the current voltage level is -4.05 V and the target voltage level is -4.00 V, the upper level code is "001" and the lower level code is "00". After performing a discharge operation of up to 12.5 mV, the upper level code is changed to "001" and the lower level code is changed to "01".

[0088] Subsequently, a discharge operation of up to 12.5 mV was executed, the upper level code was changed to "001" and the lower level code was changed to "10", a discharge operation of up to 12.5 mV was executed, the upper level code was changed to "001" and the lower level code was changed to "11", a discharge operation of up to 12.5 mV was executed, and the target voltage level corresponding to the upper level code "000" and the lower level code "00" was achieved.

[0089] The specific values ​​of the up-level and down-level codes shown in this example embodiment do not limit the scope of this disclosure and may be implemented differently depending on the specific implementation purpose of the display device.

[0090] Figure 7 The figure illustrates a timing diagram of an example implementation for changing the power supply voltage ELVSS in a display device according to an example embodiment.

[0091] refer to Figure 7 The voltage level of the feedback voltage ELVSS_FB, which is below the voltage level of the first reference voltage ELVSS_Vref, can correspond to the overcharged condition, and the voltage level of the feedback voltage ELVSS_FB, which is above the voltage level of the first reference voltage ELVSS_Vref, can correspond to the undercharged condition.

[0092] In this case, when the panel load falls within a predetermined range, the discharge rate of the power supply voltage ELVSS can be controlled by the operation of the discharge circuit 10, and the discharge rate of the power supply voltage ELVSS can be changed by operating the discharge circuit 10 during the period when the overcharge identification signal PSM_EN is logic high.

[0093] In this example embodiment, as an example when the panel load falls within a predetermined range, when the panel load is in the range of 0 mA to 20 mA or less, the power supply voltage ELVSS can be changed by operating the discharge circuit 10.

[0094] Figure 8 , Figure 9 and Figure 10 The illustration shows an example view for describing specifications that can be set in a display device according to an example embodiment.

[0095] like Figure 8 , Figure 9 and Figure 10 The diagram shows registers that can be used to store the values ​​of the VCT rise time (VCT_Rising) and the VCT fall time (VCT_Falling). For example, with "VCT_Falling[3:2]" having a value of "01", the time to change the voltage is 4.2 ms when the VCT fall time (VCT_Falling) is set to 50 mV / 35 µs, and with "VCT_Falling[3:2]" having a value of "10", the VCT fall time (VCT_Falling) is set to 50 mV / 70 µs, so the voltage fluctuation period may require 8.4 ms.

[0096] exist Figure 9 and Figure 10 In the code, “ELVSS Rising” and “ELVSS Falling” refer to the direction of voltage change, respectively, and “ELVSS_min(ex:-7.0V)” and “ELVSS_Max(ex:-1.0V)” refer to the minimum and maximum voltage values, respectively.

[0097] However, Figure 8 , Figure 9 and Figure 10 The illustrations shown are for illustrative purposes only, and the limitations of registers or specific values ​​stored in registers may vary depending on the purpose of a particular implementation of this disclosure.

[0098] Figure 11 The illustration shows a flowchart illustrating an operation method of a display device according to an example embodiment.

[0099] refer to Figure 1 , Figure 2 and Figure 11 The operation method of the display device according to the example embodiment may include the step of receiving a value of the panel load (S1101).

[0100] When the value of the panel load exceeds the threshold (S1103, "Y"), the operation method of the display device can charge the inductor L of the PMIC 100 and control the discharge rate of the power supply voltage ELVSS by adjusting the number of charging and discharging cycles of the inductor L of the PMIC 100 (S1105).

[0101] When the value of the panel load is less than or equal to the threshold (S1103, "N"), the operation method of the display device can drive the discharge circuit 10 of the PMIC 100 to control the discharge rate of the power supply voltage ELVSS through the discharge circuit 10 of the PMIC 100 (S1107).

[0102] Finally, after these two cases, the operation method of the display device may include the step of changing the power supply voltage ELVSS by controlling the discharge rate of the power supply voltage ELVSS via step S1105 or step S1107 (S1109).

[0103] The discharge circuit 10 can be based on the overcharge identification signals PSM_EN and COMP_EN (see... Figure 13 The enable signal EN generated by the circuit provides a discharge path through which the power supply voltage ELVSS can be discharged via node N2, discharge circuit 10, and ground terminal. Additionally, discharge circuit 10 can be enabled based on the enable signal EN generated by performing logical operations on the overcharge identification signals PSM_EN and COMP_EN, and the ELVSS high signal ELVSS_High.

[0104] Meanwhile, controlling the discharge rate of the power supply voltage ELVSS through the discharge circuit 10 can further include the step of controlling the discharge rate of the power supply voltage ELVSS through the resistor R_FD of the PMIC 100.

[0105] On the other hand, controlling the discharge rate of the power supply voltage ELVSS through the discharge circuit 10 may include the steps of setting an intermediate target voltage level between the current voltage level of the power supply voltage ELVSS and the target voltage level of the power supply voltage ELVSS, and the steps of repeatedly discharging the power supply voltage ELVSS based on the intermediate target voltage level.

[0106] Figure 12 The figure illustrates a circuit diagram of a power management integrated circuit for a display device according to an example embodiment.

[0107] refer to Figure 12 The power management integrated circuit 2 of the display device according to the example embodiment may further include an element 12 containing a resistor R_FD, which provides a discharge path via transistor M3 based on an enable signal EN.

[0108] The discharge rate through discharge circuit 10 may be limited by the internal clock rate, and in order to accelerate VCT discharge without increasing the clock rate, a second discharge path may be required in addition to the first discharge path through which the power supply voltage ELVSS can be discharged via node N2, discharge circuit 10, and ground terminal. For this purpose, a second discharge path through which the power supply voltage ELVSS can be further discharged can be formed via node N2, resistor R_FD, transistor M3, and ground terminal using a resistor R_FD activated or enabled by the enable signal EN, and both the first and second discharge paths can be activated or enabled simultaneously by the enable signal EN.

[0109] Figure 13 The illustration shows a circuit diagram of a power management integrated circuit for a display device according to an example embodiment, and Figure 14 The figure illustrates a circuit diagram of a power management integrated circuit for a display device according to an example embodiment.

[0110] exist Figure 2 and Figure 12 In the illustrated embodiment, the control circuit 40 is implemented using a pulse width modulation (PWM) method. The control circuit 40 can use the overcharge identification signal PSM_EN, while... Figure 13 and Figure 14 In the embodiment shown, the control circuit 40 is implemented using a pulse frequency modulation (PFM) method, and the control circuit 40 cannot use the overcharge identification signal PSM_EN.

[0111] In this case, the overcharge identification circuit 50 can provide the overcharge identification signal COMP_EN to the enable signal generation circuit 20 in the power management integrated circuit 3 of the display device according to the example embodiment. That is, the overcharge identification circuit 50 can receive the reference voltage ELVSS_Vref and the feedback voltage ELVSS_FB, determine whether overcharging has occurred and output the overcharge identification signal COMP_EN, and can supply the output overcharge identification signal COMP_EN to the enable signal generation circuit 20. Then, the discharge circuit 10 can provide a discharge path for discharging the power supply voltage ELVSS based on the enable signal EN generated according to the overcharge identification signal COMP_EN.

[0112] In this example embodiment, the overcharge detection circuit 50 may include a comparator 52. The comparator 50 compares the voltage level of the reference voltage ELVSS_Vref with the voltage level of the feedback voltage ELVSS_FB to output an overcharge detection signal COMP_EN. For example, when the voltage level of the feedback voltage ELVSS_FB is lower than the voltage level of the reference voltage ELVSS_Vref, the circuit can be determined to be in an overcharged state, and the comparator 52 can output the overcharge detection signal COMP_EN.

[0113] As described above, if necessary, depending on the operating status of the display device, when the discharge circuit 10 configured to be activated or enabled in the power management integrated circuit 3 is used, the discharge rate of the power supply voltage ELVSS can be adjusted and changed.

[0114] Meanwhile, the power management integrated circuit 4 of the display device according to the example embodiment may further include an element 12 containing a resistor R_FD, which provides a discharge path via transistor M3 based on an enable signal EN.

[0115] By using a resistor R_FD activated or enabled by the enable signal EN, a second discharge path can be formed via node N2, resistor R_FD, transistor M3 and ground terminal, and both the first discharge path and the second discharge path can be activated or enabled by the enable signal EN simultaneously.

[0116] According to some example embodiments described so far, when the power supply voltage ELVSS is discharged, it is possible not only to improve the phenomenon that the brightness change of the screen is visually identifiable due to the voltage change, but also to achieve discharge control of the power supply voltage ELVSS suitable for various frequencies such as 60Hz and 120Hz.

[0117] Although this disclosure has been described in conjunction with exemplary embodiments that are currently considered to be practiceable, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: A first transistor, controlled by a first control signal, wherein the first transistor is used to connect an input terminal to which an input voltage is applied and a first node; The second transistor is controlled by a second control signal, wherein the second transistor is used to output a power supply voltage to its second node and connect to the first node; The overcharge detection circuit is configured to receive a first reference voltage, a feedback voltage, and a second reference voltage to determine whether the circuit is overcharged and to output an overcharge detection signal. The discharge circuit is configured to provide a first discharge path based on an enable signal generated according to the overcharge identification signal, the first discharge path being used to discharge the power supply voltage. as well as Inductor, connected to the first node, When the panel load is within a predetermined range, the discharge rate of the power supply voltage is controlled by the operation of the discharge circuit, and When the panel load is outside the predetermined range, the discharge rate of the power supply voltage is controlled by adjusting the number of charging and discharging cycles of the inductor.

2. The display device according to claim 1, further comprising: The enable signal generation circuit is configured to generate the enable signal by performing logic operations on the overcharge identification signal and the ELVSS high signal. The overcharge detection circuit includes: An error amplifier is configured to amplify the difference between the first reference voltage and the feedback voltage to output an error amplification output signal; and A comparator is configured to output the overcharge identification signal by comparing the voltage level of the error amplification output signal with the voltage level of the second reference voltage. When the voltage level of the feedback voltage is higher than the voltage level of the first reference voltage, the circuit is determined to be in an overcharge state to reduce the voltage level of the error amplification output signal, and The comparator outputs the overcharge identification signal when the voltage level of the error amplification output signal is lower than the voltage level of the second reference voltage.

3. The display device according to claim 1, wherein, Multiple intermediate target voltage levels are set between the current voltage level of the power supply voltage and the target voltage level of the power supply voltage. Discharging the power supply voltage according to the intermediate target voltage level is repeatedly performed, and The intermediate target voltage level is set using an up-level code and a down-level code.

4. The display device according to any one of claims 1 to 3, further comprising: The third transistor is controlled by a third control signal, wherein the third transistor is used to connect the second node to the ground terminal; as well as A resistor is configured to provide a second discharge path via the third transistor based on the enable signal.

5. A display device, comprising: A first transistor, controlled by a first control signal, wherein the first transistor is used to connect an input terminal to which an input voltage is applied and a first node; The second transistor is controlled by a second control signal, wherein the second transistor is used to output a power supply voltage to its second node and connect to the first node; The overcharge detection circuit is configured to receive a reference voltage and a feedback voltage to determine whether the circuit is overcharged and to output an overcharge detection signal. The discharge circuit is configured to provide a first discharge path based on an enable signal generated according to the overcharge identification signal, the first discharge path being used to discharge the power supply voltage. as well as Inductor, connected to the first node, When the panel load is within a predetermined range, the discharge rate of the power supply voltage is controlled by the operation of the discharge circuit, and When the panel load is outside the predetermined range, the discharge rate of the power supply voltage is controlled by adjusting the number of charging and discharging cycles of the inductor.

6. The display device according to claim 5, wherein, The overcharge detection circuit includes a comparator configured to output an overcharge detection signal by comparing the voltage level of the reference voltage with the voltage level of the feedback voltage. When the voltage level of the feedback voltage is lower than the voltage level of the reference voltage, the circuit is determined to be in an overcharge state, and the comparator outputs the overcharge identification signal.

7. The display device according to claim 5, wherein, Multiple intermediate target voltage levels are set between the current voltage level of the power supply voltage and the target voltage level of the power supply voltage. The discharge of the power supply voltage is repeatedly performed multiple times based on the intermediate target voltage level, and The intermediate target voltage level is set using an up-level code and a down-level code.

8. The display device according to any one of claims 5 to 7, further comprising: The third transistor is controlled by a third control signal, wherein the third transistor is used to connect the second node to the ground terminal; as well as A resistor is configured to provide a second discharge path via the third transistor based on the enable signal.

9. A method of operating a display device, the method comprising the following steps: Receive the load value from the panel; Determine the value of the panel load; When the panel load value exceeds a threshold, the inductor of the power management integrated circuit is charged, and the discharge rate of the power supply voltage is controlled by adjusting the number of charging and discharging cycles of the inductor of the power management integrated circuit; and When the value of the panel load is less than or equal to the threshold, the inductor of the power management integrated circuit is charged, and the discharge rate of the power supply voltage is controlled by the discharge circuit of the power management integrated circuit.

10. The operating method according to claim 9, wherein, The discharge circuit provides a first discharge path for discharging the power supply voltage based on an enable signal generated according to an overcharge identification signal, and The discharge circuit is enabled by the enable signal generated by performing a logic operation on the overcharge identification signal and the ELVSS high signal.

11. The operating method according to claim 9, wherein, Controlling the discharge rate of the power supply voltage via the discharge circuit includes the step of controlling the discharge rate of the power supply voltage via a resistor in the power management integrated circuit.

12. The operating method according to claim 9, wherein, Controlling the discharge rate of the power supply voltage through the discharge circuit includes the following steps: Multiple intermediate target voltage levels are set between the current voltage level of the power supply voltage and the target voltage level of the power supply voltage; and The power supply voltage is repeatedly discharged based on the intermediate target voltage level.

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