A hole processing method and a semiconductor device

Abstract

The application discloses a hole processing method and a semiconductor device, and relates to the technical field of semiconductor manufacturing, aiming to solve the problems of poor contact resistance uniformity and hole structure open circuit caused by the wide top and narrow bottom of the hole, and improve the performance of the semiconductor device. A substrate is provided; etching is performed on the substrate to obtain a hole structure; the top of the hole structure is wide and the bottom is narrow; the hole structure is processed, and the hole processing method comprises at least one processing period, and each processing period comprises: a wet etching stage, which comprises: in the case that the wet etching agent is evaporated, the sidewall of the hole structure is etched by using a wet etching process to reduce the difference between the bottom width and the top width of the hole structure; and a film forming stage after the wet etching stage, which comprises: an atomic layer deposition process is adopted to form an oxide film on the sidewall of the hole structure. The semiconductor device comprises the hole structure formed by using the hole processing method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a hole processing method and a semiconductor device. Background Technology

[0002] In the fabrication of semiconductor devices, hole structures are typically used to connect layers for signal transmission.

[0003] However, as the integration of semiconductor memory elements becomes higher and higher, the inconsistent size of the hole structure, which is wide at the top and narrow at the bottom, will cause the contact resistance to become less uniform and the hole structure to become open-circuited, resulting in a decrease in the driving capability of the semiconductor device and affecting the performance of the semiconductor device. Summary of the Invention

[0004] The purpose of this invention is to provide a hole processing method and a semiconductor device to solve the problems of poor contact resistance uniformity and hole structure open circuit caused by a hole being wide at the top and narrow at the bottom, thereby improving the performance of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a hole processing method. The hole processing method includes providing a substrate; etching the substrate to obtain a hole structure; the hole structure being wider at the top and narrower at the bottom; and processing the hole structure. The hole processing method includes at least one processing cycle, each processing cycle comprising:

[0006] The wet etching stage includes: etching the sidewalls of the hole structure using a wet etching process while the wet etchant is evaporating, in order to reduce the difference between the bottom width and the top width of the hole structure.

[0007] And the film formation stage following the wet etching stage, which includes forming an oxide film on the sidewalls of the pore structure using atomic layer deposition.

[0008] Compared with existing technologies, the hole processing method provided by this invention includes a wet etching stage and a film formation stage in each processing cycle. In the wet etching stage, capillary action is utilized. When the hole structure contains a wet etchant, the wet etchant at the top of the hole structure evaporates first, leaving some wet etchant at the bottom. Only after the wet etchant at the top has evaporated does the wet etchant at the bottom evaporate. Therefore, the wet etchant etches less at the top of the hole structure and more at the bottom. Thus, by using the wet etchant to etch the hole structure over a certain period of time while the wet etchant evaporates, the lower diameter of the hole structure increases significantly, while the upper diameter increases less, thereby reducing the difference between the bottom and top widths of the hole structure. Furthermore, because the wet etching agent etches into the upper part of the hole structure, enlarging the upper hole diameter beyond the preset size, an atomic layer deposition (ALD) process is used after the wet etching stage to form a uniform oxide film on the inner wall of the hole structure. This repairs the enlarged upper hole diameter, restoring it to the preset size. Although the lower hole diameter is adjusted by the oxide film, the thickness of the oxide film formed on the hole walls remains uniform. Therefore, even after adjusting the hole structure dimensions during the film deposition stage following the wet etching stage, the difference between the upper and lower hole diameters tends to decrease. This process is repeated until the difference between the bottom and top widths of the hole structure becomes negligible or nonexistent, improving contact resistance uniformity, preventing open circuits in the hole structure, enhancing the driving capability of the semiconductor device, and improving its overall performance.

[0009] The present invention also provides a semiconductor device. The semiconductor device includes a hole structure formed using the above-described hole processing method.

[0010] Compared with the prior art, the beneficial effects of the semiconductor device provided by the present invention are the same as those of the hole processing method described in the above technical solution, and will not be repeated here. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 A schematic diagram of a hole structure in the prior art is shown;

[0013] Figure 2 A schematic diagram of a hole structure after wet etching in the prior art is shown;

[0014] Figure 3 A schematic diagram of the structure of a substrate provided in an embodiment of the present invention is shown;

[0015] Figure 4 A schematic diagram of a hole structure formed after etching a substrate, according to an embodiment of the present invention, is shown.

[0016] Figure 5 A schematic diagram of a wet etching hole structure provided in an embodiment of the present invention is shown;

[0017] Figure 6 A schematic diagram of an etching hole structure using a rotating substrate wet etching apparatus provided in an embodiment of the present invention is shown;

[0018] Figure 7 A schematic diagram of a hole structure provided in an embodiment of the present invention is shown.

[0019] Figure label:

[0020] 10 is the hole structure, 100 is the top, 101 is the bottom, 11 is the wet etchant, 12 is the substrate, 13 is the rotating substrate wet etching equipment, 14 is the etching chamber, 15 is the rotating device, 16 is the spraying device, and 17 is the cleaning device. Detailed Implementation

[0021] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0023] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] like Figure 1 and Figure 2 As the integration density of semiconductor devices increases, the size of the via structure 10 needs to be increased to increase the contact area. In existing technologies, the via structure 10 is typically formed first using dry etching, resulting in a shape that is 100mm wide at the top and 101mm narrow at the bottom. Subsequently, wet etching is used to further etch the via structure 10 to increase its size. After wet etching, some impurities and wet etching agent inevitably remain within the via structure 10, affecting subsequent processes and product performance. Therefore, the via structure 10 needs to be cleaned and dried after wet etching. In existing technologies, the via structure 10 is typically rinsed repeatedly with deionized water at a temperature of 18°C ​​to 25°C to remove residual impurities and wet etching agent.

[0027] like Figure 2 As shown, the size of the hole structure 10 obtained by further etching using wet etching is larger than the size of the hole structure 10 initially formed by dry etching. However, simply increasing the size of the hole structure 10 does not improve the uniformity of contact resistance, the problem of hole structure open circuit, or the driving capability and performance of the semiconductor device.

[0028] To address the aforementioned problems, embodiments of the present invention provide a hole processing method and a semiconductor device to solve the problems of poor contact resistance uniformity and open circuits in the hole structure caused by a hole structure that is wide at the top and narrow at the bottom, thereby improving the performance of the semiconductor device. The aforementioned hole processing method refers to processing a hole structure that is wide at the top and narrow at the bottom, reducing the difference between the bottom and top widths of the hole structure, and gradually bringing the hole diameters at various points in the hole structure closer together.

[0029] For ease of description, the following only describes the differences between the hole processing method provided in the embodiments of the present invention and the hole processing methods in the prior art. Other steps not described can be referred to the descriptions in the prior art. Of course, those skilled in the art can also improve other existing hole processing methods based on the following descriptions of the embodiments of the present invention.

[0030] Figures 3 to 7 The illustration shows schematic diagrams of various stages of a hole processing method provided by an embodiment of the present invention. The hole processing method for the hole structure provided by this embodiment of the present invention includes:

[0031] like Figure 3 As shown, a substrate 12 is provided. This substrate 12 can be a substrate without any film layers, or a substrate with some film layers. The substrate 12 without any film layers can be a silicon substrate, a germanium substrate, a silicon germanide substrate, or a substrate containing other elemental semiconductors or compound semiconductors. The substrate 12 with some film layers can be a substrate containing a dielectric layer, a substrate containing a barrier layer acting as a barrier, or a substrate with various design structures, etc., which will not be listed here.

[0032] like Figure 4 As shown, the substrate 12 is etched to obtain the hole structure 10. The hole structure 10 is wide at the top and narrow at the bottom. The substrate 12 can be processed using existing dry etching methods to obtain the hole structure 10. Alternatively, wet etching can be used to further etch the hole structure 10 to increase its size. For example, the hole structure 10 can be filled with a wet etchant, which uniformly etches the sidewalls of the hole structure 10, increasing its size to the target size while maintaining its original shape (wide at the top and narrow at the bottom).

[0033] like Figure 4As shown, the aforementioned hole structure 10 primarily serves a connectivity function in semiconductor devices. This hole structure 10 can be a via or a bottom-closed hole structure. When the substrate 12 is a substrate without any film layers, the hole structure 10 can be a hole structure connecting the substrate 12 to the peripheral circuit, or it can be a bottom-closed hole or trench structure, but is not limited to these. When the substrate 12 has some film layers, the hole structure 10 can be a hole structure between layers, or a via between metal interconnects.

[0034] After obtaining the hole structure, the hole structure is processed. The hole processing method includes at least one processing cycle. Each processing cycle includes a wet etching stage and a film formation stage following the wet etching stage.

[0035] like Figure 5 As shown, the above-mentioned wet etching stage includes etching the sidewalls of the hole structure 10 using a wet etching process while the wet etchant 11 is evaporating, so as to reduce the difference between the bottom width and the top width of the hole structure 10.

[0036] like Figure 5 As shown, the size of the hole structure 10 in a semiconductor device is generally at the nanometer level or even larger. When a wet etchant 11 is filled in it, capillary action is used for processing. Based on this, when the wet etchant 11 evaporates and the sidewalls of the hole structure 10 are etched using a wet etching process, the wet etchant 11 at the top 100 of the hole structure 10 evaporates first. At this time, the wet etchant 11 will remain at the bottom 101 of the hole structure 10. After the wet etchant 11 at the top 100 of the hole structure 10 evaporates completely, the wet etchant 11 at the bottom 101 of the hole structure 10 will evaporate. Therefore, the amount of wet etchant 11 etched at the top 100 of the hole structure 10 is small, while the amount etched at the bottom 101 of the hole structure 10 is large. Therefore, it can be seen that when the wet etchant 11 evaporates, using the wet etchant 11 to etch the hole structure 10 within a certain time can result in a large increase in the lower hole diameter and a small increase in the upper hole diameter of the hole structure 10, thereby reducing the difference between the bottom width and the top width of the hole structure 10.

[0037] There are several methods for etching the sidewalls of hole structures using wet etching processes when the wet etchant evaporates. Two possible implementations are described below as examples. It should be understood that the following descriptions are for illustrative purposes only and are not intended to limit the specific implementation.

[0038] like Figure 6As shown, in one example, the sidewalls of the aforementioned hole structure 10 are etched using a wet etchant with a rotating substrate 12. During the etching process, the centrifugal force generated by the rotating substrate 12 results in a larger contact area and impact between the wet etchant and the sidewalls of the hole structure 10, thus allowing for better etching of the sidewalls of the hole structure 10.

[0039] like Figure 6 As shown, for example, a rotating substrate wet etching apparatus 13 can be used to etch the rotating substrate 12. The rotating substrate wet etching apparatus 13 includes an etching chamber 14 and a rotating device 15 disposed within the etching chamber 14. When rotating etching is performed using the rotating substrate wet etching apparatus 13, the etching chamber 14 contains a wet etchant, and the substrate 12 is fixed in the chuck of the rotating device 15. The rotating device 15 drives the substrate 12 to rotate, so that the wet etchant sprayed by the spraying device 16 can be evenly distributed in the hole structure 10 on the surface of the substrate 12, ensuring that the concentration or temperature of the wet etchant is consistent throughout the surface of the substrate 12, which facilitates uniform etching of the sidewalls of the hole structure 10.

[0040] like Figure 6 As shown, the rotation speed of the rotating substrate wet etching apparatus 13 affects the evaporation rate of the wet etchant, which in turn affects the etching rate of the sidewall material. To more precisely control the etching process, the rotation speed of the rotating substrate etching apparatus is greater than 0 RPM and less than 100 RPM. When the rotation speed exceeds 100 RPM, on the one hand, the wet etchant inside the hole structure 10 is easily thrown off and cannot enter the bottom of the hole structure 10. On the other hand, the etching process of the wet etchant on the hole structure 10 is difficult to control. For example, the wet etchant at the bottom of the hole structure 10 may be thrown to the top, resulting in excessive etching at the top and affecting the process.

[0041] like Figure 6 As shown, in order to achieve uniform and gradient wet etching of the sidewalls of the hole structure 10, the rotation speed should be controlled between 0 RPM and 100 RPM. For example, when the rotation speed is 56 RPM, the rotating substrate wet etching apparatus 13 rotates the substrate 12 while simultaneously spraying wet etchant onto the hole structure 10 on the substrate 12 using the spray device 16. At this time, the wet etchant is uniformly distributed in the hole structure 10 on the surface of the substrate 12, resulting in uniform and gradient wet etching of the hole structure 10 on the substrate 12, and thus a better etching effect. Of course, the rotation speed of the rotating substrate etching apparatus can also be set according to actual conditions.

[0042] like Figure 5 and Figure 6As shown, in another example, the sidewalls of the hole structure 10 can be etched using a wet etchant 11 with a stationary substrate 12. In this case, when the wet etchant 11 evaporates, the wet etchant 11 at the top 100 of the hole structure 10 evaporates first, leaving some at the bottom 101. Only after the wet etchant 11 at the top 100 has evaporated completely does the wet etchant 11 at the bottom 101 evaporate. Therefore, the wet etchant 11 etchs less at the top 100 and more at the bottom 101 of the hole structure 10. Therefore, it can be seen that when the wet etchant 11 evaporates, using the wet etchant 11 to etch the hole structure 10 within a certain time can result in a large increase in the lower hole diameter and a small increase in the upper hole diameter of the hole structure 10, thereby reducing the difference between the bottom width and the top width of the hole structure 10.

[0043] like Figure 5 and Figure 6 As shown, the wet etchant 11 used in the above wet etching stage may include an oxide layer etching buffer or hydrofluoric acid. When the etching rate of the oxide layer etching buffer (BOE) or hydrofluoric acid is controlled between 25 A / min and 1100 A / min, the wet etchant 11 can more precisely control the etching amount, allowing the pore structure 10 to slowly expand in diameter during immersion in the wet etchant 11, thereby achieving pore size uniformity. The concentration of the HF stock solution in the oxide layer etching buffer or hydrofluoric acid is 36%, and the diluent used in the dilution process is water.

[0044] like Figure 5 and Figure 6 As shown, the wet etching stage described above may also include a cleaning process. After the wet etching stage of the hole structure 10 is completed, the hole structure 10 needs to be cleaned to remove residual impurities and wet etching agent 11. For example, at a temperature of 21°C to 29°C, the hole structure 10 can be repeatedly rinsed with deionized water using a cleaning device 17. Of course, other methods can also be used to clean the hole structure 10. The number of times the hole structure 10 is cleaned is equal to the number of times the hole structure 10 is wet etched. For example, at 25°C, rinsing the hole structure 10 with deionized water provides a better cleaning effect and is more conducive to subsequent processing of the hole structure 10. After cleaning the hole structure 10, it can be further dried to facilitate film formation in the subsequent film formation stage.

[0045] After the wet etching stage, the aperture of the bottom 101 of the hole structure 10 is much larger than the aperture of the top 100 of the hole structure 10. Therefore, as follows... Figure 7As shown, after the wet etching stage, an atomic layer deposition process is used in the film formation stage to form an oxide film on the sidewall of the pore structure 10, which is used to repair the upper part of the pore structure 10 whose pore size has been further enlarged by the wet etching agent.

[0046] like Figure 7 As shown, the material of the oxide film is the same as that of the substrate, which can be SiO2 or Al2O3. The thickness of the oxide film formed on the sidewalls of the pore structure 10 can be 0.5 nm to 18 nm. Since the oxide film is relatively thin, the process for forming the oxide film can be atomic layer deposition (ALD). ALD can deposit materials layer by layer in the form of single-atom films within the pore structure 10 of the substrate. Moreover, the chemical reaction of the new atomic film is directly related to the previous layer. Therefore, each reaction can deposit only one atomic layer. Thus, this process can precisely control the thickness and uniformity of the oxide film formed on the inner sidewalls of the pore structure 10.

[0047] like Figure 7 As shown, after the wet etching stage, an atomic layer deposition process is used to form an oxide film of uniform thickness on the inner wall of the hole structure 10 to repair the enlarged upper hole diameter, thus restoring the upper hole diameter of the hole structure 10 to the preset size. Although the lower hole diameter of the hole structure 10 is adjusted by the oxide film, the oxide film thickness formed on the hole wall of the hole structure 10 is uniform. Therefore, even if the size of the hole structure 10 is adjusted after the wet etching stage, the difference between the upper and lower hole diameters of the hole structure 10 tends to decrease. This process is repeated until the difference between the bottom width and top width of the hole structure 10 is reduced to a negligible or non-existent state, thereby improving the uniformity of contact resistance, preventing open circuits in the hole structure 10, improving the driving capability of the semiconductor device, and enhancing the performance of the semiconductor device.

[0048] To ensure that the difference between the bottom and top widths of the hole structure is controlled to be negligible or nonexistent, the number of processing cycles is less than or equal to 10. Therefore, the number of wet etching stages and the number of film formation stages in each processing cycle can be less than or equal to 10. Since the number of cleaning cycles for the hole structure is equal to the number of wet etching cycles, the number of cleaning cycles can also be less than or equal to 10. In this way, not only can a vertical hole structure with the required dimensions be accurately obtained, but processing costs can also be saved. It should be understood that in the embodiments provided by this invention, the number of wet etching stages, the number of film formation stages, and the number of cleaning cycles are consistent.

[0049] The following description uses one possible implementation as an example. It should be understood that the following description is for illustrative purposes only and is not intended to limit the specific implementation. Furthermore, the number of wet etching stages and film formation stages in the following processing cycle are merely examples and can be set according to actual conditions.

[0050] In one example, after a wet etching process within a processing cycle, a film can be formed to repair the upper part of the enlarged pore structure. This method of simultaneous etching and repair compensation allows for better control over the size of the resulting pore structure.

[0051] The present invention also provides a semiconductor device. The semiconductor device includes a hole structure formed using the above-described hole processing method.

[0052] Compared with the prior art, the beneficial effects of the semiconductor device provided by the present invention are the same as those of the hole processing method described in the above technical solution, and will not be repeated here.

[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0054] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A hole processing method, characterized in that, Provide a substrate; The substrate is etched to obtain a hole structure; the hole structure is wide at the top and narrow at the bottom. The hole structure is processed, and the hole processing method includes at least one processing cycle, each processing cycle including: The wet etching stage includes: etching the sidewalls of the hole structure using a wet etching process while the wet etchant is evaporating, so as to reduce the difference between the bottom width and the top width of the hole structure; And a film formation stage following the wet etching stage, the film formation stage including: forming an oxide film on the sidewalls of the pore structure using an atomic layer deposition process; the material of the oxide film is the same as the material of the substrate; The etching of the sidewalls of the hole structure using a wet etching process, under the condition of wet etchant evaporation, includes: The sidewalls of the hole structure are etched using a wet etchant and a rotating substrate etching method; Alternatively, with the substrate stationary, the sidewalls of the hole structure can be etched using a wet etchant.

2. The hole processing method according to claim 1, characterized in that, The wet etching agent includes an oxide layer etching buffer and / or hydrofluoric acid.

3. The hole processing method according to claim 1, characterized in that, The rotational rate of the etched substrate is greater than 0 RPM and less than 100 RPM.

4. The hole processing method according to claim 1, characterized in that, Both the oxide film and the substrate are SiO2 or Al2O3; and / or, The thickness of the oxide film is 0.5 nm to 18 nm.

5. The hole processing method according to claim 1, characterized in that, The operating temperature for the wet etching stage is 21℃~29℃.

6. The hole processing method according to any one of claims 1 to 5, characterized in that, The number of processing cycles is less than or equal to 10.

7. A semiconductor device, characterized in that, include: A hole structure formed using the hole processing method according to any one of claims 1 to 6.

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