Fin field effect transistor manufacturing method and fin field effect transistor structure

Abstract

The present invention relates to a method for manufacturing a fin field effect transistor, and to a semiconductor integrated circuit technology. After forming a metal gate, a gate dielectric layer and a work function layer of a metal gate structure, a portion of the end of the metal gate that exceeds the fin body area is removed. Since the work function layer has been formed, there is no need to worry about whether the formation window of the work function layer meets the process requirements. Therefore, more end areas of the metal gate can be removed, and the parasitic capacitance Cgs between the gate and the source or the parasitic capacitance Cgd between the gate and the drain of the finally formed fin field effect transistor device can be reduced as much as possible, and the process can be made simpler.

Description

Technical Field

[0001] The invention relates to semiconductor integrated circuit technology, and in particular to a method for manufacturing a fin field effect transistor. Background Art

[0002] With the continuous development of semiconductor technology, three-dimensional device Fin Field-Effect Transistor (FinFET) came into being. Compared with planar transistors, Fin Field-Effect Transistor (FinFET) has a three-dimensional channel structure, so it has better on-current and off-current characteristics, and can also improve short channel effect (SCE). With the development of semiconductor technology, the key dimensions of devices are constantly shrinking, and the market's requirements for device performance are getting higher and higher. The existing manufacturing methods of Fin Field-Effect Transistors can no longer meet market demand. Summary of the invention

[0003] The present invention provides a method for manufacturing a fin field effect transistor, comprising: S1: forming a plurality of fin bodies on a semiconductor substrate, wherein shallow trenches are formed between the fin bodies, and first field oxygen is filled in the shallow trenches, wherein the top surface of the first field oxygen is lower than the top surface of the fin body so that the fin body is exposed on the top of the first field oxygen, so that the bottoms of the fin bodies are isolated from each other by the first field oxygen; S2: forming a polysilicon layer, performing photolithography and etching to form a plurality of polysilicon gates, wherein the polysilicon gates intersect with the fin body, and the overlapping regions of the polysilicon gates and the fin body form a pseudo gate structure; S3: forming a source region and a drain region on the fin body, wherein the source region and the drain region are located at the polysilicon gate. two sides; S4: removing the polysilicon gate and forming a gate dielectric layer, the gate dielectric layer covers the surface of the fin body and the surface of the first field oxygen, and forming a work function layer, the work function layer covers the surface of the gate dielectric layer; S5: forming a metal gate, the metal gate fills the removed area of ​​the polysilicon gate, the metal gate and the fin body, the gate dielectric layer and the work function layer form a metal gate structure of a fin field effect transistor; S6: removing a portion of the end area of ​​the metal gate that exceeds the fin body area to form a first groove, and forming a dielectric layer in the first groove; and S7: forming a zeroth metal layer to lead out the source region and the drain region, the metal gate structure and the source region and the drain region located on both sides thereof form a fin field effect transistor.

[0004] Furthermore, in step S6 , a portion of the end of the metal gate that exceeds the fin region is removed by a photolithography and etching process.

[0005] Furthermore, the material of the dielectric layer is silicide.

[0006] Furthermore, the silicide is silicon dioxide.

[0007] Furthermore, the gate dielectric layer includes a high dielectric constant layer.

[0008] Furthermore, an extension direction of the polysilicon gate is perpendicular to an extension direction of the fin body.

[0009] The present invention also provides a fin field effect transistor structure, comprising: a semiconductor substrate, a plurality of fin bodies are formed on the semiconductor substrate, shallow trenches are formed between the fin bodies, a first field oxygen is filled in the shallow trenches, the top surface of the first field oxygen is lower than the top surface of the fin body so that the fin body is exposed on the top of the first field oxygen, so that the bottoms of the fin bodies are isolated from each other by the first field oxygen; a plurality of metal gates, the plurality of metal gates intersect the plurality of fin bodies, the overlapping regions of the metal gates and the fin bodies form a metal gate structure, the metal gates cover the surface of the fin body in the overlapping regions, and the plurality of metal gates also cover the first field oxygen. surface; a gate dielectric layer, located between the multiple metal gates and the fin body and the first field oxygen area covered by the multiple metal gates; a work function layer, located between the gate dielectric layer and the metal gate, a source region and a drain region of a fin-type field effect transistor are formed on the fin body, the source region and the drain region are located on both sides of the metal gate structure, and the source region and the drain region are led out through the zeroth metal layer, so that the metal gate structure and the source region and the drain region located on both sides thereof form a fin-type field effect transistor, wherein a groove is included at the end of the metal gate of the fin-type field effect transistor, the groove is filled with a dielectric layer, the bottom of the dielectric layer covers the first field oxygen, and the two side walls of the dielectric layer are adjacent to the metal gate.

[0010] Furthermore, the bottom of the dielectric layer directly contacts and covers the first field oxide, and the two sidewalls of the dielectric layer directly contact and are adjacent to the metal gate.

[0011] Furthermore, the groove is formed by photolithographically etching a portion of the end of the metal gate that exceeds the fin region, and then filling the groove with a dielectric layer.

[0012] Furthermore, the groove is located in a portion of the end of the metal gate that exceeds the fin region.

[0013] After forming the metal gate, gate dielectric layer and work function layer of the metal gate structure, a portion of the end of the metal gate that exceeds the fin body area is removed. Since the work function layer has been formed, there is no need to worry about whether the formation window of the work function layer meets the process requirements. Therefore, more end areas of the metal gate can be removed, and the parasitic capacitance Cgs between the gate and the source or the parasitic capacitance Cgd between the gate and the drain of the final fin field effect transistor device can be minimized. Therefore, the manufacturing method of the fin field effect transistor of the present invention can minimize the parasitic capacitance Cgs between the gate and the source or the parasitic capacitance Cgd between the gate and the drain on the basis of ensuring the formation window of the work function layer, and compared with the typical manufacturing method of the fin field effect transistor, no new process needs to be added, and the process can be made simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figures 1a to 1e The cross-sectional view is a schematic diagram of a polysilicon gate or a metal gate of a transistor device during the manufacturing process of a typical fin field effect transistor.

[0015] Figure 2a to Figure 2d This is a plan view of a typical transistor device during the manufacturing process of a fin field effect transistor.

[0016] Figures 3a to 3d The cross-sectional view is a schematic diagram of a polysilicon gate or a metal gate of a transistor device during the manufacturing process of a FinFET according to an embodiment of the present invention.

[0017] Figures 4a to 4d FIG. 1 is a plan view of a transistor device in a manufacturing process of a fin field effect transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0020] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0021] See also Figure 1a and Figure 1e , Figure 2a to Figure 2d , Figure 1a and Figure 1e FIG. 1 is a schematic cross-sectional view of a polysilicon gate or a metal gate of a transistor device during the manufacturing process of a typical fin field effect transistor. Figure 2a to Figure 2d FIG. 1 is a plan view of a transistor device during the manufacturing process of a typical fin field effect transistor, wherein Figure 1a For along Figure 2a A schematic cross-sectional view of the AA line of the transistor device. Figure 1b For along Figure 2c A schematic cross-sectional view of the AA line of the transistor device. Figure 1e For along Figure 2d A typical method for manufacturing a fin field effect transistor includes: S1: Figure 1a As shown, a plurality of fin bodies 120 are formed on a semiconductor substrate 100, and shallow trenches are formed between the fin bodies 120. A first field oxide 210 is filled in the shallow trenches, and a top surface of the first field oxide 210 is lower than a top surface of the fin body 120 so that the fin body 120 is exposed at the top of the first field oxide 210, so that the bottoms of the fin bodies 120 are isolated from each other by the first field oxide 210; S2: As shown in FIG. Figure 2a and Figure 1a As shown, a polysilicon layer is formed, and photolithography and etching are performed to form a plurality of polysilicon gates 110, wherein the polysilicon gates 110 intersect with the fin body 120, and an overlapping region 150 of the polysilicon gates 110 and the fin body 120 forms a pseudo gate structure, wherein the polysilicon gates 110 cover the top surface and the side surface of the fin body 120 in the overlapping region 150, and the region of the fin body 120 covered by the polysilicon gates 110 is used to form a channel region; S3: as Figure 2b and Figure 1b As shown, the partial regions 610 and 620 of the polysilicon gate 110 beyond the end of the fin region 630 are removed to form a first groove 310, and a dielectric layer 320 is formed in the first groove 310; S4: as Figure 2c As shown, a source region 141 and a drain region 142 are formed on the fin body 120, and the source region 141 and the drain region 142 are located on both sides of the polysilicon gate 110; S5: as Figure 1c As shown, remove the polysilicon gate; S6: as Figure 1d As shown, a gate dielectric layer 410 is formed, the gate dielectric layer 410 covers the surface of the fin body 120, the surface of the dielectric layer 320 and the surface of the first field oxide 210, and a work function layer 420 is formed, the work function layer 420 covers the surface of the gate dielectric layer 410; S7: Figure 1e As shown, a metal gate 510 is formed, and the metal gate 510 fills the removed area of ​​the polysilicon gate, so that the metal gate 510, the fin body 120, the gate dielectric layer 410 and the work function layer 420 form a metal gate structure of a fin field effect transistor, and the metal gate structure and the source region and the drain region located on both sides thereof form a fin field effect transistor; and S8: as Figure 2d As shown, a zeroth metal layer 130 is formed to lead out the source region 141 and the drain region 142 .

[0022] However, for the typical method for manufacturing a fin field effect transistor as described above, if too much of the partial regions 610 and 620 of the polysilicon gate 110 beyond the end of the fin region 630 is removed in step S3, Figure 1b As shown, the distance d between the dielectric layer 320 and the adjacent fin body 120 is small, which will result in a smaller filling window for forming the work function layer 420 in the subsequent step S6, such as Figure 1d As shown, the work function layer 420 may not be filled, thus affecting the device performance. If the partial regions 610 and 620 of the polysilicon gate 110 beyond the end of the fin region 630 are removed too little in step S3, the parasitic capacitance Cgs between the gate and the source region 141 or the parasitic capacitance Cgd between the gate and the drain region 142 of the finally formed fin field effect transistor device may be large, thus affecting the device performance. Figure 2dTherefore, the conventional typical method for manufacturing a fin field effect transistor requires a balance between the filling window of the work function layer and the parasitic capacitance.

[0023] The fin region 660 is a region on a semiconductor substrate of a fin field effect transistor where the fins 120 are distributed.

[0024] In one embodiment of the present invention, a method for manufacturing a fin field effect transistor is provided. Figures 3a to 3d as well as Figures 4a to 4d , Figures 3a to 3d FIG. 1 is a schematic cross-sectional view of a polysilicon gate or a metal gate of a transistor device during the manufacturing process of a fin field effect transistor according to an embodiment of the present invention. Figures 4a to 4d FIG. 1 is a schematic plan view of a transistor device in a manufacturing process of a fin field effect transistor according to an embodiment of the present invention, wherein Figure 3a For along Figure 4a A schematic cross-sectional view of the AA line of the transistor device. Figure 3d For along Figure 4d A cross-sectional schematic diagram of a transistor device along line AA. A method for manufacturing a fin field effect transistor according to an embodiment of the present invention comprises:

[0025] S1: Figure 3a and 4a As shown, a plurality of fin bodies 120 are formed on a semiconductor substrate 100, and shallow trenches are formed between the fin bodies 120. A first field oxide 210 is filled in the shallow trenches, and a top surface of the first field oxide 210 is lower than a top surface of the fin body 120 so that the fin body 120 is exposed at the top of the first field oxide 210, so that the bottoms of the fin bodies 120 are isolated from each other by the first field oxide 210;

[0026] In one embodiment, the semiconductor substrate 100 includes a silicon substrate or an SOI substrate. In one embodiment, the first field oxide 210 is deposited by a flowable Chemical Vapor Deposition (FCVD) process; after depositing the first field oxide 210, the first field oxide is chemically ground and etched so that the top surface of the first field oxide is etched back to a level lower than the top surface of the fin 120.

[0027] S2: Figure 3a and 4a As shown, a polysilicon layer is formed, and photolithography and etching are performed to form a plurality of polysilicon gates 110, wherein the polysilicon gates 110 intersect with the fins 120, and an overlapping region 150 of the polysilicon gates 110 and the fins 120 forms a pseudo gate structure;

[0028] In one embodiment, an extension direction of the polysilicon gate 110 is perpendicular to an extension direction of the fin 120 .

[0029] like Figure 4a As shown, the ends of the multiple polysilicon gates 110 extend beyond the fin body region 630, and the extending portions are relatively long. It is usually necessary to remove a portion of the ends of the polysilicon gates 110 extending beyond the fin body region 630 to reduce the parasitic capacitance Cgs between the metal gate and the source region or the parasitic capacitance Cgd between the metal gate and the drain region of the subsequently formed fin field effect transistor device.

[0030] S3: Figure 4b As shown, a source region 141 and a drain region 142 are formed on the fin body 120 , and the source region 141 and the drain region 142 are located on both sides of the polysilicon gate 110 ;

[0031] In one embodiment, forming the source region 141 and the drain region 142 more specifically includes: forming a second groove on the fin body on both sides of the dummy gate structure, filling the second groove with an embedded epitaxial layer, and performing source and drain implantation in the embedded epitaxial layer to respectively form the source region 141 and the drain region 142. When the fin transistor is an N-type device, the material of the embedded epitaxial layer is SiP; when the fin transistor is a P-type device, the material of the embedded epitaxial layer is SiGe.

[0032] S4: Figure 3b As shown, the polysilicon gate 110 is removed, and a gate dielectric layer 410 is formed, the gate dielectric layer 410 covers the surface of the fin body 120 and the surface of the first field oxide 210, and a work function layer 420 is formed, the work function layer 420 covers the surface of the gate dielectric layer 410;

[0033] In one embodiment, the gate dielectric layer 410 includes a high dielectric constant layer, and the material of the high dielectric constant layer includes silicon dioxide, silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium oxide silicate, hafnium dioxide, lanthanum oxide, zirconium dioxide, strontium titanate, and zirconium oxide silicate.

[0034] S5: Figure 3c As shown, a metal gate 510 is formed, the metal gate 510 fills the removed area of ​​the polysilicon gate 110, and the metal gate 510, the fin body 120, the gate dielectric layer 410 and the work function layer 420 form a metal gate structure of the fin field effect transistor;

[0035] S6: Figure 4c and 3d As shown, the partial regions 610 and 620 of the metal gate 510 beyond the end of the fin region 630 are removed to form a first groove 310, and a dielectric layer 320 is formed in the first groove 310;

[0036] In one embodiment, the material of the dielectric layer 320 is silicide, such as silicon dioxide.

[0037] In one embodiment, a portion of the metal gate 510 beyond the end of the fin region 630 is removed by a photolithography and etching process.

[0038] S7: Figure 4d As shown, a zeroth metal layer 130 is formed to lead out the source region 141 and the drain region 142 , and the metal gate structure and the source region 141 and the drain region 142 on both sides thereof form a fin field effect transistor.

[0039] The fin region 630 is a region on a semiconductor substrate of a fin field effect transistor where the fin 120 is distributed.

[0040] As described above, in the present invention, after the metal gate, gate dielectric layer and work function layer of the metal gate structure are formed through steps S1 to S5, a portion of the end of the metal gate that exceeds the fin body region 630 is removed in step S6. Since the work function layer has been formed, there is no need to worry about whether the formation window of the work function layer meets the process requirements. Therefore, more end regions of the metal gate can be removed, and the parasitic capacitance Cgs between the gate and the source or the parasitic capacitance Cgd between the gate and the drain of the final fin field effect transistor device can be minimized. Therefore, the manufacturing method of the fin field effect transistor of the present invention can minimize the parasitic capacitance Cgs between the gate and the source or the parasitic capacitance Cgd between the gate and the drain on the basis of ensuring the formation window of the work function layer, and compared with the typical manufacturing method of the fin field effect transistor, no new process needs to be added, and the process can be made simpler.

[0041] In one embodiment of the present invention, a fin field effect transistor structure is also provided. Figure 3d A schematic cross-sectional view of a fin field effect transistor along a metal gate, and Figure 4d Schematic diagram of the fin field effect transistor. Figure 3d and Figure 4dAs shown, a fin field effect transistor structure according to an embodiment of the present invention comprises: a semiconductor substrate 100, a plurality of fin bodies 120 are formed on the semiconductor substrate 100, shallow trenches are formed between the fin bodies 120, a first field oxide 210 is filled in the shallow trenches, a top surface of the first field oxide 210 is lower than the top surface of the fin body 120 so that the fin body 120 is exposed at the top of the first field oxide 210, so that the bottoms of the fin bodies 120 are isolated from each other by the first field oxide 210; a plurality of metal gates 510, the plurality of metal gates 510 intersect the plurality of fin bodies 120, the metal gates 510 and the overlapping regions 150 of the fin bodies 120 form a metal gate structure, the metal gates 510 cover the surface of the fin body 120 in the overlapping regions 150, and the plurality of metal gates 510 also cover the first field oxide 210. 210; a gate dielectric layer 410, located between the multiple metal gates 510 and the fin body 120 and the first field oxygen 210 covered by the multiple metal gates 510; a work function layer 420, located between the gate dielectric layer 410 and the metal gate 510, a source region 141 and a drain region 142 of a fin-type field effect transistor are formed on the fin body, the source region 141 and the drain region 142 are located on both sides of the metal gate structure, and the source region 141 and the drain region 142 are led out through the zeroth metal layer 130, so that the metal gate structure and the source region 141 and the drain region 142 located on both sides thereof form a fin-type field effect transistor, wherein a groove 310 is included at the end of the metal gate 510 of the fin-type field effect transistor, the groove is filled with a dielectric layer 320, the bottom of the dielectric layer 320 covers the first field oxygen 210, and the two side walls of the dielectric layer 320 are adjacent to the metal gate 510.

[0042] In one embodiment, the bottom of the dielectric layer 320 directly contacts and covers the first field oxide 210, and the two sidewalls of the dielectric layer 320 are directly in contact with and adjacent to the metal gate 510. In one embodiment, the groove 310 is formed by photolithographically etching a portion of the metal gate 510 beyond the end of the fin region 630, and then the dielectric layer 320 is filled in the groove 310.

[0043] More specifically, the groove 310 is located in a portion of the metal gate 510 that is beyond the end of the fin region 630. The fin region 630 is a region on a semiconductor substrate of a fin field effect transistor where the fin 120 is distributed.

[0044] In one embodiment, the material of the dielectric layer 320 is silicide, such as silicon dioxide.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a fin field effect transistor, characterized in that: include: S1: forming a plurality of fin bodies on a semiconductor substrate, wherein shallow trenches are formed between the fin bodies, and first field oxygen is filled in the shallow trenches, wherein a top surface of the first field oxygen is lower than a top surface of the fin body so that the fin body is exposed on the top of the first field oxygen, so that the bottoms of the fin bodies are isolated from each other by the first field oxygen; S2: forming a polysilicon layer, performing photolithography and etching to form a plurality of polysilicon gates, wherein the polysilicon gates intersect with the fins, and an overlapping region between the polysilicon gates and the fins forms a pseudo gate structure; S3: forming a source region and a drain region on the fin body, wherein the source region and the drain region are located on both sides of the polysilicon gate; S4: removing the polysilicon gate and forming a gate dielectric layer, the gate dielectric layer covers the surface of the fin body and the surface of the first field oxide, and forming a work function layer, the work function layer covers the surface of the gate dielectric layer; S5: forming a metal gate, the metal gate filling the removed area of ​​the polysilicon gate, and the metal gate, the fin body, the gate dielectric layer and the work function layer forming a metal gate structure of the fin field effect transistor; S6: removing a portion of the metal gate beyond the end of the fin region to form a first groove, and forming a dielectric layer in the first groove, wherein the fin region is a region on a semiconductor substrate of a fin field effect transistor where fins are distributed; as well as S7: forming a zeroth metal layer to lead out the source region and the drain region, and the metal gate structure and the source region and the drain region on both sides thereof form a fin field effect transistor.

2. The method for manufacturing a fin field effect transistor according to claim 1, wherein: In step S6 , a partial region of the end of the metal gate that exceeds the fin region is removed by a photolithography and etching process.

3. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The material of the dielectric layer is silicide.

4. The method for manufacturing a fin field effect transistor according to claim 3, wherein: The silicide is silicon dioxide.

5. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The gate dielectric layer includes a high dielectric constant layer.

6. The method for manufacturing a fin field effect transistor according to claim 1, wherein: An extension direction of the polysilicon gate is perpendicular to an extension direction of the fin body.

7. A fin field effect transistor structure, characterized in that: include: A semiconductor substrate, on which a plurality of fins are formed, wherein shallow trenches are formed between the fins, and the shallow trenches are filled with a first field oxygen, wherein a top surface of the first field oxygen is lower than a top surface of the fins so that the fins are exposed on top of the first field oxygen, so that the bottoms of the fins are isolated from each other by the first field oxygen; A plurality of metal gates, the plurality of metal gates intersecting the plurality of fins, the overlapping regions of the metal gates and the fins forming a metal gate structure, the metal gates covering the surface of the fins in the overlapping regions, and the plurality of metal gates also covering the surface of the first field oxide; A gate dielectric layer, located between the plurality of metal gates and the fin body and the first field oxygen region covered by the plurality of metal gates; A work function layer is located between the gate dielectric layer and the metal gate, and a source region and a drain region of a fin field effect transistor are formed on the fin body, the source region and the drain region are located on both sides of the metal gate structure, and the source region and the drain region are led out through the zeroth metal layer, so that the metal gate structure and the source region and the drain region located on both sides thereof form a fin field effect transistor, wherein a groove is included at the end of the metal gate of the fin field effect transistor, the groove is filled with a dielectric layer, the bottom of the dielectric layer is covered with a first field oxide, and the two side walls of the dielectric layer are adjacent to the metal gate; the groove is located in a partial area of ​​the end of the metal gate that exceeds the fin body area; the fin body area is an area where the fin body is distributed on the semiconductor substrate of the fin field effect transistor.

8. The fin field effect transistor structure according to claim 7, characterized in that: The bottom of the dielectric layer directly contacts and covers the first field oxide, and the two sidewalls of the dielectric layer directly contact and are adjacent to the metal gate.

9. The fin field effect transistor structure according to claim 7, characterized in that: The groove is formed by photolithographically etching a portion of the end of the metal gate that exceeds the fin region, and then filling the groove with a dielectric layer.

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