Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate having a fin; forming a dummy gate dielectric layer and an initial dummy gate layer on the substrate; removing a portion of the initial dummy gate layer to form a dummy gate layer; removing the dummy gate layer by one or more cover etching processes until the dummy gate dielectric layer is completely exposed, wherein the cover etching process includes: forming a protective layer on the surface of the exposed dummy gate dielectric layer; and removing a portion of the dummy gate layer by dry etching. Before each dry etching process is performed to remove a portion of the dummy gate layer, a protective layer is formed on the surface of the dummy gate dielectric layer exposed by the dummy gate layer, and the protective layer is superimposed on the dummy gate dielectric layer, so that the etching gas of the dry etching process is not easy to simultaneously penetrate the protective layer and the dummy gate dielectric layer and contact the surface of the fin, thereby causing damage to the fin, thereby effectively improving the performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently being widely used. Traditional planar transistors have weakened their ability to control channel current, resulting in short channel effects and leakage current, which ultimately affects the electrical performance of semiconductor devices.

[0003] In order to overcome the short channel effect of transistors and suppress leakage current, the prior art has proposed a fin field effect transistor (Fin FET). The fin field effect transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and a dielectric layer located on the surface of a semiconductor substrate, the dielectric layer covers a portion of the sidewall of the fin, and the surface of the dielectric layer is lower than the top of the fin; a gate structure located on the surface of the dielectric layer, and on the top and sidewall surfaces of the fin; and a source region and a drain region in the fin located on both sides of the gate structure.

[0004] In order to further reduce the device size and improve the device density, a high-K metal gate transistor is introduced based on the fin field effect transistor, that is, a high-K dielectric material is used as the gate dielectric layer and a metal material is used as the gate. The high-K metal gate transistor is formed by a gate last process, wherein a gate last process is to remove the dummy gate oxide layer and the dummy gate layer to form a gate trench, and then form a gate dielectric layer of a high-K dielectric material on the inner wall surface of the gate trench.

[0005] However, the prior art still has many problems in the process of removing the dummy gate structure. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.

[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of mutually discrete fins; forming a dummy gate dielectric layer and an initial dummy gate layer on the substrate, the dummy gate dielectric layer covering a portion of the sidewalls and the top surface of the fin, and the initial dummy gate layer being located on the dummy gate dielectric layer; using a first etching process to remove a portion of the initial dummy gate layer to form a dummy gate layer, the top surface of the dummy gate layer being lower than the top surface of the fin, and the dummy gate layer exposing a portion of the dummy gate dielectric layer; using one or more covering etching processes to remove the dummy gate layer until the dummy gate dielectric layer is completely exposed, the covering etching process comprising: forming a protective layer on the exposed surface of the dummy gate dielectric layer; using a dry etching process to remove a portion of the dummy gate layer, so that the top surface of the dummy gate layer is lower than the bottom surface of the protective layer.

[0008] Optionally, the material of the protective layer includes: silicon oxide.

[0009] Optionally, the density of the protection layer is greater than the density of the dummy gate dielectric layer.

[0010] Optionally, the method for forming a protective layer on the exposed surface of the dummy gate dielectric layer includes: forming a precursor layer on the exposed surface of the dummy gate dielectric layer; and performing oxidation treatment on the precursor layer to form the protective layer.

[0011] Optionally, the method for forming the precursor layer includes: treating the exposed surface of the dummy gate dielectric layer with a gas containing a silicon material, so that the gas containing the silicon material adheres to the exposed surface of the dummy gate dielectric layer to form the precursor layer.

[0012] Optionally, the gas containing silicon material includes: silane.

[0013] Optionally, the oxidation treatment method includes: performing oxygen plasma implantation treatment on the precursor layer.

[0014] Optionally, the thickness of the protective layer formed each time is 0.5 nanometers to 1 nanometer.

[0015] Optionally, before forming the protection layer each time, the method further includes: forming an inhibition layer on the surface of the dummy gate layer.

[0016] Optionally, after forming the protection layer each time and before removing part of the dummy gate layer, the method further includes: removing the inhibition layer.

[0017] Optionally, the material of the inhibition layer includes: acetone, ethanol or propylene glycol.

[0018] Optionally, the thickness of the inhibition layer formed each time is 0.5 nanometers to 1 nanometer.

[0019] Optionally, the first etching process includes: a wet etching process or a dry etching process.

[0020] Optionally, process parameters for removing part of the dummy gate layer by dry etching process include: etching gas includes CF4, HBr and H2; gas flow rate is 150 sccm to 300 sccm; etching time is 50s to 150s.

[0021] Optionally, the height of the dummy gate layer removed each time is 20 angstroms to 100 angstroms.

[0022] Optionally, the covering etching process is performed 5 to 10 times.

[0023] Optionally, after forming the initial dummy gate layer, the method further includes: forming a sidewall spacer on a sidewall of the initial dummy gate layer.

[0024] Optionally, after forming the sidewalls and before performing the covering etching process, it also includes: forming source-drain doping layers in the substrate on both sides of the initial pseudo-gate layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the sidewalls of the sidewalls.

[0025] Optionally, before forming the dummy gate dielectric layer and the initial dummy gate layer, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin, and a top surface of the isolation layer is lower than a top surface of the fin.

[0026] Optionally, after the dummy gate dielectric layer is completely exposed, the method further includes: forming an interface layer on surfaces of the protection layer and the dummy gate dielectric layer.

[0027] Optionally, the material of the interface layer includes: silicon oxide.

[0028] Optionally, after forming the interface layer, the method further includes: removing the interface layer, the protection layer and the dummy gate dielectric layer.

[0029] Optionally, after removing the interface layer, the protective layer and the dummy gate dielectric layer, the method further includes: forming a gate dielectric layer on the substrate, wherein the gate dielectric layer covers part of the sidewalls and the top surface of the fin; and forming a gate layer on the gate dielectric layer.

[0030] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0031] In the formation method of the technical solution of the present invention, a dry etching process is used to remove the dummy gate layer. Since the dry etching process has anisotropic characteristics, it can ensure that the corner positions of the dummy gate layer are also completely removed, so there will be no problem of incomplete removal of the dummy gate layer.

[0032] In addition, before each dry etching process is performed to remove part of the pseudo gate layer, a protective layer is formed on the surface of the pseudo gate dielectric layer exposed by the pseudo gate layer. The protective layer is superimposed on the pseudo gate dielectric layer, so that the etching gas of the dry etching process is not easy to penetrate the protective layer and the pseudo gate dielectric layer at the same time and contact the surface of the fin, thereby causing damage to the fin, thereby effectively improving the performance of the semiconductor structure finally formed.

[0033] Furthermore, the density of the protective layer is greater than that of the pseudo gate dielectric layer. By forming the protective layer with a higher density, the protective layer has better compactness, thereby better preventing the etching gas from penetrating into the surface of the fin and causing damage, effectively improving the performance of the semiconductor structure finally formed.

[0034] Furthermore, before forming the protective layer each time, it also includes: forming an inhibition layer on the surface of the pseudo gate layer. The function of the inhibition layer is, on the one hand, to cover the surface of the pseudo gate layer, so as to avoid forming the protective layer on the surface of the pseudo gate dielectric layer while also forming the protective layer on the surface of the pseudo gate layer, thereby avoiding the need to remove the protective layer on the pseudo gate layer before the subsequent etching of the pseudo gate layer; on the other hand, since the protective layer only needs to be formed on the exposed surface of the pseudo gate dielectric layer, the use of the inhibition layer will inhibit the formation of the precursor layer on its surface, and thus after the oxidation treatment, the protective layer will not be formed on the surface of the inhibition layer.

[0035] Furthermore, the material of the inhibition layer includes: acetone, ethanol or propylene glycol. This material can effectively prevent the precursor layer from being formed on the surface of the inhibition layer; in addition, this material is in liquid form, which is convenient for removal before the subsequent etching of the dummy gate layer.

[0036] Furthermore, after the pseudo gate dielectric layer is completely exposed, the method further includes: forming an interface layer on the surface of the protective layer and the pseudo gate dielectric layer. Since the thickness of the protective layer formed on the surface of the pseudo gate dielectric layer is uneven after multiple cover etching processes, and the thickness of the protective layer gradually decreases from the top surface of the fin to the bottom surface of the fin, the unevenness of the surface of the protective layer can be reduced by the interface layer, and the removal effect of the protective layer can be improved in the subsequent removal process of the protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0038] Figures 4 to 27 It is a schematic diagram of the structures of the steps of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0039] As described in the background art, there are still many problems in the prior art in the process of removing the dummy gate structure.

[0040] At present, when removing the pseudo gate layer (poly) in the pseudo gate structure, dry etching or wet etching is usually used. However, in the process of dry etching, since it is difficult to control the concentration of etching gas H2, when the concentration of H2 is high, H2 will penetrate through the pseudo gate dielectric layer of the pseudo gate structure and contact the top surface of the fin, and then easily damage the fin. In addition, in the process of wet etching, due to the diffusion characteristics of the etching solution and the generation of hydrogen bubbles, polysilicon material will usually remain. Both of these situations will affect the performance of the semiconductor device finally formed.

[0041] In order to solve the above problems, a method for forming a semiconductor structure is also provided in the prior art, which will be described in detail below with reference to the accompanying drawings.

[0042] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 has a plurality of mutually discrete fins 101; forming a dummy gate structure on the substrate 100, wherein the dummy gate structure covers a portion of the sidewalls and top surfaces of the fins 101, wherein the dummy gate structure includes a dummy gate dielectric layer 102, a dummy gate layer 103 located on the dummy gate dielectric layer 102, and a sidewall 104 located on the sidewall of the dummy gate layer 103, wherein the dummy gate layer 103 includes a first region I and a second region II located on the first region I.

[0043] Please refer to Figure 2 , the second region II of the dummy gate layer 103 is removed by dry etching.

[0044] Please refer to Figure 3 , a wet etching process is used to remove the first region I of the dummy gate layer 103.

[0045] In this embodiment, since dry etching is used to remove only the second region II of the gate layer 103, the dry etching time can be shortened, thereby reducing the penetration of H2 from the dry etching into the top surface of the fin 101, and effectively reducing the etching damage caused by the dry etching to the fin 101. However, when the wet etching process is used to remove the first region I of the dummy gate layer 103, since the wet etching is an isotropic etching process, at the corner position A of the dummy gate layer 103, the etching solution of the wet etching process is difficult to react completely with the gate layer, so there will also be residual material of the dummy gate layer 103.

[0046] On this basis, the present invention provides a method for forming a semiconductor structure, which uses a dry etching process to remove the dummy gate layer. Since the dry etching process has anisotropic characteristics, it can ensure that the corner positions of the dummy gate layer are also completely removed, so there will be no problem of incomplete removal of the dummy gate layer. In addition, before each dry etching process is performed to remove part of the dummy gate layer, a protective layer is formed on the surface of the dummy gate dielectric layer exposed by the dummy gate layer. The protective layer is superimposed on the dummy gate dielectric layer, so that the etching gas of the dry etching process is not easy to penetrate the protective layer and the dummy gate dielectric layer at the same time and contact the surface of the fin, thereby causing damage to the fin, effectively improving the performance of the semiconductor structure finally formed.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 4 to 27 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0049] Please refer to Figure 4 , providing a substrate 200 having a plurality of mutually discrete fins 201 thereon.

[0050] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown), the initial substrate having a mask layer (not shown), the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the fin 201 located on the substrate 200.

[0051] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0052] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0053] Please refer to Figure 5 , an isolation layer 202 is formed on the substrate 200 , wherein the isolation layer 202 covers a portion of the sidewall of the fin 201 , and a top surface of the isolation layer 202 is lower than a top surface of the fin 201 .

[0054] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200 ; etching and removing a portion of the initial isolation layer to form the isolation layer 202 , wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0055] The material of the isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0056] Please refer to Figure 6 After forming the isolation layer 202 , a dummy gate dielectric layer 203 and an initial dummy gate layer 204 are formed on the substrate 200 , wherein the dummy gate dielectric layer 203 covers part of the sidewalls and top surface of the fin 201 , and the initial dummy gate layer 204 is located on the dummy gate dielectric layer 203 .

[0057] In this embodiment, the material of the dummy gate dielectric layer 203 is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

[0058] In this embodiment, the material of the initial dummy gate layer 204 is polysilicon.

[0059] Please refer to Figure 7 After forming the dummy gate dielectric layer 203 and the initial dummy gate layer 204 , a sidewall spacer 205 is formed on the sidewall of the initial dummy gate layer 204 .

[0060] In this embodiment, the method for forming the side wall 205 includes: forming a side wall material layer (not shown) on the side wall and top surface of the initial pseudo gate layer 204 and the top surface of the isolation layer 202; removing the side wall material layer on the top surface of the initial pseudo gate layer 203 and the top surface of the isolation layer 202 to form the side wall 205.

[0061] In this embodiment, the material of the sidewall spacer 205 is silicon nitride.

[0062] Please refer to Figures 8 to 10 , Figure 8 is a top view of the semiconductor structure. Fig. 9 yes Figure 8 Schematic diagram of the cross section along line AA, Fig.10 yes Figure 8 In the cross-sectional diagram along line BB, after the sidewall 205 is formed, a source-drain doping layer 206 is formed in the substrate 200 on both sides of the initial pseudo-gate layer 204 ; a dielectric layer 207 is formed on the substrate 200 , and the dielectric layer 207 covers the sidewalls of the sidewall 205 .

[0063] In this embodiment, the method for forming the source-drain doped layer 206 includes: etching the fin 201 using the initial pseudo gate layer 204 and the sidewall 205 as a mask to form a plurality of epitaxial openings (not shown) in the fin 201; and forming the source-drain doped layer 206 in the epitaxial openings.

[0064] In this embodiment, the method for forming the dielectric layer 207 includes: forming an initial dielectric layer (not shown) on the substrate 200, wherein the initial dielectric layer covers the initial pseudo gate layer 204 and the side wall 205; and planarizing the initial dielectric layer until the top surfaces of the initial pseudo gate layer 204 and the side wall 205 are exposed, thereby forming the dielectric layer 207.

[0065] In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

[0066] Please refer to Fig.11 , Fig.11 and Fig.10 In accordance with the viewing direction, a first etching process is used to remove a portion of the initial dummy gate layer 204 to form a dummy gate layer 208, wherein the top surface of the dummy gate layer 208 is lower than the top surface of the fin 201, and the dummy gate layer 208 exposes a portion of the dummy gate dielectric layer 203.

[0067] The first etching process includes: a wet etching process or a dry etching process. In this embodiment, the first etching process adopts a dry etching process.

[0068] In this embodiment, a portion of the initial dummy gate layer 204 is first removed to expose a portion of the dummy gate dielectric layer 203 so that a protective layer can be subsequently formed on the exposed dummy gate dielectric layer 203 . In the subsequent process of removing the dummy gate layer 208 , the protective layer can prevent the etching gas from penetrating into the fin 201 and causing damage to the fin 201 .

[0069] After forming the dummy gate layer 208, the method further includes: removing the dummy gate layer 208 by one or more cover etching processes until the dummy gate dielectric layer 203 is completely exposed, and the method of the cover etching process includes: forming a protective layer on the exposed surface of the dummy gate dielectric layer 203; removing part of the dummy gate layer 208 by a dry etching process, so that the top surface of the dummy gate layer 208 is lower than the bottom surface of the protective layer. For the specific process, please refer to Figures 12 to 16 .

[0070] Please refer to Fig.12 , forming an inhibition layer 209 on the surface of the dummy gate layer 208 .

[0071] In this embodiment, the function of the inhibition layer 209 is, on the one hand, to cover the surface of the pseudo gate layer 208, so as to prevent the protective layer from being formed on the surface of the pseudo gate dielectric layer 203 and the protective layer from being formed on the surface of the pseudo gate layer 208, thereby avoiding the need to remove the protective layer on the pseudo gate layer 208 before the subsequent etching of the pseudo gate layer 208; on the other hand, since the protective layer only needs to be formed on the exposed surface of the pseudo gate dielectric layer 203, the use of the inhibition layer 209 will inhibit the subsequent precursor layer from being formed on its surface, and thus after the oxidation treatment, the protective layer will not be formed on the surface of the inhibition layer 209.

[0072] The material of the inhibition layer 209 includes acetone, ethanol or propylene glycol. In this embodiment, the material of the inhibition layer 209 is acetone. This material can effectively prevent the precursor layer from being formed on the surface of the inhibition layer 209. In addition, this material is in liquid form, which is convenient for removal before the subsequent etching of the dummy gate layer 208.

[0073] In this embodiment, the thickness of the inhibition layer 209 is 0.5 nanometers to 1 nanometer. The inhibition layer 209 with this thickness range can effectively prevent the subsequent precursor layer from being formed on the dummy gate layer 208 .

[0074] Please refer to Fig.13 , forming a precursor layer 210 on the exposed surface of the dummy gate dielectric layer 203 .

[0075] The method for forming the precursor layer 210 includes: treating the exposed surface of the dummy gate dielectric layer 203 with a gas containing silicon material, so that the gas containing silicon material adheres to the exposed surface of the dummy gate dielectric layer 203 to form the precursor layer 210 .

[0076] Since the gas containing silicon material has growth selectivity, this gas can adhere to the surface of the pseudo gate dielectric layer 203 to form the precursor layer 210, but will not adhere to the surface of the inhibition layer 209 to form the precursor layer 210, thereby ensuring that the protective layer formed by subsequent oxidation is only located on the pseudo gate dielectric layer 203.

[0077] In this embodiment, the gas containing silicon material includes silane.

[0078] Please refer to Fig.14 , the precursor layer 210 is oxidized to form the protective layer 211.

[0079] In this embodiment, the oxidation treatment method includes: performing oxygen plasma implantation treatment on the precursor layer 210 .

[0080] In this embodiment, the material of the protection layer 211 includes silicon oxide.

[0081] In this embodiment, the density of the protection layer 211 formed by oxidizing the precursor layer 210 is greater than the density of the dummy gate dielectric layer 203 .

[0082] By forming the protective layer 211 with a higher density, the protective layer 211 has a better compactness, thereby better preventing the etching gas from penetrating into the surface of the fin 201 to cause damage, thereby effectively improving the performance of the finally formed semiconductor structure.

[0083] In this embodiment, the thickness of the protective layer 211 is 0.5 nanometers to 1 nanometer. The protective layer 211 in this thickness range can have a good blocking effect on subsequent etching gases.

[0084] Please refer to Fig.15 After forming the protection layer 211, the inhibition layer 209 is removed.

[0085] In this embodiment, the method for removing the inhibition layer 209 includes: E-Chuck (electrostatic chuck) baking and vacuum evaporation process.

[0086] Please refer to Fig.16 After removing the inhibition layer 209 , a dry etching process is used to remove a portion of the dummy gate layer 208 , so that the top surface of the dummy gate layer 208 is lower than the bottom surface of the protection layer 211 .

[0087] In this embodiment, the dummy gate layer 208 is removed by dry etching. Since the dry etching process has anisotropic characteristics, it can ensure that the corners of the dummy gate layer 208 are also completely removed, so there will be no problem of incomplete removal of the dummy gate layer 208.

[0088] In addition, before each dry etching process is performed to remove a portion of the pseudo gate layer 208, a protective layer 211 is formed on the surface of the pseudo gate dielectric layer 203 exposed by the pseudo gate layer 208. The protective layer 211 is superimposed on the pseudo gate dielectric layer 203, so that the etching gas of the dry etching process is not easy to penetrate the protective layer 211 and the pseudo gate dielectric layer 203 at the same time and contact the surface of the fin 201, thereby causing damage to the fin 201, thereby effectively improving the performance of the semiconductor structure finally formed.

[0089] In this embodiment, process parameters for removing part of the dummy gate layer 208 by dry etching process include: etching gas includes CF4, HBr and H2; gas flow rate is 150 sccm to 300 sccm; etching time is 50s to 150s.

[0090] In this embodiment, the height of the dummy gate layer 208 removed each time is 20 angstroms to 100 angstroms. The height direction is a direction perpendicular to the top surface of the substrate 200. When the height of the dummy gate layer 208 removed at one time is less than 20 angstroms, more times of cover etching treatment are required, thereby reducing production efficiency; when the height of the dummy gate layer 208 removed at one time is greater than 100 angstroms, a larger area of ​​the dummy gate dielectric layer 203 located on the side wall of the fin 201 is exposed, and the etching gas easily penetrates from the dummy gate dielectric layer 203 on the side wall of the fin 201, thereby causing damage to the side wall of the fin 201.

[0091] At this point, one covering etching process is completed. If the dummy gate layer 208 has not been completely removed at this time, the next covering etching process needs to be performed until the dummy gate dielectric layer 203 is completely exposed.

[0092] For the convenience of description, in this embodiment, the number of times of the cover etching process is only 3 times. For the specific process, please refer to Figures 17 to 24 For a description of the relevant process, please refer to Figures 12 to 16 In the actual process, the number of times of the cover etching process is 5 to 10 times.

[0093] Please refer to Fig.25 After the dummy gate dielectric layer 203 is completely exposed, an interface layer 212 is formed on the surfaces of the protection layer 211 and the dummy gate dielectric layer 203 .

[0094] After multiple covering etching processes, the thickness of the protective layer 211 formed on the surface of the pseudo gate dielectric layer 203 is uneven, and the thickness of the protective layer 211 gradually decreases from the top surface of the fin 201 to the bottom surface of the fin 201. Therefore, the interface layer 212 can reduce the unevenness of the surface of the protective layer 211, and in the subsequent process of removing the protective layer 211, the removal effect of the protective layer 211 can be improved.

[0095] In this embodiment, the material of the interface layer 212 is silicon oxide.

[0096] Please refer to Fig.26 After forming the interface layer 212 , the interface layer 212 , the protection layer 211 and the dummy gate dielectric layer 203 are removed.

[0097] In this embodiment, the process of removing the interface layer 212, the protective layer 211 and the dummy gate dielectric layer 203 adopts a dry etching process; in other embodiments, the process of removing the interface layer, the protective layer and the dummy gate dielectric layer may also adopt a wet etching process.

[0098] Please refer to Fig. 27 After removing the interface layer 212 , the protective layer 211 and the pseudo gate dielectric layer 203 , a gate dielectric layer 213 is formed on the substrate 200 , and the gate dielectric layer 213 covers part of the sidewalls and the top surface of the fin 201 ; and a gate layer 214 is formed on the gate dielectric layer 213 .

[0099] In this embodiment, the gate dielectric layer 213 is made of a high-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9).

[0100] The material of the gate layer 214 includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the gate layer 214 is tungsten.

[0101] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of mutually discrete fins thereon; forming a dummy gate dielectric layer and an initial dummy gate layer on the substrate, wherein the dummy gate dielectric layer covers a portion of the sidewalls and the top surface of the fin, and the initial dummy gate layer is located on the dummy gate dielectric layer; Using a first etching process to remove a portion of the initial dummy gate layer to form a dummy gate layer, wherein a top surface of the dummy gate layer is lower than a top surface of the fin, and the dummy gate layer exposes a portion of the dummy gate dielectric layer; The dummy gate layer is removed by one or more covering etching processes until the dummy gate dielectric layer is completely exposed, wherein the covering etching process comprises: forming a protective layer on the exposed surface of the dummy gate dielectric layer; removing part of the dummy gate layer by a dry etching process so that the top surface of the dummy gate layer is lower than the bottom surface of the protective layer; wherein, Before forming the protection layer each time, forming an inhibition layer on the surface of the dummy gate layer; After forming the protection layer each time and before removing a portion of the dummy gate layer, the inhibition layer is removed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protection layer includes silicon oxide.

3. The method for forming a semiconductor structure according to claim 1, wherein: The density of the protection layer is greater than the density of the dummy gate dielectric layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming a protective layer on the exposed surface of the dummy gate dielectric layer comprises: forming a precursor layer on the exposed surface of the dummy gate dielectric layer; and performing oxidation treatment on the precursor layer to form the protective layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the precursor layer includes: treating the exposed surface of the dummy gate dielectric layer with a gas containing silicon material, so that the gas containing silicon material adheres to the exposed surface of the dummy gate dielectric layer to form the precursor layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The gas containing silicon material includes: silane.

7. The method for forming a semiconductor structure according to claim 4, wherein: The oxidation treatment method includes: performing oxygen plasma implantation treatment on the precursor layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the protective layer formed each time is 0.5 nanometers to 1 nanometer.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the inhibition layer includes: acetone, ethanol or propylene glycol.

10. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the inhibition layer formed each time is 0.5 nm to 1 nm.

11. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process includes: a wet etching process or a dry etching process.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of removing part of the dummy gate layer by dry etching process include: etching gas includes CF4, HBr and H2; gas flow rate is 150sccm~300sccm; etching time is 50s~150s.

13. The method for forming a semiconductor structure according to claim 1, wherein: The height of the dummy gate layer removed each time is 20 angstroms to 100 angstroms.

14. The method for forming a semiconductor structure according to claim 1, wherein: The number of times of the covering etching process is 5 to 10 times.

15. The method for forming a semiconductor structure according to claim 1, wherein: After forming the initial dummy gate layer, the method further includes: forming a sidewall spacer on the sidewall of the initial dummy gate layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: After forming the sidewalls and before performing the covering etching process, the method further includes: forming source-drain doping layers in the substrate on both sides of the initial pseudo-gate layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the sidewalls of the sidewalls.

17. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the dummy gate dielectric layer and the initial dummy gate layer, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin, and a top surface of the isolation layer is lower than a top surface of the fin.

18. The method for forming a semiconductor structure according to claim 1, wherein: After the dummy gate dielectric layer is completely exposed, the method further includes: forming an interface layer on the surfaces of the protection layer and the dummy gate dielectric layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the interface layer includes silicon oxide.

20. The method for forming a semiconductor structure according to claim 18, wherein: After forming the interface layer, the method further includes: removing the interface layer, the protection layer and the dummy gate dielectric layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: After removing the interface layer, the protective layer and the pseudo gate dielectric layer, the method further includes: forming a gate dielectric layer on the substrate, wherein the gate dielectric layer covers part of the sidewalls and the top surface of the fin; and forming a gate layer on the gate dielectric layer.

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