Semiconductor devices and their manufacturing methods

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an interlayer dielectric layer over a substrate, the substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the interlayer dielectric layer; a capacitor covered by the interlayer dielectric layer in the cell region; a contact plug penetrating the interlayer dielectric layer in the first peripheral region; a metal interconnect formed over the contact plug through the capping layer; and a through-electrode penetrating the capping layer and the interlayer dielectric layer and extending into the substrate in the second peripheral region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0122841, filed on September 23, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a capping layer, metal interconnects, and through-electrodes. Various embodiments of the present invention also relate to a method for manufacturing a semiconductor device. Background Technology

[0004] As the integration density of semiconductor devices increases, the area available for dielectric materials used in and between metal interconnects is decreasing. Therefore, technological improvements are needed to ensure proper operation and reduce the likelihood of device failures due to dielectric material defects. While various technologies have been proposed, further refinements are required. Summary of the Invention

[0005] Various embodiments of the present invention relate to a semiconductor device having a capping layer and a sacrificial layer, which can reduce process defects and improve device quality. Various other embodiments of the present invention relate to methods of manufacturing the semiconductor device of the present invention.

[0006] According to one embodiment of the present invention, a semiconductor device includes: an interlayer dielectric layer above a substrate, the substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer above the interlayer dielectric layer; a capacitor covered by the interlayer dielectric layer in the cell region; a contact plug penetrating the interlayer dielectric layer in the first peripheral region; a metal interconnect formed above the contact plug through the capping layer; and a through electrode penetrating the capping layer and the interlayer dielectric layer and extending into the substrate in the second peripheral region.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a contact plug that penetrates an interlayer dielectric layer over a substrate; forming a capping layer over the interlayer dielectric layer and the contact plug; forming a trench that exposes the upper surface of the contact plug by etching the capping layer; forming a sacrificial layer that fills the trench over the capping layer; forming a through-hole that penetrates the interlayer dielectric layer, the capping layer, and the sacrificial layer and extends into the substrate; removing the sacrificial layer to expose the trench; forming a metal interconnect in the trench; and forming a through-hole electrode in the through-hole.

[0008] These and other features and advantages of the present invention will be better understood by those skilled in the art through the following accompanying drawings and detailed description. Attached Figure Description

[0009] Figures 1 to 17 An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0010] Figure 18 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0011] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, in the various figures and embodiments of the invention, the same reference numerals refer to the same parts.

[0012] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that a third layer exists between the first layer and the second layer or the substrate.

[0013] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. Although the invention has been described with reference to dynamic random access memory (DRAM) for the sake of simplicity, the inventive concept is not limited thereto and can be applied to other memory or semiconductor devices.

[0014] Figures 1 to 17 An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] refer to Figure 1 A substrate 11 can be fabricated. Substrate 11 may include a semiconductor material. For example, substrate 11 may include a silicon substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. Substrate 11 may include a first region R1 and a second region R2. The first region R1 may be referred to as a "first peripheral region." The first region R1 may refer to the region where at least one transistor will be formed. The second region R2 may be referred to as a "second peripheral region." The second region R2 may refer to the region where at least one through-electrode will be formed.

[0016] An isolation layer 13 may be formed in the substrate 11 of the first region R1. For example, the isolation layer 13 may be formed by a shallow trench isolation (STI) process, which includes forming an isolation trench 12 and filling the isolation trench 12 with the isolation layer 13. The isolation layer 13 may define an active region 14. The isolation layer 13 may include, for example, silicon nitride, silicon oxide, or a combination thereof.

[0017] refer to Figure 2 A pre-gate dielectric layer 21A can be formed above the substrate 11. The pre-gate dielectric layer 21A may include a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The high-k material may include hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), or a combination thereof. The pre-gate dielectric layer 21A may also include an interface layer. The interface layer may include silicon oxide, silicon nitride, or a combination thereof. The pre-gate dielectric layer 21A may be formed as a stacked structure of the interface layer and the high-k material. The interface layer may be formed on the substrate 11, and then the high-k material may be formed on the interface layer.

[0018] A pre-gate electrode layer 22A may be formed over a pre-gate dielectric layer 21A. The pre-gate electrode layer 22A may comprise a semiconductor material. The pre-gate electrode layer 22A may be doped with impurities. Impurities can be doped using a doping process (e.g., implantation). According to an embodiment of the invention, the pre-gate electrode layer 22A may comprise polysilicon. According to another embodiment of the invention, the pre-gate electrode layer 22A may be formed of a metal-containing material.

[0019] A pre-blocking metal layer 23A may be formed above the pre-bottom gate electrode layer 22A. The height (or thickness) of the pre-blocking metal layer 23A may be less than the height of the pre-bottom gate electrode layer 22A. The pre-blocking metal layer 23A may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof. According to an embodiment of the present invention, the pre-blocking metal layer 23A may include a titanium nitride (TiN)-containing material.

[0020] A pre-gate electrode layer 24A may be formed above a pre-blocking metal layer 23A. The pre-gate electrode layer 24A may comprise a material whose resistivity is lower than that of the pre-bottom gate electrode layer 22A. For example, the pre-gate electrode layer 24A may comprise a metal, a metal nitride, a metal silicide, or a combination thereof. According to embodiments of the invention, the pre-gate electrode layer 24A may comprise tungsten (W) or a tungsten compound.

[0021] A pre-gate hard mask layer 25A may be formed above the pre-upper gate electrode layer 24A. The pre-gate hard mask layer 25A may be formed of a dielectric material having etch selectivity relative to the pre-upper gate electrode layer 24A. The height of the pre-gate hard mask layer 25A may be greater than the height of the pre-upper gate electrode layer 24A. The pre-gate hard mask layer 25A may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to an embodiment of the present invention, the pre-gate hard mask layer 25A may be formed of silicon nitride.

[0022] A gate mask 26 may be formed over the pre-gate hard mask layer 25A of the first region R1. The gate mask 26 may include a photoresist pattern. The gate mask 26 may extend in one direction or another. The gate mask 26 may be formed over only a portion of the first region R1. The second region R2 may not be protected by the gate mask 26. In other words, the pre-gate hard mask layer 25A of the second region R2 may be completely exposed.

[0023] refer to Figure 3 The gate structure 27 can be formed above the substrate 11 of the first region R1. This can expose the substrate 11 of the second region R2 again. The gate structure 27 can be formed above the active region 14 of the first region R1. The gate structure 27 can be at least one selected from planar gates, recessed gates, buried gates, omega gates, and fin gates. According to one embodiment of the present invention, the gate structure 27 can be a planar gate.

[0024] The gate structure 27 may include a gate dielectric layer 21, a lower gate electrode layer 22, a barrier metal layer 23, an upper gate electrode layer 24, and a gate hard mask layer 25. The gate structure 27 can be formed by etching the pre-gate hard mask layer 25A, the pre-upper gate electrode layer 24A, the pre-barrier metal layer 23A, the pre-lower gate electrode layer 22A, and the pre-gate dielectric layer 21A using a gate mask 26. Therefore, the gate dielectric layer 21 can be formed by etching the pre-gate dielectric layer 21A, the lower gate electrode layer 22 can be formed by etching the pre-lower gate electrode layer 22A, the barrier metal layer 23 can be formed by etching the pre-barrier metal layer 23A, the upper gate electrode layer 24 can be formed by etching the pre-upper gate electrode layer 24A, and the gate hard mask layer 25 can be formed by etching the pre-gate hard mask layer 25A.

[0025] After the gate structure 27 is formed, the gate mask 26 can be removed.

[0026] Subsequently, the substrate 11 of the first region R1 can be doped with impurities. Therefore, source / drain regions SD can be formed on both sides of the gate structure 27 in the substrate 11. During etching and doping of the first region R1, the second region R2 can be protected by an etching mask (not shown). Therefore, the source / drain regions SD can be formed only in the substrate 11 of the first region R1. After forming the source / drain regions SD in the first region R1, the etching mask (not shown) of the second region R2 can be removed.

[0027] The source / drain region (SD) can include N-type or P-type impurities. The source / drain region (SD) can include low-concentration and high-concentration source / drain regions. High-concentration source / drain regions can have a greater junction depth than low-concentration source / drain regions. High-concentration source / drain regions can have a higher doping concentration than low-concentration source / drain regions.

[0028] refer to Figure 4 The gate spacer 28 can be formed on the two sidewalls of the gate structure 27 in the first region R1. The second region R2 can be protected by an etch mask (not shown). After the gate spacer 28 is formed in the first region R1, the etch mask (not shown) can be removed.

[0029] Gate spacer 28 may be formed of a dielectric material. For example, gate spacer 28 may include a low-k material. Gate spacer 28 may include an oxide or a nitride. Gate spacer 28 may include silicon oxide, silicon nitride, or a metal oxide. Gate spacer 28 may include SiO2, Si3N4, or SiN.

[0030] Gate spacer 28 may include multiple layers of spacers. Gate spacer 28 may include air gaps. Thus, a pair of linear air gaps may be formed on the two sidewalls of gate spacer 28. This pair of linear air gaps may be symmetrical. According to some embodiments of the invention, the multiple layers of spacers may include a first spacer, a second spacer, and a third spacer, and the third spacer may be located between the first spacer and the second spacer. The multiple layers of spacers may include a NON (nitride-oxide-nitride) structure, wherein oxide spacers are located between nitride spacers. According to another embodiment of the invention, the multiple layers of spacers may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

[0031] refer to Figure 5 A low-level interlayer dielectric layer 30 can be formed above the exposed surfaces of the substrate 11 in the first region R1 and the second region R2. The low-level interlayer dielectric layer 30 can fill the gaps between adjacent gate structures 27.

[0032] The low-level interlayer dielectric layer 30 can be planarized to expose the upper surface of the gate structure 27. Therefore, the height of the gate structure 27 in the first region R1 and the height of the low-level interlayer dielectric layer 30 in the second region R2 can be the same. During the planarization process of the low-level interlayer dielectric layer 30, the gate spacer 28 can be planarized in a manner that exposes the upper surface of the gate structure 27. The low-level interlayer dielectric layer 30 can extend parallel to the gate structure 27.

[0033] The low-level interlayer dielectric layer 30 may be formed of a material with etch selectivity relative to the gate spacer 28. The low-level interlayer dielectric layer 30 may include a dielectric material. For example, the low-level interlayer dielectric layer 30 may include silicon oxide or silicon nitride. The low-level interlayer dielectric layer 30 may include a spin-on dielectric material (SOD).

[0034] Subsequently, metal interconnect contact holes 31 can be formed in the low-level interlayer dielectric layer 30 of the first region R1. A metal interconnect contact mask (not shown) can be formed to form the metal interconnect contact holes 31. The low-level interlayer dielectric layer 30 can be etched by using the metal interconnect contact mask as an etching mask. Thus, a portion of the substrate 11 can be exposed. The metal interconnect contact holes 31 can expose the surface of the source / drain region SD. The metal interconnect contact holes 31 can be formed to be spaced apart from the gate structure 27. A pair of metal interconnect contact holes 31 can be formed, each metal interconnect contact hole located on either side of the gate structure 27.

[0035] refer to Figure 6 The metal interconnect contact hole 31 can be filled with an ohmic contact layer 32, a conductive liner 33, and a low-level contact plug 34. In this case, the second region R2 can be protected by an etching mask (not shown). After the ohmic contact layer 32, the conductive liner 33, and the low-level contact plug 34 are formed in the first region R1, the etching mask (not shown) can be removed.

[0036] First, an ohmic contact layer 32 can be formed in the metal interconnect contact hole 31. The ohmic contact layer 32 can be formed over the source / drain region SD exposed by the metal interconnect contact hole 31. To form the ohmic contact layer 32, a process for depositing a silicideable metal layer can be performed, followed by an annealing process. The ohmic contact layer 32 may include a metal silicide. For example, the ohmic contact layer 32 may include cobalt silicide (CoSi). x The ohmic contact layer 32 may include cobalt silicide in the "CoSi2 phase". Therefore, the contact resistance can be improved.

[0037] Subsequently, a conductive liner 33 may be selectively formed over the ohmic contact layer 32. The conductive liner 33 may also cover the sidewalls of the metal interconnect contact hole 31. The conductive liner 33 may cover the low-level interlayer dielectric layer 30 exposed by the metal interconnect contact hole 31. For example, the conductive liner 33 may comprise a metal or a metal nitride. The conductive liner 33 may comprise titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0038] A low-level contact plug 34 can be formed above the conductive liner 33. The low-level contact plug 34 can fill the metal interconnect contact hole 31. A planarization process can be performed to form the low-level contact plug 34. Therefore, the upper surface of the low-level contact plug 34 can be at the same level as the upper surface of the low-level interlayer dielectric layer 30. The low-level contact plug 34 can include a metal or a metal compound. For example, the low-level contact plug 34 can include a tungsten (W)-containing material. The low-level contact plug 34 can include tungsten or a tungsten compound.

[0039] The low-level contact plug 34 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Plasma can be used to enhance the deposition effect. For example, the low-level contact plug 34 can be formed by methods such as plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD).

[0040] refer to Figure 7 A low-level metal interconnect 35 can be formed above the low-level contact plug 34. The low-level contact plug 34 and the low-level metal interconnect 35 can be referred to as a "lower metal interconnect structure". Although this embodiment shows one "lower metal interconnect structure" disposed above a source / drain region SD, according to another embodiment of the invention, two or more lower metal interconnect structures can be stacked. In other words, one or more "lower metal interconnect structures" can be formed and stacked on top of each other. When forming the low-level metal interconnect 35, the second region R2 can be protected by an etching mask (not shown). After the low-level metal interconnect 35 is formed in the first region R1, the etching mask (not shown) can be removed.

[0041] From a top plan view, the low-level metal interconnect 35 can extend linearly. The low-level metal interconnect 35 can be electrically connected to the low-level contact plug 34. The low-level metal interconnect 35 can be electrically connected to the source / drain region SD through the low-level contact plug 34. The width of the low-level metal interconnect 35 can be greater than the width of the low-level contact plug 34. The height of the low-level metal interconnect 35 can be less than the height of the low-level contact plug 34.

[0042] The low-level metal interconnect 35 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), PECVD, or PEALD processes. The methods for forming the low-level contact plug 34 and the low-level metal interconnect 35 can differ. For example, the low-level contact plug 34 can be formed by chemical vapor deposition (CVD), while the low-level metal interconnect 35 can be formed by physical vapor deposition (PVD). According to another embodiment of the invention, the low-level contact plug 34 and the low-level metal interconnect 35 can be integrally formed by a single deposition process.

[0043] The low-level metal interconnect 35 may comprise a metal or a metal compound. The low-level metal interconnect 35 may comprise, for example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), molybdenum (Mo), or combinations thereof. The low-level metal interconnect 35 may be a single layer or multiple layers. According to embodiments of the present invention, the low-level metal interconnect 35 may comprise a tungsten (W)-containing material.

[0044] Subsequently, a lower cover layer 36 can be formed over the low-level interlayer dielectric layer 30 and the low-level metal interconnect 35. The lower cover layer 36 can fill the space between the low-level metal interconnects 35. The lower cover layer 36 can cover the sidewall portion of the low-level metal interconnect 35. The height of the lower cover layer 36 can be the same as the height of the low-level metal interconnect 35. A planarization process can be performed to form the lower cover layer 36. Therefore, the upper surface of the low-level metal interconnect 35 can be exposed. The lower cover layer 36 can protect the low-level metal interconnect 35 from the effects of subsequent processes.

[0045] The lower capping layer 36 may include a dielectric material. For example, the lower capping layer 36 may include silicon nitride. The lower capping layer 36 may include a poor step capping material. The lower capping layer 36 may be formed, for example, by a plasma-enhanced chemical vapor deposition (PECVD) process.

[0046] An etch stop layer 37 may be formed over the lower cover layer 36 and the low-level metal interconnect 35. The thickness of the etch stop layer 37 may be thinner than the thickness of the low-level metal interconnect 35. The etch stop layer 37 may include a nitrogen-containing material.

[0047] refer to Figure 8 An interlayer dielectric layer 38 can be formed above the etch stop layer 37.

[0048] The height of the interlayer dielectric layer 38 may be greater than the height of the lower-level interlayer dielectric layer 30. The interlayer dielectric layer 38 may comprise a single-layer or multi-layer stacked structure. The interlayer dielectric layer 38 may comprise a dielectric material. The interlayer dielectric layer 38 may comprise an oxide or a nitride. The interlayer dielectric layer 38 may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The interlayer dielectric layer 38 may comprise TEOS.

[0049] A pre-contact hole hard mask layer 39A may be formed over the interlayer dielectric layer 38. The pre-contact hole hard mask layer 39A may include a material with etching selectivity relative to the interlayer dielectric layer 38. The pre-contact hole hard mask layer 39A may include a dielectric material. The pre-contact hole hard mask layer 39A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to an embodiment of the present invention, the pre-contact hole hard mask layer 39A may include silicon nitride.

[0050] A contact hole mask pattern 40 can be formed over the pre-contact hole hard mask layer 39A. The contact hole mask pattern 40 may include a photoresist pattern. The contact hole mask pattern 40 may cover the pre-contact hole hard mask layer 39A of the second region R2.

[0051] refer to Figure 9 Contact holes 41 can be formed in the interlayer dielectric layer 38 of the first region R1.

[0052] The pre-contact hole hard mask layer 39A can be etched using the contact hole mask pattern 40 as an etching mask. Therefore, the contact hole hard mask 39 can be formed. The interlayer dielectric layer 38 can be etched using the contact hole hard mask 39 as an etching mask. Therefore, the contact hole 41 can be formed.

[0053] Contact hole 41 can penetrate contact hole hard mask 39 and interlayer dielectric layer 38. The upper surface of low-level metal interconnect 35 can be partially exposed by contact hole 41.

[0054] After the contact hole 41 is formed, the contact hole mask pattern 40 can be removed.

[0055] refer to Figure 10 This can form a contact plug 42 that fills the contact hole 41.

[0056] Contact plug 42 may be formed above the low-level metal interconnect 35. Contact plug 42 may penetrate the contact hole hard mask 39 and the interlayer dielectric layer 38. A planarization process may be performed to form contact plug 42. Therefore, the upper surface of contact plug 42 may be at the same level as the upper surface of contact hole hard mask 39. Contact plug 42 may include a metal or metal compound. For example, contact plug 42 may include a tungsten-containing material. Contact plug 42 may include tungsten or a tungsten compound.

[0057] Contact plug 42 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Plasma can be used to enhance the deposition effect. In other words, low-level contact plug 34 can be formed using methods such as plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD).

[0058] According to another embodiment of the invention, the contact plug 42 may have the same structure as the low-level contact plug 34. In other words, the contact hole 41 may be filled with an ohmic contact layer (not shown), a conductive liner (not shown), and the contact plug 42.

[0059] First, an ohmic contact layer (not shown) can be formed in the contact hole 41. An ohmic contact layer (not shown) can be formed over the low-level metal interconnect 35 exposed by the contact hole 41. To form the ohmic contact layer (not shown), a process for depositing a silicideable metal layer can be performed, followed by an annealing process. The ohmic contact layer (not shown) may include cobalt silicide (CoSi). x ).

[0060] Subsequently, a conductive liner (not shown) may be selectively formed over the ohmic contact layer (not shown). The conductive liner (not shown) may cover the sidewalls and bottom surface of the contact hole 41. The conductive liner (not shown) may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0061] Contact plug 42 may be formed above a conductive liner (not shown). Contact plug 42 may fill contact hole 41. A planarization process may be performed to form contact plug 42.

[0062] refer to Figure 11 A pre-covering layer 50A can be formed over the contact hole hard mask 39 and the contact plug 42.

[0063] The pre-cover layer 50A may cover the contact hole hard mask 39 and the contact plug 42. The thickness of the pre-cover layer 50A may be greater than the thickness of the contact hole hard mask 39. The pre-cover layer 50A may include an oxygen-containing material. The pre-cover layer 50A may include an oxide. The pre-cover layer 50A may include silicon oxide. The pre-cover layer 50A may consist only of oxides. The pre-cover layer 50A may not contain nitrides. The pre-cover layer 50A may not contain nitrides.

[0064] A pre-metal interconnect hard mask layer 51A may be formed over a pre-cover layer 50A. The pre-metal interconnect hard mask layer 51A may include a material with etching selectivity relative to the pre-cover layer 50A. The pre-metal interconnect hard mask layer 51A may include a dielectric material. The pre-metal interconnect hard mask layer 51A may include, for example, silicon nitride, silicon oxynitride, carbon-containing materials, or combinations thereof.

[0065] The metal interconnect mask 52 may be formed on the pre-metal interconnect hard mask layer 51A. The metal interconnect mask 52 may include a photoresist pattern.

[0066] refer to Figure 12 The pre-metal interconnect hard mask layer 51A can be etched using the metal interconnect mask 52 as an etching mask. Therefore, the metal interconnect hard mask layer 51 can be formed. The pre-cover layer 50A can be etched using the metal interconnect hard mask layer 51 as an etching mask. Therefore, the cover layer 50 and the trench 53 can be formed.

[0067] The trench 53 can penetrate the metal interconnect hard mask layer 51 and the cover layer 50 to partially expose the contact hole hard mask 39. The upper surface of the contact plug 42 can be exposed through the trench 53. Viewed from above, the trench 53 can extend linearly in a direction perpendicular to the stacking direction.

[0068] After the cover layer 50 and the trench 53 are formed, the metal interconnect mask 52 and the metal interconnect hard mask layer 51 can be removed.

[0069] refer to Figure 13 A sacrificial layer 54 can be formed above the cover layer 50 and the trench 53 can be filled.

[0070] The sacrificial layer 54 can cover the upper surface of the cover layer 50 and fill the trench 53. The height from the upper surface of the contact hole hard mask 39 to the upper surface of the sacrificial layer 54 can be greater than the height from the upper surface of the contact hole hard mask 39 to the upper surface of the cover layer 50. The height from the upper surface of the cover layer 50 to the upper surface of the sacrificial layer 54 can be less than the height from the upper surface of the contact hole hard mask 39 to the upper surface of the cover layer 50.

[0071] The sacrificial layer 54 may include, for example, oxide or polycrystalline silicon. The sacrificial layer 54 may include a spin-on dielectric material (SOD). The sacrificial layer 54 may include carbon. The sacrificial layer 54 may include one selected from spin-on carbon (SOC), high-density plasma (HDP), and borosilicate glass (BPSG). In one embodiment, the sacrificial layer 54 may include hard mask carbon. Hard mask carbon may include a carbon layer deposited by a chemical vapor deposition (CVD) process. According to an embodiment of the present invention, the sacrificial layer 54 may include spin-on carbon (SOC).

[0072] refer to Figure 14 A pre-perforated hard mask layer 55A can be formed above the sacrificial layer 54.

[0073] The pre-penetrating via hard mask layer 55A may cover the first region R1. The pre-penetrating via hard mask layer 55A may include a material with etching selectivity relative to the sacrificial layer 54. The pre-penetrating via hard mask layer 55A may include a dielectric material. For example, the pre-penetrating via hard mask layer 55A may include silicon nitride, silicon oxynitride, carbon-containing materials, or combinations thereof.

[0074] The through-hole mask pattern 56 can be formed over the pre-through-hole hard mask layer 55A. The through-hole mask pattern 56 may include a photoresist pattern.

[0075] refer to Figure 15 The pre-via hard mask layer 55A can be etched using the through-via mask pattern 56 as an etching mask. As a result, the through-via hard mask 55 can be formed. Using the through-via hard mask 55 as an etching mask, the sacrificial layer 54, capping layer 50, contact via hard mask 39, interlayer dielectric layer 38, etch stop layer 37, lower capping layer 36, and low-level interlayer dielectric layer 30 can be etched. As a result, through-via 57 can be formed.

[0076] The through-hole 57 can be formed spaced apart from the contact plug 42. The through-hole 57 can be formed spaced apart from the trench 53. The width of the through-hole 57 can be greater than the width of the contact plug 42. The width of the through-hole 57 can be greater than the width of the trench 53, but is not limited thereto. The through-hole 57 can penetrate the sacrificial layer 54, the capping layer 50, the contact hole hard mask 39, the interlayer dielectric layer 38, the etch stop layer 37, the lower capping layer 36, and the low-level interlayer dielectric layer 30, and can extend into the substrate 11. The depth of the through-hole 57 in the substrate 11 can be greater than the depth of the isolation layer 13. According to another embodiment of the invention, the through-hole 57 can penetrate the substrate 11. In one embodiment, the sidewalls of the through-hole 57 can have a bevel. The sidewalls of the through-hole 57 can have an inclined profile. The width of the through-hole 57 can decrease as it decreases from a high level to a low level.

[0077] After the through hole 57 is formed, the through hole hard mask 55 can be removed.

[0078] refer to Figure 16 This can remove the sacrificial layer 54.

[0079] With the sacrificial layer 54 removed, the capping layer 50 and the trench 53 can be exposed again. Therefore, the upper surface of the contact plug 42 can be exposed. The sacrificial layer 54 can be removed by a variety of suitable methods, such as leaching processes, ashing processes, etc. For example, when the sacrificial layer 54 is formed by SOD, it can be removed by a leaching process; when it is formed by SOC, it can be removed by an ashing process. When performing a wet leaching process to remove the sacrificial layer 54, wet chemicals such as hydrofluoric acid or buffered oxide etchant (BOE) can be used.

[0080] refer to Figure 17 A dielectric liner 58 can be formed around the sidewalls and bottom surface of the through-hole 57. According to another embodiment of the invention, the dielectric liner 58 may have a shape that only surrounds the sidewalls of the through-hole 57 without covering the bottom surface of the through-hole 57. The dielectric liner 58 may include a dielectric material. The dielectric liner 58 may include, for example, oxides, nitrides, or combinations thereof. The dielectric liner 58 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to an embodiment of the invention, the dielectric liner 58 may include oxides. According to another embodiment of the invention, the dielectric liner 58 may also be formed in the trench 53.

[0081] Although not shown, a barrier layer may be formed above the dielectric liner 58. The barrier layer may be a single layer or a layer of two or more layers. The barrier layer may include a metallic material. The barrier layer may include a metal or a metal compound. The barrier layer may include materials such as Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, or WN.

[0082] Subsequently, a metal material filling the through-hole 57 can be formed above the dielectric liner 58. A metal material filling the trench 53 can be formed above the contact plug 42. The metal material can cover the capping layer 50. A planarization process can be performed to expose the upper surface of the capping layer 50. As a result, a through electrode 60 can be formed above the dielectric liner 58. A metal interconnect 59 can be formed above the contact plug 42. The through electrode 60 and the metal interconnect 59 can be formed simultaneously. The through electrode 60 and the metal interconnect 59 can be formed separately. The upper surface of the through electrode 60 and the upper surface of the metal interconnect 59 can be at the same level. The sidewalls of the metal interconnect 59 can directly contact the capping layer 50.

[0083] The through-electrode 60 and the metal interconnect 59 may include one or more stacked structures. The metal material filling the through-electrode 60 and the metal interconnect 59 may include a metal with high conductivity. The metal material filling the through-electrode 60 and the metal interconnect 59 may include the same material. The metal material may include one or more selected from: Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr. For example, the through-electrode 60 and the metal interconnect 59 may include copper (Cu) or tungsten (W). According to an embodiment of the invention, the through-electrode 60 and the metal interconnect 59 may include copper (Cu). The metal material may be formed by any suitable method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), PECVD, PEALD, etc.

[0084] The method for manufacturing a semiconductor device according to embodiments of the present invention can improve RC delay and reduce process defects, such as ion migration, because the capping layer 50 is located between the metal interconnects 59. Therefore, the characteristics of the semiconductor device can be improved.

[0085] Furthermore, when the metal interconnect 59 and the through electrode 60 are formed simultaneously, process stability can be ensured and the process can be simplified, which leads to an increase in yield.

[0086] Figure 18 This is a cross-sectional view showing a semiconductor device 100 according to an embodiment of the present invention.

[0087] refer to Figure 18 The semiconductor device 100 may include a substrate 101. The substrate 101 may include a cell region C, a first peripheral region P1, and a second peripheral region P2. The cell region C may include a capacitor CAP. The first peripheral region P1 may include a metal interconnect ML. The second peripheral region P2 may include a through-hole electrode TSV.

[0088] Substrate 101 may include, for example, a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, combinations thereof, or multilayers thereof. In another example, substrate 101 may include other semiconductor materials, such as germanium. In yet another example, substrate 101 may include a group III-V semiconductor substrate, such as a compound semiconductor substrate like GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0089] An isolation layer 103 can be formed in the substrate 101 of the cell region C and the first peripheral region P1. The isolation layer 103 can be formed using a shallow trench isolation (STI) process. The isolation layer 103 can be formed in a trench 102. The trench 102 can be formed in the substrate 101 of the cell region C and the first peripheral region P1. The isolation layer 103 can define a plurality of cell active regions 104C in the cell region C. The isolation layer 103 can define a peripheral active region 104P in the first peripheral region P1. The cell active regions 104C and the peripheral active regions 104P can have a shape that is isolated by the isolation layer 103.

[0090] First, the description unit region C will be used.

[0091] The cell region C may include the cell source / drain region CSD. The cell source / drain region CSD may be doped with N-type or P-type impurities.

[0092] Bit line contact plugs 106 may be formed above substrate 101. Bit line contact plugs 106 may be coupled to the cell source / drain region CSD. Bit line contact plugs 106 may be formed through the cell interlayer dielectric layer 105. The cell interlayer dielectric layer 105 may be formed above substrate 101. The cell interlayer dielectric layer 105 may include a dielectric material. The lower surface of bit line contact plugs 106 may be located at a lower level than the upper surface of substrate 101. Bit line contact plugs 106 may be formed of polysilicon or a metallic material.

[0093] The bitline structure BL can be formed above the bitline contact plug 106. The bitline structure BL may include a stack of cell barrier layer 107, bitline 108 and bitline hard mask 109.

[0094] A cell barrier layer 107 may be formed above the bit line contact plug 106. The cell barrier layer 107 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof.

[0095] The linewidth of bit line 108 and the linewidth of bit line contact plug 106 can be the same. Bit line 108 can extend in one direction while covering cell barrier layer 107. Bit line 108 can include metal, metal nitride, metal silicide, or combinations thereof. According to embodiments of the present invention, bit line 108 can include tungsten (W) or tungsten compounds.

[0096] A bitline hard mask 109 may be formed over the bitline 108. The thickness of the bitline hard mask 109 may be greater than the thickness of the bitline 108. The bitline hard mask 109 may include a dielectric material. In one embodiment, the bitline hard mask 109 may include silicon nitride.

[0097] Bit line spacers 110 can be formed on two sidewalls of the bit line structure BL. Bit line spacers 110 can be formed of a dielectric material. Bit line spacers 110 can include multiple layers of spacers. The multiple layers of spacers can include a first spacer, a second spacer, and a third spacer, with the third spacer located between the first and second spacers. The multiple layers of spacers can include a non-non-polar structure, wherein oxide spacers are located between nitride spacers. According to another embodiment of the invention, the multiple layers of spacers can include a first spacer, a second spacer, and an air gap between the first and second spacers.

[0098] Storage node contact plugs (SNCs) can be formed on the two sidewalls of bit line contact plugs 106 and bit line structure BL. Storage node contact plugs (SNCs) can be formed independently on both sides of bit line structure BL. Storage node contact plugs (SNCs) can be located between substrate 101 and capacitor CAP. Storage node contact plugs (SNCs) can include a lower plug (not shown), a cell ohmic contact layer (not shown), and an upper plug (not shown).

[0099] A lower plug (not shown) can be formed that penetrates the interlayer dielectric layer 105. The lower plug (not shown) may be bulb-shaped. The lower plug (not shown) may include a silicon-containing material. The lower plug (not shown) may include polycrystalline silicon. A unit ohmic contact layer (not shown) may be formed above the lower plug (not shown). The unit ohmic contact layer (not shown) may include a metal silicide. An upper plug (not shown) may be formed above the unit ohmic contact layer (not shown). The upper plug (not shown) may include a metal-containing material. The upper plug (not shown) may include tungsten (W).

[0100] A landing pad 115 may be formed above the storage node contact plug SNC. The landing pad 115 may be electrically connected to the storage node contact plug SNC. The landing pad 115 may overlap with a portion of the bit line structure BL.

[0101] A cell cover layer 116 can be formed to cover the bit line structure BL. The cell cover layer 116 can partially cover the upper surface of the bit line structure BL. The cell cover layer 116 can partially cover the upper surface of the bit line spacer 110. The cell cover layer 116 can cover the sidewall of the bonding pad 115. The upper surface of the cell cover layer 116 can be at the same level as the upper surface of the bonding pad 115. The cell cover layer 116 can include a dielectric material. The cell cover layer 116 can include silicon nitride. An etch stop layer 132 can be formed above the bonding pad 115 and the cell cover layer 116.

[0102] A capacitor CAP can be formed above the bonding pad 115. The capacitor CAP can be electrically connected to the storage node contact plug SNC. The capacitor CAP can be covered by the interlayer dielectric layer 133.

[0103] A capacitor CAP may include a lower electrode LE, a dielectric layer EL, and an upper electrode TE. The lower electrode LE may have a cylindrical or cylindrical shape. According to embodiments of the invention, the lower electrode LE may have a cylindrical shape. The lower electrode LE may include a metal or a metal compound. The dielectric layer EL may have a shape surrounding the lower electrode LE. The dielectric layer EL may include a high-k material. The dielectric layer EL can be formed by depositing a high-k material such as zirconium oxide (ZrO2). The dielectric layer EL may be formed from a composite layer. For example, the dielectric layer EL may be formed from a composite layer ZAZ (ZrO2 / Al2O3 / ZrO2). The upper electrode TE may be formed on top of the dielectric layer EL. The upper electrode TE may cover the dielectric layer EL. The upper electrode TE may include a metal or a metal compound. For example, the upper electrode TE may be formed by depositing titanium nitride (TiN) and tungsten (W).

[0104] An interlayer dielectric layer 133 may be formed on the upper electrode TE. The interlayer dielectric layer 133 may comprise a single-layer or multi-layer stacked structure. The interlayer dielectric layer 133 may comprise oxides, nitrides, or combinations thereof. In one embodiment, the interlayer dielectric layer 133 may comprise TEOS.

[0105] A contact hole hard mask 134 may be formed over the interlayer dielectric layer 133. The contact hole hard mask 134 may include a material with etching selectivity relative to the interlayer dielectric layer 133. The contact hole hard mask 134 may include a dielectric material.

[0106] A first interconnect E1 can be formed that penetrates the hard mask 134 of the contact hole and the interlayer dielectric layer 133. The first interconnect E1 can directly contact the upper electrode TE. Therefore, the first interconnect E1 can be electrically connected to the capacitor CAP. The first interconnect E1 can be formed simultaneously with the contact plug CP, which will be described later. The first interconnect E1 can also be formed separately from the contact plug CP, which will be described later. The structure of the first interconnect E1 can be the same as that of the contact plug CP. The material of the first interconnect E1 can be the same as that of the contact plug CP.

[0107] A capping layer 135 may be formed over the contact hole hard mask 134. The capping layer 135 may be formed to be thicker than the contact hole hard mask 134. The capping layer 135 may cover the contact hole hard mask 134. The thickness of the capping layer 135 may be greater than the thickness of the contact hole hard mask 134.

[0108] The capping layer 135 may include an oxygen-containing material. The capping layer 135 may include an oxide. The capping layer 135 may include silicon oxide. The capping layer 135 may consist only of oxides. The capping layer 135 may be formed of oxides. The capping layer 135 may not contain nitrides. The capping layer 135 may be nitride-free.

[0109] The second interconnect E2 may be formed on top of the first interconnect E1. The second interconnect E2 may penetrate the cover layer 135. The upper surface of the second interconnect E2 may be at the same level as the upper surface of the cover layer 135. The second interconnect E2 may be formed simultaneously with the metal interconnect ML, which will be described later. The second interconnect E2 may be formed separately from the metal interconnect ML. The structure of the second interconnect E2 may be the same as the structure of the metal interconnect ML. The material of the second interconnect E2 may be the same as the material of the metal interconnect ML.

[0110] The first outer region P1 will then be described.

[0111] The first peripheral region P1 may include a transistor. The transistor may include a peripheral active region 104P, a gate structure PG above the peripheral active region 104P, gate spacers 125 formed on the two sidewalls of the gate structure PG, and a peripheral source / drain region PSD formed in the peripheral active region 104P aligned with the two sides of the gate structure PG. The peripheral source / drain region PSD may be doped with N-type or P-type impurities.

[0112] The gate structure PG may include a gate dielectric layer 120 formed over the peripheral active region 104P, a lower gate electrode 121 formed over the gate dielectric layer 120, a peripheral barrier layer 122 formed over the lower gate electrode 121, an upper gate electrode 123 formed over the peripheral barrier layer 122, and a gate hard mask 124 formed over the upper gate electrode 123. The gate structure PG may include a stack of the gate dielectric layer 120, the lower gate electrode 121, the peripheral barrier layer 122, and the upper gate electrode 123. According to an embodiment of the present invention, the gate structure PG may be a planar gate.

[0113] The gate dielectric layer 120 may be located above the substrate 101. The gate dielectric layer 120 may include a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof.

[0114] The lower gate electrode 121 may be formed above the gate dielectric layer 120. The lower gate electrode 121 may comprise polysilicon. According to another embodiment of the present invention, the lower gate electrode 121 may be formed of a metal-containing material.

[0115] The peripheral barrier layer 122 may be located above the lower gate electrode 121. The height of the peripheral barrier layer 122 may be lower than the height of the lower gate electrode 121. The peripheral barrier layer 122 may include titanium nitride (TiN).

[0116] The upper gate electrode 123 may be located above the peripheral barrier layer 122. The upper gate electrode 123 may include a metal, a metal nitride, a metal silicide, or a combination thereof. The upper gate electrode 123 may include tungsten (W) or a tungsten compound.

[0117] The gate hard mask 124 may be located above the upper gate electrode 123. The gate hard mask 124 may include a material with etching selectivity relative to the upper gate electrode 123. The height of the gate hard mask 124 may be greater than the height of the upper gate electrode 123. The gate hard mask 124 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0118] Gate spacers 125 may be located on both sidewalls of the gate structure PG. Gate spacers 125 may be formed of a dielectric material. Gate spacers 125 may include oxides or nitrides. Gate spacers 125 may include multilayer spacers. Gate spacers 125 may include air gaps.

[0119] A low-level interlayer dielectric layer 130 can be formed to cover the gate structure PG and the gate spacer 125. The low-level interlayer dielectric layer 130 may include a dielectric material. The height of the low-level interlayer dielectric layer 130 may be the same as the height of the gate structure PG.

[0120] The peripheral source / drain region PSD can be coupled to the low-level metal interconnect 129 via a low-level contact plug 128. The low-level contact plug 128 can penetrate the low-level interlayer dielectric layer 130. A peripheral ohmic contact layer 126 and a conductive liner 127 can be formed between the low-level contact plug 128 and the peripheral source / drain region PSD.

[0121] A peripheral ohmic contact layer 126 may be formed over the substrate 101. The peripheral ohmic contact layer 126 may include a metal silicide. A conductive liner 127 may be formed over the peripheral ohmic contact layer 126 and the sidewalls of the low-level interlayer dielectric layer 130. The conductive liner 127 may include titanium nitride and may be optionally omitted. A low-level contact plug 128 may be formed over the conductive liner 127. The low-level contact plug 128 may penetrate the low-level interlayer dielectric layer 130 to couple to the peripheral source / drain region PSD. The upper surface of the low-level contact plug 128 may be at the same level as the upper surface of the low-level interlayer dielectric layer 130. The low-level contact plug 128 may include a metal, a metal nitride, a metal silicide, or a combination thereof. The low-level contact plug 128 may include tungsten (W) or a tungsten compound.

[0122] A low-level metal interconnect 129 may be formed above the low-level contact plug 128. The low-level metal interconnect 129 can be coupled to the peripheral source / drain region PSD via the low-level contact plug 128 and the peripheral ohmic contact layer 126. The low-level metal interconnect 129 may include a metallic material. The low-level metal interconnect 129 may include one selected from gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), molybdenum (Mo), and combinations thereof.

[0123] The lower cover layer 131 may fill the space between the low-level metal interconnects 129. The lower cover layer 131 may cover the sidewall portions of the low-level metal interconnects 129. The height of the lower cover layer 131 may be at the same height as the low-level metal interconnects 129. The lower cover layer 131 may include a dielectric material. The lower cover layer 131 may include silicon nitride.

[0124] An etch stop layer 132 may be formed over the lower cover layer 131 and the low-level metal interconnect 129. The etch stop layer 132 may include a nitrogen-containing material.

[0125] Interlayer dielectric layer 133 may be formed above etch stop layer 132. The height of interlayer dielectric layer 133 may be greater than the height of the lower horizontal interlayer dielectric layer 130. Interlayer dielectric layer 133 may include a single-layer or multi-layer stacked structure. Interlayer dielectric layer 133 may include oxides, nitrides, or combinations thereof. Interlayer dielectric layer 133 may include TEOS.

[0126] The contact hole hard mask 134 can be formed above the interlayer dielectric layer 133.

[0127] A contact plug CP can be formed that penetrates the hard mask 134 of the contact hole, the interlayer dielectric layer 133, and the etch stop layer 132. The contact plug CP can directly contact the upper surface of the low-level metal interconnect 129. Therefore, the contact plug CP can be electrically connected to the low-level metal interconnect 129. The contact plug CP can include a metal, a metal nitride, a metal silicide, or a combination thereof. The contact plug CP can include tungsten (W) or a tungsten compound. Although not shown, the contact plug CP may also include an ohmic contact layer above the low-level metal interconnect 129, and a conductive liner surrounding the sidewalls and bottom surface of the contact plug CP above the ohmic contact layer.

[0128] A cover layer 135 may be formed over the contact hole hard mask 134. The cover layer 135 may cover the contact hole hard mask 134. The thickness of the cover layer 135 may be greater than the thickness of the contact hole hard mask 134.

[0129] The capping layer 135 may include an oxygen-containing material. The capping layer 135 may include an oxide. The capping layer 135 may include silicon oxide. The capping layer 135 may consist only of oxides. The capping layer 135 may be formed of oxides. The capping layer 135 may not contain nitrides. The capping layer 135 may be nitride-free.

[0130] Metal interconnect ML can be formed on the contact plug CP. Metal interconnect ML can extend linearly. The sidewalls of metal interconnect ML can directly contact cover layer 135. The upper surface of metal interconnect ML can be at the same level as the upper surface of cover layer 135. The height of metal interconnect ML can be greater than the height of the lower level metal interconnect 129.

[0131] The metal interconnect ML may include one or more materials selected from Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr. The metal interconnect ML may include one, or two or more, stacked structures. According to embodiments of the present invention, the metal interconnect ML may include copper (Cu). The metal interconnect ML may include the same structure as the second interconnect E2. The metal interconnect ML may include the same material as the second interconnect E2.

[0132] The contact plug CP and the metal interconnect ML can be referred to as a "metal interconnect structure". Although this embodiment shows one "metal interconnect structure", according to another embodiment of the invention, two or more "metal interconnect structures" can be stacked. In other words, one or more "metal interconnect structures" can be formed.

[0133] The second outer region P2 will then be described.

[0134] The through-electrode TSV can be formed spaced apart from the metal interconnect ML and extend into the substrate 101. The through-electrode TSV can penetrate the low-level interlayer dielectric layer 130, the lower capping layer 131, the etch stop layer 132, the interlayer dielectric layer 133, the contact hole hard mask 134, and the capping layer 135. The depth to which the through-electrode TSV extends into the substrate 101 can be greater than the depth of the isolation layer 103 of the first peripheral region P1. According to another embodiment of the invention, the through-electrode TSV can penetrate the substrate 101. The upper surface of the through-electrode TSV can be at the same level as the upper surface of the capping layer 135. Therefore, the through-electrode TSV, the metal interconnect ML, and the upper surface of the capping layer 135 can be at the same level.

[0135] The through-electrode TSV may comprise a material such as a metal interconnect ML. The through-electrode TSV may comprise one or more materials selected from Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr. The through-electrode TSV may comprise one, or two or more, stacked structures. According to embodiments of the present invention, the through-electrode TSV may comprise copper (Cu).

[0136] A dielectric liner 140 may be formed between the through-electrode TSV and the substrate 101. The dielectric liner 140 may extend between the through-electrode TSV and the capping layer 135. According to another embodiment of the invention, the dielectric liner 140 may only cover the sidewalls of the through-electrode TSV and may not cover the bottom surface of the through-electrode TSV. The dielectric liner 140 may include a dielectric material. The dielectric liner 140 may include oxides, nitrides, or combinations thereof. The dielectric liner 140 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. According to another embodiment of the invention, the metal interconnect ML or the second interconnect E2 may also include the dielectric liner 140.

[0137] Although not shown, a barrier layer (not shown) may be selectively formed between the dielectric liner 140 and the through-electrode TSV. The barrier layer (not shown) may surround the sidewalls and bottom surface of the through-electrode TSV. The barrier layer (not shown) may be a single layer or a layer of two or more layers. The barrier layer (not shown) may include a metallic material. The barrier layer (not shown) may include a metallic material or a metallic compound. The barrier layer (not shown) may include materials such as Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, or WN. According to another embodiment of the invention, the metal interconnect ML or the second interconnect E2 may also include a barrier layer.

[0138] In the semiconductor device 100 according to an embodiment of the present invention, since the capping layer 135 is located between the metal interconnects ML, RC delay can be improved and process defects such as ion migration can be reduced. Therefore, the characteristics of the semiconductor device can be improved.

[0139] According to embodiments of the present invention, process defects can be reduced by forming an oxide capping layer, thereby improving the characteristics of semiconductor devices.

[0140] According to embodiments of the present invention, ion migration defects in metal interconnects can be improved by forming an oxide capping layer.

[0141] According to embodiments of the present invention, process stability can be ensured by simultaneously forming metal interconnects and through electrodes, and yield can be improved by simplifying the process.

[0142] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: An interlayer dielectric layer above a substrate, the substrate comprising a cell region, a first peripheral region, and a second peripheral region; A cover layer above the interlayer dielectric layer; A capacitor located in the unit region and covered by the interlayer dielectric layer; A contact plug, wherein the contact plug is located in the first peripheral region and penetrates the interlayer dielectric layer; A metal interconnect formed above the contact plug, extending through the cover layer; as well as A through-electrode that penetrates the capping layer and the interlayer dielectric layer and extends into the substrate in the second peripheral region.

2. The semiconductor device of claim 1, wherein, The coating layer is formed of oxides.

3. The semiconductor device of claim 1, wherein, The metal interconnects and the through-electrode are made of the same material.

4. The semiconductor device of claim 1, wherein, The metal interconnect and the through electrode comprise copper (Cu).

5. The semiconductor device of claim 1, wherein, The sidewalls of the metal interconnects are in direct contact with the cover layer.

6. The semiconductor device of claim 1, wherein, The upper surface of the cover layer is at the same level as the upper surface of the metal interconnect and the upper surface of the through electrode.

7. The semiconductor device of claim 1, wherein, The first peripheral area also includes: A low-level contact plug above the substrate; and The low-level metal interconnect on the low-level contact plug, The upper surface of the low-level metal interconnect is in direct contact with the contact plug.

8. The semiconductor device of claim 1, wherein, The unit region also includes: Bit lines on the substrate; and Storage node contact plugs are located on the two sidewalls of the bit line and between the substrate and the capacitor.

9. A method for manufacturing a semiconductor device, comprising: A contact plug that penetrates the interlayer dielectric layer is formed above the substrate; A cover layer is formed over the interlayer dielectric layer and the contact plug; Grooves are formed by etching the cover layer to expose the upper surface of the contact plug; A sacrificial layer is formed above the cover layer to fill the trench; Forming through-holes that penetrate the interlayer dielectric layer, the capping layer, and the sacrificial layer and extend into the substrate; Remove the sacrificial layer to expose the trench; Metal interconnects are formed in the trench; as well as A through electrode is formed in the through hole.

10. The method of claim 9, wherein, The coating layer is formed of oxides.

11. The method of claim 9, wherein, The sacrificial layer comprises one selected from spin-coated carbon SOC and hard mask carbon.

12. The method of claim 9, wherein, The contact plug comprises tungsten W.

13. The method of claim 9, wherein, The metal interconnect and the through electrode comprise copper (Cu).

14. The method of claim 9, wherein, Simultaneously, the metal interconnect and the through electrode are formed.

15. The method of claim 9, further comprising: Before forming the contact plug, one or more lower metal interconnect structures are formed over the substrate.

16. The method of claim 15, wherein, The lower metal interconnect structure includes: The low-level contact plug above the substrate, and the low-level metal interconnect above the low-level contact plug.

17. The method of claim 9, further comprising: A gate structure is formed on the substrate before the contact plug that penetrates the interlayer dielectric layer is formed on the substrate.

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