Semiconductor structure

Abstract

The embodiment of the present application provides a semiconductor structure, which comprises a substrate and a dielectric layer on the substrate; a conductive plug, a first part of the conductive plug is in the substrate, and a second part of the conductive plug is in the dielectric layer; and a capacitor array, the capacitor array at least surrounds the second part of the conductive plug. The embodiment of the present application is beneficial to reducing the influence of the deformation stress generated by the conductive plug on functional elements.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure. Background Technology

[0002] In existing technologies, to achieve chip integration and assembly along the Z-axis, through-silicon via (TSV) technology is commonly used to interconnect chips. Specifically, TSV technology involves forming vias connecting the top and bottom sides of a wafer and filling these vias with conductive material to form an interconnect structure. The conductive material can include different types of metals.

[0003] However, in practical applications, the configuration of the interconnect structure can affect components located on the surface of the silicon wafer as well as components located within the dielectric layer on the silicon wafer. Summary of the Invention

[0004] This invention provides a semiconductor structure that helps reduce the impact of deformation stress generated by conductive plugs on functional components.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate and a dielectric layer located on the substrate; a conductive plug, wherein a first portion of the conductive plug is located within the substrate and a second portion of the conductive plug is located within the dielectric layer; and a capacitor array, wherein the capacitor array at least surrounds the second portion of the conductive plug.

[0006] Additionally, the substrate includes a functional area and an exclusion area, the functional area being located on the side of the exclusion area away from the conductive plug, and the exclusion area and the functional area having the capacitor array, the capacitor array of the exclusion area surrounding a second portion of the conductive plug.

[0007] Furthermore, the substrate of the exclusion region has an active region, and the capacitor array of the exclusion region is electrically connected to the active region. This facilitates the operation of the capacitor array of the exclusion region through the active region, thereby enabling the capacitor array of the exclusion region to serve as a backup capacitor for use during fuse repair.

[0008] Furthermore, the capacitor array in the exclusion region is arranged in the same way as the capacitor array in the functional region. The capacitor arrays in the exclusion region and the functional region can be formed using the same fabrication process, which helps reduce the difficulty of semiconductor structure fabrication.

[0009] Furthermore, in the direction from the exclusion area to the functional area, there is a preset distance between the capacitor array in the exclusion area and the capacitor array in the functional area. This preset distance helps prevent the capacitor array in the exclusion area, affected by conductive plugs, from influencing the capacitor array in the functional area, thus ensuring high data storage accuracy and good structural stability of the capacitor array in the functional area.

[0010] In addition, the capacitor array of the functional area surrounds the second part of the conductive plug, and the surrounding shape of the capacitor array of the exclusion area is different from the surrounding shape of the capacitor array of the functional area.

[0011] In addition, the semiconductor structure also includes an isolation ring structure that surrounds at least the second portion of the conductive plug and is located between the conductive plug and the capacitor array. This allows functional elements arranged on the side of the capacitor array furthest from the conductive plug to be arranged at a higher density.

[0012] In addition, the capacitor array is composed of multiple discontinuous capacitor sub-arrays; it also includes an isolation ring structure, which is composed of multiple discontinuous isolation sub-rings, the isolation sub-rings being located between adjacent capacitor sub-arrays, the isolation ring structure and the capacitor array forming a pattern surrounding the conductive plug, and the isolation ring structure being electrically isolated from the capacitor array.

[0013] In addition, the capacitor array is grounded. This shields the electric field of the conductive plugs, thereby preventing the electric field of the conductive plugs from affecting the operation of the functional components.

[0014] Furthermore, in the direction where the conductive plug faces the capacitor array, the distance between the conductive plug and the capacitor array is 0.05μm to 50μm. If the distance is too close, the capacitor array is easily damaged by the deformation of the conductive plug, which will prevent the capacitor array from achieving the effect of deformation isolation and prevent the capacitor array from being used as a backup capacitor; if the distance is too far, it will compress the reserved space of the functional area.

[0015] Furthermore, in a direction perpendicular to the substrate surface, the top surface of the second portion of the conductive plug is lower than or flush with the top surface of the capacitor array. This ensures that the deformation stress generated by the conductive plug must pass through the interfaces in the capacitor array or bypass the capacitor array, preventing it from directly affecting the active region within the substrate or the functional elements within the dielectric layer. This reduces the deformation stress transmitted to the functional elements or active region, ensuring good performance of the functional elements or active region.

[0016] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:

[0017] In the above technical solution, a capacitor array is used as a deformation isolation structure. The capacitor array can have more interfaces, including the contact interface between the upper electrode and the lower electrode. When deformation stress is transmitted in the capacitor array, the deformation stress needs to continuously pass through or bypass the interface, thus generating a large transmission attenuation. This helps to ensure that the deformation stress has less impact on the functional elements located on the side of the capacitor array away from the conductive plug, thereby ensuring that the semiconductor structure has good performance. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure;

[0020] Figure 2 for Figure 1 Top view of the semiconductor structure shown;

[0021] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0022] Figure 4 for Figure 3 Top view of the semiconductor structure shown;

[0023] Figure 5 A cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present invention;

[0024] Figure 6 for Figure 5 Top view of the semiconductor structure shown;

[0025] Figure 7 A top view of yet another semiconductor structure provided in an embodiment of the present invention;

[0026] Figure 8 This is a top view of another semiconductor structure provided in an embodiment of the present invention.

[0027] Wherein, 10, 20: substrate; 11, 21: dielectric layer; 12, 22, 42, 52: conductive plugs; 13, 23, 43, 53: isolation ring structure; 201, KOZ: exclusion region; 202: functional region; 203: active region; 204: isolation structure; 24, 44, 54: capacitor array; 24a: capacitor unit; 24b: lower electrode; 24c: upper electrode; 24d: capacitor contact window; 241: first capacitor array; 242: second capacitor array. Detailed Implementation

[0028] refer to Figure 1 and Figure 2 , Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure. Figure 2 for Figure 1 The semiconductor structure shown is a top view. The semiconductor structure includes: a substrate 10 and a dielectric layer 11 located on the substrate 10; and a conductive plug 12 located within the substrate 10 and the dielectric layer 11.

[0029] The conductive plug 12 typically contains a metallic material, which is prone to expansion and contraction under thermal stress. When the coefficient of thermal expansion of the conductive plug 12 differs from that of the dielectric layer 11 and the substrate 10, stress concentration occurs, leading to deformation of the substrate 10 and the dielectric layer 11. This deformation can affect the functional characteristics of the functional components in the functional region and may even cause structural damage to the semiconductor structure.

[0030] The functional area is the working region of the functional element, including the surface of the substrate 10 and the interior of the dielectric layer 11. The functional element on the surface of the substrate 10 usually refers to the active region.

[0031] It should be noted that the stress that causes the substrate 10 and dielectric layer 11 to deform may originate not only from the direct stress of the conductive plug 12, but also from the secondary stress generated by the deformation of other adjacent membrane layers. For example, the compressive stress of the conductive plug 12 causes the substrate 10 to deform, and the deformed substrate 10, due to the change in structure, applies stress to the dielectric layer 11, thereby causing the dielectric layer 11 to deform as well.

[0032] Currently, simply setting up a grounded isolation ring structure 13 to shield part of the electric field of the conductive plug 12 and reduce its influence does not solve or counteract the deformation of the substrate 10 and dielectric layer 11. To avoid the deformation of the substrate 10 and dielectric layer 11 affecting the functional components in the functional area, the functional components are usually placed outside the KeepOut Zone (KOZ), i.e., away from the conductive plug 12. However, this solution greatly reduces the reserved space for the functional components, which is not conducive to the integration of chips or functional components.

[0033] To address the above problems, this invention provides a semiconductor structure in which a capacitor array is arranged around a conductive plug to reduce the magnitude of deformation stress passing through the capacitor array. This ensures that the deformation stress has a smaller impact on the functional area located on the side of the capacitor array away from the conductive plug, thereby ensuring that the functional elements in the functional area can work effectively and that the semiconductor structure has good performance.

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0035] In this embodiment, reference Figure 3 and Figure 4 The semiconductor structure includes: a substrate 20 and a dielectric layer 21 located on the substrate 20; a conductive plug 22, a first portion of which is located within the substrate 20 and a second portion of which is located within the dielectric layer 21; and a capacitor array 24, which at least surrounds the second portion of the conductive plug 22.

[0036] The capacitor array 24 is composed of multiple capacitor units 24a arranged in a direction parallel to the surface of the substrate 20 and away from the conductive plug 22. The capacitor array 24 has multiple interfaces, which will hinder the transmission of deformation stress, i.e. attenuate the deformation stress, ensure that the deformation stress transmitted to the functional area 202 is small, and ensure that the functional elements of the functional area 202 have good performance.

[0037] In this embodiment, the capacitor unit 24a includes a double-sided capacitor unit, and the capacitor array 24 is formed by continuously arranging the double-sided capacitor units. The interface in the capacitor array 24 mainly refers to the contact interface between the lower electrode 24b and the upper electrode 24c. In other embodiments, the capacitor unit includes a single-sided capacitor unit, and the capacitor array can be formed by arranging the capacitor units at intervals. The interface in the capacitor array also includes the sidewall surface of the capacitor unit.

[0038] In this embodiment, the substrate 20 includes an exclusion region 201 and a functional region 202. The functional region 202 is located on the side of the exclusion region 201 away from the conductive plug 22. Both the exclusion region 201 and the functional region 202 contain a capacitor array 24, with the capacitor array 24 surrounding the second part of the conductive plug 22. By providing the capacitor array 24 at the edge of the exclusion region 201 as a transition, the difference between the component arrangement density of the exclusion region 201 and the component arrangement density of the functional region 202 is avoided, ensuring that functional components with a higher component arrangement density can be arranged in the functional region 202, and ensuring that the functional components in the functional region 202 can operate effectively.

[0039] It should be noted that, Figure 1The structure shown is only an example with a capacitor array 24 arranged in the functional area 202. In fact, any functional element can be arranged in the functional area 202. In addition, for the sake of simplicity, the capacitor array 24 in the exclusion area 201 will be referred to as the first capacitor array 241, and the capacitor array 24 in the functional area 202 will be referred to as the second capacitor array 242.

[0040] In this embodiment, the substrate 20 of the exclusion region 201 has an active region 203, and the first capacitor array 241 is electrically connected to the active region 203 of the exclusion region 201. This helps to ensure that the first capacitor array 241 can be actuated through the active region 203, thereby enabling the first capacitor array 241 to be used as a spare capacitor during fuse repair.

[0041] Specifically, the exclusion region 201 also has a capacitor contact window 24d connecting the active region 203 and the first capacitor array 241, as well as necessary bit lines (not shown) and word lines (not shown). That is, the electrical structure of the exclusion region 201 can be exactly the same as the electrical structure of the functional region 202. The only difference between the two is the positional difference and the fact that the electrical structure of the exclusion region 201 is not put into actual use before repair.

[0042] In addition, the substrate 20 of the exclusion region 201 also has an isolation structure 204 that isolates adjacent active regions 203. Since the first capacitor array 241 is composed of multiple capacitor units 24a, the first capacitor array 241 corresponds to multiple active regions 203 and multiple isolation structures 204. The presence of multiple isolation structures 204 can make the transmission of deformation stress in the substrate 20 attenuate more, thereby avoiding deformation stress from passing through the substrate 20 and causing a greater impact on the functional elements in the dielectric layer 21.

[0043] In this embodiment, the first capacitor array 241 and the second capacitor array 242 are arranged in the same way. Thus, the first capacitor array 241 and the second capacitor array 242 can be formed under the same fabrication process, which helps to reduce the difficulty of semiconductor structure fabrication.

[0044] In this embodiment, when the capacitor array 24 surrounds the conductive plug 22, the capacitor array 24 located at the edge of the structure under the same manufacturing process is selected as the capacitor array 24 surrounding the conductive plug 22. Since the capacitor array 24 at the edge of the structure is easily affected by the edge effect during the formation process, for example, the top opening of the trench at the edge of the structure is smaller in multiple trenches formed by etching with the same mask, so the data storage performance of the capacitor array 24 at the edge of the structure may be poor.

[0045] In cases where the data storage performance of the capacitor array 24 at the edge of the structure may be poor, using it as a transitional high-density functional element located in the exclusion region 201 is beneficial to realizing the value of the capacitor array 24 at the edge of the structure and avoids the capacitor array 24 at the edge of the structure occupying the space of the functional region 202. This allows for the placement of more high-performance capacitor arrays 24 within the functional region 202, thereby improving the performance of the semiconductor structure.

[0046] In other embodiments, when a capacitor array surrounds a conductive plug, a space reserved for the conductive plug can be embedded in the entire capacitor array area. In this case, the capacitor array in a part of the area close to and surrounding the reserved space is more susceptible to the influence of the conductive plug. This part of the area can be defined as an exclusion area, and the capacitor array in this part of the area can be defined as a spare capacitor.

[0047] In this embodiment, a first preset distance d1 is provided between the first capacitor array 241 and the second capacitor array 242 in the direction from the exclusion area 201 toward the functional area 202. The existence of the first preset distance d1 helps to prevent the first capacitor array 241, which is affected by the conductive plug 22, from affecting the second capacitor array 242, thus ensuring that the second capacitor array 242 has better performance.

[0048] The influence of the first capacitor array 241 on the second capacitor array 242 includes potential influence and structural influence.

[0049] Regarding the effect of potential: In this embodiment, in order to avoid the electric field of the conductive plug 22 affecting the performance of the functional elements of the functional area 202, the first capacitor array 241 is grounded itself, or grounded through the active area 203, the capacitor contact window 24d, the word line or the bit line to form an electrostatic shield; accordingly, the grounded first capacitor array 241 is at a low potential, while at least some capacitor cells 24a of the second capacitor array 242 that stores data have stored charge, that is, at least some capacitor cells 24a are at a high potential. In order to avoid the transfer and leakage of charge due to the potential difference, a first preset spacing d1 is used for isolation, which can effectively block the charge transfer path, thereby ensuring the accuracy and effectiveness of data storage of the second capacitor array 242.

[0050] The grounded first capacitor array 242 can be disconnected from the ground wire when it is put into use later, so as to store data.

[0051] Regarding the structural impact: Since the upper electrode 24c of the current capacitor array 24 is usually an integrally formed continuous film layer without internal interfaces, deformation stress can be transmitted through the upper electrode 24c with minimal transmission attenuation. Thus, the continuous arrangement of the first capacitor array 241 and the second capacitor array 242 may make the second capacitor array 242 more susceptible to deformation stress. Furthermore, the electrodes of the capacitor array 24 are typically high aspect ratio structures, making them more sensitive to deformation stress and prone to collapse under stress. Therefore, setting a first preset spacing d1 to separate the upper electrodes 24c of different capacitor arrays 24 helps to ensure that the second capacitor array 242 experiences less deformation stress and maintains higher structural stability.

[0052] In this embodiment, the first preset spacing d1 is 0.2μm to 20μm, for example, 1μm, 5μm or 10μm. If the first preset spacing d1 is too small, the first capacitor array 241 will affect the data storage accuracy and structural stability of the second capacitor array 242; if the first preset spacing d1 is too large, it will compress the reserved space of the functional area 202.

[0053] In other embodiments, reference is made to Figure 5 and Figure 6 The capacitor array 34 is a continuously formed whole, with the first capacitor array 341 and the second capacitor array 342 arranged consecutively. In this way, the first capacitor array 341 and the second capacitor array 342 can be continuously formed using the same mask, reducing the difficulty of semiconductor structure fabrication.

[0054] In this embodiment, the second capacitor array 242 surrounds the second part of the conductive plug 22, and the surrounding shape of the first capacitor array 241 is different from the surrounding shape of the second capacitor array 242.

[0055] In a specific example, both the first capacitor array 241 and the second capacitor array 242 completely surround the conductive plug 22, but their surrounding shapes are different. This allows the spacing between the first capacitor array 241 and the second capacitor array 242 to differ in different directions away from the conductive plug 22. Furthermore, it allows the portions of the second capacitor array 242 that are more sensitive to deformation stress to be located farther from the first capacitor array 241, thereby ensuring high structural stability for any part of the second capacitor array 242.

[0056] Specifically, the first capacitor array 241 can be circular, and the second capacitor array 242 can be elliptical, with the part corresponding to the endpoint of the major axis of the ellipse being the part of the second capacitor array 242 that is sensitive to deformation stress; or, the first capacitor array 241 can be square, and the second capacitor array 242 can be circular; or, the first capacitor array 241 can be circular, and the second capacitor array 242 can be a rhombus or other polygons.

[0057] In another specific example, the first capacitor array 241 does not completely surround the conductive plug 22, while the second capacitor array 242 completely surrounds the conductive plug 22. Thus, by strategically placing the first capacitor array 241 in a portion of the area, sensitive portions of the second capacitor array 242 can be protected, thereby ensuring high overall structural stability of the second capacitor array 242.

[0058] Specifically, the first capacitor array 241 can be arc-shaped, and the second capacitor array 242 can be circular; the first capacitor array 241 can be linear, and the second capacitor array 242 can be square, etc.

[0059] In this embodiment, the semiconductor structure further includes an isolation ring structure 23, which at least surrounds the second portion of the conductive plug 22. The isolation ring structure 23 is located between the conductive plug 22 and the first capacitor array 241, and the arrangement density of the first capacitor array 241 is greater than the arrangement density of the isolation ring structure 23. Thus, functional elements with a higher arrangement density can be arranged in the functional region 202.

[0060] Furthermore, the isolation ring structure 23 can be grounded, while the first capacitor array 241 can be ungrounded. The isolation ring structure 23 serves as electrostatic shielding, and the first capacitor array 241 serves to block deformation stress. Thus, when the first capacitor array 241 is subsequently put into use, it is not necessary to disconnect its grounding wire, which improves the practicality of the semiconductor structure.

[0061] The isolation ring structure 23 may include a contact portion extending in the same direction as the conductive plug 22, and a metal portion disposed on top of the contact portion.

[0062] In other embodiments, the semiconductor structure does not include an isolation ring structure; electrical isolation and deformation stress isolation are achieved solely by setting a grounded first capacitor array. This helps save space occupied by the isolation ring structure, further compressing the exclusion zone and providing more reserved space for functional elements in the functional area.

[0063] In other embodiments, reference is made to Figure 7 The capacitor array 44 is composed of multiple discontinuous capacitor sub-arrays, and the isolation ring structure 43 includes multiple discontinuous isolation sub-rings. The isolation sub-rings are located between two adjacent capacitor sub-arrays. The isolation ring structure 43 and the capacitor array 44 form a pattern surrounding the conductive plug 42. The pattern can be any shape such as square, circle, ellipse or polygon.

[0064] Among them, the isolation ring structure 43 is electrically isolated from the capacitor array 44. The isolation ring structure 43 is grounded and plays the role of electrostatic shielding. The capacitor array 44 is not grounded and plays the role of blocking deformation stress.

[0065] In yet another embodiment, reference is made to Figure 8 The capacitor array 54, which includes multiple capacitor subarrays, forms a first pattern surrounding the conductive plug 52, and the isolation ring structure 53, which includes multiple isolation subrings, forms a second pattern surrounding the conductive plug 52. The first pattern and the second pattern have the same shape but different positions. In the direction from the conductive plug 52 toward the capacitor array 54, the orthographic projection of the second pattern can complement the first pattern, thus forming a complete closed pattern.

[0066] In other embodiments, the shapes of the first pattern and the second pattern may be different, and the orthographic projection of the second pattern may partially overlap with the first pattern or there may be a gap between them.

[0067] In this embodiment, a second preset distance d2 is provided between the conductive plug 22 and the first capacitor array 241 in the direction facing the conductive plug 22 toward the first capacitor array 241. The second preset distance d2 is 0.5μm to 50μm, for example, 2μm, 10μm or 25μm. If the second preset distance d2 is too small, the first capacitor array 241 is easily damaged by the deformation stress of the conductive plug 22, which will cause the first capacitor array 241 to fail to play the role of deformation isolation and to fail to be used as a spare capacitor; if the second preset distance d2 is too large, it will compress the reserved space of the functional area 202.

[0068] In this embodiment, in the direction perpendicular to the surface of the substrate 20, the top surface of the second portion of the conductive plug 22 is lower than or flush with the top surface of the first capacitor array 241. This ensures that the deformation stress generated by the conductive plug 22 and applied to the dielectric layer 21 must pass through the interface in the first capacitor array 241 or bypass the first capacitor array 241, and cannot directly affect the active region 203 on the surface of the substrate 20 or the functional elements within the dielectric layer 21. This reduces the deformation stress transmitted to the functional elements or the active region 203, ensuring good performance of the functional elements or the active region 203.

[0069] In this embodiment, a capacitor array is used as a deformation isolation structure. The capacitor array can have more interfaces, including the contact interface between the upper electrode and the lower electrode. When deformation stress is transmitted in the capacitor array, the deformation stress needs to continuously pass through or bypass the interface, thereby generating a large transmission attenuation. This helps to ensure that the deformation stress has less impact on the components located on the side of the capacitor array away from the conductive plug, thereby ensuring that the semiconductor structure has good performance.

[0070] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate and dielectric layer located on the substrate; A conductive plug, wherein a first portion of the conductive plug is located within the substrate and a second portion of the conductive plug is located within the dielectric layer; A capacitor array, the capacitor array at least surrounding a second portion of the conductive plug; The substrate includes a functional area and an exclusion area, the functional area being located on the side of the exclusion area away from the conductive plug, and the exclusion area and the functional area having the capacitor array, the capacitor array of the exclusion area surrounding a second portion of the conductive plug.

2. The semiconductor structure according to claim 1, characterized in that, The substrate of the exclusion region has an active region, and the capacitor array of the exclusion region is electrically connected to the active region of the exclusion region.

3. The semiconductor structure according to claim 1, characterized in that, The capacitor array in the exclusion zone is arranged in the same way as the capacitor array in the functional zone.

4. The semiconductor structure according to claim 1, characterized in that, In the direction from the exclusion area to the functional area, there is a preset distance between the capacitor array in the exclusion area and the capacitor array in the functional area.

5. The semiconductor structure according to claim 1, characterized in that, The capacitor array in the functional area surrounds the second part of the conductive plug, and the surrounding shape of the capacitor array in the exclusion area is different from the surrounding shape of the capacitor array in the functional area.

6. A semiconductor structure, characterized in that, include: Substrate and dielectric layer located on the substrate; A conductive plug, wherein a first portion of the conductive plug is located within the substrate and a second portion of the conductive plug is located within the dielectric layer; A capacitor array, the capacitor array at least surrounding a second portion of the conductive plug; An isolation ring structure is provided, which at least surrounds a second portion of the conductive plug and is located between the conductive plug and the capacitor array.

7. A semiconductor structure, characterized in that, include: Substrate and dielectric layer located on the substrate; A conductive plug, wherein a first portion of the conductive plug is located within the substrate and a second portion of the conductive plug is located within the dielectric layer; A capacitor array, the capacitor array at least surrounding a second portion of the conductive plug; The capacitor array is composed of multiple discontinuous capacitor subarrays; it also includes an isolation ring structure, which is composed of multiple discontinuous isolation subrings, the isolation subrings being located between adjacent capacitor subarrays, the isolation ring structure and the capacitor array forming a pattern surrounding the conductive plug, and the isolation ring structure being electrically isolated from the capacitor array.

8. The semiconductor structure according to any one of claims 1-7, characterized in that, The capacitor array is grounded.

9. The semiconductor structure according to any one of claims 1-7, characterized in that, In the direction in which the conductive plug faces the capacitor array, the distance between the conductive plug and the capacitor array is 0.05μm to 50μm.

10. The semiconductor structure according to any one of claims 1-7, characterized in that, In a direction perpendicular to the substrate surface, the top surface of the second portion of the conductive plug is lower than or flush with the top surface of the capacitor array.

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