Gate structure and its formation method

Abstract

This disclosure relates to gate structures and methods of forming the same. A device includes: a first gate region having a first gate length; a first spacer located on a sidewall of the first gate region; a semiconductor layer located above the first gate region; a second gate region located above the semiconductor layer, wherein a second gate length of the second gate region is equal to the first gate length; and a second spacer located on a sidewall of the second gate region, wherein the second spacer is narrower than the first spacer.

Description

Technical Field

[0001] This disclosure generally relates to gate structures and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first gate region having a first gate length; a first spacer located on a sidewall of the first gate region; a semiconductor layer located above the first gate region; a second gate region located above the semiconductor layer, wherein a second gate length of the second gate region is equal to the first gate length; and a second spacer located on a sidewall of the second gate region, wherein the second spacer is narrower than the first spacer.

[0005] According to another embodiment of this disclosure, a transistor is provided, comprising: a first nanostructure; a second nanostructure located on the first nanostructure, wherein the first nanostructure is wider than the second nanostructure; and a gate structure surrounding the first nanostructure and the second nanostructure, wherein the gate structure comprises: a first region located on the first nanostructure; and a second region located on the second nanostructure, wherein the second region has the same gate length as the first region.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: depositing a first semiconductor layer on a substrate; depositing a second semiconductor layer on the first semiconductor layer; depositing a third semiconductor layer on the second semiconductor layer, wherein the germanium concentration of the first semiconductor layer is greater than that of the third semiconductor layer; etching a first opening through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; etching the first semiconductor layer and the third semiconductor layer through the first opening, wherein after etching the first semiconductor layer and the third semiconductor layer, the first semiconductor layer has the same width as the third semiconductor layer; forming a source / drain region in the first opening; and replacing the first semiconductor layer and the third semiconductor layer with a gate structure, wherein the gate structure is disposed around the second semiconductor layer. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B ,and Figure 20C This is a cross-sectional view of an intermediate stage in the manufacture of a transistor, according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "below," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0012] The various embodiments described herein provide nanoFETs (e.g., nanowire FETs, nanosheet FETs, gate all-around (GAA), etc.). Each nanoFET may include a stacked gate region having a relatively uniform gate length surrounding a channel region. A gate region of uniform length can be obtained, for example, by replacing sacrificial nanosheets disposed between semiconductor nanosheets, which subsequently provide the channel region in the finished transistor. The sacrificial nanosheets may be deposited with different concentrations of germanium, such that each sacrificial nanosheet can be etched with a different amount to compensate for the non-uniform anisotropic etching process used to pattern the sacrificial nanosheets. As a result, the contours of the sacrificial nanosheets (and the resulting gate region) can be more precisely controlled to provide improved uniformity. Furthermore, defects such as silicon-germanium residues after the removal of the sacrificial nanosheets can be avoided by doping the sacrificial nanosheets with a group III element (e.g., boron, etc.).

[0013] Figure 1 An example of a nanoFET according to some embodiments is shown in a three-dimensional view. The nanoFET includes nanostructures 55 (e.g., nanosheets, nanowires, etc.) situated above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 serve as channel regions for the nanoFET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude above and from between adjacent isolation regions 68. Although the STI region 68 is described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or a combination of the semiconductor substrate and the isolation region. Furthermore, although the bottom portion of the fin 66 is shown as being a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0014] A gate dielectric layer 100 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 102 is located above the gate dielectric layer 100. An epitaxial source / drain region 92 is disposed on the fin 66 and located on the opposite side of the gate dielectric layer 100 and the gate electrode 102.

[0015] Figure 1Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 66 and in a direction, for example, between the epitaxial source / drain regions 92 of the nanoFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, the following figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are described in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Moreover, some embodiments consider aspects used in planar devices such as planar FETs or FinFETs.

[0017] Figures 2A to 20C This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2A to 5 6A Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A It shows Figure 1 The reference cross section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 10C , Figure 10D , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H , Figure 18B , Figure 19B and Figure 20B It shows Figure 1 The reference cross section B-B' is shown. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13C , Figure 18C , Figure 19C and Figure 20C It shows Figure 1 The reference cross section C-C' is shown.

[0018] exist Figure 2A and Figure 2B A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0019] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0020] In addition, Figure 2A and Figure 2BIn this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 is removed, and the second semiconductor layer 53 is patterned to form the channel region of the nanoFET in the p-type region 50P and the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanoFET in the n-type region 50N; and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nanoFET in the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N; and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P.

[0021] exist Figure 2A and Figure 2B In this illustration, the multilayer stack 64 is shown as three layers including each of the first semiconductor layer 51 and the second semiconductor layer 53, for illustrative purposes only. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53, such as... Figure 2B The diagram shows four layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. Each layer of the multilayer stack 64 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the deposition of the multilayer stack 64 can be performed in a single chamber without breaking the vacuum. Furthermore, the deposition of the multilayer stack 64 can be an isothermal or hybrid process. The process temperature for depositing each of the first semiconductor layer 51 and the second semiconductor layer 53 can be in the range of about 550 °C to about 700 °C, and the pressure for depositing the first semiconductor layer 51 and the second semiconductor layer 53 can be in the range of about 1 Torr to 50 Torr. In some embodiments, the relative thickness of each of the first semiconductor layer 51 and / or the second semiconductor layer 53 can be the same.

[0022] In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (e.g., silicon, germanium, etc.), and the second semiconductor layer 53 may be formed of a second semiconductor material (e.g., silicon, silicon carbon, etc.). In such embodiments, the precursor flowing during the deposition of the first semiconductor layer 51 may include GeH4, H2, HCl, combinations thereof, etc., and the precursor flowing during the deposition of the second semiconductor layer 53 may include SiH4, SiH2Cl2, HCl, H2, N2, combinations thereof, etc. The first semiconductor material and the second semiconductor material may be materials that have high etch selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the NSFET.

[0023] In some embodiments, the germanium concentration in each first semiconductor layer 51 is varied to change the etching sensitivity of each first semiconductor layer 51. The germanium concentration in the first semiconductor layer 51 can be increased in the direction toward the substrate 50. As a result, during subsequent etching processes (e.g., as... Figure 10A and Figure 10B As described above, the lower first semiconductor layer can be etched more easily, which compensates for the uneven etching characteristics of the etching process. For example, in Figure 2A and Figure 2B In this process, semiconductor layer 51A can have a higher germanium concentration than semiconductor layer 51B, and semiconductor layer 51B can have a higher germanium concentration than semiconductor layer 51C. Figure 2B In this process, semiconductor layer 51C may further have a higher germanium concentration than semiconductor layer 51D. In some embodiments, the germanium concentration of semiconductor layer 51A may be in the range of 25% to 45%; the germanium concentration of semiconductor layer 51B may be in the range of 20% to 40%; the germanium concentration of semiconductor layer 51C may be in the range of 15% to 35%; and the germanium concentration of semiconductor layer 51D may be in the range of 10% to 30%. It has been observed that when the germanium concentration of the first semiconductor layer 51 falls within the above ranges, a relatively uniform gate structure can be formed in subsequent processes. Other germanium concentrations are also possible.

[0024] In some embodiments, an in-situ doping process can be performed on each first semiconductor layer 51 to dope the first semiconductor layer 51 with a group III element. For example, each first semiconductor layer 51 can be doped with boron by allowing a boron-containing precursor (e.g., B₂H₆, etc.) to flow during the deposition of the first semiconductor layer 51. Other group III element dopants are also possible.

[0025] Doping group III elements into the first semiconductor layer 51 can help enhance sensitivity to etching and reduce the risk of etch failure during subsequent etching processes (e.g., as shown in the image). Figure 10A and Figure 10B Defects (e.g., undesirable residues in the first semiconductor layer 51) as described above. The first semiconductor layers 51A, 51B, 51C, and 51D may have varying concentrations of group III element dopants. For example, the concentration of group III element dopants in the first semiconductor layer 51 may increase in the direction toward the substrate 50. For example, in... Figure 2A and Figure 2B In this process, semiconductor layer 51A may have a higher concentration of group III element dopant than semiconductor layer 51B, and semiconductor layer 51B may have a higher concentration of group III element dopant than semiconductor layer 51C. Figure 2B In this process, semiconductor layer 51C may further have a higher group III element dopant concentration than semiconductor layer 51D. In some embodiments, the group III element dopant concentration of semiconductor layer 51A may be 5 × 10⁻⁶. 19 atoms / cm 3 Up to 5×10 20 atoms / cm 3 Within a certain range; the concentration of group III element dopant in semiconductor layer 51B can be 1×10⁻⁶. 19 atoms / cm 3 Up to 8×10 19 atoms / cm 3 Within a certain range; the concentration of group III element dopants in the 51C semiconductor layer can be 5 × 10⁻⁶. 18 atoms / cm 3 Up to 3×10 19 atoms / cm 3 Within a certain range; and the concentration of group III element dopants in semiconductor layer 51D can be 1×10⁻⁶. 18 atoms / cm 3 Up to 8×10 18 atoms / cm 3 Within the aforementioned range. It has been observed that when the concentration of the group III element dopant in the first semiconductor layer 51 falls within the aforementioned range, manufacturing defects can be advantageously reduced when etching the first semiconductor layer 51. Other embodiments may include other concentrations of group III element dopant.

[0026] Furthermore, each first semiconductor layer 51A may have a uniform concentration of group III element dopant or a varying concentration of group III element dopant. For example, Figure 2C , Figure 2D and Figure 2E The concentration of Group III element dopant in the first semiconductor layer 51 according to some alternative embodiments is shown. It can be... Figure 2C , Figure 2D and Figure 2E The dopant concentration shown is applied to any of the first semiconductor layers 51 described above (e.g., layers 51A, 51B, 51C, and / or 51D). Figure 2C In this configuration, the concentration of group III element dopant in the first semiconductor layer 51 is between P1 and P2, where P1 is the minimum dopant concentration and P2 is the maximum dopant concentration. In some embodiments, the minimum dopant concentration P1 is 0%. The thickness of the region 57 of the first semiconductor layer 51 containing the group III element dopant can, for example, be in the range of about 1 nm to about 5 nm. Figure 2C In one embodiment, the first semiconductor layer 51 has the highest concentration of group III element dopant at its top surface 51' and bottom surface 51', and the concentration of group III element dopant in the first semiconductor layer 51 is a gradient that decreases toward the center of the first semiconductor layer 51.

[0027] Figure 2D It shows the relationship with Figure 2C Similar configurations, the difference is Figure 2D The first semiconductor layer 51 has the highest group III element dopant concentration P3, which is less than Figure 2C The maximum dopant concentration P2 of the first semiconductor layer 51 is similar to that in [the previous sentence]. Figure 2C In one embodiment, the minimum group III element dopant concentration of the first semiconductor layer is P1, and the thickness of the region 57 containing the group III element dopant in the first semiconductor layer 51 can be in the range of, for example, about 1 nm to about 5 nm. Similar to... Figure 2C ,exist Figure 2D In the first semiconductor layer 51, the top surface 51' and bottom surface 51' of the first semiconductor layer 51 have the highest concentration of group III element dopant, and the concentration of group III element dopant in the first semiconductor layer 51 is a gradient that decreases toward the center of the first semiconductor layer 51.

[0028] exist Figure 2E In this configuration, the concentration of group III element dopant in the first semiconductor layer 51 is between P1 and P2, where P1 is the minimum dopant concentration and P2 is the maximum dopant concentration. In some embodiments, the minimum dopant concentration P1 is 0%. The thickness of the region 57 containing the group III element dopant in the first semiconductor layer 51 can, for example, range from about 1 nm to about 5 nm. Figure 2EIn one embodiment, the first semiconductor layer 51 has the highest concentration of Group III dopant at horizontal level 51'' within its interior. The Group III dopant concentration is a gradient that decreases in the direction away from horizontal level 51''. As will be explained later, the dopant concentration of the Group III dopant in the first semiconductor layer 51 can be used to determine the shape of the resulting gate region and the shape of the internal sidewall spacers in the resulting transistor. Furthermore, different dopant concentration distributions can be obtained in the first semiconductor layer 51 by varying the flow rate and / or concentration of the precursor containing the Group III dopant during deposition of the first semiconductor layer 51.

[0029] Now for reference Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50 by etching trenches in multilayer stack 64 and substrate 50, respectively. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55. Although Figure 3 The subsequent process shows that it is based on Figure 2A Further processing of the embodiments, but this processing can also be applied to Figure 2B Examples of implementations.

[0030] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins 66 and nanostructures 55. Typically, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns, for example, with spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0031] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to have a consistently consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 continuously increases in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0032] exist Figure 4 In this embodiment, a shallow trench isolation (STI) region 68 is formed near the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide such as silicon oxide, a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fin 66, and nanostructure 55. Subsequently, a filler material, such as that discussed above, can be formed on the liner.

[0033] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back, or combinations thereof, can be used. The planarization process exposes the nanostructure 55 so that, after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material are flush.

[0034] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of fins 66 in regions 50N and 50P protrude between adjacent STI regions 68. Furthermore, the top surface of the STI regions 68 can have a flat surface, a convex surface, a concave surface (e.g., recessed), or a combination thereof, as shown. The top surface of the STI regions 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of fins 66 and nanostructures 55). For example, oxide removal using, for example, diluted hydrofluoric acid (dHF) can be used.

[0035] The above text is about Figures 2A to 4 The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes relative to the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxial growth material can be doped in situ during growth, which can avoid prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0036] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are illustrated and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N or may be formed in a different order in the p-type region 50P and the n-type region 50N.

[0037] In addition, Figure 4In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the regions, with a concentration ranging from about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0038] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region, with a concentration ranging from approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0039] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation, although in-situ and implantation doping can be used together.

[0040] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and the dummy dielectric layer 70 can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized (e.g., by CMP). The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0041] Figures 6A to 20C Various additional steps in manufacturing the embodiment device are shown. Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B and Figure 20C Features in region 50N or region 50P are shown. Figure 6A and Figure 6B In this process, acceptable photolithography and etching techniques can be used to process mask layer 74 (see...). Figure 5 The pattern is then patterned to form a mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of fin 66. The pattern of mask 78 can be used to separate each dummy gate 76 from adjacent dummy gate 76 entities. The dummy gate 76 can also have a length direction substantially perpendicular to the length direction of fin 66.

[0042] exist Figure 7A and Figure 7B In, respectively in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation or deposition via CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited via CVD, ALD, etc.

[0043] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation can be performed for lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the above... Figure 4The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and exposed nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N. An impurity of an appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and exposed nanostructures 52 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have a density of 1 x 10⁻⁶. 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 The impurity concentration within the specified range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0044] exist Figure 8A and Figure 8B In this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for self-alignment of the subsequently formed source / drain regions and for protecting the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using suitable etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can be used as an etch stop layer when patterning the second spacer layer 82, and that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etching stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 8A As shown. Subsequently, the second spacer 83 serves as a mask when etching the exposed portion of the first spacer layer 80, thereby forming as shown... Figure 8A The first spacer 81 is shown.

[0045] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8BAs shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0046] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), and / or additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0047] exist Figure 9A and Figure 9B In some embodiments, a first recess 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54, and extend into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched such that the bottom surface of the first recess 86 is arranged lower than the top surface of the STI region 68, etc.

[0048] The fin 66, nanostructure 55, and substrate 50 can be etched using anisotropic etching processes such as RIE, NBE, etc., to form the first recess 86. During the etching process for forming the first recess 86, a first spacer 81, a second spacer 83, and a mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50. Each layer of the nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. After the first recess 86 reaches the desired depth, a timed etching process can be used to stop etching the first recess 86. Due to the non-uniform nature of the anisotropic etching process, the width of the first recess 86 can decrease in the direction toward the substrate 50. As a result, each nanostructure 55 can have tapered sidewalls and its width increases in the direction toward the substrate 50. For example, the width of nanostructure 52A is greater than the width of nanostructure 52B, and the width of nanostructure 52B is greater than the width of nanostructure 52C. Furthermore, the width of nanostructure 54A is greater than the width of nanostructure 54B, and the width of nanostructure 54B is greater than the width of nanostructure 54C.

[0049] exist Figure 10A and Figure 10B In this process, the portions of the sidewalls of each layer of the multilayer stack 64 exposed by the first recess 86 are etched to form sidewall recesses 88 in the n-type region 50N and the p-type region 50P. The multilayer stack 64 is formed of a first semiconductor material (e.g., a first nanostructure 52). Isotropic etching processes (e.g., wet etching, etc.) can be used to etch the sidewalls. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, cyclic dry etching (e.g., plasma etching using CF4, helium, etc.) and wet etching (e.g., wet cleaning using HF, HCl, sulfur peroxide mixture (SPM), etc.) processes can be used to etch the sidewalls of the first nanostructure 52. Because each nanostructure 52 has a different material composition, the same etching process can be used to etch the lower nanostructure 52 at a higher rate than the upper nanostructure 52. As a result, the recess 88 increases in size in the direction toward the substrate 50. In various embodiments, the inclusion of germanium and / or group III element dopants (if present) increases the etch selectivity of the first nanostructure 52 relative to the second nanostructure 54. As a result, after the recess, each nanostructure 52 can have a relatively uniform width W1, and the width difference of the nanostructures 52 from previous etching processes can be reduced (e.g., in...). Figure 9A and Figure 9B (Middle). The width W1 can be measured between opposite sidewalls of each nanostructure 52 in a cross-section extending through the fin 66 and perpendicular to the longitudinal dimension of the dummy gate 76.

[0050] For example, as described above, the germanium and / or Group III element dopant concentration of nanostructure 52A is greater than that of nanostructure 52B, and the germanium and / or Group III element dopant concentration of nanostructure 52B is greater than that of nanostructure 52C. The higher germanium and / or Group III element dopant concentration allows for a higher etching rate when etching the recess 88. Thus, when patterning the recess 88, more etching is performed on nanostructure 52A than on nanostructure 52B, and vice versa. Therefore, by adjusting the relative germanium and / or Group III element dopant concentration of each nanostructure 52, the width W1 of each nanostructure 52 becomes relatively uniform after etching the recess 88. Therefore, the non-uniform etching of the recess 86 can be compensated, and the resulting gate structure instead of the nanostructure 52 can have a relatively uniform gate length (e.g., the gate distance between the corresponding source / drain regions can correspond to the width W1 and be relatively uniform in the resulting structure).

[0051] Although the sidewalls of the first nanostructure 52 in the recess 88 are Figure 10B The center is shown as concave, but the sidewall can be straight or convex. Different sidewall profiles of the first nanostructure 52 can be formed by adjusting the group III element dopant concentration distribution of the nanostructure 52 (e.g., from above). Figure 2A The first semiconductor layer 51 described in the text is patterned. For example... Figure 10B The concave sidewalls of the first nanostructure 52 in the middle can be formed by having the above-mentioned... Figure 2C The dopant concentration of group III elements described in [the document] is used to achieve this. As another example, Figure 10C The straight sidewalls of the first nanostructure 52 in the middle can be formed by having the above-mentioned... Figure 2D The concentration of group III element dopant described in [the text] is used to achieve this. Furthermore, Figure 10D The convex sidewalls of the first nanostructure 52 in the middle can be formed by having the above-mentioned... Figure 2E This is achieved using the group III element dopant concentration described herein. The distance by which each recess 88 extends beyond the sidewall of the second nanostructure 54 can be adjusted by regulating the germanium concentration of each first nanostructure 52. Furthermore, including group III element dopant can reduce or eliminate residues left from the first nanostructure 52 in the recess 88. Therefore, defects can be reduced and device performance can be improved.

[0052] exist Figures 11A-11B In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first nanostructure 52 will be replaced by the corresponding gate structure.

[0053] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The internal spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer wall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the first internal spacer 90 may extend beyond or be recessed relative to the sidewall of the second nanostructure 54.

[0054] Additionally, the width of the internal spacers 90 can increase in the direction toward the substrate 50. For example, the width W2 of the topmost internal spacer 90 can be in the range of about 1 nm to about 3 nm. It has been observed that leakage may occur when the minimum width of the internal spacer 90 is less than the above range. Furthermore, the width W3 of the bottommost internal spacer 90 can be in the range of about 2 nm to about 5 nm. In various embodiments, the width W2 of the topmost internal spacer 90 is the minimum width of the internal spacer 90, while the width W3 of the bottommost internal spacer 90 is the maximum width of the internal spacer. The difference between width W2 and width W3 can be in the range of about 1 nm to about 4 nm, and the ratio of width W2 to width W3 can be in the range of about 0.1 to about 1. Widths W2 and W3 can be measured between opposite sidewalls of each respective internal spacer 90 in a cross-section extending through the fin 66 and perpendicular to the longitudinal dimension of the dummy gate 76.

[0055] exist Figures 12A-12C In this configuration, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance. Figure 12B As shown, an epitaxial source / drain region 92 is formed in the first recess 86 such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nanoFET.

[0056] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface that protrudes relative to the corresponding upper surface of the nanostructure 55 and can have facets.

[0057] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by masking the n-type region 50N (e.g., NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material that applies compressive strain to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface that protrudes relative to the corresponding surface of the multilayer stack 64 and can have small facets.

[0058] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region can be approximately 1 x 10⁻⁶. 19 atoms / cm 3 To approximately 1x10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0059] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as... Figure 12A As shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 12C As shown. In Figure 12A and Figure 12C In the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0060] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments in which the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on top of the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on top of the second semiconductor material layer 92B.

[0061] exist Figures 13A-13C In, respectively in Figure 6A , Figure 12A and Figure 12B The first interlayer dielectric (ILD) 96 is deposited on the structure shown. Figures 7A-12C The process remains unchanged. Figure 6A (See cross-section shown). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.) having an etch rate different from that of the first ILD 96 described above.

[0062] exist Figures 14A-14BIn this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0063] exist Figure 15A and Figure 15B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form the second recess 98. A portion of the dummy gate dielectric 71 located within the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than etching the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers a portion of the nanostructure 55 that serves as a channel region in the subsequently completed nanoFET. The portions of the nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer while the dummy gate 76 is etched. The dummy gate dielectric 71 can then be removed after the removal of the dummy gate 76.

[0064] exist Figure 16A and Figure 16B In this process, the first nanostructure 52 is removed to extend the second recess 98. The first nanostructure 52 can be removed by performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, substrate 50, and STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, the first nanostructure 52 can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. Removing the first nanostructure 52 exposes the internal spacers 90. Due to the above process, the distance between the pairs of internal spacers 90 is relatively uniform.

[0065] exist Figure 17A , Figure 17B and Figure 17C In this process, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, CESL 94, first spacer 81, and STI region 68.

[0066] like Figure 17C As shown, according to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers. For example, in some embodiments, the gate dielectric layer 100 may include an interface oxide layer 100A and a high-k layer 100B located above the interface oxide layer 100A. In some embodiments, the interface oxide layer 100A includes silicon oxide, silicon oxynitride, etc., and the high-k dielectric layer 100B may have a k value greater than 7.0 and includes metal oxides or silicates of citrate, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The method for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0067] Gate electrodes 102 are deposited on the gate dielectric layer 100 and fill the remaining portion of the second recess 98. Gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in Figure 17A and Figure 17B A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54.

[0068] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0069] After filling the second recess 98, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 100 and gate electrode 102, which lie above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and gate dielectric layer 100 thus forms the replacement gate structure of the resulting nanoFET. The gate electrode 102 and gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0070] Due to the aforementioned process and the width variation of the spacer 90, each region of the gate structure 100 / 102 surrounding the nanostructure 54 (e.g., gate regions 100 / 102A, 100 / 102B, and 100 / 102C) can have a relatively uniform gate length L. G (For example, the minimum distance between each gate structure 100 / 102 between the epitaxial source / drain regions 92). Gate length L G The width W1 of the nanostructure 52 described above can be approximated. Therefore, due to the constant gate structure length, the performance of the gate full-around can be improved. For example, in various embodiments, improved gate metal filling and better channel conduction control can be achieved.

[0071] Figures 17C to 17H Detailed views of various configurations of the gate structure 100 / 102 and the internal spacer 90 according to various embodiments are shown. Figure 17C , Figure 17D and Figure 17E An embodiment in which the internal spacer 90 is flush with the sidewall of the nanostructure 54B is shown, and Figure 17F , Figure 17G and Figure 17H An embodiment in which the internal spacer 90 is recessed relative to the sidewall of the nanostructure 54B is shown. Figure 17F , Figure 17G and Figure 17H In the middle, the epitaxial source / drain region 92 further extends through the sidewalls of the nanostructure 54B and extends between the nanostructures 54B. Figure 17C and Figure 17F An embodiment is shown in which the nanostructure 52 has concave sidewalls and the internal spacer 90 has convex sidewalls. Thus, the resulting gate structure 100 / 102 also has concave sidewalls. For example, this can be achieved by providing the first semiconductor layer 51 with the above-mentioned... Figure 2C To achieve the doping concentration described in [the document] Figure 17C and Figure 17F Examples of implementations. Figure 17D and Figure 17GAn embodiment is shown in which the nanostructure 52 is formed with straight sidewalls, and the internal spacer 90 is also formed with straight sidewalls. Thus, the resulting gate structure 100 / 102 also has straight sidewalls. For example, this can be achieved by providing the first semiconductor layer 51 with the above-mentioned... Figure 2D To achieve the doping concentration described in [the document] Figure 17D and Figure 17G Examples of implementations. Figure 17E and Figure 17H An embodiment is shown in which the nanostructure 52 has convex sidewalls and the internal spacer 90 has concave sidewalls. Thus, the resulting gate structure 100 / 102 also has convex sidewalls. For example, this can be achieved by providing the first semiconductor layer 51 with the above-mentioned... Figure 2E To achieve the doping concentration described in [the document] Figure 17E and Figure 17H Examples of implementations.

[0072] exist Figures 18A-18C In this process, the gate structure (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed, forming a recess between the gate structure directly above and the opposing portion of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The subsequently formed gate contacts (e.g., referred to below) Figures 20A-20C The gate contact 114 discussed penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0073] like Figures 18A-18C As further shown, a second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0074] exist Figures 19A-19CIn the process, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108, which exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using anisotropic etching processes (e.g., RIE, NBE, etc.). In some embodiments, a first etching process can be used to etch the third recess 108 through the second ILD 106 and the first ILD 96; a second etching process can be used to etch the third recess 108 through the gate mask 104; and then a third etching process can be used to etch the third recess 108 through the CESL 94. A mask, such as a photoresist, can be formed and patterned on the second ILD 106 to mask portions of the second ILD 106 relative to the first and second etching processes. In some embodiments, the etching process may over-etch, and therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., at the same level or equidistant from the substrate) or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., the bottom of the third recess 108 is closer to the substrate). Although Figure 19B The third recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section. However, in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of short-circuiting subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0075] Next, in Figures 20A-20CIn the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive features (e.g., gate structures 100 / 102 and / or silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to gate structures 100 / 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0076] although Figures 20A-20C Contacts 112 extending into each epitaxial source / drain region 92 are shown, but contacts 112 may be omitted from some epitaxial source / drain regions 92. For example, as explained in more detail below, conductive features (e.g., power rails) may subsequently be attached via the back side of one or more epitaxial source / drain regions 92. For these particular epitaxial source / drain regions 92, the source / drain contacts 112 may be omitted, or may be dummy contacts that are not electrically connected to any of the conductive lines (e.g., conductive line features) above.

[0077] The various embodiments described herein provide nanoFETs comprising stacked gate regions having relatively uniform gate lengths surrounding a channel region. Gate regions of uniform length can be obtained, for example, by replacing sacrificial nanosheets disposed between semiconductor nanosheets, which subsequently provide the channel region in the finished transistor. The sacrificial nanosheets can be deposited with varying concentrations of germanium, such that each sacrificial nanosheet can be etched with a different amount to compensate for non-uniform anisotropic etching processes used to pattern the sacrificial nanosheets. As a result, the contours of the sacrificial nanosheets (and the resulting gate regions) can be more precisely controlled to provide improved uniformity. Furthermore, defects such as silicon-germanium residues after the removal of the sacrificial nanosheets can be avoided by doping the sacrificial nanosheets with group III elements (e.g., boron, etc.).

[0078] In one embodiment, a device includes: a first gate region having a first gate length; a first spacer located on a sidewall of the first gate region; a semiconductor layer located above the first gate region; a second gate region located above the semiconductor layer, wherein a second gate length of the second gate region is equal to the first gate length; and a second spacer located on a sidewall of the second gate region, wherein the second spacer is narrower than the first spacer. Optionally, in some embodiments, the sidewall of the first gate region facing the first spacer is convex. Optionally, in some embodiments, the sidewall of the first gate region facing the first spacer is concave. Optionally, in some embodiments, the sidewall of the first gate region facing the first spacer is straight. Optionally, in some embodiments, the sidewall of the first spacer opposite to the first gate region is flush with the sidewall of the semiconductor layer. Optionally, in some embodiments, the sidewall of the first spacer opposite to the first gate region is recessed relative to the sidewall of the semiconductor layer. Optionally, in some embodiments, the device further includes a source / drain region adjacent to the first gate region and the second gate region, wherein the source / drain region extends between the semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer is disposed below the first gate region. Optionally, in some embodiments, the second semiconductor layer is wider than the first semiconductor layer.

[0079] In one embodiment, a transistor includes: a first nanostructure; a second nanostructure located on the first nanostructure, wherein the first nanostructure is wider than the second nanostructure; and a gate structure surrounding the first and second nanostructures, wherein the gate structure includes: a first region located on the first nanostructure; and a second region located on the second nanostructure, wherein the second region has the same gate length as the first region. Optionally, in some embodiments, a first spacer on the sidewall of the first region of the gate structure is wider than a second spacer on the sidewall of the second region of the gate structure. Optionally, in some embodiments, the sidewall of the first spacer is aligned with the sidewall of the first nanostructure. Optionally, in some embodiments, the transistor further includes: a source / drain region adjacent to the gate structure, wherein the source / drain region extends between the first and second nanostructures.

[0080] In one embodiment, a method includes: depositing a first semiconductor layer on a substrate; depositing a second semiconductor layer on the first semiconductor layer; depositing a third semiconductor layer on the second semiconductor layer, wherein the germanium concentration of the first semiconductor layer is greater than that of the third semiconductor layer; etching a first opening through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; etching the first semiconductor layer and the third semiconductor layer through the first opening, wherein after etching the first semiconductor layer and the third semiconductor layer, the first semiconductor layer has the same width as the third semiconductor layer; forming a source / drain region in the first opening; and replacing the first semiconductor layer and the third semiconductor layer with a gate structure, wherein the gate structure is disposed around the second semiconductor layer. Optionally, in some embodiments, the group III element dopant concentration of the first semiconductor layer is greater than that of the third semiconductor layer. Optionally, in some embodiments, the group III element dopant is boron. Optionally, in some embodiments, etching the first semiconductor layer and the third semiconductor layer defines a second opening adjacent to the first semiconductor layer and a third opening adjacent to the third semiconductor layer, wherein the second opening and the third opening are connected to the first opening; and wherein the method further includes: forming a first spacer in the second opening; and forming a second spacer in the third opening. Optionally, in some embodiments, the width of the second spacer is in the range of 1 nm to 3 nm. Optionally, in some embodiments, the second opening is wider than the third opening. Optionally, in some embodiments, the concentration of group III element dopant in the first semiconductor layer is highest at the top and bottom surfaces of the first semiconductor layer. Optionally, in some embodiments, the concentration of group III element dopant in the first semiconductor layer is highest inside the first semiconductor layer.

[0081] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0082] Example 1 is a semiconductor device comprising: a first gate region having a first gate length; a first spacer located on a sidewall of the first gate region; a semiconductor layer located above the first gate region; a second gate region located above the semiconductor layer, wherein a second gate length of the second gate region is equal to the first gate length; and a second spacer located on a sidewall of the second gate region, wherein the second spacer is narrower than the first spacer.

[0083] Example 2 is the device described in Example 1, wherein the sidewall of the first gate region facing the first spacer is convex.

[0084] Example 3 is the device described in Example 1, wherein the sidewall of the first gate region facing the first spacer is concave.

[0085] Example 4 is the device described in Example 1, wherein the sidewall of the first gate region facing the first spacer is straight.

[0086] Example 5 is the device described in Example 1, wherein the sidewall of the first spacer opposite to the first gate region is flush with the sidewall of the semiconductor layer.

[0087] Example 6 is the device described in Example 1, wherein the sidewall of the first spacer opposite to the first gate region is recessed relative to the sidewall of the semiconductor layer.

[0088] Example 7 is the device described in Example 6, further comprising: a source / drain region adjacent to the first gate region and the second gate region, wherein the source / drain region extends between the semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer is disposed below the first gate region.

[0089] Example 8 is the device described in Example 7, wherein the second semiconductor layer is wider than the semiconductor layer.

[0090] Example 9 is a transistor comprising: a first nanostructure; a second nanostructure situated on the first nanostructure, wherein the first nanostructure is wider than the second nanostructure; and a gate structure surrounding the first nanostructure and the second nanostructure, wherein the gate structure comprises: a first region situated on the first nanostructure; and a second region situated on the second nanostructure, wherein the second region has the same gate length as the first region.

[0091] Example 10 is the transistor described in Example 9, wherein a first spacer on the sidewall of the first region of the gate structure is wider than a second spacer on the sidewall of the second region of the gate structure.

[0092] Example 11 is the transistor described in Example 10, wherein the sidewall of the first spacer is aligned with the sidewall of the first nanostructure.

[0093] Example 12 is the transistor described in Example 9, further comprising: a source / drain region adjacent to the gate structure, wherein the source / drain region extends between the first nanostructure and the second nanostructure.

[0094] Example 13 is a method of forming a semiconductor device, comprising: depositing a first semiconductor layer on a substrate; depositing a second semiconductor layer on the first semiconductor layer; depositing a third semiconductor layer on the second semiconductor layer, wherein the germanium concentration of the first semiconductor layer is greater than that of the third semiconductor layer; etching a first opening through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; etching the first semiconductor layer and the third semiconductor layer through the first opening, wherein after etching the first semiconductor layer and the third semiconductor layer, the first semiconductor layer has the same width as the third semiconductor layer; forming a source / drain region in the first opening; and replacing the first semiconductor layer and the third semiconductor layer with a gate structure, wherein the gate structure is disposed around the second semiconductor layer.

[0095] Example 14 is the method described in Example 13, wherein the group III element dopant concentration of the first semiconductor layer is greater than the group III element dopant concentration of the third semiconductor layer.

[0096] Example 15 is the method described in Example 14, wherein the group III element dopant is boron.

[0097] Example 16 is the method of Example 13, wherein etching the first semiconductor layer and the third semiconductor layer defines a second opening adjacent to the first semiconductor layer and a third opening adjacent to the third semiconductor layer, wherein the second opening and the third opening are connected to the first opening; and wherein the method further includes: forming a first spacer in the second opening; and forming a second spacer in the third opening.

[0098] Example 17 is the method described in Example 16, wherein the width of the second spacer is in the range of 1 nm to 3 nm.

[0099] Example 18 is the method described in Example 16, wherein the second opening is wider than the third opening.

[0100] Example 19 is the method described in Example 13, wherein the concentration of group III element dopant in the first semiconductor layer is highest at the top and bottom surfaces of the first semiconductor layer.

[0101] Example 20 is the method described in Example 13, wherein the concentration of group III element dopant in the first semiconductor layer is highest inside the first semiconductor layer.

Claims

1. A semiconductor device, comprising: A first gate region having a first gate length; The first spacer is located on the sidewall of the first gate region; A semiconductor layer is located above the first gate region; A second gate region is located above the semiconductor layer, wherein the second gate length of the second gate region is equal to the first gate length; and A second spacer is located on the sidewall of the second gate region, wherein the second spacer is narrower than the first spacer. The first gate region and the second gate region are formed by replacing the third semiconductor layer and the fourth semiconductor layer with gate structures, respectively. The third semiconductor layer and the fourth semiconductor layer are doped with boron. The boron concentration in the third semiconductor layer is non-uniform, and the boron concentration varies along the thickness direction of the third semiconductor layer. Specifically, the boron concentration decreases continuously from the first position to the second position of the third semiconductor layer, remains unchanged from the second position to the third position, and increases continuously from the third position to the fourth position. Furthermore, the first, second, third, and fourth positions of the third semiconductor layer are arranged sequentially along a straight line with the same thickness direction as the third semiconductor layer.

2. The device according to claim 1, wherein, The sidewall of the first gate region facing the first spacer is convex.

3. The device according to claim 1, wherein, The sidewall of the first gate region facing the first spacer is concave.

4. The device according to claim 1, wherein, The sidewall of the first gate region facing the first spacer is straight.

5. The device according to claim 1, wherein, The sidewall of the first spacer opposite to the first gate region is flush with the sidewall of the semiconductor layer.

6. The device according to claim 1, wherein, The sidewall of the first spacer opposite to the first gate region is recessed relative to the sidewall of the semiconductor layer.

7. The device according to claim 6, further comprising: A source / drain region is adjacent to the first gate region and the second gate region, wherein the source / drain region extends between the semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer is disposed below the first gate region.

8. The device according to claim 7, wherein, The second semiconductor layer is wider than the semiconductor layer.

9. A transistor, comprising: First nanostructure; A second nanostructure is located on top of the first nanostructure, wherein the first nanostructure is wider than the second nanostructure; A gate structure surrounding the first nanostructure and the second nanostructure, wherein the gate structure comprises: A first region, located on the first nanostructure; and A second region, located on top of the second nanostructure, wherein the second region has the same gate length as the first region. The first region and the second region are formed by replacing the first semiconductor layer and the second semiconductor layer with the gate structure, respectively. The first semiconductor layer and the second semiconductor layer are doped with boron. The boron concentration of the first semiconductor layer is non-uniform. The boron concentration varies along the thickness direction of the first semiconductor layer. The boron concentration continuously decreases from the first position to the second position of the first semiconductor layer, remains unchanged from the second position to the third position of the first semiconductor layer, and continuously increases from the third position to the fourth position of the first semiconductor layer. The first, second, third, and fourth positions of the first semiconductor layer are arranged sequentially along a straight line with the same thickness direction as the first semiconductor layer.

10. The transistor according to claim 9, wherein, The first spacer on the sidewall of the first region of the gate structure is wider than the second spacer on the sidewall of the second region of the gate structure.

11. The transistor of claim 10, wherein, The sidewall of the first spacer is aligned with the sidewall of the first nanostructure.

12. The transistor of claim 9, further comprising: A source / drain region is adjacent to the gate structure, wherein the source / drain region extends between the first nanostructure and the second nanostructure.

13. A method of forming a semiconductor device, comprising: A first semiconductor layer is deposited on the substrate; A second semiconductor layer is deposited on top of the first semiconductor layer; A third semiconductor layer is deposited on top of the second semiconductor layer, wherein the germanium concentration of the first semiconductor layer is greater than that of the third semiconductor layer; The first semiconductor layer is doped with boron, wherein the first boron concentration of the first semiconductor layer is non-uniform, wherein the first boron concentration varies along the thickness direction of the first semiconductor layer, wherein the first boron concentration continuously decreases from the first position to the second position of the first semiconductor layer, remains unchanged from the second position to the third position of the first semiconductor layer, and continuously increases from the third position to the fourth position of the first semiconductor layer, and wherein the first, second, third and fourth positions of the first semiconductor layer are arranged sequentially along a straight line with the same thickness direction as the first semiconductor layer; The third semiconductor layer is doped with boron; The first opening is etched through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; The first semiconductor layer and the third semiconductor layer are etched through the first opening, wherein, after etching the first semiconductor layer and the third semiconductor layer, the first semiconductor layer has the same width as the third semiconductor layer; A source / drain region is formed in the first opening; and The first semiconductor layer and the third semiconductor layer are replaced by a gate structure, wherein the gate structure is disposed around the second semiconductor layer.

14. The method according to claim 13, wherein, Etching the first semiconductor layer and the third semiconductor layer defines a second opening adjacent to the first semiconductor layer and a third opening adjacent to the third semiconductor layer, wherein the second opening and the third opening are connected to the first opening; and wherein the method further includes: A first spacer is formed in the second opening; and A second spacer is formed in the third opening.

15. The method according to claim 14, wherein, The width of the second spacer is in the range of 1 nm to 3 nm.

16. The method of claim 14, wherein, The second opening is wider than the third opening.

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