Magnetic storage device

Abstract

Embodiments provide a magnetic storage device capable of simultaneously suppressing memory cell breakdown and data write errors. According to one embodiment, a magnetic storage device includes a magnetoresistive element having a first end and a second end. A first switch is located between the first end and a first wire. A second switch is located between the second end and a second wire. A third switch is located between the first end and a third wire. A fourth switch is located between the second end and a fourth wire. A driver is connected to the first wire and the second wire and is configured to provide a current to the first wire that is set based on a voltage at the first end and a voltage at the second end.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2020-152702, filed September 11, 2020, and U.S. Patent Application No. 17 / 189240, filed March 1, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to magnetic storage devices. Background Technology

[0004] Storage devices using magnetoresistive elements are well known. Summary of the Invention

[0005] The embodiment provides a magnetic storage device capable of simultaneously suppressing memory cell corruption and data write errors.

[0006] Generally, according to one embodiment, the magnetic storage device includes: a magnetoresistive element having a first terminal and a second terminal; a first switch located between the first terminal and a first wiring; a second switch located between the second terminal and the second wiring; a third switch located between the first terminal and the third wiring; and a fourth switch located between the second terminal and the fourth wiring. A driver is connected to the first wiring and the second wiring and is configured to provide a current to the first wiring of a magnitude based on the voltage at the first terminal and the voltage at the second terminal. Attached Figure Description

[0007] Figure 1 A block diagram of a magnetic storage device according to a first embodiment is shown.

[0008] Figure 2 This is a circuit diagram of a memory cell array according to the first embodiment.

[0009] Figure 3 A portion of a memory primitive array according to a first embodiment is shown.

[0010] Figure 4 A portion of a memory primitive array according to a first embodiment is shown.

[0011] Figure 5 The structure of a memory cell according to the first embodiment is shown.

[0012] Figure 6 Some aspects of the magnetic storage device according to the first embodiment are shown.

[0013] Figure 7The components and connections of a write driver according to a first embodiment are shown.

[0014] Figure 8 The signal states during data writing in the magnetic storage device according to the first embodiment are shown.

[0015] Figure 9 Some aspects related to data writing in a magnetic storage device according to the first embodiment are shown.

[0016] Figure 10 The state of the selected memory cell before and after writing to P according to the first embodiment is shown.

[0017] Figure 11 The state of the selected memory cell before and after AP writing is shown according to the first embodiment.

[0018] Figure 12 Some aspects of the data writing process in the magnetic storage device according to the first embodiment are shown.

[0019] Figure 13 Some aspects of the data writing process in the magnetic storage device according to the first embodiment are shown.

[0020] Figure 14 The components and connections of the first magnetic storage device are shown for comparative purposes.

[0021] Figure 15 For comparative purposes, some components and connections of the second magnetic storage device are shown. Detailed Implementation

[0022] Example embodiments will now be described with reference to the accompanying drawings. In the following description, the same reference numerals will be applied to elements having substantially the same function and configuration, and repeated descriptions of these elements may be omitted. There may be cases where additional numbers or letters are added to the end of the reference numerals to specifically distinguish different instances from multiple elements having substantially the same function and configuration.

[0023] The accompanying drawings are schematic, and various elements or aspects are shown in different dimensions and ratios in different drawings. Furthermore, unless expressly or clearly excluded, all descriptions of any exemplary embodiment may also be used as descriptions of other exemplary embodiments.

[0024] In the specification, the statement that the first element is "connected" to the second element means that the first element can be directly connected to the second element, but it also includes electrical connections between these elements formed by one or more conductive elements. Furthermore, such connections via conductive elements can be constant (e.g., using a wire) or via switching elements that can be in an on or off state at different times.

[0025] Generally, for ease of description, an xyz orthogonal coordinate system will be used to describe the example embodiments. Such a coordinate system is not a limitation. In the following description, descriptive terms such as "down" indicate a position closer to the z-axis compared to one or more other elements, and descriptive terms such as "up" similarly indicate a position farther from the z-axis compared to one or more other elements.

[0026] 1. First Embodiment

[0027] 1.1. Structure (Configuration)

[0028] 1.1.1. Overall Structure

[0029] Figure 1 A block diagram of a magnetic storage device according to a first embodiment is shown. Figure 1 As shown, the magnetic storage device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0030] The memory primitive array 11 includes multiple memory primitives MC, multiple word lines WL, and multiple bit lines BL. The memory primitives MC can store data in a non-volatile manner. Each memory primitive MC is connected to one word line WL and one bit line BL. The word line WL is associated with a row. The bit line BL is associated with a column. One or more memory primitives MC are specified by selecting one row and one or more columns.

[0031] The input / output circuit 12 receives, for example, various control signals CNT, various commands CMD, address signals ADD, and data (write data) DAT from the memory controller 2, and sends, for example, data (read data) DAT to the memory controller 2.

[0032] The row selection circuit 14 receives the address signal ADD from the input / output circuit 12 and causes a word line WL associated with the row specified by the received address signal ADD to be selected.

[0033] The column selection circuit 15 receives the address signal ADD from the input / output circuit 12 and causes a state in which multiple bit lines BL associated with the column specified by the received address signal ADD are selected.

[0034] Control circuit 13 receives control signal CNT and command CMD from input / output circuit 12. Control circuit 13 controls write circuit 16 and read circuit 17 based on the control indicated by control signal CNT and command CMD. Specifically, control circuit 13 provides voltage to write circuit 16 for writing data during data writing in memory cell array 11. Furthermore, control circuit 13 provides voltage for reading data from memory cell array 11 to read circuit 17.

[0035] The write circuit 16 receives write data DAT from the input / output circuit 12 and provides a voltage for writing data to the column selection circuit 15 based on the control performed by the control circuit 13 and the write data DAT.

[0036] The read circuit 17 includes a sense amplifier and, based on control executed by the control circuit 13, uses a voltage for reading data to determine the data stored in the memory cell MC. The determined data is provided to the input / output circuit 12 as read data DAT.

[0037] 1.1.2. Circuit Configuration of Memory Cell Array

[0038] Figure 2 This is a circuit diagram of the memory cell array 11 according to the first embodiment. (See diagram below.) Figure 2 As shown, the memory primitive array 11 includes M+1 (M is a natural number) word lines WLa (WLa <0> WLa <1> ......WLa <m>) and M+1 word lines WLb (WLb <0> WLb <1> ......WLb <m>The memory primitive array 11 also includes N+1 (N is a natural number) bit lines BL (BL... <0> BL <1> ......BL <n>).

[0039] Each memory primitive MC (MCa and MCb) has two nodes, connected to a word line WL at the first node N1 and to a bit line BL at the second node N2. More specifically, for all combinations of all cases where α is an integer equal to or greater than 0 and equal to or less than M, and for all combinations of all cases where β is an integer equal to or greater than 0 and equal to or less than N, memory primitive MCa comprises memory primitive MCa<α,β>, and memory primitive MCa<α,β> is connected between word line WLa<α> and bit line BL<β>. Similarly, for all combinations of all cases where α is an integer equal to or greater than 0 and equal to or less than M, and for all combinations of all cases where β is an integer equal to or greater than 0 and equal to or less than N, memory primitive MCb comprises memory primitive MCb<α,β>, and memory primitive MCb<α,β> is connected between word line WLb<α> and bit line BL<β>.

[0040] Each memory cell MC includes a magnetoresistive element VR (VRa or VRb) and a switching element SE (SEa or SEb). More specifically, for all combinations of cases where α is an integer equal to or greater than 0 and equal to or less than M, and for all combinations of cases where β is an integer equal to or greater than 0 and equal to or less than N, the memory cell MCa<α,β> includes the magnetoresistive element VRa<α,β> and the switching element SEa<α,β>. Furthermore, for all combinations of cases where α is equal to or greater than 0 and equal to or less than M, and for all combinations of cases where β is an integer equal to or greater than 0 and equal to or less than N, the memory cell MCb<α,β> includes the magnetoresistive element VRb<α,β> and the switching element SEb<α,β>.

[0041] In each memory cell MC, a magnetoresistive element VR and a switching element SE are connected in series. The magnetoresistive element VR is connected to a word line WL, and the switching element SE is connected to a bit line BL.

[0042] A magnetoresistive element VR can switch between a state where it has low resistance Ra and a state where it has high resistance Rap. A magnetoresistive element CR can store one bit of data using the difference between these two resistance states.

[0043] The switching element SE has two terminals. When a voltage less than a first threshold is applied between the two terminals in a first direction, the switching element SE is in a high-resistance state, such as a non-conductive state (also known as an off state). On the other hand, when a voltage equal to or greater than the first threshold is applied between the two terminals in the first direction, the switching element SE is in a low-resistance state, such as a conductive state (also known as an on state). The switching element can switch between the high-resistance state and the low-resistance state based on the magnitude of the voltage applied in the first direction, or similarly, based on the magnitude of the voltage applied in a second direction opposite to the first direction. Whether current is supplied to the magnetoresistive element VR connected to the switching element SE, i.e., whether the magnetoresistive element VR is selected, can be controlled by turning the switching element SE on or off.

[0044] 1.1.3. Structure of Memory Cell Array

[0045] Figure 3 and Figure 4 The structure of a portion of a cross-section of the memory primitive array 11 according to the first embodiment is shown. Figure 3 The cross section along the xz plane is shown. Figure 4 The cross section along the yz plane is shown.

[0046] like Figure 3 and Figure 4 As shown, multiple conductors 21 are stacked on top of a semiconductor substrate. The conductors 21 extend along the y-axis and are arranged relative to each other along the x-axis. Each conductor 21 serves as a word line WL.

[0047] Each conductor 21 has an upper surface that connects to the bottom surface of a plurality of memory cells MCb. Each memory cell MCb has, for example, a circular shape in the xy-plane. The memory cells MCb are aligned along the y-axis on each conductor 21, and in this arrangement, the memory cells MCb are arranged in a matrix pattern in the xy-plane. Each memory cell MCb includes a structure serving as a switching element SEb and a structure serving as a magnetoresistive element VRb. Each of the switching element SEb and the magnetoresistive element VRb includes one or more layers.

[0048] Multiple conductors 22 are disposed above the memory cell MCb. The conductors 22 extend along the x-axis and are arranged relative to each other along the y-axis. Each conductor 22 has a bottom surface that contacts the upper surface of the memory cell MCb aligned with each other along the x-axis. Each conductor 22 serves as a bit line BL.

[0049] Each conductor 22 has an upper surface connected to the bottom surface of a memory cell MCa. Each memory cell MCa has, for example, a circular shape in the xy-plane. Memory cells MCa are aligned with other memory cells MCa along the x-axis on each conductor 22, and through this arrangement, the memory cells MCa are arranged in a matrix pattern in the xy-plane. Each memory cell MCa has a structure serving as a switching element SEa and a structure serving as a magnetoresistive element VRa. The switching element SEa and the magnetoresistive element VRa each comprise one or more layers.

[0050] The additional conductor 21 can be located on the upper surface of the memory cells MCa aligned with each other along the y-axis.

[0051] You can also set it repeatedly along the z-axis. Figure 3 and Figure 4 The structure shown represents the layer from the bottom layer of conductor 21 to the memory cell MCa. Figure 2 The memory primitive array 11 shown.

[0052] The memory cell array 11 also includes interlayer insulators in the regions where conductors 21, conductors 22 and memory cells MC are not located.

[0053] Figure 5 A representative portion of the structure of the memory primitive MC according to the first embodiment is shown. (See diagram below.) Figure 5 As shown, the switching element SE includes a lower electrode 24, a variable resistive material 25 formed as a layer in this example, and an upper electrode 26. The lower electrode 24 is located on the upper surface of conductor 21 or 22. The variable resistive material 25 is located on the upper surface of the lower electrode 24. The upper electrode 26 is located on the upper surface of the variable resistive material 25.

[0054] For example, the lower electrode 24 and the upper electrode 26 contain titanium nitride (TiN) or are made of titanium nitride (TiN).

[0055] The variable resistive material 25 is, for example, a switching element between two terminals, where the first terminal is one of the upper or bottom surfaces of the variable resistive material 25, and the second terminal is the other of the upper and bottom surfaces of the variable resistive material 25. A magnetoresistive element VR is located on the upper surface of each upper electrode 26. The magnetoresistive element VR in this embodiment exhibits a tunneling magnetoresistive effect, and the case of a magnetic tunnel junction (MTJ) element will be described as an example. Specifically, the magnetoresistive element VR includes a ferromagnetic layer 31, an insulating layer 32, and a ferromagnetic layer 33. In one example, the insulating layer 32 is located on the upper surface of the ferromagnetic layer 31, and the ferromagnetic layer 33 is located on the upper surface of the insulating layer 32, such as... Figure 5 As shown.

[0056] The ferromagnetic layer 31 has an easy magnetization axis in the direction passing through the interface of the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33, for example, an easy magnetization axis at an angle equal to or greater than 45° and equal to or less than 90° with respect to the interface, and an easy magnetization axis in a direction perpendicular to the interface, for example. The magnetization orientation in the ferromagnetic layer 31 is intended to remain unchanged even when data is read and written in the magnetic storage device 1. The ferromagnetic layer 31 can be used as a so-called reference layer. The ferromagnetic layer 31 may include multiple stacked ferromagnetic layers and / or conductive layers.

[0057] The insulating layer 32 contains, for example, magnesium oxide (MgO) or is made of magnesium oxide (MgO) and serves as a so-called tunnel barrier.

[0058] For example, the ferromagnetic layer 33 comprises or is made of cobalt iron boron (CoFeB) or iron boride (FeB). The ferromagnetic layer 33 has an easy magnetization axis in the direction passing through the interface of the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33, for example, an easy magnetization axis at an angle equal to or greater than 45° and equal to or less than 90° to the interface, and an easy magnetization axis in, for example, a direction perpendicular to the interface. The magnetization orientation in the ferromagnetic layer 33 varies according to the data written, and the ferromagnetic layer 33 can be used as a so-called storage layer.

[0059] If the magnetization orientation in ferromagnetic layer 33 is parallel to the magnetization orientation in ferromagnetic layer 31, the magnetoresistive element VR has a low resistance value. If the magnetization orientation in ferromagnetic layer 33 is antiparallel to the magnetization orientation in ferromagnetic layer 31, the resistance value of the magnetoresistive element VR is higher than the resistance when the magnetization orientations in ferromagnetic layers 31 and 33 are antiparallel. A memory cell MC in a state where the magnetization orientation in ferromagnetic layer 33 is parallel to the magnetization orientation in ferromagnetic layer 31 is called being in the "P state". A memory cell MC in a state where the magnetization orientation in ferromagnetic layer 33 is antiparallel to the magnetization orientation in ferromagnetic layer 31 is called being in the "AP state".

[0060] If a write current Iwp of a specific magnitude flows from ferromagnetic layer 33 to ferromagnetic layer 31, the magnetization orientation in ferromagnetic layer 33 becomes parallel to the magnetization orientation in ferromagnetic layer 31. This operation of reversing the magnetization orientation can be called "P-write". On the other hand, if a write current Iwap of a specific magnitude flows from ferromagnetic layer 31 to ferromagnetic layer 33, the magnetization orientation in ferromagnetic layer 33 becomes antiparallel to the magnetization orientation in ferromagnetic layer 31. This operation of reversing the magnetization orientation can be called "AP-write". The write current Iwp can be called "P-write current", and the write current Iwap can be called "AP-write current". The AP-write current Iwap is greater than the P-write current Iwp. In some cases, both the AP-write current Iwap and the P-write current Iwp can be called the write current Iw. Therefore, the term write current Iw represents the P-write current when a P-write is performed on the selected memory cell MC, and represents the AP-write current Iwap when an AP-write is performed on the selected memory cell MC.

[0061] The memory element MC may include additional conductors, insulators, and / or ferromagnets.

[0062] Figure 6 Details of some parts of the magnetic storage device 1 according to the first embodiment are shown. More specifically, Figure 6 The components, connections, and overall layout of the memory primitive array 11, row selection circuit 14, column selection circuit 15, and write circuit 16 are shown. Figure 6 Only one memory primitive MC is shown as a representative of the other memory primitives.

[0063] like Figure 6 As shown, and as referenced Figure 2 The memory cell MC is connected to a word line WL at the first node N1 and to a bit line BL at the second node N2. When the memory cell MC is of type MCa, the word line WL connected to the memory cell MC is word line WLa. On the other hand, when the memory cell MC is of type MCb, the word line WL connected to the memory cell MC is word line WLb.

[0064] The row selection circuit 14 includes multiple local row switches TLY1, multiple local row switches TLY2, a global row switch TGY1, and a global row switch TGY2. Each word line WL is connected at its first end to the first end of a local row switch TLY1. The word line WL is connected to the first end of the local row switch TLY1 located on the same side, for example, connected to... Figure 4 The first end of the local row switch TLY1 is located on the smaller coordinate side (i.e., on the left side) along the y-axis in the structure.

[0065] Each local row switch TLY1 receives a control signal LY from another element in the row selection circuit 14 at its control terminal and is turned on or off based on this control signal LY. Each local row switch TLY1 may be an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) and receives the control signal LY at its gate terminal. The row selection circuit 14 sets the control signal LY to be provided to only one of the local row switches TLY1 designated by the address signal to a specified / indicating level (e.g., high level). Therefore, only the local row switch TLY1 that receives the control signal LY at the selected specified level is then turned on from the multiple local row switches TLY1.

[0066] The second end (the other end) of each local line switch TLY1 is connected to the local word line LWL1. By turning on one of the multiple local line switches TLY1, the word line WL connected to that local line switch TLY1 is connected to the local word line LWL1 via the turned-on local line switch TLY1.

[0067] Local word line LWL1 is connected to global word line GWL1 via global row switch TGY1. Global row switch TGY1 receives a control signal GY from another element in row selection circuit 14 at its control terminal and is turned on or off based on the control signal GY. Global row switch TGY1 may be an n-type MOSFET and receives the control signal GY at its gate terminal.

[0068] Each word line WL is connected at its second (other) end to the first (one) end of a local line switch TLY2. The word line WL is connected to the first end of the local line switch TLY2 located on the same side, for example, connected to... Figure 4 The first end of the local row switch TLY2 is located on the larger coordinate side of the y-axis (that is, on the right side) in the structure.

[0069] Each local row switch TLY2 receives a control signal LY from another element in the row selection circuit 14 at its control terminal and is turned on or off based on this control signal LY. Each local row switch TLY2 may be an n-type MOSFET and receives the control signal LY at its gate terminal. The row selection circuit 14 sets the control signal LY to a selectable level (e.g., high level) only for one of the multiple local row switches TLY2 designated by the address signal ADD. Therefore, only the local row switch TLY2 that receives the selectable control signal LY is then turned on from the multiple local row switches TLY2.

[0070] The second end (the other end) of each local line switch TLY2 is connected to the local word line LWL2. By turning on one of the multiple local line switches TLY2, the word line WL connected to that local line switch TLY2 is connected to the local word line LWL2 via that local line switch TLY2.

[0071] A pair of local row switches TLY1 and TLY2 connected to the same word line WL receive the same control signal LY at each of their gates. By setting the control signal LY associated with a particular word line WL to a specified selected level, the word line WL is connected to both local word lines LWL1 and LWL2.

[0072] Local word line LWL2 is connected to global word line GWL2 via global row switch TGY2. Global row switch TGY2 receives a control signal GY from another element in row selection circuit 14 at its control terminal and is turned on or off based on the control signal GY. Global row switch TGY2 may be an n-type MOSFET and receives the control signal GY at its gate terminal.

[0073] The column selection circuit 15 includes multiple local column switches TLX1, multiple local column switches TLX2, a global column switch TGX1, and a global column switch TGX2. Each bit line BL is connected at one end (first end) to the first end (one end) of a local column switch TLX1. The bit line BL is connected to the first end of the local column switch TXL1 located on the same side, for example, connected to... Figure 3 The first end of the local column switch TLX1 is located on the smaller coordinate side (i.e., on the left side) along the y-axis in the structure.

[0074] Each local column switch TLX1 receives a control signal LX from another element in the column selection circuit 15 at its control terminal and is turned on or off based on this control signal LX. Each local column switch TLX1 may be an n-type MOSFET and receives the control signal LX at its gate terminal. The column selection circuit 15 sets the control signal LX to be provided to only one of the local column switches TLX1 designated by the address signal ADD at the specified selected level (e.g., high level). Therefore, only the local row switch TLX1 that receives the control signal LX at the specified selected level is then turned on from the multiple local column switches TLX1.

[0075] The second end (the other end) of each local column switch TLX1 is connected to the local bit line LBL1. By turning on one of the multiple local column switches TLX1, the bit line BL connected to that local column switch TLX1 is connected to the local bit line LBL1 via that local column switch TLX1.

[0076] Local bit line LBL1 is connected to global bit line GBL1 via global column switch TGX1. Global column switch TGX1 receives a control signal GX from another element in column select circuit 15 at its control terminal and is turned on or off based on the control signal GX. Global column switch TGX1 may be an n-type MOSFET and receives the control signal GX at its gate terminal.

[0077] Each bit line BL is connected at its second end (the other end) to the first end (one end) of a local column switch TLX2. The bit lines BL are connected to the first end of the local column switch TLX2 located on the same side, for example, to... Figure 3 The first end of the local column switch TLX2 on the larger coordinate side (that is, on the right side) along the y-axis in the structure.

[0078] Each local column switch TLX2 receives a control signal LX from another element in the column selection circuit 15 at its control terminal and is turned on or off based on this control signal LX. Each local column switch TLX2 may be an n-type MOSFET and receives the control signal LX at its gate terminal. The column selection circuit 15 sets the control signal LX to be provided to only one of the local column switches TLX2 specified by the address signal ADD at the designated selected level (e.g., high level). Therefore, only the local row switch TLX2 that receives the control signal LX at the designated selected level is then turned on from the multiple local column switches TLX2.

[0079] The second end (the other end) of each local column switch TLX2 is connected to the local bit line LBL2. By turning on one of the multiple local column switches TLX2, the bit line BL connected to that local column switch TLX2 is connected to the local bit line LBL2 via the local column switch TLX2.

[0080] A pair of local column switches TLX1 and TLX2 connected to the same bit line BL receive the same control signal LX at their gates. Bit line BL is connected to both local bit lines LBL1 and LBL2 by setting the control signal LX associated with the specific bit line BL to a specified selected level.

[0081] Local bit line LBL2 is connected to global bit line GBL2 via global column switch TGX2. Global column switch TGX2 receives a control signal GX from another element in column select circuit 15 at its control terminal and is turned on or off based on the control signal GX. Global column switch TGX2 may be an n-type MOSFET and receives the control signal GX at its gate terminal.

[0082] The write circuit 16 includes a write driver 161. The write driver 161 is located outside the memory primitive array 11. In one example, the write driver 161 may be located on one side of the global word line GWL2, on one side of the second end of the word line WL, or on the right side of the memory primitive array 11. In one example, the write driver 161 may be located on one side of the global bit line GBL2, on one side of the second end of the bit line BL, or on the bottom side of the memory primitive array 11.

[0083] The write driver 161 has a first node S+, a second node S-, a third node M+, and a fourth node M-. The first node S+ is connected to the global word line GWL1. The second node S- is connected to the global bit line GBL1. The third node M+ is connected to the global word line GWL2. The fourth node M- is connected to the global bit line GBL2.

[0084] The write driver 161 also receives a reference voltage Vref of a fixed magnitude from the control circuit 13, etc.; however, this fixed magnitude is dynamically selected from a plurality of possible magnitudes. The write driver 161 can output a current of variable magnitude from the first node S+. The write driver 161 can draw current at the second node S-. The write driver 161 allows the current output from the first node S+ to flow through the conductive element connected between the first node S+ and the second node S- to the second node S-. The current output from the first node S+ of the write driver 161 can be referred to as the output current IO of the write driver 161.

[0085] The write driver 161 changes the magnitude of the output current IO based on the voltage applied to the third node M+ and the voltage applied to the fourth node M-. Specifically, the write driver 161 acts as a negative feedback circuit, which outputs a decreasing output current IO as the difference between the voltage at the third node M+ and the voltage at the fourth node M- increases. The voltage at the third node M+ and the voltage at the fourth node M- can have different magnitudes. The write driver 161 outputs an output current IO from the first node S+, which allows a voltage substantially the same as the reference voltage Vref to be applied to the memory cell MC, which is the target for data writing. The setting of the output current IO is independent of the magnitudes of the voltages at the third node M+ and the fourth node M-, but is based on the magnitudes of the voltages at the third node M+ and the fourth node M-.

[0086] The memory cell to which data is written can be referred to as the selected memory cell MCS. In this document, "substantially identical" means that two or more aspects are identical in principle or ideally, but unintentional errors or differences from the ideal are also included in this description. Therefore, when the write driver 161 is mentioned as allowing an output current IO with a voltage substantially the same magnitude as the reference voltage Vref to be applied to the selected memory cell MCS, this means that the write driver 161 outputs an output current IO that is designed to allow a voltage with the same magnitude as the reference voltage Vref to be applied to the selected memory cell MCS, but in practice, differences may occur.

[0087] More specifically, the output current IO of the write driver 161 is adjusted such that the sum of the voltage at the fourth node M- and the reference voltage Vref is equal to the voltage at the third node M+. To achieve this negative feedback operation, the third node M+ and the fourth node M- are connected to the first node N1 and the second node N2 of the selected memory primitive MCS, respectively.

[0088] Figure 7 An example of the components and connections of the write driver 161 according to the first embodiment is shown. Figure 7 As shown, the write driver 161 includes an operational amplifier OP, a capacitor C (referred to as capacitor C), and a p-type MOSFET TP1. The write driver 161 may also include n-type MOSFETs TN1, TN2, TN3, and TN4, as well as a p-type MOSFET TP2, for performing control to enable or disable the write driver 161.

[0089] The non-inverting input terminal of the operational amplifier is used as the third node M+ of the write driver 161. The voltage at node M+ will be referred to as voltage VM+. The first terminal of transistor TN1 (one of the source and drain) is used as node Tref and receives the reference voltage Vref. The second terminal of transistor TN1 (the other of the source and drain) is connected to the inverting input terminal of operational amplifier OP. For example, the gate of transistor TN1 receives the control signal PC from control circuit 13.

[0090] In the cases of AP write and P write, the reference voltage Vref has different magnitudes. In the case of AP write, the magnitude of the reference voltage Vref allows a voltage with the same magnitude as the reference voltage to be applied to the selected memory cell MCS, and allows the AP write current Iwap to flow through the selected memory cell MCS. The magnitude of the reference voltage Vref in the case of AP write can be based on the average characteristics of the memory cell MC. For example, this value can be set or selected taking into account the normal or expected variations in the characteristics of the memory cell MC in, for example, magnetic storage device 1.

[0091] In the case of a P write, the magnitude of the reference voltage Vref allows a voltage of the same magnitude as the reference voltage Vref to be applied to the selected memory cell MCS, and allows the P write current Iwp to flow through the selected memory cell MCS. The magnitude of the reference voltage Vref in the case of a P write can be based on the average characteristics of the memory cell MC. For example, this value can be set or selected taking into account normal or expected variations in the characteristics of the memory cell MC in, for example, magnetic storage device 1.

[0092] The first terminal of transistor TN2 serves as the fourth node M-. The voltage at node M- will be referred to as voltage VM-. The second terminal of transistor TN2 is connected to the inverting input terminal of operational amplifier OP via capacitor C. The gate of transistor TN2 receives, for example, a control signal WT from control circuit 13. The second terminal of transistor TN2 is also connected to a node at ground potential via transistor TN3. For example, the gate of transistor TN3 receives a control signal PC from control circuit 13.

[0093] The first terminal of transistor TP2 is connected to the node at the power supply potential Vdd. The gate of transistor TP2 receives the control signal ˉWT. The symbol "ˉ" indicates the inverse logic of the signal applied by the signal with the symbol "ˉ". The second terminal of transistor TP2 is connected to the first terminal of transistor TP1. The gate of transistor TP1 is connected to the output terminal of operational amplifier OP. The second terminal of transistor TP1 serves as the first node S+ of write driver 161.

[0094] The first terminal of transistor TN4 is used as the second node S- of write driver 161. The second terminal of transistor TN4 is connected to the node at ground potential.

[0095] The magnitude of the output current IO depends on the voltage applied to the gate of transistor TP1. In other words, when the difference between the voltage at the non-inverting input terminal and the voltage at the inverting input terminal increases, the operational amplifier OP outputs a smaller voltage, i.e., applies a smaller voltage to the gate of transistor TP1. When the voltage applied to the gate of transistor TP1 decreases, the magnitude of the output current IO increases. Conversely, when the voltage applied to the gate of transistor TP1 increases, the magnitude of the output current IO decreases.

[0096] When a high-level control signal WT is received, the write driver 161 is enabled and can perform operations.

[0097] 1.2. Operation

[0098] Figure 8 The diagram shows some signal states over time during data writing in the magnetic storage device 1 according to the first embodiment.

[0099] like Figure 8 As shown, before writing data begins, the control signal PC is high, while the control signal WT is low. When the control signal WT is low, the write driver 161 is disabled. Because the control signal PC is high, therefore Figure 7 Transistors TN1 and TN3 are shown in the ON state. One end (first terminal) of the capacitor C connected to transistor TN1 has a voltage Vref. The other end (second terminal) connected to transistor TN3 has a ground potential (=0[V]).

[0100] As data is written, the control signal PC goes low at clock time t1. The low level of the control signal PC continues until clock time t4. As a result of the control signal PC going low, Figure 7 Transistors TN1 and TN3 are turned off, and capacitor C enters an electrically floating state.

[0101] At clock time t2, the control signal WT goes high. The control signal WT controls the write period and remains high during the write operation. The high level of the control signal WT continues until clock time t3. The write driver 161 is enabled between clock time t2 and clock time t3. Because the control signal WT goes high, transistor TN2 is turned on, and the voltage at the second terminal of capacitor C rises from 0 to VM-. Since capacitor C is floating, the voltage rise at the first terminal of capacitor C is the same as the voltage rise at the second terminal. In other words, the voltage at the first terminal of capacitor C becomes Vref+VM-. Therefore, when the write driver 161 is enabled, a voltage of Vref+VM- is applied to the inverting input terminal of the operational amplifier.

[0102] The control signal WT returns to a low level at clock time t3, while the control signal PC returns to a high level at clock time t4.

[0103] Figure 9 The state during data writing in the magnetic storage device 1 according to the first embodiment is shown. Figure 9 It shows the relationship with Figure 7 Same components and range, and also indicates the same as Figure 7 A similar layout. Figure 9 This shows the status during a data write operation in a selected memory cell (MCS). The word line WL connected to the selected memory cell (MCS) will be referred to as the selected word line WLS. The bit line BL connected to the selected memory cell (MCS) will be referred to as the selected bit line BLS. Figure 9 Only the switches TLY1, TGY1, TLY2, TGY2, TLX1, TGX1, TLX2, and TGX2 that are turned on are shown. During data writing in the selected memory primitive MCS, Figure 9 The switch, not shown, is turned off.

[0104] Figure 9 The selected memory cell MC is referred to as the selected memory cell MCS1. In this example, the selected memory cell MCS1 is located near the center of the memory cell array 11. The row selection circuit 14 and the column selection circuit 15 are configured to operate based on the row and column of the selected memory cell MCS during data writing, that is, based on the selected word line WLS and the selected bit line BLS.

[0105] Global row switch TGY1 and local row switch (selected local row switch) TLY1, connected to the selected word line WLS, remain on during data writing. Therefore, the first node N1 of the selected memory primitive MCS1 is connected to the first node S+ of the write driver 161 via the selected word line WLS, the selected local row switch TLY1, the local word line LWL1, the global row switch TGY1, and the global word line GWL1. The current path between the first node S+ and the first node N1 of the selected memory primitive MCS1 has a resistance value RX1.

[0106] The global column switch TGX1 and the local column switch (selected local column switch) TLX1, connected to the selected bit line BLS, remain in the ON state during data writing. Therefore, the second node N2 of the selected memory primitive MCS1 is connected to the second node S- of the write driver 161 via the selected bit line BLS, the selected local column switch TLX1, the local bit line LBL1, the global column switch TGX1, and the global bit line GBL1. The current path between the second node N2 and the second node S- of the selected memory primitive MCS1 has a resistance value RY1. The current path connecting the first node S+ and the second node S- is formed by the selected memory primitive MCS1 connected between the first node S+ and the second node S- of the write driver 161. The current shown as a thick solid line / arrow can flow through this current path by enabling the write driver 161 in the current path formation state. This current allows data to be written to the selected memory primitive MCS1. The magnitude of the current depends on the data to be written, i.e., whether the write corresponds to an AP write or a P write. The magnitude of the current to be supplied also depends on the position of the selected memory cell MCS1 in the memory cell array 11.

[0107] Global row switch TGY2 and local row switch (selected local row switch) TLY2, connected to the selected word line WLS, remain on during data writing. Therefore, the first node N1 of the selected memory cell MCS1 is also connected to the third node M+ of the write driver 161 via the selected word line WLS, the selected local row switch TLY2, the local word line LWL2, the global row switch TGY2, and the global word line GWL2. Thus, as shown by the dashed line, the third node M+ receives voltage V11 at the first node N1 of the selected memory cell MCS.

[0108] The global row switch TGY2 and the local column switch (selected local column switch) TLX2, connected to the selected bit line BLS, remain on during data writing. Therefore, the second node N2 of the selected memory cell MCS1 is also connected to the fourth node M- of the write driver 161 via the selected bit line BLS, the selected local column switch TLX2, the local bit line LBL2, the global column switch TGX2, and the global bit line GBL2. Thus, as shown by the dashed line / arrow, the fourth node M- receives voltage V12 at the second node N2 of the selected memory cell MC.

[0109] The state in which the selected memory cell MCS is electrically connected to the first node S+, the second node S-, the third node M+, and the fourth node M- of the write driver 161 is referred to as the magnetic storage device 1 being in the write-selected state with respect to the selected memory cell MCS.

[0110] As referenced above Figure 6 Regardless of the voltage magnitudes at the third node M+ and the fourth node M-, the write driver 161 outputs an output current IO (used as the write current IW) that allows a voltage substantially the same as the reference voltage Vref to be applied across the selected memory cell MCS1. The reference voltage Vref has different magnitudes in the cases of AP writes and P writes, as reference... Figure 7 The AP write current Iwap flows through the selected memory cell MCS1 during AP writes, and the P write current Iwp flows through the selected memory cell MCS1 during P writes, using a reference voltage Vref whose magnitude is based on the data to be written.

[0111] Because the data write is complete, the resistance of the selected memory cell MCS1 after the write operation differs from that before the write operation. Therefore, the voltages V11 and V22 immediately after the write operation—that is, the voltages V11 and V22 immediately after the resistance switch—have different magnitudes than the voltages V11 and V12 before the write operation. However, the output current IO also changes based on the voltage change. Therefore, the voltage applied to the selected memory cell MCS1 is essentially the same before and after the write operation.

[0112] Figure 10 The state of the selected memory cell MCS1 before and after a P-write according to the first embodiment is shown. Before the P-write, the selected memory cell MCS1 has a resistor Rap in a high-resistance state. For the P-write, a reference voltage Vref is set to have a magnitude equal to the voltage Vp (in some cases referred to as the P-write voltage Vp) intended to be applied to the selected memory cell MCS1 for the P-write. Based on this setting, the write driver 161 outputs a P-write current Iwp1, the magnitude of which is obtained by dividing the P-write voltage Vp by the resistor Rap, thereby applying the P-write voltage Vp to the selected memory cell MCS1 based on the voltage V11 at the first node N1 and the voltage V12 at the second node N2 of the selected memory cell MCS1.

[0113] The P-write operation is completed by supplying the P-write current Iwp1, and the selected memory cell MCS1 is set to a resistor Rp. Simultaneously, the voltage V11 at the first node N1 and the voltage V12 at the second node of the selected memory cell MCS1 change. Based on this change, the write driver 161 outputs an output current IO with a magnitude based on the changed voltages V11 and V12. In other words, the write driver 161 outputs a P-write current Iwp2 with a magnitude obtained by dividing the P-write voltage Vp by the resistor Rp. The P-write current Iwp2 is greater than the P-write current Iwp1. Since the P-write operation is complete, the P-write current Iwp2 flows, so even after the P-write operation is complete, the P-write voltage Vp continues to be applied to the selected memory cell MCS1.

[0114] The same phenomenon occurs when writing to the AP. Figure 11 The state of the selected memory cell MCS1 before and after an AP write, according to the first embodiment, is shown. Before the AP write, the selected memory cell MCS1 has a resistor Rp in a low-resistance state. For the AP write, a reference voltage Vref is set to have a magnitude equal to the voltage Vap (in some cases referred to as the AP write voltage Vap) intended to be applied to the selected memory cell MCS1 for the AP write. Based on this setting, the write driver 161 outputs an AP write current Iwap1, the magnitude of which is obtained by dividing the AP write voltage Vap by the resistor Rp, thereby applying the AP write voltage Vap to the selected memory cell MCS1 based on the voltage V11 at the first node N1 and the voltage V12 at the second node N2 of the selected memory cell MCS1.

[0115] AP writing is completed by providing an AP write current Iwap1, and the selected memory cell MCS1 is set to a resistor Rap. Simultaneously, the voltage V11 at the first node N1 and the voltage V12 at the second node of the selected memory cell MCS1 change. Based on this change, the write driver 161 outputs an output current IO with a magnitude based on the changed voltages V11 and V12. In other words, the write driver 161 outputs an AP write current Iwap2 with a magnitude obtained by dividing the AP write voltage Vap by the resistor Rap. The AP write current Iwap2 is less than the AP write current Iwap1. Since the AP write is complete, the AP write current Iwap2 flows, so even after the AP write is complete, the AP write voltage Vap continues to be applied to the selected memory cell MCS1.

[0116] In this way, the selected memory cell MCS receives a voltage of substantially the same magnitude before and after the resistance of the selected memory cell MCS changes.

[0117] Through control performed by the write driver 161, the output current IO (i.e., the write current Iw) has a size that allows substantially the same reference voltage Vref to be applied to the selected memory primitive MCS, regardless of the location of the selected memory primitive MCS in the memory primitive array 11.

[0118] The position of the selected memory cell MCS within the memory cell array 11 determines the resistance of the current path connecting the first node S+ and the second node S- of the write driver 161 in the magnetic storage device 1 under write-selected state. This is because the position of the selected memory cell MCS affects the route of the current path. In other words, the distance of the current path connecting the first node S+ and the first node N1 of the selected memory cell MCS, as well as the distance of the current path connecting the second node N2 and the second node S- of the selected memory cell MCS, depends on the position of the selected memory cell MCS. Furthermore, the distance (length) of the current path affects the resistance of the current path. Therefore, the resistance of the current path connecting the first node S+ and the second node S- of the write driver 161 depends on the position of the selected memory cell MCS. This means that the voltage at the first node N1 and the voltage at the second node N2 of the selected memory cell MCS also depend on the position of the selected memory cell MCS within the memory cell array 11.

[0119] exist Figure 9 When the write is selected, the write driver 161 outputs an output current IO1 with a specific value set based on the voltage V11 at the first node N1 and the voltage V12 at the second node N2 of the selected memory primitive MCS1.

[0120] The position of the selected memory cell MCS in the memory cell array 11 affects the voltage at the first node N1 and the second node N2 of the selected memory cell MCS. Figure 9 similar, Figure 12 and Figure 13 The state of the magnetic storage device 1 during data writing according to the first embodiment is shown; however, Figure 12 and Figure 13 It shows the relationship with Figure 9 The write state of selected memory primitives MCS2 and MCS3, which are located at different positions of the selected memory primitive MCS1, is selected.

[0121] like Figure 12 As shown, the selected memory cell MCS2 is closer to the write driver 161 than the selected memory cell MCS1. In other words, Figure 12 The selected word line WLS ratio Figure 9 The selected word line WLS is closer to the local bit line LBL2. Furthermore... Figure 12 The selected bit line BLS ratio Figure 9 The selected bit line BLS is closer to the local word line LWL2. The current path between the first node S+ and the first node N1 of the selected memory primitive MCS2 has a resistance value RX2, and the current path between the second node N2 and the second node S- of the selected memory primitive MCS2 has a resistance value RY2. For Figure 9 The memory cell MCS1 shown has a resistance value RX2 that is less than the resistance value RX1. Additionally, for... Figure 9 In the memory cell MCS1e shown, the resistance value RY2 is less than the resistance value RY1. Therefore, the voltage V21 at the first node N1 of the selected memory cell MCS2 is lower than the voltage V11 at the first node N1 of the selected memory cell MCS1. Furthermore, the voltage V22 at the second node N2 of the selected memory cell MCS2 is lower than the voltage V12 at the first node N1 of the selected memory cell MCS1.

[0122] For reference Figure 6 The output current IO of the write driver 161 is adjusted so that the sum of the voltage at the fourth node M- and the reference voltage Vref is equal to the voltage at the third node M+. Figure 12 When the write operation is selected, the write driver 161 therefore outputs an output current IO2. The output current IO2 is less than... Figure 9 The output current IO1 shown is used to write the selected state.

[0123] exist Figure 12 In the write-selected state shown, the resistance values ​​RX2 and RY2 are both lower than [value missing]. Figure 9 The resistor values ​​RX1 and RY1 are shown in the write-selected state. Therefore, the voltage set by the output current IO1, resistor value RX1, and resistor value RY1 is essentially equal to the voltage set by the output current IO2, resistor value RX2, and resistor value RY2. In other words, the voltages applied to both selected memory cells MCS1 and MCS2 are each essentially equal to the reference voltage Vref.

[0124] like Figure 13 As shown, compared to the selected memory cell MCS1 in the memory cell array 11, the selected memory cell MCS3 is farther from the write driver 161. In other words, Figure 13 The selected word line WLS ratio Figure 9 The selected word line WLS is closer to the local bit line LBL1. Furthermore... Figure 13 The selected bit line BLS ratio Figure 9 The selected bit line BLS is closer to the local word line LWL1. Therefore, the current path between the first node S+ and the first node N1 of the selected memory primitive MCS3 has a resistance value RX3, while the current path between the second node N2 and the second node S- of the selected memory primitive MCS3 has a resistance value RY3. Resistance value RX3 is higher than resistance value RX1, and resistance value RY3 is higher than resistance value RY1. The voltage V31 at the first node N1 of the selected memory primitive MCS3 is higher than the voltage V11 at the first node N1 of the selected memory primitive MCS1, and the voltage V32 at the second node N2 of the selected memory primitive MCS3 is higher than the voltage V12 at the first node N1 of the selected memory primitive MCS1.

[0125] exist Figure 13 When the write operation is selected, the write driver 161 outputs current IO3. The output current IO3 is greater than... Figure 9 The output current IO1 is shown in the selected state. Figure 13 In the write-selected state shown, the resistance values ​​RX3 and RY3 are respectively higher than... Figure 9 The resistor values ​​RX1 and RY1 are shown in the write-selected state. Therefore, the voltage set by the output current IO1, resistor RX1, and resistor RY1 is essentially equal to the voltage set by the output current IO3, resistor RX3, and resistor RY3. In other words, a voltage essentially equal to the reference voltage Vref is applied to both the selected memory cells MCS1 and MCS3.

[0126] 1.3. Advantages (Effects)

[0127] According to the first embodiment, a magnetic storage device 1 is provided that can suppress data write errors while also suppressing damage to the memory cell MC.

[0128] The following two configurations are possible configurations for providing write current to the memory primitive array. Figure 14 For comparative purposes, a portion of the components and connections of the first magnetic storage device 100 are shown. Figure 15 For comparative purposes, a portion of the components and connections of the second magnetic storage device 200 are shown.

[0129] like Figure 14 As shown, the magnetic storage device 100 includes a memory cell array 11, a row selection circuit 14, a column selection circuit 15, and a write circuit. The write circuit includes a constant voltage source CV and provides a voltage of a specific constant magnitude between the constant voltage source CV and a ground potential node.

[0130] During data writing, a voltage is applied through a constant voltage source CV, and the write current flows from the constant voltage source CV to the ground node via the column select circuit 15, word line WL (selected word line WLS), selected memory cell MCS, bit line BL (selected bit line BLS), and row select circuit 14. When data is written to the selected memory cell MCS101 or MCS102 in the magnetic storage device 100, the following may occur: In the memory cell MC, the selected memory cell MCS101 is positioned closest to both the column select circuit 15 and the row select circuit 14. In the memory cell MC, the selected memory cell MCS102 is positioned furthest from both the column select circuit 15 and the row select circuit 14.

[0131] When data is written to the selected memory cell MCS101, the current path from the constant voltage source CV to the selected memory cell MCS101 is short. Therefore, the total resistance in this current path is low. Consequently, depending on the magnitude of the voltage provided by the constant voltage source CV, the magnitude of the write current may become excessive, and depending on the write current, the selected memory cell MCS101 may be damaged.

[0132] To suppress damage to the memory cell MC caused by such excessive write current, the magnitude at the constant voltage source CV can be suppressed. However, in this case, data write errors may occur in the selected memory cell MCS102. In other words, the current path from the constant voltage source CV to the selected memory cell MCS102 is long. Therefore, the total resistance in this current path is large. Consequently, if the voltage supplied by the constant voltage source CV remains small, a sufficient voltage may not be applied to the selected memory cell MCS102, and thus the required write current will not flow through the selected memory cell MCS102. Due to the insufficient magnitude of the supplied write current, data writing in the selected memory cell MCS102 may fail.

[0133] like Figure 15 As shown, the magnetic storage device 200 includes a memory cell array 11. The magnetic storage device 200 also includes a row selection circuit 14 (see...). Figure 14 ), column selection circuit 15 (see Figure 14 The magnetic storage device 200 includes a write circuit. The write circuit includes a constant current source CI. The write circuit of the magnetic storage device 200 causes a constant current to flow from the constant current source CI to the ground potential node. In the case of AP writing, the write circuit causes an AP write current Iwap with the same magnitude as the constant current source CI to flow.

[0134] By utilizing a constant voltage source provided through the constant current source CI, it is possible to suppress both damage to the memory cell MC and data write failures. However, in the case of AP write, the selected memory cell MCS103 may be damaged due to the continuous flow of the AP write current Iwap, which has the same constant magnitude. Unexpected changes in the characteristics of the memory cell MC are unavoidable, and each memory cell MC may require slightly different durations before the AP write is successfully completed, during which the AP write current Iwap must be provided. Therefore, in some cases, even after the selected memory cell MCS103 has entered the AP state, the AP write current Iwap may still flow through the selected memory cell MCS103 because the AP write current Iwap continues to be provided even after the transition to the AP state has been achieved for the selected memory cell MCS103. A larger AP write current Iwap results in a larger resistance Rap for the memory cell MC set to the AP state. Therefore, if the AP write current Iwap continues to flow through the selected memory cell MCS103 that has transitioned to the AP state, a voltage VH higher than the voltage VL applied to the selected memory cell MCS103 in the P state will be applied across the selected memory cell MCS103. Specifically, the AP write current Iwap will flow through memory cells MC that easily / quickly transition to the AP state. Even after the transition to the AP state is complete, the AP write current IWap may continue to flow through such memory cells MC for a prolonged period, and such memory cells MC are more likely to be damaged due to the prolonged application of a high voltage VH.

[0135] According to the first embodiment, the write driver 161 receives the voltage at the first node N1 of the selected memory primitive MC at the third node M+, receives the voltage at the second node N2 at the fourth node M-, and provides a current from the first node S+ to the selected memory primitive MCS whose magnitude is based on the voltage at the first node N1 and the second node N2 of the selected memory primitive MCS. To achieve this, the magnetic storage device 1 includes switches TLY1, TGY1, TLY2, TGY2, TLX1, TGX1, TLX2, and TGX2, and wiring LWL2, GWL2, LBL2, and GBL2 for connecting the third node M+ and the fourth node M- of the write driver 161 to the first node N1 and the second node N2 of the selected memory primitive MCS, respectively.

[0136] With the above configuration, a write current Iw, whose magnitude is based on the voltage at the first node N1 and the second node N2 of the selected memory cell MCS, is first provided to the selected memory cell MCS, while a write current Iw whose magnitude is based on the resistance of the selected memory cell MCS is also provided to the selected memory cell MCS. This prevents the same write current Iw as before the change in resistance in the selected memory cell MCS (caused by writing data into the selected memory cell MCS) from flowing through the selected memory cell MCS even after the change. Therefore, it prevents a large voltage caused by a current of the same magnitude as before the change in resistance in the selected memory cell MCS and a large voltage caused by the change in resistance from being applied to the selected memory cell MCS. This suppresses damage to the selected memory cell MCS.

[0137] Furthermore, based on the same principle, regardless of the position of the selected memory cell MCS in the memory cell array 11, a write current Iw of substantially the same magnitude can flow through the selected memory cell MCS. This is because the resistance connecting the first node N1 of the selected memory cell MCS to the component of the write driver 161 and the resistance connecting the second node N2 of the selected memory cell MCS to the component of the write driver 161 depend on the position of the selected memory cell MCS, and the write current Iw depends on the voltage at the first node N1 and the voltage at the second node N2 of the selected memory cell MCS. Regardless of the position of the selected memory cell MCS, in the case of AP writing, an AP write current Iwap of substantially the same magnitude flows through the selected memory cell MCS, and in the case of P writing, a P write current Iwp of substantially the same magnitude flows through the selected memory cell MCS. Therefore, write errors caused by insufficient write current Iw due to the position of the selected memory cell MCS are prevented.

[0138] Therefore, damage to the memory cell MC and data write failure that may occur in the magnetic storage device 100 due to the provision of a constant voltage, as well as damage to the selected memory cell MCS that may occur in the magnetic storage device 200 due to the provision of a constant current, can be suppressed. In other words, a magnetic storage device 1 can be provided that can simultaneously suppress damage to the memory cell MC and data write failure.

[0139] Although certain embodiments have been described, these embodiments are given by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and variations may be made to the forms of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications falling within the scope and spirit of this disclosure.

[0140] Label Explanation

[0141] 1: Magnetic storage device; 2: Memory controller; 11: Memory cell array; 12: Input / output circuit; 13: Control circuit; 14: Row selection circuit; 15: Column selection circuit; 16: Write circuit; 17: Read circuit; MC: Memory cell; WL: Word line; BL: Bit line; VR: Magnetoresistive element; SE: Switching element; 21: Conductor; 22: Conductor; 24: Lower electrode; 25: Variable resistor material; 26: Upper electrode; 31: Ferromagnetic layer; 32: Insulating layer; 33: Ferromagnetic layer; Iw: Write current; Iwap: AP write current; Iwp: P write current; LWL1: Local word line LWL2: Local word line, GWL1: Global word line, GWL2: Global word line, LBL1: Local bit line, LBL2: Local bit line, GBL1: Global local bit line, GBL2: Global local bit line, TLY1: Local row switch, TGY1: Global row switch, TLY2: Local row switch, TGY2: Global row switch, TLX1: Local column switch, TGX1: Global column switch, TLX2: Local column switch, TGX2: Global column switch, S+: First node, S-: Second node, M+: Third node, M-: Fourth node, 161: Write driver, IO: Output current.< / n> < / m> < / m>

Claims

1. A magnetic storage device, comprising: A magnetoresistive element having a first terminal and a second terminal; A first switch is located between the first end and the first wiring; The second switch is located between the second terminal and the second wiring; A third switch is located between the first end and the third wiring; The fourth switch is located between the second terminal and the fourth wiring; as well as A driver, connected to the first wiring and the second wiring, is configured to provide a current to the first wiring of a magnitude set based on the voltage at the first terminal and the voltage at the second terminal.

2. The magnetic storage device according to claim 1, further comprising: The fifth wiring is connected to the first end and between the first switch and the third switch; as well as The sixth wiring is connected to the second end and between the second switch and the fourth switch.

3. The magnetic storage device according to claim 2, wherein... The fifth wiring is connected to the first switch at the third end and to the third switch at the fourth end, and The sixth wiring is connected to the second switch at the fifth end and to the fourth switch at the sixth end.

4. The magnetic storage device according to claim 1, wherein... The driver includes a first node connected to the first end via the first switch and a second node connected to the second end via the second switch, and The driver is configured to output the current from the first node and draw the current at the second node.

5. The magnetic storage device of claim 4, wherein the drive includes a third node connected to the first end via the third switch and a fourth node connected to the second end via the fourth switch.

6. The magnetic storage device according to claim 4, wherein The driver is configured to receive a reference voltage, and The magnitude of the current is based on the sum of the voltage at the second terminal and the reference voltage, as well as the voltage at the first terminal.

7. The magnetic storage device according to claim 4, wherein The driver includes an operational amplifier, and The operational amplifier is configured to receive the voltage at the first terminal at the non-inverting input terminal and to receive a voltage at the inverting input terminal equal to the sum of the voltage at the second terminal and a reference voltage.

8. The magnetic storage device according to claim 7, wherein The driver includes a first transistor. The first transistor is connected to the first node, and The gate of the first transistor receives the output of the operational amplifier.

9. A magnetic storage device, comprising: A magnetoresistive element having a first terminal and a second terminal; An operational amplifier having a non-inverting input terminal connected to the first terminal and an inverting input terminal receiving a voltage equal to the sum of a reference voltage and a voltage at the second terminal; as well as A first transistor is connected between the first terminal and a first node at a first potential, and the gate of the first transistor receives the output of the operational amplifier. The operational amplifier is configured to adjust the output to provide a current of a magnitude set based on the voltage at the first terminal and the voltage at the second terminal.

10. The magnetic storage device according to claim 9, further comprising: A second transistor is connected between the second terminal and a second node at a second potential lower than the first potential.

11. The magnetic storage device according to claim 10, further comprising: A first wiring is connected to the first end; A first switch is connected between the first wiring and the first transistor; as well as The second wiring is connected to the second end, wherein The second transistor is connected between the second wiring and the second node.

12. The magnetic storage device according to claim 11, further comprising: A third switch is connected between the first wiring and the in-phase input terminal; as well as A capacitor is connected between the second wiring and the inverting input terminal.

13. A magnetic storage device, comprising: A magnetoresistive element having a first terminal and a second terminal; as well as A driver having a first node connected to the first end and a second node connected to the second end, the driver being configured to provide a current of a magnitude set based on the voltage at the first end and the voltage at the second end from the first node, and to draw the current out at the second node.

14. The magnetic storage device according to claim 13, wherein The driver includes a third node connected to the first end and a fourth node connected to the second end, and The driver is configured to provide a current from the first node of a magnitude determined based on the voltage at the first node and the voltage at the second node.

15. The magnetic storage device of claim 14, wherein the drive is configured to: Receive reference voltage, and The current is provided from the first node based on the sum of the voltage at the fourth node and the reference voltage, as well as the magnitude of the voltage at the third node.

16. The magnetic storage device according to claim 15, wherein The driver includes an operational amplifier, and The operational amplifier receives the voltage of the fourth node at the non-inverting input terminal and receives a voltage at the inverting input terminal equal to the sum of the voltage at the third node and the reference voltage.

17. The magnetic storage device according to claim 16, wherein The driver includes a first transistor. The first transistor is connected to the first node, and The gate of the first transistor receives the output of the operational amplifier.

18. The magnetic storage device according to claim 17, further comprising: A first switch is located between the first end and the first wiring; The second switch is located between the second terminal and the second wiring; A third switch is located between the first end and the third wiring; as well as The fourth switch is located between the second terminal and the fourth wiring.

19. The magnetic storage device according to claim 18, further comprising: The fifth wiring is connected to the first end and between the first switch and the third switch; as well as The sixth wiring is connected to the second end and between the second switch and the fourth switch.

20. The magnetic storage device according to claim 19, wherein The fifth wiring is connected to the first switch at the third end and to the third switch at the fourth end, and The sixth wiring is connected to the second switch at the seventh end and to the fourth switch at the eighth end.

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