Semiconductor device and electronic system including the same

Abstract

A semiconductor memory device includes a substrate having a first region, a second region, and a third region; main separation regions extending in a first direction and spaced apart from each other in a second direction; first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction; and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are located between the main separation regions in the second direction at a first pitch, the second auxiliary separation regions are disposed between the main separation regions in the second direction at a second pitch smaller than the first pitch, and the first auxiliary separation regions and the second auxiliary separation regions are offset with respect to each other in the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0122365, filed with the Korean Intellectual Property Office on September 22, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some example embodiments relate to a semiconductor device and / or an electronic system including the semiconductor device. Background Technology

[0004] In electronic systems that store data, semiconductor devices capable of storing large amounts of data are desired. Therefore, methods to increase the data storage capacity of semiconductor devices are being researched. For example, semiconductor devices incorporating three-dimensional memory cells instead of two-dimensional memory cells have been proposed as a method to increase the data storage capacity of semiconductor devices. Summary of the Invention

[0005] Some example embodiments provide a semiconductor device with improved reliability.

[0006] Alternatively or additionally, some example embodiments provide an electronic system that includes a semiconductor device with improved reliability.

[0007] According to some example embodiments, a semiconductor device includes: a substrate having a first region, a second region, and a third region; a first stacked structure including first gate electrodes stacked and spaced apart from each other and a first interlayer insulating layer alternately stacked with the first gate electrodes; a second stacked structure on the first stacked structure and including a second gate electrode and a second interlayer insulating layer alternately stacked with the second gate electrode; the second gate electrodes being stacked and spaced apart from each other in the first region and arranged in a stepped shape in a first direction while extending in a first direction, the stepped shape being in the second and third regions; main separation regions in the first and third regions, the main separation regions penetrating the first and second stacked structures, the main separation regions extending in the first direction and spaced apart from each other in a second direction perpendicular to the first direction; in the first region and In the second region, there is a first auxiliary separation region that penetrates a first and a second stacked structure between the main separation regions. The first auxiliary regions extend in a first direction and are spaced apart from each other in a second direction. In the third region, there is a second auxiliary separation region that penetrates the first and a second stacked structure between the main separation regions. The second auxiliary separation region extends in a first direction and is spaced apart from each other in a second direction. There is also a first channel structure and a second channel structure, each of which includes a channel layer and has a first width. The first and second channel structures respectively penetrate the first and second stacked structures. Finally, there is a dummy structure that penetrates the first and second stacked structures and has a second width greater than the first width. The first auxiliary separation regions are arranged between the main separation regions at a first spacing in the second direction, and the second auxiliary separation regions are arranged between the main separation regions at a second spacing in the second direction, where the second spacing is smaller than the first spacing.

[0008] According to some example embodiments, a semiconductor device includes: a substrate having a first region, a second region, and a third region; a stacked structure including a plurality of gate electrodes stacked on and spaced apart from each other on the first region and extending in a stepped configuration on the second and third regions in a first direction; a channel structure, each penetrating the stacked structure and including a channel layer; main separation regions in the first to third regions, penetrating the stacked structure, extending in the first direction, and spaced apart from each other in a second direction perpendicular to the first direction; and a first auxiliary separation region in the first and second regions, the first auxiliary separation region penetrating the stacked junction between the main separation regions. The main separation regions extend in a first direction and are spaced apart in a second direction; a second auxiliary separation region in a third region, the second auxiliary separation region penetrating the stacked structure between the main separation regions, extending in the first direction and spaced apart in the second direction; and a first lower separation region between the main separation regions and penetrating at least one gate electrode, the at least one gate electrode including the lowest gate electrode among the gate electrodes, the first lower separation region between at least one of the first auxiliary separation regions and between the at least one of the second auxiliary separation regions adjacent to the at least one of the first auxiliary separation regions, and connecting the at least one of the first auxiliary separation regions to the at least one of the second auxiliary separation regions. The first auxiliary separation regions are arranged between the main separation regions in the second direction at a first spacing, the second auxiliary separation regions are arranged between the main separation regions in the second direction at a second spacing less than the first spacing, and the first auxiliary separation regions and the second auxiliary separation regions are offset relative to each other in the second direction.

[0009] According to some example embodiments, an electronic system includes: a semiconductor memory device including a first substrate; an active or passive circuit on the first substrate; a second substrate on the active or passive circuit and having a first region, a second region, and a third region; a stacked structure including a plurality of gate electrodes stacked and spaced apart from each other on the second substrate of the first to third regions and extending in a first direction and arranged in a stepped shape in the first direction, the stepped shape being in the second and third regions, the stacked structure including a first interlayer insulating layer alternately stacked with the gate electrodes; a channel structure, each penetrating the stacked structure and including a channel layer; a main separation region penetrating the stacked structure, the main separation regions extending in the first direction and spaced apart from each other in a second direction perpendicular to the first direction, the main separation regions being on the second substrate of the first to third regions; and a first auxiliary separation region penetrating the stacked structure between the main separation regions, the first auxiliary separation region being in the second substrate of the first to third regions. Extending in a first direction and spaced apart in a second direction, the first auxiliary separation region is located in the first and second regions; a second auxiliary separation region extends in the first direction and is spaced apart in the second direction, and is located in the third region; a first lower separation region is located between the main separation regions and penetrates at least one gate electrode, the at least one gate electrode including the lowest gate electrode among a plurality of gate electrodes, the first lower separation region being located between at least one of the first auxiliary separation regions and a second auxiliary separation region adjacent to the at least one of the first auxiliary separation regions, and connecting the at least one of the first auxiliary separation regions to the second auxiliary separation region; input / output pads electrically connected to active or passive circuitry; and controller circuitry electrically connected to the semiconductor memory device via the input / output pads and configured to control the semiconductor memory device. In this semiconductor memory device, the first auxiliary separation regions are arranged between the main separation regions at a first spacing in the second direction, and the second auxiliary separation regions are arranged between the main separation regions at a second spacing less than the first spacing in the second direction. Attached Figure Description

[0010] The above and other aspects, features and advantages of the exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figures 1 to 3 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0012] Figures 4 to 7 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0013] Figure 8This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0014] Figure 9 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0015] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0016] Figure 11 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0017] Figure 12 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0018] Figure 13 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0019] Figure 14 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0020] Figures 15A to 18C This is a schematic cross-sectional view illustrating a method of manufacturing / processing a semiconductor device according to some example embodiments.

[0021] Figure 19 It is a schematic diagram of an electronic system including a semiconductor device according to some example embodiments.

[0022] Figure 20 It is a schematic perspective view of an electronic system including a semiconductor device according to some example embodiments.

[0023] Figure 21 This is a schematic cross-sectional view of a semiconductor package according to some example embodiments. Detailed Implementation

[0024] Hereinafter, some exemplary embodiments will be described with reference to the accompanying drawings.

[0025] Figures 1 to 3 This is a schematic plan view of a semiconductor device according to some example embodiments. Figure 2 yes Figure 1 A magnified view of region "A". Figure 3 yes Figure 2 A magnified view of region "B".

[0026] Figures 4 to 7 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments. Figure 4 It is along Figure 2 A cross-sectional view taken from line I-I'. Figure 5 It is along Figure 2 A cross-sectional view taken from line II-II'. Figure 6 It is along Figure 2 The cross-sectional view taken from line III-III'. Figure 7 It is along Figure 2 The cross-sectional view taken from line IV-IV'.

[0027] Reference Figures 1 to 7 The semiconductor device 100 may include: a peripheral circuit structure PERI, which includes a base substrate 301; and a memory cell structure CELL, which includes a substrate 101. The memory cell structure CELL, or a portion thereof, may be disposed above the peripheral circuit structure PERI. Alternatively or additionally, in some example embodiments, the memory cell structure CELL, or a portion thereof, may be disposed below the peripheral circuit structure PERI. Alternatively or additionally, in some example embodiments, the memory cell structure CELL and the peripheral circuit structure PERI may be joined together, for example, by a copper-to-copper (Cu-to-Cu) bonding.

[0028] The peripheral circuit structure PERI may include a base substrate 301, a source / drain region 305 and a device isolation layer 310 in the base substrate 301, a circuit element 320, a circuit contact plug 370, a circuit interconnect 380, and a peripheral insulating layer 390 disposed on the base substrate 301.

[0029] The base substrate 301 may have an upper surface extending in directions X and Y. An active region may be defined in the base substrate 301 by a device isolation layer 310. A source / drain region 305 comprising at least one impurity such as boron, phosphorus, arsenic, and carbon may be disposed in a portion of the active region. The base substrate 301 may be a single-crystal structure or a polycrystalline structure and may include a semiconductor material, such as at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. The base substrate 301 may be configured as a bulk wafer or an epitaxial layer.

[0030] Circuit element 320 may include active circuitry such as planar transistors and / or three-dimensional transistors. Alternatively or additionally, circuit element 320 may include diodes. Alternatively or additionally, circuit element 320 may include passive circuitry such as at least one of resistors, capacitors, and inductors. Circuit element 320 may be single-terminal, and / or may have two terminals, and / or three terminals, and / or more than three terminals. Circuit element 320 may be linear, and / or may be non-linear. Each or at least one of circuit elements 320 may include a circuit gate dielectric layer 322, a spacer layer 324, and a circuit gate electrode 325. Source / drain regions 305 may be disposed on opposite sides of the base substrate 301 adjacent to the circuit gate electrode 325.

[0031] A peripheral insulating layer 390 may be disposed on a circuit element 320 on a base substrate 301. A circuit contact plug 370 may penetrate the peripheral insulating layer 390 to connect to a source / drain region 305. Electrical signals may be applied to the circuit element 320 through the circuit contact plug 370. In an area not shown, the circuit contact plug 370 may also be connected to a circuit gate electrode 325. Circuit interconnects 380 may be connected to the circuit contact plug 370 and may be configured in multiple layers. The circuit contact plug 370 may be connected to one of the circuit gate electrodes 325, one source / drain region 305 on one side of the circuit gate electrode 325, and another source / drain region 305 on the other side of the circuit gate electrode 325; however, the exemplary embodiment is not limited thereto.

[0032] The memory cell structure CELL may include a substrate 101 having a first region R1, a second region R2, and a third region R3. The memory cell structure CELL may have a first stacked structure ST1 and a second stacked structure ST2 stacked on the substrate 101, a first channel structure CH1 and a second channel structure CH2 penetrating the first stacked structure ST1 and the second stacked structure ST2 respectively, and a dummy structure DS penetrating the first stacked structure ST1 and the second stacked structure ST2. The memory cell structure CELL may further include: a main separation region MS1 ​​that penetrates the first stacked structure ST1 and the second stacked structure ST2, extends in the X direction, and is spaced apart from each other in the Y direction; a first auxiliary separation region MS2a that penetrates the first stacked structure ST1 and the second stacked structure ST2 between the main separation regions MS1, extends in the X direction, and is spaced apart from each other in the Y direction; a second auxiliary separation region MS2b that penetrates the first stacked structure ST1 and the second stacked structure ST2 between the main separation regions MS1, extends in the X direction, is spaced apart from each other in the Y direction, and is shifted relative to the first auxiliary separation region MS2a in the Y direction; and an upper separation region SS that penetrates a portion of the upper part of each of the first stacked structure ST1 and the second stacked structure ST2 and is alternately disposed with the first auxiliary separation region MS2a in the Y direction. The memory cell structure CELL may further include lower separation regions GS1 and GS2 that penetrate a portion of the lowermost gate electrode 130.

[0033] The first region R1 of substrate 101 may be or include a region in which gate electrodes 130 and 230 are vertically stacked and a channel structure CH is provided, and may be or include a region in which memory cells are provided. The second region R2 and the third region R3 of substrate 101 may be or include regions in which gate electrodes 130 extend to different lengths, and may be referred to as stepped regions. The second region R2 and / or the third region R3 may correspond to the region where the memory cells are electrically connected to the peripheral circuit structure PERI. The second region R2 and / or the third region R3 may be disposed at at least one end of the first region R1 in at least one direction (e.g., direction X). The second region R2 may correspond to the upper part of the stepped region, and may correspond to the region that begins with the step shape formed by the gate electrodes 130 and 230, which will be described later. The first auxiliary separation region MS2a and the second auxiliary separation region MS2b may be alternately disposed on the boundary between the second region R2 and the third region R3. The second auxiliary separation region MS2b is disposed offset relative to the first auxiliary separation region MS2a on the boundary between the second region R2 and the third region R3. In some example embodiments, the second region R2 may be the region located at the end of the upper gate electrode 230U constituting the string select transistor. In some example embodiments, gate electrodes 130 and 230 may be exposed upward in the second region R2 and the third region R3 to connect to the contact plug 280. The third region R3 may be a stepped region other than the region located at the end of the upper gate electrode 230U. Gate electrodes 130 and 230 may include a first gate electrode 130 constituting the first stacked structure ST1 and a second gate electrode 230 constituting the second stacked structure ST2.

[0034] Substrate 101 may have an upper surface extending in directions X and Y. Substrate 101 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may also include impurities. Substrate 101 may be configured as a polycrystalline semiconductor layer, such as a doped or undoped polycrystalline silicon layer, and / or may be configured as an epitaxial layer.

[0035] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked to be disposed on the upper surface of the first region R1 of the substrate 101. The first horizontal conductive layer 102 may not extend to the second region R2 and the third region R3 of the substrate 101, while the second horizontal conductive layer 104 may extend to the second region R2 and the third region R3.

[0036] The first horizontal conductive layer 102 can be used as part of the common source line of the semiconductor device 100. For example, the first horizontal conductive layer 102 can be used together with the substrate 101 as a common source line. Figure 4As shown, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 around the channel layer 140.

[0037] like Figure 7 As shown, the second horizontal conductive layer 104 may contact the substrate 101 in some areas where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not provided. The second horizontal conductive layer 104 may be bent to extend above the substrate 101 while covering the end of the first horizontal conductive layer 102 or the horizontal insulating layer 110.

[0038] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise semiconductor materials. For example, both the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 may be a doped layer, and the second horizontal conductive layer 104 may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102. However, in some example embodiments, the second horizontal conductive layer 104 may be replaced by an insulating layer.

[0039] A horizontal insulating layer 110 may be disposed on the substrate 101 parallel to the first horizontal conductive layer 102 in at least a portion of the second region R2 and the third region R3. For example... Figure 5 and Figure 6 As shown, the horizontal insulating layer 110 may include a first insulating layer to a third insulating layer 111, 112, and 113 sequentially stacked on a second region R2 and a third region R3 of the second substrate 101. The horizontal insulating layer 110 may be a layer remaining after a portion of the horizontal insulating layer 110 has been replaced by a first horizontal conductive layer 102 during the process of manufacturing the semiconductor device 100.

[0040] The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may include different insulating materials than the second horizontal insulating layer 112. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may include the same material. For example, the first horizontal insulating layer 111 and the third horizontal insulating layer 113 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the first sacrificial insulating layer 118.

[0041] The first stacked structure ST1 may include a first interlayer insulating layer 120 and a first gate electrode 130 alternately stacked on the substrate 101. The second stacked structure ST2 may include a second interlayer insulating layer 220 and a second gate electrode 230 alternately stacked on the first stacked structure ST1.

[0042] Gate electrodes 130 and 230 may include a lower gate electrode 130L constituting the gate of a ground select transistor, memory gate electrodes 130M and 230M constituting a plurality of memory cells, and an upper gate electrode 230U constituting the gate of a string select transistor. The number of memory gate electrodes 130M and 230M constituting memory cells may be determined according to the capacity of the semiconductor device 100. According to embodiments, the number of upper gate electrodes 230U and the number of lower gate electrodes 130L may each be one to four or more. In addition, the upper gate electrodes 230U and the lower gate electrodes 130L may have the same structure as the memory gate electrodes 130M and 230M, or they may have a different structure than the memory gate electrodes 130M and 230M. In some example embodiments, the first gate electrode 130 and the second gate electrode 230 may also include gate electrodes 130 and 230 disposed above the upper gate electrode 230U and / or below the lower gate electrode 130L, and constituting an erase transistor used in an erase operation using gate-induced drain leakage (GIDL). Some of the gate electrodes 130 and 230 that are adjacent to the upper gate electrode 230U or the lower gate electrode 130L (e.g., memory gate electrodes 130M and 230M) may be dummy gate electrodes.

[0043] Gate electrodes 130 and 230 may be vertically stacked to be spaced apart from each other, and may extend to different lengths in at least one region to form a stepped structure with a stepped shape. For example... Figure 7 As shown, the second gate electrode 230 may be stacked in the first region R1 to be spaced apart from each other, and may extend in a stepped manner in the X direction in the second region R2 and the third region R3. For example, the second gate electrode 230 may form a stepped structure between the second gate electrodes 230 in the X direction. In a region not shown, the first gate electrode 130 may extend in a stepped manner in the X direction in the third region R3. In some example embodiments, a predetermined number (e.g., two to five) of the gate electrodes 130 and 230 may constitute a single gate group to form a stepped structure between the gate groups in the X direction. In this case, the gate electrodes 130 and 230 constituting the single gate group may also be configured to have a stepped structure in the Y direction. Due to the stepped structure, the gate electrodes 130 and 230 may have a stepped shape in which the lower gate electrodes 130 and 230 extend further than the upper gate electrodes 130 and 230, and may provide ends exposed above the interlayer insulating layers 120 and 220. Gate electrodes 130 and 230 may be connected at their ends to contact plug 280. Therefore, the first gate electrode 130 and the second gate electrode 230 may be connected to the upper interconnect structure. In some example embodiments, gate electrodes 130 and 230 may each have increased thickness at their ends.

[0044] The first gate electrode 130 and the second gate electrode 230 may comprise a metallic material, such as tungsten (W). According to some example embodiments, gate electrodes 130 and 230 may comprise polycrystalline silicon and / or metal silicide materials. In some example embodiments, gate electrodes 130 and 230 may also comprise a diffusion barrier. For example, the diffusion barrier may comprise tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. The material composition, thickness, and / or number of the first gate electrode 130 may be the same as or different from the material composition, thickness, and / or number of the second gate electrode 230.

[0045] Interlayer insulating layers 120 and 220 may include a first interlayer insulating layer 120 constituting a first stacked structure ST1 and a second interlayer insulating layer 220 constituting a second stacked structure ST2. The first interlayer insulating layer 120 may be disposed between the first gate electrodes 130, and the second interlayer insulating layer 220 may be disposed between the second gate electrodes 230. Similar to the gate electrodes 130 and 230, the interlayer insulating layers 120 and 220 may be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 and may be configured to extend in direction X. Each of the interlayer insulating layers 120 and 220 may include an insulating material such as silicon oxide and / or silicon nitride. An intermediate insulating layer 125 with a relatively large thickness may be disposed at the uppermost part of the first stacked structure ST1. The material composition, thickness, and / or number of the interlayer insulating layers 120 may be the same as or different from the material composition, thickness, and / or number of the interlayer insulating layers 220.

[0046] The main separation region MS1, the first auxiliary separation region MS2a, and the second auxiliary separation region MS2b can be configured to extend in the X direction through the first stacked structure ST1 and the second stacked structure ST2. The main separation region MS1 ​​and the auxiliary separation regions MS2a and MS2b can be configured to be parallel to each other. The main separation region MS1, the first auxiliary separation region MS2a, and the second auxiliary separation region MS2b can penetrate the entire gate electrode 130 and 230 stacked on the substrate 101 to connect to the substrate 101. The main separation region MS1 ​​extends as a single region in the X direction, and the first auxiliary separation region MS2a and the second auxiliary separation region MS2b can extend intermittently between a pair of main separation regions MS1 or can be disposed only in specific regions.

[0047] The first auxiliary separation region MS2a may extend in the X direction within the first region R1 and the second region R2, and the second auxiliary separation region MS2b may extend in the X direction within the third region R3. In some example embodiments, the first auxiliary separation region MS2a may extend in the X direction within the region where the memory cell is disposed and within the region where the end of the upper gate electrode 230U constituting or corresponding to the string select transistor is disposed.

[0048] The first auxiliary separation region MS2a and the second auxiliary separation region MS2b can be set to be spaced apart from each other on the boundary between the second region R2 and the third region R3. The first auxiliary separation region MS2a and the second auxiliary separation region MS2b can be set alternately in the X direction. The first auxiliary separation region MS2a and the second auxiliary separation region MS2b can be set to be offset relative to each other in the Y direction.

[0049] like Figure 2 As shown, a first auxiliary separation region MS2a may be arranged between a pair of main separation regions MS1 in the Y direction at a first spacing P1, and a second auxiliary separation region MS2b may be arranged between a pair of main separation regions MS1 in the Y direction at a second spacing P2, which is different in size from the first spacing P1. In the specification, the term "spacing" refers to length, such as the minimum length from the center of one component to the center of another component. In some example embodiments, the second auxiliary separation region MS2b may be arranged between a pair of main separation regions MS1 at a second spacing P2 smaller than the first spacing P1. The distance P2 from the center of the main separation region MS1 ​​to the center of the second auxiliary separation region MS2b may be greater than the distance P3 from the center of the main separation region MS1 ​​to the center of the upper separation region SS. The distance P2 between the centers of the second auxiliary separation regions MS2b may be greater than the distance P3 from the center of the main separation region MS1 ​​to the center of the upper separation region SS. The distance P2 between the centers of the second auxiliary separation regions MS2b may be greater than the distance from the center of the first auxiliary separation region MS2a to the center of the upper separation region SS. In some example embodiments, the number and / or arrangement of the first auxiliary separation region MS2a and the second auxiliary separation region MS2b are not limited to... Figure 1 As shown, the ratio of the first spacing P1 to the second spacing P2 can be changed in various ways. Therefore, the relative sizes of the first spacing P1 and the second spacing P2 can be changed in various ways. Alternatively or alternatively, the ratio of the first spacing P1 to the second spacing P2 can be a rational ratio, such as one of 1 / 2, 1 / 3 or 2 / 3, 1 / 4 or 3 / 4, 1 / 5, 2 / 5, 3 / 5, 4 / 5, etc.; however, the example embodiment is not limited to this, and the ratio of the first spacing P1 to the second spacing P2 can be an irrational number.

[0050] like Figures 4 to 6As shown, an insulating layer 185 may be disposed in the main separation region MS1 ​​and the first auxiliary separation region MS2a and the second auxiliary separation region MS2b. The insulating layer 185 may have a high aspect ratio, for example, a high ratio between its height in direction Z and its diameter or length in one or both directions X and Y, resulting in a tapered width (e.g., decreasing in the direction toward the substrate 101) shape. However, the exemplary embodiments are not limited thereto; the insulating layer 185 may have a side surface perpendicular to the upper surface of the substrate 101. In some exemplary embodiments, a conductive layer may be further disposed in the insulating layer 185 in the main separation region MS1 ​​and the first separation region MS2a and the second separation region MS2b. Therefore, the conductive layer can serve as a common source line of the semiconductor device 100 and / or a contact plug connected to the common source line.

[0051] like Figure 1 and Figure 2 As shown, the upper separation region SS can extend in the X direction within the first region R1 and the second region R2, between the main separation region MS1 ​​and the second auxiliary separation region MS2a, and between the second auxiliary separation regions MS2a. The upper separation region SS can be configured to penetrate a portion of the second gate electrode 230, including the uppermost gate electrode 230U, among the gate electrodes 130 and 230. Figure 4 and Figure 5 As shown, the upper separation region SS can separate a total of, for example, four second gate electrodes 230 (including the upper gate electrode 230U) from each other in the Y direction. However, in some example embodiments, the number of second gate electrodes 230 separated by the upper separation region SS can be varied in various ways. The upper gate electrodes 230U separated by the upper separation region SS can form different string select lines. The upper separation region SS may include an insulating material. The insulating material may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0052] Each of the channel structures CH may include a first channel structure CH1 penetrating the first stacked structure ST1 and a second channel structure CH2 penetrating the second stacked structure ST2. Each channel structure CH may constitute or correspond to a single memory cell string and may be configured to form rows and columns on the first region R1 while being spaced apart from each other. Channel structures CH1 may be disposed between main separation regions MS1 in the first region R1. Channel structures CH may be disposed between the main separation region MS1 ​​and the first auxiliary separation region MS2a in the first region R1, and between the first auxiliary separation regions MS2a. Channel structures CH may be configured to form a grid pattern such as a rectangle (e.g., a square grid pattern) and / or may be disposed in a zigzag pattern (e.g., a hexagonal pattern) in one direction. Each or either of the first and second channel structures CH may have a columnar shape and may taper, for example, may have sloping side surfaces that narrow in the direction toward the substrate 101 according to the aspect ratio. Some of the channel structures CH disposed in the first region R1 that are adjacent to the second region R2 may be dummy channels. The channel structure CH overlapping the upper separation region SS can also be a dummy channel. In this case, the dummy channel may have the same (or similar) structure as the channel structure CH, but may not perform any actual function in the semiconductor device 100. The dummy channel structure CH may float during the operation of the semiconductor device 100; however, the example embodiment is not limited thereto.

[0053] like Figure 4 As shown in the enlarged view, a channel layer 140 may be disposed in a channel structure CH. In the channel structure CH, the channel layer 140 may be formed annularly to fill the insulating layer 150 around the channel. However, according to some example embodiments, the channel layer 140 may have a cylindrical shape and / or a prism shape without a channel-filling insulating layer 150. The channel layer 140 may be connected at its lower portion to a first horizontal conductive layer 102. The channel layer 140 may comprise a semiconductor material such as doped or undoped polycrystalline silicon and / or doped or undoped monocrystalline silicon.

[0054] The channel structure CH can be configured such that the upper first channel structure CH1 and the lower upper second channel structure CH2 are connected to each other. (Described below) Figure 15A and Figure 16AIn the process steps described herein, the first channel structure CH1 and the second channel structure CH2 have channel holes formed by performing etching processes (e.g., dry etching processes) in different process steps, resulting in a width difference between the upper end of the first channel structure CH1 and the lower end of the second channel structure CH2. Due to this width difference, the channel structure CH may have a curved portion or curved profile in the region connecting the upper end of the first channel structure CH1 and the lower end of the second channel structure CH2. The channel layer 140, the gate dielectric layer 145, and the channel filling insulating layer 150 may be in a state where they are connected to each other between the first channel structure CH1 and the second channel structure CH2.

[0055] The channel pad 255 may be disposed only on the upper end of the second channel structure CH2. However, in some example embodiments, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 255. In this case, the channel pad 255 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2. The channel pad 255 may be configured to cover the upper surface of the channel-filling insulating layer 150 and be electrically connected to the channel layer 140. The channel pad 255 may comprise, for example, doped or undoped polysilicon.

[0056] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not shown in detail, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially stacked from the channel layer 140. The tunneling layer can tunnel charge to the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In some example embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrodes 130 and 230.

[0057] In some example embodiments, the number of stacked structures and / or the number of channel structures stacked in the Z direction can be varied in various ways.

[0058] The dummy structure DS can penetrate the first stacked structure ST1 and the second stacked structure ST2. The dummy structure DS can be disposed in the third region R3 between the main separation regions MS1. The dummy structure DS can also be disposed in the third region R3 between the main separation region MS1 ​​and the second auxiliary separation region MS2b, and between the second auxiliary separation region MS2b. In some example embodiments, the dummy structure DS can be disposed in the second region R2 between the main separation region MS1 ​​and the first auxiliary separation region MS2a, and between the first auxiliary separation region MS2a.

[0059] Reference Figure 3 The shape of the dummy structure DS can be elliptical; however, the example embodiments are not limited to this. Figure 3 As shown, the width of each dummy structure DS can be greater than the width L1 of each channel structure CH. The width of each dummy structure DS can be defined as the average of the length L3 of the major axis and the length L2 of the minor axis. In some example embodiments, such as Figure 2 As shown, when viewed from above, each of the dummy structures DS may have a shape different from that of each of the channel structures CH. In some example embodiments, the width of each of the dummy structures DS may be about two or more times the width L1 of each of the channel structures CH. In some example embodiments, the length L2 of the minor axis and the length L3 of the major axis of each of the dummy structures DS may be greater than the width L1 of each of the channel structures CH. In some example embodiments, the length L2 of the minor axis and the length L3 of the major axis of each of the dummy structures DS may be about two or more times the width of each of the channel structures CH. The dummy structures DS may be arranged such that the orientation of the minor axis and / or the major axis varies, and may not be aligned with the X or Y direction. In the second region R2 and the third region R3, at least some of the dummy structures DS may include four dummy structures DS adjacent to one of the contact plugs 280 connected to the ends of the gate electrodes 130 and 230. As described above, the first auxiliary separation region MS2a can be arranged at a first spacing P1, and the second auxiliary separation region MS2b can be arranged at a second spacing P2, which is different in size from the first spacing P1. Therefore, each of the dummy structures DS provided in the third region R3 can have a relatively large size. When each of the dummy structures DS is formed to have a relatively large size, even below... Figures 17A to 17C During the etching process described in the paper to form the dummy structure DS, the dummy structure DS can also be stably formed as the height of each of the stacked structures ST1 and ST2 increases.

[0060] like Figure 3 As shown, the distance D2 between dummy structures DS can be greater than the distance D3 between channel structures CH. Since the third region R3 includes a larger area than each of the first region R1 and the second region R2 in which the same number of dummy structures DS can be formed, the dummy structures DS can be formed stably or more stably with respect to adjacent contact plugs 280 in the third region R3.

[0061] Since the dummy structure DS is formed by performing an etching process such as dry etching, in order to... Figures 17A to 17CThe process described in the diagram simultaneously penetrates the first stacked structure ST1 and the second stacked structure ST2, so each of the dummy structures DS can have a tapered profile; for example, the width of each dummy structure DS can continuously decrease from the upper part of the second stacked structure ST2 to the lower part of the first stacked structure ST1. The dummy structure DS can have a continuous width at the boundary where the first stacked structure ST1 and the second stacked structure ST2 connect to each other. For example, unlike the channel structure CH, the dummy structure DS may not include curved portions.

[0062] The upper surface of the dummy structure DS can be positioned at a higher level than the upper surface of the channel structure CH. For example... Figure 4 As shown, the upper surface of the channel structure CH can be coplanar with the first upper insulating layer 290. Figure 5 As shown, the upper surface of the dummy structure DS can be coplanar with the upper surface of the second upper insulating layer 292 disposed on the upper insulating layer 290.

[0063] The dummy structure DS may include an insulating material. The insulating material may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. When the dummy structure DS, instead of the channel structure CH, is disposed in the second region R2 and the third region R3 corresponding to the stepped region, the electrical reliability of the contact plug 280 connected to the stepped region can be improved because the dummy structure DS can be formed of an insulating material.

[0064] The lower separation regions GS1 and GS2 may be located at the same level as the lowest ground selected gate electrode among the gate electrodes 130 and 230. The lower separation regions GS1 and GS2 may penetrate at least one of the first gate electrodes 130, including the lowest gate electrode, between the main separation regions MS1.

[0065] The lower separation region GS1 can be configured to connect adjacent first auxiliary separation regions MS2a and second auxiliary separation regions MS2b on the boundary between the second region R2 and the third region R3, or in a region adjacent to this boundary. Therefore, the ground selection gate electrode can be connected between some of the first auxiliary separation regions MS2a and some of the second auxiliary separation regions MS2b, but it can be divided into three sub-gate electrodes by the lower separation region GS1 on the boundary between the second region R2 and the third region R3. Each of the first lower separation regions GS1 may include a first portion GS1a disposed in a direction parallel to the first auxiliary separation region MS2a and a second portion GS1b disposed in a direction perpendicular to the second auxiliary separation region MS2b. The first portion GS1a and the second portion GS1b of the first lower separation region GS1 may be disposed perpendicular to each other and may extend in different directions. In some example embodiments, the two first lower separation regions GS1 disposed between the main separation regions MS1 may be symmetrical in the direction Y about the extension line of the upper separation region SS disposed between them. In some example embodiments, the two first lower separation regions GS1 may be centrally symmetrical in the direction Y about a pair of main separation regions MS1. In some example embodiments, a second portion GS1b of the first lower separation region GS1 may be arranged toward the adjacent main separation region MS1 ​​of a pair of main separation regions MS1 and perpendicular to the first portion GS1a.

[0066] In the third region R3, the second lower separation region GS2 can be configured as a region adjacent to the second auxiliary separation regions MS2b, which are spaced apart from each other in the X direction. Unlike the first lower separation region GS1, when viewed in a plan view (e.g., from above), the second lower separation region GS2 may only have a portion disposed in a direction parallel to the second auxiliary separation region MS2b.

[0067] The lower separation regions GS1 and GS2 may be formed of, for example, silicon oxide, and may comprise the same material as the interlayer insulating layer 120. In some example embodiments, the number and / or arrangement of the lower separation regions GS1 and GS2 are not limited to... Figure 1 As shown, and can be changed in various ways.

[0068] The first upper insulating layer 290, the second upper insulating layer 292, and the third upper insulating layer 294 may be sequentially stacked on the second stacked structure ST2. The first upper insulating layer 290 may be configured to cover the substrate 101 and the gate electrode 130 and the peripheral insulating layer 390 on the substrate 101. The first to third upper insulating layers 290, 292, and 294 may be formed of insulating material and may be formed to have the same (or alternatively, different) thickness and / or material composition as each other. In some example embodiments, each of the first to third upper insulating layers 290, 292, and 294 may include multiple insulating layers.

[0069] In the first region R1, the channel contact plug 270 can penetrate the second upper insulating layer 292 and the third upper insulating layer 294 and can be electrically connected to the channel structure CH. A bit line 275 can be disposed on the channel contact plug 270 for electrical connection to the channel contact plug 270. Each of the channel contact plug 270 and the bit line 275 may include a conductive material (e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), etc.) and may also include a diffusion barrier layer.

[0070] The contact plug 280 may be formed perpendicularly in the Z direction to have a cylindrical shape and may be electrically connected to the first gate electrode 130 and the second gate electrode 230. The contact plug 280 may include a conductive material (e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), etc.) and may each include a diffusion barrier layer.

[0071] exist Figures 8 to 14 In, with Figures 1 to 7 The same components shown are referred to by the same labels, and their descriptions will be omitted.

[0072] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0073] Reference Figure 8 In semiconductor device 100a, the upper surface of the channel structure CH may have substantially the same level as the upper surface of the dummy structure DS. The upper surface of the channel structure CH, the upper surface of the dummy structure DS, and the upper surface of the first upper insulating layer 290 may be coplanar with each other. Unlike the etching process performed after the formation of the channel structure CH, the etching process of the dummy structure DS can be performed after the formation of the channel structure CH. Figures 16A to 16C The channel structure CH simultaneously forms a virtual structure DS. Figures 17A to 17C The process steps for forming the dummy structure DS described in the text are similar. For example, the etching process for the dummy structure DS can be performed simultaneously during the etching process for the second channel structure CH2 in the channel structure CH.

[0074] Figure 9 This is a schematic plan view of a semiconductor device according to some example embodiments. Figure 9 Showing with Figure 1 The region corresponding to region "A".

[0075] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0076] Reference Figure 9 and Figure 10In semiconductor device 100b, the dummy structure DS may be disposed only between the main separation region MS1 ​​and the second auxiliary separation region MS2b in the third region R3, and between the second auxiliary separation region MS2b. The dummy structure DS may be disposed in the third region R3, which has an area larger than the second region, and the dummy channel structure DCH may be disposed in the second region R2. The dummy structure DS may be disposed between the main separation region MS1 ​​and the second auxiliary separation region MS2b, and between the second auxiliary separation region MS2b, and the dummy channel structure DCH may be disposed between the main separation region MS1 ​​and the first auxiliary separation region MS2a in the second region R2, and between the first auxiliary separation region MS2a in the second region R2. Alternatively or additionally, the channel structure CH may be disposed between the main separation region MS1 ​​and the first auxiliary separation region MS2a in the first region R1, and between the first auxiliary separation region MS2a in the first region R1. The dummy channel structure DCH may have the same (or similar) structure as the channel structure CH, but may not perform any actual function in the semiconductor device 100b, and / or may float during operation of the semiconductor device 100b. In some example embodiments, some of the channel structures CH adjacent to the second region R2 may be dummy channel structures DCH. The dummy channel structures DCH may not be electrically connected to each other via channel contact plugs 270 and bit lines 275. The contact plugs 280 of the second region R2 may be located at the other end of the gate electrodes 130 and 230 in the region not shown.

[0077] Figure 11 This is a schematic plan view of a semiconductor device according to some example embodiments. Figure 11 Showing with Figure 1 The region corresponding to region "A".

[0078] Figure 12 This is a schematic cross-sectional view of a semiconductor device according to some example embodiments.

[0079] Reference Figure 11 and Figure 12In semiconductor device 100c, a dummy structure DS can be disposed on the entire stepped region where the ends of gate electrodes 130 and 230 are formed, and on at least a portion of the region where memory cells are disposed. The dummy structure DS can be disposed in the second region R2 and the third region R3, the channel structure CH can be disposed in the first region R1, and the dummy structure DS can be disposed in at least a portion of the first region R1 adjacent to the second region R2. In addition to the second region R2 and the third region R3 where contact plugs 280 are disposed, the dummy structure DS can also be disposed in at least a portion of the first region R1 where contact plugs 280 are not disposed. In the first region R1, the channel structure CH can be disposed between the main separation region MS1 ​​and the first auxiliary separation region MS2a, and between the first auxiliary separation regions MS2a. The dummy structure DS can be disposed in a portion of the first region R1 adjacent to the second region R2, between the main separation region MS1 ​​and the first auxiliary separation region MS2a in the second region R2, and between the second auxiliary separation region MS2b in the third region R3.

[0080] Figure 13 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0081] Reference Figure 13 In the semiconductor device 100d, the second auxiliary separation region MS2b may be arranged with two or more different spacings. The second auxiliary separation region MS2b may be arranged, for example, with a second spacing P2 and a fourth spacing P4 that are different from each other. The second auxiliary separation region MS2b may be arranged asymmetrically between a pair of main separation regions MS1. In some example embodiments, at least one of the second spacing P2 and the fourth spacing P4 may be different from the first spacing P1. In some example embodiments, the fourth spacing P4 may be twice the second spacing P2; however, the example embodiments are not limited thereto. In some example embodiments, the distances P2 and P4 between the centers of the second auxiliary separation regions MS2b may each be greater than the distance P3 from the center of the main separation region MS1 ​​to the center of the upper separation region SS and the distance from the center of the upper separation region SS to the center of the first auxiliary separation region MS2a.

[0082] Figure 14 This is a schematic plan view of a semiconductor device according to some example embodiments.

[0083] Reference Figure 14In semiconductor device 100e, the second auxiliary separation region MS2b may be arranged at two or more different pitches. The second auxiliary separation region MS2b may be arranged, for example, at a fifth pitch P5 and a sixth pitch P6. The second auxiliary separation region MS2b may be arranged symmetrically between a pair of main separation regions MS1. In some example embodiments, at least one of the fifth pitch P5 and the sixth pitch P6 may be different from the first pitch P1. In some example embodiments, the fifth pitch P5 may be twice the sixth pitch P6; however, the example embodiments are not limited thereto. In some example embodiments, the distances P5 and P6 between the centers of the second auxiliary separation regions MS2b may each be greater than the distance P3 from the center of the main separation region MS1 ​​to the center of the upper separation region SS and the distance from the center of the separation region SS to the center of the first auxiliary separation region MS2a.

[0084] The second portion GS1b of the first lower separation region GS1 may be configured to be perpendicular to the first portion GS1a of the first lower separation region GS1 and opposite to the adjacent one of the pair of main separation regions MS1. In some example embodiments, the two first lower separation regions GS1 disposed between the pair of main separation regions MS1 may be asymmetrical about the center of the pair of main separation regions MS1. In some example embodiments, the two first lower separation regions GS1 disposed between the pair of main separation regions MS1 may be alternately disposed in the Y direction. In some example embodiments, the two first lower separation regions GS1 disposed between the pair of main separation regions MS1 may have first portions GS1a of different lengths.

[0085] Figures 15A to 18C This is a schematic cross-sectional view illustrating a method of manufacturing / processing a semiconductor device according to some example embodiments. Figure 15A , Figure 16A , Figure 17A and Figure 18A Each of them along Figure 2 The cross-section taken by line I-I' illustrates the manufacturing method. Figure 15B , Figure 16B , Figure 17B and Figure 18B Each of them along Figure 2 The cross-section taken by line II-II' illustrates the manufacturing / processing method, each of Figures 15c, 16c, 17c, and 18c respectively along... Figure 2 The cross-section taken by line Ⅲ-Ⅲ' shows the manufacturing / processing method.

[0086] Refer to 15A to Figure 15CA peripheral circuit structure PERI, including circuit elements 320 and a lower interconnect structure, can be formed on a base substrate 301. A substrate 101, on which a memory cell structure CELL, a horizontal insulating layer 110, and a second horizontal conductive layer 104 are disposed, can be formed. Then, a first sacrificial insulating layer 118 and a first interlayer insulating layer 120 can be alternately stacked to form a first stacked structure ST1. A portion of the first stacked structure ST1, including the first sacrificial insulating layer 118 and the first interlayer insulating layer 120, can be removed, and then a through-sacrificial layer 119 can be formed.

[0087] A device isolation layer 310 may be formed in a base substrate 301, and a circuit gate dielectric layer 322 and a circuit gate electrode 325 may be sequentially formed on the base substrate 301. The device isolation layer 310 may be formed by, for example, a shallow trench isolation (STI) process, and may be formed using deposition processes such as high-density plasma (HDP) deposition and / or spin-on glass (SOG) processes. The circuit gate dielectric layer 322 and the circuit gate electrode 325 may be formed using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD). The circuit gate dielectric layer 322 may be formed of silicon oxide, and the circuit gate electrode 325 may be formed of at least one of doped or undoped polysilicon and metal silicides, but the exemplary embodiments are not limited thereto. A spacer layer 324 and a source / drain region 305 may be formed on the two sidewalls of the circuit gate dielectric layer 322 and the circuit gate electrode 325. According to an embodiment, the spacer layer 324 may comprise multiple layers. Then, doping processes such as beamline ion implantation and / or plasma-assisted doping (PLAD) can be performed to form the source / drain region 305.

[0088] In the underlying interconnect structure, circuit contact plugs 370 can be formed by forming a portion of the peripheral insulating layer 390, etching the portion to be removed, and filling the removed portion with conductive material. Circuit interconnects 380 can be formed, for example, by depositing conductive material and patterning the deposited conductive material. The deposition of conductive material can be performed using at least one of CVD, physical vapor deposition (PVD), and electrochemical deposition processes.

[0089] The peripheral insulating layer 390 may include multiple insulating layers. During various process steps in forming the lower interconnect structure, a portion of the peripheral insulating layer 390 may be formed, and another portion of the peripheral insulating layer 390 may be formed on the uppermost circuit interconnect 380. Therefore, the peripheral insulating layer 390 can ultimately be formed to cover the circuit element 320 and the lower interconnect structure.

[0090] Then, a substrate 101 can be formed on the peripheral insulating layer 390. The substrate 101 can be formed of, for example, polysilicon, and can be formed by a CVD process. The polysilicon forming the substrate 101 may include impurities such as at least one of boron, phosphorus, arsenic, and carbon.

[0091] The first to third horizontal insulating layers 111, 112, and 113 constituting the horizontal insulating layer 110 may be sequentially stacked on the substrate 101. The horizontal insulating layer 110 may be or include multiple layers, some of which are used in subsequent processes. Figure 4 The first horizontal conductive layer 102 is replaced. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may comprise or be composed of a material different from or composed of the material of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 and the third horizontal insulating layer 113 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the first sacrificial insulating layer 118. The horizontal insulating layer 110 may be removed in some areas by a patterning process.

[0092] The second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110 and may contact the second substrate 101 in the area where the horizontal insulating layer 110 is removed. Therefore, the second horizontal conductive layer 104 may be bent along the end of the horizontal insulating layer 110 and may extend upward toward the second substrate 101 while covering the end.

[0093] The first sacrificial insulating layer 118 can be multiple layers, some of which are used in subsequent processes with the first gate electrode (see [link]). Figures 4 to 6 The first sacrificial insulating layer 118 may comprise or be composed of a material different from or consisting of the material of the first interlayer insulating layer 120, and may be formed of a material that has etch selectivity relative to the interlayer insulating layer 120 under specific etch conditions. For example, the first interlayer insulating layer 120 may be formed or composed of at least one of silicon oxide and silicon nitride, and the first sacrificial insulating layer 118 may be formed of a material different from the material of the first interlayer insulating layer 120, said material being selected from or consisting of the group consisting of silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the thickness and number of the first interlayer insulating layer 120 and the first sacrificial insulating layer 118 may be varied in various ways other than those shown.

[0094] It can be respectively in the first region R1 of substrate 101 with Figure 4A through-sacrificial layer 119 is formed at the location corresponding to the first channel structure CH1 to penetrate the first stacked structure ST1. First, a via corresponding to the first channel structure CH1 can be formed. Due to the height of the first stacked structure ST1, the via can taper, for example, the sidewalls of the via may not be perpendicular to the upper surface of the substrate 101. In some example embodiments, the via can be formed to cause a portion of the substrate 101 to be recessed. The through-sacrificial layer 119 can be formed by filling the via with an insulating material.

[0095] Reference Figures 16A to 16C A second sacrificial insulating layer 218 and a second interlayer insulating layer 220 may be alternately stacked on the first stacked structure ST1 to form a second stacked structure ST2. Then, a channel structure CH may be formed in the upper separation region SS of the stacked structure ST2 that penetrates the first region R1 and the second region R2, as well as in the first region R1.

[0096] Similar to the first laminated structure ST1, the second laminated structure ST2 can be formed by alternately laminating the interlayer insulation layer 220 and the second sacrificial insulation layer 218. A first upper insulation layer 290 can be formed to cover the upper portion of the laminated structures ST1 and ST2 of the sacrificial insulation layers 118 and 218 and the interlayer insulation layers 120 and 220.

[0097] The second sacrificial insulating layer 218 can be replaced with a second gate electrode 230 in subsequent processes. The second sacrificial insulating layer 218 can be formed, include, or consist of a material different from that of the second interlayer insulating layer 220. For example, the second interlayer insulating layer 220 can be formed, include, or consist of at least one of silicon oxide and silicon nitride, and the second sacrificial insulating layer 218 can be formed, include, or consist of a material different from that of the second interlayer insulating layer 220, selected from the group consisting of silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the thickness of the second interlayer insulating layer 220 may not all be uniform.

[0098] The upper separation region SS can be formed by removing some of the second sacrificial insulating layer 218 and interlayer insulating layer 220 in the first region R1 and the second region R2. The upper separation region SS can be formed by exposing the area to be formed of the upper separation region SS using an additional mask layer, removing a predetermined number of the second sacrificial insulating layer 218 and interlayer insulating layer 220 from the top, and depositing insulating material. The upper separation region SS can be formed in the Z direction. Figure 4 It extends below the region of the upper gate electrode 230U.

[0099] Similar to the case of the first stacked structure ST1, an etching process can be performed in the first region R1 at the position corresponding to the second channel structure CH2, thereby forming a via to penetrate the second stacked structure ST2. Due to the height of the second stacked structure ST2, the sidewall of the via penetrating the second stacked structure ST2 may not be perpendicular to the upper surface of the first stacked structure ST1. Therefore, the width of the via penetrating the upper surface of the sacrificial layer 119 and the lower part of the via in the second stacked structure ST1 may be discontinuous. The channel structure CH can be formed by removing the through sacrificial layer 119 of the first stacked structure ST1 to form a channel via extending from the first stacked structure ST1 to the second stacked structure ST2 and filling the channel via. Figures 15A to 16C As described, since the channel structure CH is formed by two etching processes performed respectively in the first stacked structure ST1 and the second stacked structure ST2, the channel structure CH can have a curved portion at the boundary between the first stacked structure ST1 and the second stacked structure ST2. Furthermore, since the channel structure CH is formed only in the first region R1 and not in the second region R2 and the third region R3 for stable formation, the electrical reliability of the semiconductor can be improved.

[0100] Reference Figures 17A to 17C A second upper insulating layer 292 can be stacked on the first upper insulating layer 290, and a dummy structure DS can be formed in the second region R2 and the third region R3.

[0101] The dummy structure DS can be formed by forming holes in the second region R2 and the third region R3 to simultaneously penetrate the first upper insulating layer 290 and the second upper insulating layer 292, as well as the first laminated structure ST1 and the second laminated structure ST2, and filling the holes with insulating material. The dummy structure DS can be formed to have a wider width than the channel structure CH, and the dummy structure DS can be configured such that the distance between the dummy structures DS is greater than the distance between the channel structures CH. The dummy structure DS can simultaneously penetrate the first laminated structure ST1 and the second laminated structure ST2, and can have a width that continuously decreases from the upper end of the dummy structure DS to the lower end of the dummy structure.

[0102] Now refer to Figures 18A to 18C A third upper insulating layer 293 can be stacked on the second upper insulating layer 292, and first to third openings OP1, OP2 and OP3 can be formed to penetrate the stacked structure. The first to third horizontal insulating layers 111, 112 and 113 can be removed in the first region R1 through the first to third openings OP1, OP2 and OP3, and then a first horizontal conductive layer 102 can be formed. The sacrificial insulating layers 118 and 218 can be replaced with conductive material to form gate electrodes 130 and 230.

[0103] It can be done in conjunction with Figures 4 to 6In the region corresponding to the main separation region MS1, an etching process is performed on the first to third upper insulating layers 290, 292, and 294 and the stacked structures ST1 and ST2 to form a first opening OP1 extending in the X direction in the first to third regions R1, R2, and R3. This can be achieved by etching in conjunction with... Figure 4 and Figure 5 In the region corresponding to the first auxiliary separation region MS2a, an etching process is performed on the first upper insulating layer to the third upper insulating layer 290, 292 and 294 and the stacked structures ST1 and ST2 to form a second opening OP2 extending in the X direction in the first region R1 and the second region R2. This can be achieved by etching in conjunction with... Figure 6 In the region corresponding to the second auxiliary separation region MS2b, an etching process is performed on the first upper insulating layer to the third upper insulating layer 290, 292 and 294 and the stacked structure ST1 and ST2 to form a third opening OP3 extending in the direction X in the third region R3.

[0104] The first opening to the third opening OP1, OP2 and OP3 can be formed to have substantially the same width, and can be formed such that the distance from the center of the first opening OP1 to the center of the second opening OP2 in the Y direction is greater than the distance from the center of the first opening OP1 to the center of the third opening OP3 in the Y direction.

[0105] The second horizontal insulating layer 112 can be exposed by performing a back etching process while forming additional sacrificial spacer layers in openings OP1, OP2, and OP3. The second horizontal insulating layer 112 can be selectively removed from the exposed area, and then the first horizontal insulating layer 111 and the third horizontal insulating layer 113 disposed above and below the exposed area can be removed.

[0106] The first to third horizontal insulating layers 111, 112, and 113 can be removed by, for example, an isotropic process (e.g., a wet etching process including chemicals such as hydrogen fluoride and / or nitric acid and / or phosphoric acid). During the process of removing the first horizontal insulating layer 111 and the third horizontal insulating layer 113, a portion of the gate dielectric layer 145 exposed in the region where the second horizontal insulating layer 112 is removed can also be removed. A conductive material can be deposited on the region where the first to third horizontal insulating layers 111, 112, and 113 are removed to form a first horizontal conductive layer 102, and then the sacrificial spacer layer can be removed in the opening.

[0107] The sacrificial insulating layers 118 and 218 can be selectively removed relative to the interlayer insulating layers 120 and 220 and the second horizontal conductive layer 104 using a wet etching process. Therefore, multiple tunnel portions can be formed between the interlayer insulating layers 120 and 220. The conductive material forming the gate electrodes 130 and 230 can fill the tunnel portions. The conductive material may include metals, doped or undoped polysilicon, and / or metal silicide materials.

[0108] return Figures 4 to 6 An insulating layer 185 can be formed in the openings OP1, OP2 and OP3 to form the main separation region MS1, the first auxiliary separation region MS2a and the second auxiliary separation region MS2b.

[0109] Figure 19 It is a schematic diagram of an electronic system including a semiconductor device according to an example embodiment.

[0110] Reference Figure 19 According to some example embodiments, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be or include: a storage device including one or more semiconductor devices 1100; or an electronic device including a storage device. For example, the electronic system 1000 may be or include: a solid-state drive (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0111] Semiconductor device 1100 may be a non-volatile memory device, such as referenced in [reference]. Figures 1 to 14 The NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100f and a second structure 1100s on the first structure 1100f. In some example embodiments, the first structure 1100f may be disposed adjacent to the second structure 1100s. The first structure 1100f may be or include peripheral circuitry structures including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100s may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line and the common source line CSL.

[0112] In the second structure 1100s, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, an upper transistor adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to some example embodiments, the number of lower transistors LT1 and LT2 and / or the number of upper transistors UT1 and UT2 may be varied in various ways.

[0113] In some example embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word lines WL may be the gate electrodes of memory cell transistors MCT, respectively. Upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0114] In some example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used in an erase operation to erase data stored in the memory cell transistor MCT using gate-induced drain leakage (GIDL).

[0115] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect line 1115 extending from the first structure 1100f to the second structure 1100s. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect line 1125 extending from the first structure 1100F to the second structure 1100S.

[0116] In the first structure 1100f, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first structure 1100f to the second structure 1100s.

[0117] The controller 1200 may be or include a processor 1210, a NAND controller 1220, and a host interface 1230. According to some example embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100. In this case, the controller 1200 may control the plurality of semiconductor devices 1000.

[0118] Processor 1210 controls all operations of electronic system 1000, including controller 1200. Processor 1210 may operate based on specific (or alternatively, predetermined) firmware and may control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, data to be read from memory cell transistors (MCTs) of semiconductor device 1100, etc., may be sent via NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from an external host via host interface 1230, processor 1210 may control semiconductor device 1100 in response to the control command.

[0119] Figure 20 It is a schematic perspective view of an electronic system including a semiconductor device according to some example embodiments.

[0120] Reference Figure 20 An electronic system 2000 according to some exemplary embodiments of the present invention includes a main substrate 2001, a controller 2002 mounted on the main substrate 2001, and one or more semiconductor packages 2003 and DRAMs 2004. The semiconductor packages 2003 and DRAMs 2004 are connected to the controller 2002 via interconnect patterns 2005 formed on the main substrate 2001.

[0121] The main board 2001 may include a connector 2006, which includes a plurality of pins for connection to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host according to at least one interface such as Universal Serial Bus (USB), High-Speed ​​Peripheral Component Interconnect (PCI-Express), Serial Advanced Technology Attachment (SATA), M-PHY for Universal Flash Memory (UFS), etc. The electronic system 2000 may communicate with the external host according to any one of the interfaces. In some example embodiments, the electronic system 2000 may operate using power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0122] The controller 2002 can write data to or read data from the semiconductor package 2003. The controller 2002 can improve the operating speed of the electronic system 2000.

[0123] DRAM 2004 can be a buffer memory used to reduce speed differences between semiconductor package 2003, data storage space, and external host. DRAM 2004 included in electronic system 2000 can also operate as a cache memory and / or provide space for temporary data storage during control operations of semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0124] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be or may include a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 respectively disposed on the lower surface of the semiconductor chips 2200, connection structures 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structures 2400 on the package substrate 2100.

[0125] The packaging substrate 2100 may be or may include a printed circuit board (PCB) including an upper packaging pad 2130. Each of the semiconductor chips 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to... Figure 19 The input / output pads 1101. Each of the semiconductor chips 2200 may include a first stacked structure ST1, a second stacked structure ST2, and a channel structure CH. Each of the semiconductor chips 2200 may include a reference... Figures 1 to 14 The semiconductor device described.

[0126] In some example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 and the upper package pads 2130 to each other. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using wire bonding and may be electrically connected to the upper package pads 2130 of the package substrate 2100. According to some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure having through-silicon vias (TSVs) instead of using the wire bonding connection structure 2400.

[0127] In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the controller 2002 and the semiconductor chip 2200 are mounted on an additional interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected by wiring formed in the interposer substrate.

[0128] Figure 21 This is a schematic cross-sectional view of a semiconductor package according to some example embodiments.

[0129] Figure 21 Show Figure 20 Example embodiments of semiconductor packaging 2003, and conceptually illustrated along... Figure 20 The area cut off by line V-V' of the semiconductor package 2003.

[0130] Reference Figure 21 In semiconductor packaging 2003, the packaging substrate 2100 can be a printed circuit board (PCB). The packaging substrate 2100 may include a packaging substrate body portion 2120 and upper packaging pads disposed on the upper surface of the packaging substrate body portion 2120. Figure 20The upper package pad 2130 (2130) is disposed on the lower surface of the main body portion 2120 of the package substrate 2120 or exposed through the main body portion 2120 of the package substrate 2120, and the lower package pad 2125 is internal wiring 2135 electrically connecting the upper package pad 2130 and the lower package pad 2125 to each other. The upper package pad 2130 can be electrically connected to the connection structure 2400. The lower package pad 2125 can be connected to the interconnect pattern 2005 of the main substrate 2010 of the electronic system 2000 through the conductive connection portion 2800, such as... Figure 20 As shown.

[0131] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may have a peripheral circuit region including peripheral interconnects 3110. The second structure 3200 includes a common source line 3205, a stacked structure ST on the common source line 3205, a channel structure CH penetrating the stacked structure ST, a bit line 275 electrically connected to the channel structure CH, and a word line electrically connected to the stacked structure ST. Figure 19 Gate interconnect 3235 of WL).

[0132] As shown in the enlarged view, in each of the first structure 3100, the second structure 3200, and the semiconductor chip 2200, the substrate 101 may include a first region having a channel structure CH and a second region R2 and a third region R3 corresponding to the stepped region. Furthermore, each of the first structure 3100, the second structure 3200, and the semiconductor chip 2200 may be disposed in the second region R2 and the third region R3, and may also include dummy structures DS, each of which has a width greater than the width of each of the channel structures CH.

[0133] Each of the semiconductor chips 2200 may include a through interconnect 3245 electrically connected to a peripheral interconnect 3110 of the first structure 3100 and extending into the interior of the second structure 3200. The through interconnect 3245 may be disposed outside the stacked structure ST and may be further configured to penetrate the stacked structure ST. Each of the semiconductor chips 2200 may also include an input / output pad 2210 electrically connected to the peripheral interconnect 3110. Figure 20 ).

[0134] As described above, the auxiliary separation regions of the memory cell region and the auxiliary separation regions of the stepped region can be arranged at different spacings to provide semiconductor devices and electronic systems including them with improved reliability.

[0135] Although some exemplary embodiments have been described above with reference to the various figures, the various embodiments are not intended to be mutually exclusive unless the context clearly indicates otherwise. For example, a semiconductor device may have some features described with reference to one figure, and may also have some features described with reference to another figure.

[0136] Any element disclosed above may be included or implemented in processing circuitry, such as hardware including logic circuitry; hardware / software combinations such as processors executing software; or combinations thereof. More specifically, processing circuitry may include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0137] Although some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate having a first region, a second region, and a third region; The first stacked structure includes a first gate electrode stacked and spaced apart from each other, and a first interlayer insulating layer stacked alternately with the first gate electrode; The second stacked structure is on the first stacked structure and includes a second gate electrode and a second interlayer insulating layer alternately stacked with the second gate electrode, the second gate electrode being stacked in the first region to be spaced apart from each other and arranged in a stepped shape in the first direction while extending in the first direction, the stepped shape being in the second region and the third region; In the first region to the third region, the main separation region penetrates the first stacked structure and the second stacked structure, the main separation region extends in the first direction and is spaced apart from each other in a second direction perpendicular to the first direction; In the first region and the second region, there is a first auxiliary separation region that penetrates the first stacked structure and the second stacked structure between the main separation regions. The first auxiliary separation region extends in the first direction and is spaced apart from each other in the second direction. In the third region, there is a second auxiliary separation region that penetrates the first and second stacked structures between the main separation regions. The second auxiliary separation region extends in the first direction and is spaced apart from each other in the second direction. A first channel structure and a second channel structure, each of the first channel structure and the second channel structure including a channel layer and having a first width, the first channel structure and the second channel structure respectively penetrating the first stacked structure and the second stacked structure. as well as A dummy structure that penetrates both the first and second stacked structures and has a second width greater than the first width. The first auxiliary separation region is arranged between the main separation regions in the second direction at a first spacing, and the second auxiliary separation region is arranged between the main separation regions in the second direction at a second spacing, wherein the second spacing is smaller than the first spacing.

2. The semiconductor device according to claim 1, wherein, The first channel structure and the second channel structure are located between the first auxiliary separation region in the first region, and The dummy structure exists between the first auxiliary separation regions in the second region and between the second auxiliary separation regions in the third region.

3. The semiconductor device according to claim 1, wherein, The first channel structure and the second channel structure are located between the first auxiliary separation region, and The dummy structure is located between the second auxiliary separation regions.

4. The semiconductor device according to claim 1, wherein, The first channel structure and the second channel structure are located between the first auxiliary separation region in the first region, and The dummy structure is located between the portion of the first region adjacent to the second region and the first auxiliary separation region in the second region, and between the second auxiliary separation regions in the third region.

5. The semiconductor device according to claim 1, wherein, The distance between the second channel structures is smaller than the distance between the dummy structures.

6. The semiconductor device according to claim 1, further comprising: A lower separation region is provided between the main separation regions and penetrating at least one first gate electrode, the at least one first gate electrode including the lowest gate electrode among the first gate electrodes, the lower separation region connecting at least one of the first auxiliary separation regions to one of the second auxiliary separation regions adjacent to the at least one of the first auxiliary separation regions.

7. The semiconductor device according to claim 6, wherein, Each of the lower separation regions includes a first portion in a direction parallel to the first auxiliary separation region and a second portion in a direction perpendicular to the second auxiliary separation region.

8. The semiconductor device according to claim 1, wherein, The dummy structure includes insulating material.

9. The semiconductor device according to claim 1, wherein, Each of the first channel structure and the second channel structure further includes a gate dielectric layer between the gate electrode and the channel layer, and a channel-filling insulating layer in the channel layer.

10. The semiconductor device according to claim 1, wherein, The second width of each of the dummy structures is more than twice the first width of each of the first channel structure and the second channel structure.

11. The semiconductor device according to claim 1, wherein, The semiconductor device includes a curved portion connecting the upper end of the first channel structure to the lower end of the second channel structure, and Each of the dummy structures has a width that decreases continuously from the upper part of the second stacked structure to the lower part of the first stacked structure.

12. The semiconductor device according to claim 1, further comprising: In the first region and the second region, there is an upper separation region that penetrates a portion of the upper part of the second stacked structure and alternates with the first auxiliary separation region in the second direction. In the second direction, the distance from the center of the main separation region to the center of the second auxiliary separation region is greater than the distance from the center of the main separation region to the center of the upper separation region.

13. The semiconductor device according to claim 1, wherein, When viewed in a plan view, each of the dummy structures has a shape different from that of each of the first channel structure and the second channel structure.

14. A semiconductor device, comprising: A substrate having a first region, a second region, and a third region; A stacked structure comprising a plurality of gate electrodes stacked on a first region and spaced apart from each other, and arranged in a stepped shape on a second region and a third region while extending in a first direction; Each of the channel structures penetrates the stacked structure and includes a channel layer; In the first region to the third region, the main separation region penetrates the stacked structure, extends in the first direction, and is spaced apart from each other in a second direction perpendicular to the first direction; In the first region and the second region, there is a first auxiliary separation region that penetrates the stacked structure between the main separation regions, extends in the first direction, and is spaced apart from each other in the second direction; In the third region, a second auxiliary separation region extends in the first direction and is spaced apart from each other in the second direction, penetrating the stacked structure between the main separation regions; as well as A first lower separation region is located between the main separation regions and penetrates at least one gate electrode, the at least one gate electrode including the lowest gate electrode among the plurality of gate electrodes. The first lower separation region lies between at least one of the first auxiliary separation regions and an adjacent one of the second auxiliary separation regions, and connects the at least one of the first auxiliary separation regions to the adjacent one of the second auxiliary separation regions. The first auxiliary separation region is arranged between the main separation regions in the second direction at a first spacing, and the second auxiliary separation region is arranged between the main separation regions in the second direction at a second spacing smaller than the first spacing, and the first auxiliary separation region and the second auxiliary separation region are offset relative to each other in the second direction.

15. The semiconductor device according to claim 14, wherein, Each of the first lower separation regions includes a first portion arranged in a direction parallel to the first auxiliary separation region and a second portion arranged in a direction perpendicular to the second auxiliary separation region.

16. The semiconductor device according to claim 14, wherein, The two in the first lower separation region between the main separation regions are centrally symmetrical about the main separation region in the second direction.

17. The semiconductor device of claim 14, further comprising: A second lower separation region penetrates at least one gate electrode, the at least one gate electrode including the lowest gate electrode among the plurality of gate electrodes, the second lower separation region being adjacent to the region where the second auxiliary separation regions are spaced apart from each other in the second direction, and connecting the second auxiliary separation regions spaced apart from each other in the second direction.

18. The semiconductor device according to claim 14, wherein, Each of the channel structures has a first width and is located between the first auxiliary separation regions in the first region. The semiconductor device includes dummy structures that penetrate the stacked structure and each has a second width greater than the first width, and The dummy structure is located between the first auxiliary separation regions in the second region, and between the second auxiliary separation regions in the third region.

19. An electronic system comprising: A semiconductor memory device, comprising a first substrate; An active or passive circuit is located on the first substrate; A second substrate is provided on the active or passive circuit and has a first region, a second region and a third region. A stacked structure comprising a plurality of gate electrodes stacked and spaced apart from each other on a second substrate in a first region to a third region and arranged in a stepped shape in a first direction, the stepped shape being in the second region and the third region; the stacked structure comprising a first interlayer insulating layer alternately stacked with the plurality of gate electrodes. Each of the channel structures penetrates the stacked structure and includes a channel layer; The main separation region penetrates the stacked structure, the main separation region extends in the first direction and is spaced apart from each other in a second direction perpendicular to the first direction, the main separation region is on the second substrate on the first region to the third region; A first auxiliary separation region penetrates the stacked structure between the main separation regions, the first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, the first auxiliary separation regions being in the first region and the second region; A second auxiliary separation region penetrates the stacked structure between the main separation regions, the second auxiliary separation regions extend in the first direction and are spaced apart from each other in the second direction, the second auxiliary separation regions being in the third region; A first lower separation region is located between the main separation regions and penetrates at least one gate electrode, the at least one gate electrode including the lowest gate electrode among the plurality of gate electrodes. The first lower separation region is located between at least one of the first auxiliary separation regions and one of the second auxiliary separation regions adjacent to the at least one of the first auxiliary separation regions, and connects the at least one of the first auxiliary separation regions to the one of the second auxiliary separation regions. Input / output pads, which are electrically connected to the active or passive circuitry; as well as A controller circuit, electrically connected to the semiconductor memory device via the input / output pads and configured to control the semiconductor memory device. In the semiconductor memory device, the first auxiliary separation region is arranged between the main separation regions in the second direction at a first spacing, and the second auxiliary separation region is arranged between the main separation regions in the second direction at a second spacing smaller than the first spacing.

20. The electronic system according to claim 19, wherein, The semiconductor memory device further includes: An upper separation region, which penetrates a portion of the upper part of the stacked structure and is arranged alternately with the first auxiliary separation region, the upper separation region being located in the first region and the second region; and Each of the virtual structures penetrates the stacked structure. Each of the channel structures has a first width, and each of the dummy structures has a second width greater than the first width.

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