Semiconductor memory device and method of manufacturing the same

Abstract

The present technology relates to a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a laminate having a plurality of interlayer insulating layers and a plurality of gates alternately laminated on a substrate, and a plurality of channel structures passing through the laminate in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer extending vertically in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of other regions of the core insulating layer.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to semiconductor memory devices with a vertical channel structure and methods of manufacturing the same. Background Technology

[0002] Recently, the paradigm for computing environments has shifted to ubiquitous computing, enabling the use of computer systems anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops is rapidly increasing. These portable electronic devices typically utilize memory systems that employ semiconductor memory devices, i.e., data storage devices. These data storage devices serve as either primary or secondary storage devices in portable electronic devices.

[0003] The advantages of semiconductor data storage devices that use memory devices are: excellent stability and durability due to the absence of mechanical drivers, very fast information access speed, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), etc.

[0004] Memory devices are mainly divided into volatile memory devices and non-volatile memory devices.

[0005] Non-volatile memory devices have relatively slow write and read speeds; however, they retain stored data even when power is cut off. Therefore, non-volatile memory devices are used to store data that must be retained regardless of power supply conditions. Non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR and NAND types. Summary of the Invention

[0006] A semiconductor memory device according to an embodiment of the present disclosure includes: a stack having a plurality of interlayer insulating layers and a plurality of gates alternately stacked on a substrate; and a plurality of channel structures extending through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer extending vertically in the same direction as the plurality of channel structures, and the dielectric constant of a local region of the core insulating layer is lower than the dielectric constant of other regions of the core insulating layer.

[0007] A semiconductor memory device according to an embodiment of the present disclosure includes: a stack having a plurality of interlayer insulating layers and a plurality of gates alternately stacked on a substrate; and a plurality of channel structures extending through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer extending vertically in the same direction as the plurality of channel structures. At least one first gate disposed at the uppermost portion of the gate corresponds to a drain-select transistor, at least one second gate disposed at the lowermost portion of the gate corresponds to a source-select transistor, and the remaining gates correspond to memory cells. A local region in the core insulating layer adjacent to the first gate or the second gate has a lower dielectric constant than other regions adjacent to the remaining gates.

[0008] A method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure includes: forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate; forming a plurality of holes penetrating the stack in a vertical direction; sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on the sidewall of each of the plurality of holes; forming a core insulating layer on the sidewall of the channel layer to fill the central region of the plurality of holes; and implanting a dopant into a local region such that the dielectric constant of the local region of the core insulating layer is lower than the dielectric constant of other regions of the core insulating layer.

[0009] A method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure includes: forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate; forming a plurality of holes penetrating the stack in a vertical direction; sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on the sidewall of each of the plurality of holes; and forming a core insulating layer on the sidewall of the channel layer to fill the central region of the plurality of holes, wherein the step of forming the core insulating layer includes forming a gap in a local region of the core insulating layer.

[0010] A semiconductor memory device according to an embodiment of the present disclosure includes: a stack having a plurality of interlayer insulating layers and a plurality of gates alternately stacked on a substrate; and a plurality of channel structures extending through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer extending vertically in the same direction as the plurality of channel structures, and the dielectric constant of a portion of the core insulating layer is different from the dielectric constant of other portions of the core insulating layer.

[0011] A semiconductor memory device according to an embodiment of the present disclosure includes: a stack having a plurality of interlayer insulating layers and a plurality of gates alternately stacked on a substrate; and a plurality of channel structures extending through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer and a charge storage layer extending vertically in the same direction as the plurality of channel structures, and a gap is formed in a portion of the core insulating layer adjacent to the gate. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 2 This is an example Figure 1 The circuit diagram of the memory cell array.

[0014] Figure 3A and Figure 3B This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 4 This is a perspective view illustrating a portion of a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 5A yes Figure 4 A magnified view of region D.

[0017] Figure 5B yes Figure 4 A magnified view of region S.

[0018] Figures 6A to 6E This is a cross-sectional view illustrating a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0019] Figure 7 This is a perspective view illustrating a portion of a memory cell array of a semiconductor memory device according to another embodiment of the present disclosure.

[0020] Figure 8A yes Figure 7 A magnified view of region D.

[0021] Figure 8B yes Figure 7 A magnified view of region S.

[0022] Figures 9A to 9E This is a cross-sectional view illustrating a method for manufacturing a memory cell array according to another embodiment of the present disclosure.

[0023] Figure 10This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0024] Figure 11 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0025] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative of embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms, and the descriptions are not limited to those described in this specification or application.

[0026] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement the technical spirit of the present disclosure.

[0027] Embodiments of this disclosure are intended to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device, which can improve erase characteristics by increasing the leakage current characteristics and gate-induced drain leakage (GIDL) current of the select transistors included in the cell string.

[0028] According to this technology, the leakage current characteristics of the select transistor are improved by forming a low-dielectric-constant core insulating layer beneath the channel of the select transistor. Furthermore, the gate-induced drain leakage (GIDL) current generated in the select transistor during the erase operation increases, thus improving the erase operation characteristics.

[0029] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The semiconductor memory device 10 includes peripheral circuitry PC and memory cell array 20.

[0031] The peripheral circuit PC can be configured to control programming operations for storing data in the memory cell array 20, reading operations for outputting data stored in the memory cell array 20, and erasing operations for erasing data stored in the memory cell array 20.

[0032] As an implementation, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0033] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 can be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0034] Control circuit 35 can control peripheral circuit PC based on command CMD and address ADD.

[0035] The voltage generator 31 can generate various operating voltages for programming, reading and erasing operations based on the control circuit 35, such as pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage and read voltage.

[0036] The row decoder 33 can select a memory block based on the control circuit 35. The row decoder 33 can be configured to apply an operating voltage to the word line WL connected to the selected memory block.

[0037] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. Page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations based on control circuitry 35. Page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations based on control circuitry 35. Page buffer group 37 can select bit line BL based on control circuitry 35.

[0038] Structurally, the memory cell array 20 can overlap with a portion of the peripheral circuit PC.

[0039] Figure 2 This is an example Figure 1 The circuit diagram of the memory cell array.

[0040] Reference Figure 2 The memory cell array 20 may include multiple cell strings CS1 and CS2 connected between the source line SL and multiple bit lines BL. The multiple cell strings CS1 and CS2 may be connected together to multiple word lines WL1 to WLn.

[0041] Each of the multiple cell strings CS1 and CS2 may include at least one source selection transistor SST connected to the source line SL, at least one drain selection transistor DST connected to the bit line BL, and multiple memory cells MC1 to MCn connected in series between the source selection transistor SST and the drain selection transistor DST.

[0042] The gates of multiple memory cells MC1 to MCn can be connected to multiple word lines WL1 to WLn that are spaced apart and stacked. The multiple word lines WL1 to WLn can be positioned between the source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same height.

[0043] The gate of the source-select transistor (SST) can be connected to the source-select line (SSL). The gate of the drain-select transistor (DST) can be connected to the drain-select line corresponding to the gate of the drain-select transistor (DST).

[0044] The source line SL can be connected to the source of the source select transistor SST. The drain of the drain select transistor DST can be connected to the bit line corresponding to the drain of the drain select transistor DST.

[0045] Multiple unit strings CS1 and CS2 can be divided into string groups connected to two or more drain select lines DSL1 and DSL2, respectively. Unit strings connected to the same word line and the same bit line can be independently controlled by different drain select lines. Additionally, unit strings connected to the same drain select line can be independently controlled by different bit lines.

[0046] In one implementation, two or more drain selection lines DSL1 and DSL2 may include a first drain selection line DSL1 and a second drain selection line DSL2. Multiple unit strings CS1 and CS2 may include a first unit string CS1 connected to a first string group of the first drain selection line DSL1 and a second string CS2 connected to a second string group of the second drain selection line DSL2.

[0047] Figure 3A and Figure 3B This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0048] Reference Figure 3A and Figure 3B Each of the semiconductor memory devices 10A and 10B may include peripheral circuitry PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuitry PC.

[0049] Each gate stack (GST) may include a source select line SSL, multiple word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 separated from each other at the same height by a first slit S1.

[0050] The source select line SSL and multiple word lines WL1 to WLn can extend in a first direction X and a second direction Y, and can be formed into a flat plate shape parallel to the upper surface of the substrate SUB. The first direction X can be the direction pointed to by the X-axis of the XYZ coordinate system, and the second direction Y can be the direction pointed to by the Y-axis of the XYZ coordinate system.

[0051] Multiple word lines WL1 to WLn can be spaced apart and stacked on each other in the third direction Z. The third direction Z can be the direction pointed to by the Z-axis of the XYZ coordinate system. Multiple word lines WL1 to WLn can be set between two or more drain select lines DSL1 and DSL2 and source select line SSL.

[0052] The gate stack GST can be separated from each other by the second slit S2. The first slit S1 can be formed on the third direction Z and is shorter than the second slit S2, and can overlap with multiple word lines WL1 to WLn.

[0053] Each of the first slit S1 and the second slit S2 can extend in a straight line, a zigzag shape, or a wavy shape. The width of each of the first slit S1 and the second slit S2 can be varied in various ways according to design rules.

[0054] Reference Figure 3A According to the implementation method, the source selection line SSL can be set closer to the peripheral circuit PC than two or more drain selection lines DSL1 and DSL2.

[0055] The semiconductor memory device 10A may include: a source line SL disposed between a gate stack GST and a peripheral circuit PC; and multiple bit lines BL, which are spaced further from the peripheral circuit PC than the source line SL. The gate stack GST may be disposed between the multiple bit lines BL and the source line SL.

[0056] Reference Figure 3B According to the implementation method, two or more drain select lines DSL1 and DSL2 can be configured to be closer to the peripheral circuit PC than the source select line SSL.

[0057] The semiconductor memory device 10B may include multiple bit lines BL disposed between a gate stack GST and a peripheral circuit PC, and the source line SL may be farther from the peripheral circuit PC than the multiple bit lines BL. The gate stack GST may be disposed between the multiple bit lines BL and the source line SL.

[0058] Again, refer to Figure 3A and Figure 3B Multiple bit lines BL can be formed from various conductive materials. Source lines SL may include doped semiconductor layers. As an embodiment, source lines SL may include n-type doped silicon layers.

[0059] Although not shown in the figure, the peripheral circuit PC can be electrically connected to multiple bit lines BL, source lines SL, and multiple word lines WL1 to WLn through interconnects of various structures.

[0060] Figure 4This is a perspective view illustrating a portion of a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0061] Reference Figure 4 The memory cell array 20 may include gate stacks GST separated from each other by slits SI and channel structures CH passing through each gate stack GST.

[0062] The slit SI can be filled with a vertical structure VS. As an implementation, the vertical structure VS may include an insulating material.

[0063] Each of the gate stacks (GSTs) may include an interlayer insulating layer (ILD) and a gate GA that are alternately stacked in one direction. Hereinafter, the direction in which the interlayer insulating layer (ILD) and the gate GA are alternately stacked is referred to as the stacking direction.

[0064] At least one gate in the bottom layer of the gate GA can be used as a source select line, and at least one gate in the top layer can be used as a drain select line.

[0065] The gate GA may include at least one of a doped semiconductor, a metal, a metal silicide, or a metal nitride layer. The gate GA may be used as the gate of a memory cell or the gate of a select transistor.

[0066] The channel structure CH can extend in the stacking direction and can be surrounded by the gate GA.

[0067] The channel structure CH is formed such that the dielectric constant of the core insulating layer adjacent to the drain-select transistor or source-select transistor is lower than the dielectric constant of the core insulating layer adjacent to the memory cell. For example, the channel structure CH can be formed by implanting impurities into the core insulating layer adjacent to the drain-select transistor or source-select transistor.

[0068] In embodiments of this disclosure, as described above Figure 3A As shown, the following embodiment is described as an example: one or more gate stacks disposed at the bottommost portion of the gate stack GST can be used as source select lines, and one or more gate stacks disposed at the topmost portion can be used as drain select lines. However, this disclosure is not limited thereto, and as described above... Figure 3B As shown, one or more gate stacks disposed at the bottommost portion can be used as drain select lines, and one or more gate stacks disposed at the topmost portion of the gate stack GST can be used as source select lines.

[0069] Figure 5A yes Figure 4 A magnified view of region D.

[0070] Reference Figure 5AThe channel structure CH may include a barrier insulating layer 111, a charge storage layer 113, a tunnel insulating layer 115, a channel layer 117, and a core insulating layer 119 extending in the vertical direction.

[0071] The core insulating layer 119 may extend vertically from the central region of the channel structure CH and may be formed of an insulating layer such as an oxide layer. Dopants may be implanted into localized regions of the core insulating layer 119, and these dopant-implanted localized regions may have a lower dielectric constant than other regions. For example, dopants may be implanted into the region of the vertically extending core insulating layer 119 adjacent to the gate GA, which serves as the drain select line DSL, but not into the region of the vertically extending core insulating layer 119 adjacent to the gate GA, which serves as the word line WLn. That is, dopants are implanted into the core insulating layer 119 adjacent to the drain select transistor, and therefore the dielectric constant of the core insulating layer 119 adjacent to the drain select transistor is lower than the dielectric constant of the core insulating layer 119 adjacent to the memory cell.

[0072] The dopant injected into the core insulating layer 119 can be carbon (C) or fluorine (F), or both carbon and fluorine.

[0073] The channel layer 117 can be used as a channel region for a cell string. The channel layer 117 may include a semiconductor layer. As an embodiment, the channel layer 117 may include silicon.

[0074] The tunnel insulation layer 115 may surround the sidewall of the trench layer 117. The tunnel insulation layer 115 may be formed of a silicon oxide layer capable of charge tunneling.

[0075] The charge storage layer 113 may surround the sidewall of the tunnel insulation layer 115. The charge storage layer 113 may be formed of a material layer capable of storing data altered by using Fowler Nord-Heim tunneling. As an embodiment, the charge storage layer 113 may be formed of a charge trapping nitride layer.

[0076] The barrier insulating layer 111 may surround the sidewall of the charge storage layer 113. The barrier insulating layer 111 may include an oxide layer capable of blocking charge.

[0077] As described above, in the embodiments of this disclosure, by implanting dopant into local regions of the core insulating layer 119, the core insulating layer 119 can be formed such that the dielectric constant of the core insulating layer 119 adjacent to the drain select transistor is lower than the dielectric constant of the core insulating layer 119 adjacent to the memory cell. Therefore, the bulk effect of the drain select transistor is reduced, the threshold voltage is increased, and the leakage current is reduced. Furthermore, during the erase operation, gate-induced drain leakage (GIDL) current can be more easily generated based on the voltage difference between the source and the body of the drain select transistor.

[0078] Figure 5B yes Figure 4 A magnified view of region S.

[0079] Reference Figure 5B Dopant can be implanted into local regions of the core insulating layer 119, and the implanted local regions can have a lower dielectric constant than other regions. For example, dopant is implanted into the region of the vertically extending core insulating layer 119 adjacent to the gate GA used as the source select line SSL, and dopant is not implanted into the region of the vertically extending core insulating layer 119 adjacent to the gate GA used as the word line WL1. That is, dopant is implanted into the core insulating layer 119 adjacent to the source select transistor, therefore, the dielectric constant of the core insulating layer 119 adjacent to the source select transistor is lower than the dielectric constant of the core insulating layer 119 adjacent to the memory cell.

[0080] The dopant injected into the core insulating layer 119 can be carbon (C) or fluorine (F), or both carbon and fluorine.

[0081] As described above, in the embodiments of this disclosure, by implanting dopant into local regions of the core insulating layer 119, the core insulating layer 119 is formed such that the dielectric constant of the core insulating layer 119 adjacent to the source selection transistor is lower than the dielectric constant of the core insulating layer 119 adjacent to the memory cell. Therefore, the bulk effect of the source selection transistor is reduced, the threshold voltage is increased, and the leakage current is reduced. Furthermore, during the erase operation, gate-induced drain leakage (GIDL) current can be more easily generated based on the voltage difference between the source and body of the source selection transistor.

[0082] Based on the above description Figure 4 , Figure 5A and Figure 5BIn embodiments of this disclosure, the core insulating layer is formed such that the dielectric constant of the core insulating layer adjacent to the drain-select transistor or the source-select transistor is lower than the dielectric constant of the core insulating layer adjacent to the memory cell. Therefore, the leakage current characteristics of the drain-select transistor or the source-select transistor, as well as the generation of GIDL current during erase operations, can be increased.

[0083] Figures 6A to 6E This is a cross-sectional view illustrating a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0084] Reference Figure 6A A laminate ST in which interlayer insulating layer 101 and sacrificial layer 103 can be alternately stacked can be formed. The laminate ST can be formed on a substrate (not shown) having peripheral circuitry.

[0085] The sacrificial layer 103 may be formed of a material different from that of the interlayer insulating layer 101. For example, the interlayer insulating layer 101 may be formed of an oxide such as silicon oxide. The sacrificial layer 103 may be formed of a material with an etch rate different from that of the interlayer insulating layer 101. For example, the sacrificial layer 103 may be formed of a nitride such as silicon nitride.

[0086] Reference Figure 6B A hole 105 is formed through the stacked material ST. Subsequently, a barrier insulating layer 111, a charge storage layer 113, a tunnel insulating layer 115, and a channel layer 117 can be sequentially formed on the sidewall of the hole 105.

[0087] The barrier insulating layer 111 may include an oxide layer capable of blocking electric charge. As an embodiment, the barrier insulating layer 111 may be formed of Al2O3.

[0088] The charge storage layer 113 can be formed of a charge trapping layer, a material layer with conductive nanodots, or a phase change material layer. For example, the charge storage layer 113 can store data that has changed through the use of Fowler-Nordheim tunneling. For this purpose, the charge storage layer 113 can be formed of a silicon nitride layer capable of trapping charges.

[0089] The tunnel insulation layer 115 can be formed of a silicon oxide layer capable of charge tunneling.

[0090] The channel layer 117 may include a semiconductor layer. As an embodiment, the channel layer 117 may include silicon.

[0091] Reference Figure 6C The channel structure 121 can be formed by filling the central region of the hole 105 with the core insulation layer 119.

[0092] In the process of forming the core insulating layer 119, an impurity implantation process may be performed to form an impurity implantation region in a localized area of ​​the core insulating layer 119. In an embodiment, the impurity implantation region may be a region in the core insulating layer 119 adjacent to the region where a drain select transistor is to be formed or an area where a source select transistor is to be formed.

[0093] In this embodiment, after forming the core insulating layer 119 from the lower surface of the hole 105 to the height of the source selection transistor, an impurity implantation process can be performed to implant impurities into the core insulating layer 119 in the region adjacent to the region where the source selection transistor is to be formed. Subsequently, after forming the core insulating layer 119 to the height of the drain selection transistor in the central region of the hole 105, an impurity implantation process can be performed to implant impurities into the core insulating layer 119 in the region adjacent to the region where the drain selection transistor is to be formed.

[0094] In another embodiment, after the core insulating layer 119 extends from its lower surface to the central region of the opening-filled via 105, an impurity implantation process is performed to implant impurities into regions adjacent to the region where a source-select transistor is to be formed and regions adjacent to the region where a drain-select transistor is to be formed. In this case, the implantation depth can be adjusted during the impurity implantation process to implant impurities into regions adjacent to the region where a source-select transistor is to be formed and regions adjacent to the region where a drain-select transistor is to be formed.

[0095] The impurities used during the impurity injection process can be carbon or fluorine, or both carbon and fluorine.

[0096] Due to impurities, the dielectric constant of the regions in the core insulating layer 119 that have been injected with impurities can be lower than the dielectric constant of other regions in the core insulating layer 119.

[0097] Reference Figure 6D This can form a slit SI that passes through the stacked material ST. The area exposed through the slit SI... Figure 6C The sidewalls of the sacrificial layer 103 are shown. Thereafter, they can be removed via slit SI. Figure 6C The sacrificial layer 103 is shown. Therefore, an opening can be formed that exposes the side portion of the blocking insulating layer 111. The opening can be defined between the interlayer insulating layers 101.

[0098] Reference Figure 6E The gate 131 can be filled in the space (i.e., the opening) where the sacrificial layer has been removed. For example, after depositing a conductive material to fill the opening, the conductive material inside the slit can be removed, allowing the conductive material to pass through the slit and divide into the gate 131. The slit can then be filled with an insulating material to form a vertical structure 133.

[0099] Therefore, the core insulating layer 119 can be formed by implanting impurities into the core insulating layer 119 adjacent to the drain select transistor DST or the source select transistor SST. Thus, the core insulating layer 119 adjacent to the drain select transistor DST or the source select transistor SST can have a relatively lower dielectric constant than the core insulating layer 119 adjacent to the memory cell.

[0100] In embodiments of this disclosure, the core insulating layer 119 can be formed such that the dielectric constant of the local region is lower than that of other regions by implanting dopant only in local regions. However, by implanting dopant throughout the entire region of the core insulating layer 119, the entire region of the core insulating layer 119 can be formed with a low dielectric constant.

[0101] Figure 7 This is a perspective view illustrating a portion of a memory cell array of a semiconductor memory device according to another embodiment of the present disclosure.

[0102] Reference Figure 7 The memory cell array 20 may include gate stacks GST separated from each other by slits SI and channel structures CH passing through each gate stack GST.

[0103] The slit SI can be filled with a vertical structure VS. As an implementation, the vertical structure VS may include an insulating material.

[0104] Each of the gate stacks (GSTs) may include an interlayer insulating layer (ILD) and a gate GA that are alternately stacked in one direction. Hereinafter, the direction in which the interlayer insulating layer (ILD) and the gate GA are alternately stacked is referred to as the stacking direction.

[0105] At least one gate in the bottom layer of the gate GA can be used as a source select line, and at least one gate in the top layer can be used as a drain select line.

[0106] The gate GA may include at least one of a doped semiconductor, a metal, a metal silicide, or a metal nitride layer. The gate GA may be used as the gate of a memory cell or the gate of a select transistor.

[0107] The channel structure CH can extend in the stacking direction and can be surrounded by the gate GA.

[0108] According to embodiments of the present disclosure, the channel structure CH can be formed such that the dielectric constant of the core insulating layer adjacent to the drain-select transistor or source-select transistor is lower than the dielectric constant of the core insulating layer adjacent to the memory cell. For example, a gap can be formed in the core insulating layer adjacent to the drain-select transistor or source-select transistor.

[0109] In embodiments of this disclosure, as described above Figure 3A As shown, the following embodiment is described as an example: one or more gate stacks disposed at the bottommost portion of the gate stack (GST) serve as source select lines, and one or more gate stacks disposed at the topmost portion serve as drain select lines. However, this disclosure is not limited thereto, and as described above... Figure 3B As shown, one or more gate stacks disposed at the bottommost portion can be used as drain select lines, and one or more gate stacks disposed at the topmost portion of the gate stack GST can be used as source select lines.

[0110] Figure 8A yes Figure 7 A magnified view of region D.

[0111] Reference Figure 8A The channel structure CH may include a barrier insulating layer 211, a charge storage layer 213, a tunnel insulating layer 215, a channel layer 217, and a core insulating layer 219 extending in the vertical direction.

[0112] The core insulating layer 219 can extend vertically from the central region of the channel structure CH and can be formed of an insulating layer such as an oxide layer. Gap air can be formed in localized regions of the core insulating layer 219, and the localized regions where gap air is formed can have a lower dielectric constant than other regions. For example, gap air can be formed in a region of the core insulating layer 219 extending vertically adjacent to the gate GA used as the drain select line DSL, and gap air is not formed in a region of the core insulating layer 219 extending vertically adjacent to the gate GA used as the word line WLn. That is, gap air can be formed in the core insulating layer 219 adjacent to the drain select transistor, therefore, the dielectric constant of the core insulating layer 219 adjacent to the drain select transistor can be lower than the dielectric constant of the core insulating layer 219 adjacent to the memory cell.

[0113] The channel layer 217 can be used as the channel region of a cell string. The channel layer 217 may include a semiconductor layer. As an embodiment, the channel layer 217 may include silicon.

[0114] The tunnel insulation layer 215 may surround the sidewall of the trench layer 217. The tunnel insulation layer 215 may be formed of a silicon oxide layer capable of charge tunneling.

[0115] The charge storage layer 213 may surround the sidewall of the tunnel insulation layer 215. The charge storage layer 213 may be formed of a material layer capable of storing data altered by using Fowler Nord-Heim tunneling. As an embodiment, the charge storage layer 213 may be formed of a charge trapping nitride layer.

[0116] The barrier insulating layer 211 may surround the sidewalls of the charge storage layer 213. The barrier insulating layer 211 may include an oxide layer capable of blocking charge.

[0117] As described above, in the embodiments of this disclosure, by forming gaps Air in local regions of the core insulating layer 219, the core insulating layer 219 can be formed such that the dielectric constant of the core insulating layer 219 adjacent to the drain select transistor is lower than the dielectric constant of the core insulating layer 219 adjacent to the memory cell. Therefore, the bulk effect of the drain select transistor is reduced, the threshold voltage is increased, and the leakage current is reduced. Furthermore, during the erase operation, gate-induced drain leakage (GIDL) current can be more easily generated based on the voltage difference between the source and the body of the drain select transistor.

[0118] Figure 8B yes Figure 7 A magnified view of region S.

[0119] Reference Figure 8B A gap Air can be formed in a localized region of the core insulating layer 219, and the localized region in which the gap Air is formed can have a lower dielectric constant than other regions. For example, the gap Air can be formed in a region of the core insulating layer 219 extending in the vertical direction adjacent to the gate GA used as the source select line SSL, and the gap Air may not be formed in a region of the core insulating layer 219 extending in the vertical direction adjacent to the gate GA used as the word line WL1. That is, the gap Air can be formed in the core insulating layer 219 adjacent to the source select transistor, and therefore, the dielectric constant of the core insulating layer 219 adjacent to the source select transistor is lower than the dielectric constant of the core insulating layer 219 adjacent to the memory cell.

[0120] As described above, in the embodiments of this disclosure, by forming gaps Air in local regions of the core insulating layer 219, the core insulating layer 219 can be formed such that the dielectric constant of the core insulating layer 219 adjacent to the source selection transistor is lower than the dielectric constant of the core insulating layer 219 adjacent to the memory cell. Therefore, the bulk effect of the source selection transistor is reduced, the threshold voltage is increased, and the leakage current is reduced. Furthermore, during the erase operation, gate-induced drain leakage (GIDL) current can be more easily generated based on the voltage difference between the source and body of the source selection transistor.

[0121] Based on the above description Figure 7 , Figure 8A and Figure 8BIn embodiments of this disclosure, the core insulating layer can be formed such that the dielectric constant of the core insulating layer adjacent to the drain-select transistor or the source-select transistor is lower than the dielectric constant of the core insulating layer adjacent to the memory cell. Therefore, the leakage current characteristics of the drain-select transistor or the source-select transistor, as well as the generation of GIDL current during erase operations, can be increased.

[0122] Figures 9A to 9E This is a cross-sectional view illustrating a method for manufacturing a memory cell array according to another embodiment of the present disclosure.

[0123] Reference Figure 9A A laminate ST in which an interlayer insulating layer 201 and a sacrificial layer 203 are alternately stacked can be formed. The laminate ST can be formed on a substrate (not shown) having peripheral circuitry.

[0124] The sacrificial layer 203 can be formed of a material different from that of the interlayer insulating layer 201. For example, the interlayer insulating layer 201 can be formed of an oxide such as silicon oxide. The sacrificial layer 203 can be formed of a material with an etch rate different from that of the interlayer insulating layer 201. For example, the sacrificial layer 203 can be formed of a nitride such as silicon nitride.

[0125] Reference Figure 9B A hole 205 is formed through the stacked material ST. Subsequently, a barrier insulating layer 211, a charge storage layer 213, a tunnel insulating layer 215, and a channel layer 217 can be sequentially formed on the sidewall of the hole 205.

[0126] The barrier insulating layer 211 may include an oxide layer capable of blocking electric charge. As an embodiment, the barrier insulating layer 211 may be formed of Al2O3.

[0127] The charge storage layer 213 can be formed of a charge trapping layer, a material layer with conductive nanodots, or a phase change material layer. For example, the charge storage layer 213 can store data that changes through the use of Fowler-Nordheim tunneling. For this purpose, the charge storage layer 213 can be formed of a silicon nitride layer capable of trapping charges.

[0128] The tunnel insulation layer 215 can be formed of a silicon oxide layer capable of charge tunneling.

[0129] The channel layer 217 may include a semiconductor layer. As an embodiment, the channel layer 217 may include silicon.

[0130] Reference Figure 9C The channel structure 221 can be formed by filling the central region of the hole 205 with the core insulating layer 219.

[0131] In the process of forming the core insulating layer 219, gaps Air can be formed in local areas of the core insulating layer 219 by adjusting the deposition rate and step coverage. In an embodiment, gaps Air can be formed in regions of the core insulating layer 219 adjacent to the region where a drain selection transistor is to be formed or adjacent to the region where a source selection transistor is to be formed.

[0132] Due to the gap Air, the dielectric constant of the region of the core insulating layer 219 in which the gap Air is formed can be lower than the dielectric constant of other regions of the core insulating layer 219.

[0133] Reference Figure 9D This can form a slit SI that passes through the stacked material ST. The area exposed through the slit SI... Figure 9C The sidewalls of the sacrificial layer 203 are shown. Subsequently, it can be removed via slit SI. Figure 9C The sacrificial layer 203 is shown. Therefore, an opening can be formed that exposes the side portion of the blocking insulating layer 211. The opening can be defined between the interlayer insulating layers 201.

[0134] Reference Figure 9E The gate 231 can be filled in the space (i.e., the opening) where the sacrificial layer has been removed. For example, after depositing a conductive material to fill the opening, the conductive material inside the slit can be removed, allowing the conductive material to pass through the slit and divide into the gate 231. The slit can then be filled with an insulating material to form a vertical structure 233.

[0135] Therefore, a gap Air can be formed inside the core insulating layer 219 adjacent to the drain select transistor DST or the core insulating layer 219 adjacent to the source select transistor SST. Thus, the core insulating layer 219 adjacent to the drain select transistor DST or the core insulating layer 219 adjacent to the source select transistor SST can have a relatively lower dielectric constant than the core insulating layer 219 adjacent to the memory cell.

[0136] In embodiments of this disclosure, by forming gaps Air only in localized areas, the core insulating layer 219 can be formed such that the dielectric constant of the localized areas is lower than that of other areas. However, by forming gaps Air throughout the entire area of ​​the core insulating layer 219, the entire area of ​​the core insulating layer 219 can be formed with a low dielectric constant.

[0137] Figure 10 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0138] Reference Figure 10 The memory system 1100 includes a semiconductor memory device 1120 and a memory controller 1110.

[0139] Semiconductor memory device 1120 includes multiple channel structures through a stacked structure in which multiple interlayer insulating layers and multiple gates are alternately stacked. The multiple channel structures may include a barrier insulating layer, a charge storage layer, a tunnel insulating layer, a channel layer, and a core insulating layer. In one embodiment, the dielectric constant of the core insulating layer adjacent to the drain select transistor may be lower than the dielectric constant of the core insulating layer adjacent to the memory cell and the core insulating layer adjacent to the source select transistor. In another embodiment, the dielectric constants of the core insulating layers adjacent to the drain select transistor and the core insulating layers adjacent to the source select transistor may be lower than the dielectric constant of the core insulating layer adjacent to the memory cell.

[0140] Semiconductor memory device 1120 can be like Figure 4 or Figure 7 It is configured in the same way as the semiconductor memory device shown.

[0141] The semiconductor memory device 1120 can be a multi-chip package configured with multiple flash memory chips.

[0142] The memory controller 1110 can be configured to control the semiconductor memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the memory controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. Additionally, the error correction block 1114 detects and corrects errors contained in data read from the memory device 1120, and the memory interface 1115 performs interface connections with the memory device 1120. Furthermore, the memory controller 1110 may also include a read-only memory (ROM) storing code data for interfacing with the host.

[0143] Figure 11 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0144] Reference Figure 11 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0145] Memory system 1210 may include semiconductor memory device 1212 and memory controller 1211. Semiconductor memory device 1212 includes multiple channel structures through a stacked structure in which multiple interlayer insulating layers and multiple gates are alternately stacked. The multiple channel structures may include a barrier insulating layer, a charge storage layer, an anti-trap layer, a tunnel insulating layer, a channel layer, and a core insulating layer. In one embodiment, the dielectric constant of the core insulating layer adjacent to the drain select transistor may be lower than the dielectric constant of the core insulating layer adjacent to the memory cell and the core insulating layer adjacent to the source select transistor. In another embodiment, the dielectric constants of the core insulating layers adjacent to the drain select transistor and the core insulating layers adjacent to the source select transistor may be lower than the dielectric constant of the core insulating layer adjacent to the memory cell.

[0146] Semiconductor memory device 1212 can be like Figure 4 or Figure 7 It is configured in the same way as the semiconductor memory device shown.

[0147] Although the detailed description of this disclosure describes specific embodiments, various modifications and variations can be made without departing from the scope and spirit of this disclosure. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be determined by the claims of this disclosure and their equivalents.

[0148] Cross-references to related applications

[0149] This application claims priority to Korean Patent Application No. 10-2020-0125019, filed on September 25, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A stack having multiple interlayer insulating layers and multiple gates alternately stacked on a substrate; as well as Multiple channel structures that extend vertically through the laminate. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer extending vertically in the same direction as the plurality of channel structures. Wherein, the dielectric constant of a local region of the core insulating layer is lower than the dielectric constant of other regions of the core insulating layer, and The local region corresponds to a drain-select transistor or a source-select transistor, and the other regions correspond to memory cells.

2. The semiconductor memory device according to claim 1, wherein, At least one first gate disposed at the uppermost portion of the plurality of gates corresponds to one of the drain-select transistor and the source-select transistor, and at least one second gate disposed at the lowermost portion of the plurality of gates corresponds to the other of the drain-select transistor and the source-select transistor.

3. The semiconductor memory device according to claim 2, wherein, The local region of the core insulating layer is adjacent to the first gate or the second gate.

4. The semiconductor memory device according to claim 2, wherein, The local region of the core insulating layer is adjacent to the first gate and the second gate.

5. The semiconductor memory device according to claim 1, wherein, Dopant is implanted in the local region of the core insulating layer.

6. The semiconductor memory device according to claim 5, wherein, The dopant is carbon, fluorine, or both carbon and fluorine.

7. The semiconductor memory device according to claim 1, wherein, The local area of ​​the core insulation layer includes a gap.

8. A semiconductor memory device, the semiconductor memory device comprising: A stack having a plurality of interlayer insulating layers and a plurality of gates alternately stacked on a substrate; as well as Multiple channel structures that extend vertically through the laminate. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer extending vertically in the same direction as the plurality of channel structures. At least one first gate disposed at the uppermost portion of the plurality of gates corresponds to a drain-select transistor, at least one second gate disposed at the lowermost portion of the plurality of gates corresponds to a source-select transistor, and the remaining gates of the plurality of gates correspond to memory cells. A local region in the core insulating layer adjacent to the first gate or the second gate has a lower dielectric constant than other regions adjacent to the remaining gates.

9. The semiconductor memory device according to claim 8, wherein, Dopant is implanted in the local region of the core insulating layer.

10. The semiconductor memory device according to claim 9, wherein, The dopant is carbon, fluorine, or both carbon and fluorine.

11. The semiconductor memory device according to claim 8, wherein, A gap is formed in the local area of ​​the core insulation layer.

12. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A laminate is formed by alternately stacking multiple interlayer insulating layers and multiple sacrificial layers on a substrate; Multiple holes are formed that pass through the laminate in a vertical direction; A charge storage layer, a tunnel insulation layer, and a channel layer are sequentially formed on the sidewall of each of the plurality of holes; A core insulating layer is formed on the sidewall of the channel layer to fill the central region of the plurality of holes; as well as Dopant is implanted into localized regions such that the dielectric constant of these localized regions of the core insulating layer is lower than that of other regions of the core insulating layer. The local region corresponds to a drain-select transistor or a source-select transistor, and the other regions correspond to memory cells.

13. The method of claim 12, further comprising the step of: Remove the plurality of sacrificial layers; and A gate is formed in the space where the sacrificial layer has been removed.

14. The method according to claim 13, wherein, The at least one first gate disposed at the lowest portion of the gate and the at least one second gate disposed at the highest portion of the gate correspond to a selection transistor.

15. The method according to claim 14, wherein, The local region is the area in the core insulating layer adjacent to the first gate or the second gate.

16. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A laminate is formed by alternately stacking multiple interlayer insulating layers and multiple sacrificial layers on a substrate; Multiple holes are formed that pass through the laminate in a vertical direction; A charge storage layer, a tunnel insulation layer, and a channel layer are sequentially formed on the sidewall of each of the plurality of holes; as well as A core insulating layer is formed on the sidewalls of the channel layer to fill the central region of the plurality of holes. The step of forming the core insulating layer includes forming a gap in a local region of the core insulating layer, the local region corresponding to a drain-select transistor or a source-select transistor. The dielectric constant of a local region of the core insulating layer is lower than the dielectric constant of other regions of the core insulating layer corresponding to the memory cell.

17. The method of claim 16, further comprising the step of: Remove the plurality of sacrificial layers; and A gate is formed in the space where the sacrificial layer has been removed.

18. The method according to claim 17, wherein, The at least one first gate disposed at the lowest portion of the gate and the at least one second gate disposed at the highest portion of the gate correspond to a selection transistor.

19. The method according to claim 18, wherein, The local region is the area in the core insulating layer adjacent to the first gate or the second gate.

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