Backplane

Abstract

The present invention provides a backplane. The backplane includes a substrate and pixel structures arranged in an array on the substrate; the pixel structures include power lines, gate lines and data lines that intersect in rows and columns, an anode of the backplane located on the substrate, a driving transistor electrically connected to the anode, and a switching transistor electrically connected to the driving transistor; the width direction of the channel in the active layer pattern of the driving transistor is the row direction, and in the row direction, the channel extends from the data line on one side of the pixel structure to the power line on the other side of the pixel structure. The pixel structure provided by the present invention can reduce the area of the pixel structure and increase the aspect ratio of the TFT (thin film transistor), so as to improve the driving ability of the driving transistor and the resolution of the backplane.

Description

Technical Field

[0001] The present invention relates to the field of display technology or 3D printing technology, and particularly to a backplane. Background Art

[0002] In the prior art, when manufacturing a backplane, when the size of the pixel region occupied by the pixel structure in the backplane is small, it is impossible to reasonably layout the driving transistor and the switching transistor in the pixel structure, resulting in the inability to increase the aspect ratio of the driving transistor and the inability to improve the driving ability of the driving transistor. Summary of the Invention

[0003] The main object of the present invention is to provide a backplane to solve the problem in the prior art that when manufacturing a backplane, when the size of the pixel region occupied by the pixel structure in the backplane is small, the aspect ratio of the driving transistor cannot be increased.

[0004] To achieve the above object, the present invention provides a backplane, which includes a substrate and pixel structures arranged in an array on the substrate;

[0005] The pixel structure includes a power line, gate lines and data lines arranged in a row-column interleaved manner, an anode of the backplane located on the substrate, a driving transistor electrically connected to the anode, and a switching transistor electrically connected to the driving transistor;

[0006] The gate lines extend along the row direction of the array and are located on the side of the pixel structure close to the next row of pixel structures; the data lines extend along the column direction of the array, and the power line includes a power line extending along the column direction; the data lines and the power line extending along the column direction are located on opposite sides of the pixel structure;

[0007] In the pixel region where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction;

[0008] The gate of the driving transistor extends from the data line to the power line direction in the row direction, and the gate of the driving transistor extends from the gate line of the upper row of pixel structures to the direction of the switching transistor in the column direction;

[0009] The width direction of the channel in the active layer pattern of the driving transistor is the row direction, and the channel extends from the data line on one side of the pixel structure to the power line on the other side of the pixel structure in the row direction;

[0010] The source and the drain of the driving transistor extend along the row direction respectively, and the source and the drain of the driving transistor are arranged in sequence along the column direction;

[0011] The gate of the driving transistor is connected to the drain of the switching transistor, the source of the driving transistor is electrically connected to the power supply line, and the drain of the driving transistor is electrically connected to the anode;

[0012] The source of the switching transistor is electrically connected to the data line, and the gate of the switching transistor is electrically connected to the gate line. Compared with the prior art, the backplane according to the embodiment of the present invention can make the gate of the driving transistor occupy most of the area in the column direction of the pixel region, and the driving transistor and the switching transistor are compactly arranged, and the channel in the active layer pattern of the driving transistor extends in the row direction from the data line located on one side of the pixel structure to the power supply line located on the other side of the pixel structure, so that the aspect ratio of the driving transistor is large to improve the driving ability of the driving transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram of an embodiment of a pixel structure in the backplane according to at least one embodiment of the present invention;

[0014] Figure 2 is a layout schematic diagram of the backplane according to at least one embodiment of the present invention;

[0015] Figure 3 is another layout schematic diagram of the backplane according to at least one embodiment of the present invention;

[0016] Figure 4 and Figure 5 is Figure 2 a top view of the gate metal layer in;

[0017] Figure 6 is Figure 2 a top view of the active layer in;

[0018] Figure 7 is Figure 2 a top view of the source-drain metal layer in;

[0019] Figure 8 is Figure 3 a top view of the conductive layer in;

[0020] Figure 9 is a top view of an embodiment of the conductive layer;

[0021] Figure 10 is Figure 2 a top view of the capacitor electrode layer in;

[0022] Figure 11 is Figure 2 a top view of the anode layer in;

[0023] Figure 12 is inFigure 3 Schematic diagram showing the addition of reference numerals to each via hole on the basis of the embodiment of the backplane shown;

[0024] Figure 13 is based on Figure 3 Schematic diagram showing the addition of the A-A' sectional line on the basis of

[0025] Figure 14 is Figure 13 Cross-sectional view of the backplane shown in the A-A' direction;

[0026] Figure 15A Schematic layout diagram of a backplane according to at least one embodiment of the present invention;

[0027] Figure 15B is Figure 15A Cross-sectional view of the backplane shown in the B-B' direction;

[0028] Figure 16 is Figure 3 Top view of another conductive layer used in the embodiment of the backplane shown. Detailed implementation manner

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0030] The backplane provided by the present application can be used at least for the printing backplane in a 3D printing system. The backplane is provided with printing anodes, which are distributed in an array, and the backplane drives the anodes to realize 3D printing. Or the backplane provided by the present application can be used at least in the display field to drive pixel electrodes (at this time, the anode of the backplane can be a pixel electrode, but not limited thereto) to realize liquid crystal display or OLED (organic light emitting diode) display.

[0031] The backplane according to the embodiment of the present invention may include a pixel structure disposed on a substrate; as Figure 1 shown, the pixel structure may include a driving transistor T1, a switching transistor T2, a storage capacitor C1, and an anode 10;

[0032] The gate G1 of the driving transistor T1 is electrically connected to the first electrode plate C1a of the storage capacitor C1. The source S1 of the driving transistor T1 is electrically connected to the power supply line V1. The drain D1 of the driving transistor T1 is electrically connected to the anode 10;

[0033] The gate G2 of the switching transistor T2 is electrically connected to the gate line G0, the source S2 of the switching transistor T2 is electrically connected to the data line D0, and the drain D2 of the switching transistor T2 is electrically connected to the first electrode C1a of the storage capacitor C1;

[0034] The second electrode C1b of the storage capacitor C1 is electrically connected to the anode 10.

[0035] As Figure 1 When the embodiment of the pixel structure shown is in operation, under the control of the gate driving signal provided by the gate line G0, T2 is turned on to supply the data voltage on the data line D0 to the gate of T1. T1 controls the connection or disconnection between the power supply line V1 and the pixel electrode 10 under the control of the potential of its gate; C1 is used to maintain the potential of the gate of T1.

[0036] The backplane according to the embodiment of the present invention includes a substrate and pixel structures arranged in an array on the substrate;

[0037] The pixel structure includes a power supply line, gate lines and data lines that intersect in rows and columns, an anode of the backplane located on the substrate, a driving transistor electrically connected to the anode, and a switching transistor electrically connected to the driving transistor;

[0038] The gate lines extend along the row direction of the array and are located on one side of the pixel structure close to the next row of pixel structures; the power supply line includes a power supply line extending along the column direction; the data line and the power supply line extending along the column direction are located on opposite sides of the pixel structure;

[0039] In the pixel region where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction;

[0040] The gate of the driving transistor extends from the data line to the power supply line direction in the row direction, and the gate of the driving transistor extends from the gate line of the upper row of pixel structures to the direction of the switching transistor in the column direction;

[0041] The width direction of the channel in the active layer pattern of the driving transistor is the row direction, and the channel extends from the data line on one side of the pixel structure to the power supply line on the other side of the pixel structure in the row direction;

[0042] The source and drain of the driving transistor extend along the row direction respectively, and the source and drain of the driving transistor are arranged in sequence along the column direction; the source and drain of the driving transistor are disposed between the active layer pattern of the driving transistor and the substrate, or the source and drain of the driving transistor are disposed on a side of the active layer pattern away from the substrate.

[0043] The gate of the driving transistor is connected to the drain of the switching transistor, the source of the driving transistor is electrically connected to the power supply line, and the drain of the driving transistor is electrically connected to the anode.

[0044] The source of the switching transistor is electrically connected to the data line, and the gate of the switching transistor is electrically connected to the gate line.

[0045] In the backplane according to the embodiment of the present invention, in the pixel region where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction, and in the row direction of the gate of the driving transistor, it extends from the data line on one side of the pixel structure to the power supply line on the other side of the pixel structure, so as to occupy most of the row direction of the pixel region, and the gate of the driving transistor extends from the gate line of the pixel structure in the upper row to the direction of the switching transistor in the column direction, so that the gate of the driving transistor occupies most of the column direction of the pixel region, and the driving transistor and the switching transistor are compactly arranged, and the channel in the active layer pattern of the driving transistor extends from the data line on one side of the pixel structure to the power supply line on the other side of the pixel structure in the row direction, so that the aspect ratio of the driving transistor is large to improve the driving ability of the driving transistor.

[0046] In the embodiment of the present invention, the source and drain of the driving transistor can be disposed on the source-drain metal layer, and the source-drain metal layer can be disposed between the active layer of the driving transistor and the substrate, or the source-drain metal layer can be disposed on a side of the active layer away from the substrate.

[0047] In specific implementation, the data line and the power supply line extending along the column direction are located on opposite sides of the pixel structure, the data line can be located on the first side of the pixel structure, and the power supply line extending along the column direction can be located on the second side of the pixel structure, and the first side and the second side are opposite sides.

[0048] In an embodiment of the present invention, the gate of the driving transistor extending from the data line towards the power supply line in the row direction means that: in the row direction, the extending direction of the gate of the driving transistor is from the data line towards the power supply line. Here, the data line may be a data line located on the first side of the pixel structure where the driving transistor is located, and the power supply line may be a power supply line extending in the column direction located on the second side of the pixel structure where the driving transistor is located, but not limited thereto.

[0049] In an embodiment of the present invention, the gate of the driving transistor extending from the gate line of the pixel structure in the upper row towards the switching transistor in the column direction means that: in the column direction, the extending direction of the gate of the driving transistor is from the gate line of the pixel structure in the upper row towards the switching transistor.

[0050] In an embodiment of the present invention, the channel extending from the data line located on one side of the pixel structure towards the power supply line located on the other side of the pixel structure in the row direction means that: in the row direction, the extending direction of the channel is from the data line located on one side of the pixel structure towards the power supply line located on the other side of the pixel structure.

[0051] In specific implementation, the gate line has a first protrusion, and the data line has a second protrusion.

[0052] The width direction of the channel of the active layer pattern of the switching transistor is perpendicular to the width direction of the channel of the driving transistor. The gate of the switching transistor is the first protrusion, and the source of the switching transistor is the second protrusion.

[0053] The drain of the switching transistor and the extension part are of an integral structure. The extension part extends towards the power supply line, and the orthographic projection of the extension part on the substrate partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate. The drain of the switching transistor is electrically connected to the gate of the driving transistor through a via hole.

[0054] During actual operation, the gate of the switching transistor is the first protrusion of the gate line, the source of the switching transistor is the second protrusion of the data line, and the drain of the switching transistor is electrically connected to the gate of the driving transistor through the extension part. The extension part extends towards the power supply line, so that the layout of the switching transistor and the driving transistor is compact.

[0055] As Figure 2 shown, the backplane described in the embodiment of the present invention includes a substrate and pixel structures arranged in an array on the substrate.

[0056] The left pixel structure (the left pixel structure isFigure 2 The first pixel structure 21 on the left side in

[0057] includes a power supply line, a first gate line G01 and a first data line D01 that are arranged in a row-column interleaved manner, an anode 10 of the backplane located on the substrate, a driving transistor electrically connected to the anode 10, and a switching transistor electrically connected to the driving transistor;

[0058] In the pixel region where the first pixel structure 21 is located, the driving transistor and the switching transistor are arranged in sequence along the column direction;

[0059] As Figure 2 and Figure 4 shown, the gate G1 of the driving transistor in the first pixel structure 21 extends in the row direction from the first data line D01 towards the power supply line V1, and the gate G1 of the driving transistor extends in the column direction from the gate line of the upper row of pixel structures (in Figure 2 , the gate line of the upper row of pixel structures is the second gate line G02) towards the switching transistor;

[0060] As Figure 2 and Figure 6 shown, the width direction of the channel 511 in the active layer pattern of the driving transistor is the row direction, and the channel 511 extends in the row direction from the first data line D01 towards the power supply line V1;

[0061] As Figure 2 and Figure 7 shown, the source S1 and the drain D1 of the driving transistor extend along the row direction respectively, and the source S1 and the drain D1 of the driving transistor are arranged in sequence along the column direction; the source S1 and the drain D1 of the driving transistor are both located in the source-drain metal layer, and the source-drain metal layer is provided on the side of the active layer away from the substrate;

[0062] As Figure 2 and Figure 4 shown, the first gate line G01 has a first protrusion, the main body of the first gate line G01 extends in the row direction, and the first protrusion protrudes from the main body of G01, and the gate G2 of the switching transistor is the first protrusion;

[0063] AsFigure 2 and Figure 7 As shown in Figure 7 , the first data line D01 has a second protrusion. The main body of the first data line D01 extends in the column direction, and the second protrusion protrudes from the main body of D01. The source S2 of the switching transistor is the second protrusion.

[0064] As Figure 2 , Figure 4 and Figure 7 As shown in Figure 2 , Figure 4 , and Figure 7 , the gate G2 of the switching transistor is the first protrusion, and the source S2 of the switching transistor is the second protrusion, so that the position occupied by the switching transistor is small.

[0065] In a preferred case, two adjacent pixel structures in the same row of pixel structures are mirror - set, and symmetric pixel structures are adopted to save pixel area and increase the aspect ratio of the driving transistor.

[0066] Optionally, the two adjacent pixel structures can be mirror - set on opposite sides of the power line, or the adjacent pixel structures can also be mirror - set on opposite sides of the data line.

[0067] In a specific implementation, two adjacent pixel structures in a row of pixel structures can be mirror - set on both sides of the power line; two pixel structures mirror - set on both sides of the power line share one power line, and the power line is located between the two driving transistors of the mirror - set; the data lines in the two pixel structures mirror - set on both sides of the power line are located on the side of the pixel structure away from the power line.

[0068] In an embodiment of the present invention, when two adjacent pixel structures are mirror - set on both sides of the power line, the two adjacent pixel structures can share the power line to save pixel area; and, the first data line in the first pixel structure is located on the side of the first pixel structure away from the power line, and the second data line in the second pixel structure is located on the side of the second pixel structure away from the power line, so as to increase the area of the pixel structure and be beneficial to increasing the aspect ratio of the driving transistor in the pixel structure. Among them, the first pixel structure and the second pixel structure are mirror - set on both sides of the power line.

[0069] Optionally, the sources of the two driving transistors in the two mirror - set pixel structures are connected and are an integral structure, and the two driving transistors in the two mirror - set pixel structures can share the source, so as to increase the aspect ratio of the driving transistor.

[0070] As Figure 2As shown, the first pixel structure 21 and the second pixel structure 22 are mirror - arranged on both sides of the power line V1; the first pixel structure 21 and the second pixel structure 22 share the power line V1; the power line is located between the driving transistors included in the first pixel structure 21 and the driving transistors included in the second pixel structure 22; the first pixel structure 21 includes a first data line D01, and the second pixel structure 22 includes a second data line D02. The first data line D01 is located on the side of the first pixel structure 21 away from the power line V1, and the second data line D02 is located on the side of the second pixel structure 22 away from the power line V1.

[0071] As Figure 2 and Figure 7 shown, the source S1 of the driving transistor in the first pixel structure 21 is connected to the source of the driving transistor in the second pixel structure 22, and the source S1 of the driving transistor in the first pixel structure 21 and the source of the driving transistor in the second pixel structure 22 are of an integral structure.

[0072] Optionally, the length of the gate of the driving transistor in the column direction is greater than the length of the active layer pattern of the driving transistor in the column direction, such that the gate of the driving transistor extends towards the switching transistor relative to the active layer, and there is no overlapping area between the extended part of the gate of the driving transistor and the projection of the active layer pattern of the driving transistor on the substrate; the drain of the driving transistor is electrically connected to the anode through a capacitive electrode layer; the capacitive electrode layer and the extended part of the gate have an overlapping area on the substrate, and the capacitive electrode layer and at least the extended part of the gate form a capacitor.

[0073] In specific implementation, the capacitive electrode layer serves both as a connection layer and as an electrode of the storage capacitor.

[0074] As Figure 2 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 10 shown, the length of the gate G1 of the driving transistor in the column direction is greater than the length of the active layer pattern 51 of the driving transistor in the column direction, such that the gate G1 of the driving transistor extends towards the switching transistor relative to the active layer, and there is no overlapping area between the extended part 40 of the gate G1 and the projection of the active layer pattern 51 of the driving transistor on the substrate; the drain D1 of the driving transistor is electrically connected to the anode 10 through a capacitive electrode layer;

[0075] As Figure 2 、 Figure 4 、 Figure 5 and Figure 10As shown, the capacitive electrode layer and the extension portion 40 of the gate G1 have an overlapping area on the substrate, and the capacitive electrode layer and at least the extension portion 40 of the gate form a capacitor.

[0076] Optionally, the capacitive electrode layer is located between the drain of the driving transistor and the anode. A first insulating layer is provided between the capacitive electrode layer and the drain of the driving transistor, and a second insulating layer is provided between the capacitive electrode layer and the anode;

[0077] The capacitive electrode layer is electrically connected to the drain of the driving transistor through a via provided in the first insulating layer, and the capacitive electrode layer is electrically connected to the anode through a via in the second insulating layer;

[0078] Among them, the orthographic projection of the capacitive electrode layer on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate to form a capacitor.

[0079] Optionally, the drain of the driving transistor is located in the source-drain metal layer, the anode is located in the anode layer, the capacitive electrode layer A9 is located between the source-drain metal layer A4 and the anode layer A11. A first insulating layer A5 is provided between the capacitive electrode layer A9 and the source-drain metal layer A4, and a second insulating layer A10 is provided between the capacitive electrode layer A9 and the anode layer A11. The capacitive electrode layer A9 is electrically connected to the drain of the driving transistor through a via, and the capacitive electrode layer A9 is electrically connected to the anode through a via, and the orthographic projection of the capacitive electrode layer A9 on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate to form a capacitor.

[0080] In an embodiment of the present invention, the power supply line is formed of the same layer and the same material as the capacitive electrode layer, so that there is enough space in the source-drain metal layer to set the source of the driving transistor and the drain of the driving transistor, so that the aspect ratio of the driving transistor can be set to be larger to improve the driving ability of the driving transistor.

[0081] In an embodiment of the present invention, the backplane further includes the first insulating layer, the organic resin layer, the conductive layer and the third insulating layer sequentially provided between the drain of the driving transistor and the capacitive electrode layer;

[0082] The organic resin layer and the conductive layer are used to block hydrogen; the orthographic projection of the organic resin layer on the substrate covers the orthographic projection of the active layer pattern on the substrate, and the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the active layer pattern on the substrate; the organic resin layer and the conductive layer prevent the active layer pattern from being damaged;

[0083] The drain of the driving transistor is electrically connected to the conductive layer through a via hole penetrating the first insulating layer and the organic resin layer, and the conductive layer is electrically connected to the capacitive electrode layer through a via hole penetrating the third insulating layer.

[0084] During actual operation, the organic resin layer is used to enhance the ability to block hydrogen and improve the stability of the backplane; the conductive layer covers the organic resin layer to enhance the ability to block hydrogen and can also prevent the lamination of the capacitive electrode layer from affecting the organic resin layer.

[0085] Optionally, the conductive layer can be made of ITO (indium tin oxide), and the organic resin layer can be made of an organic insulating material, but not limited thereto.

[0086] Such as Figure 3 and Figure 14 As shown in

[0087] The drain of the driving transistor is located in the source-drain metal layer A4. The backplane according to the embodiment of the present invention further includes the first insulating layer A5, the organic resin layer A6, the conductive layer A7, and the third insulating layer A8 sequentially disposed between the source-drain metal layer A4 and the capacitive electrode layer A9;

[0088] The drain of the driving transistor is electrically connected to the conductive layer A7 through a via hole penetrating the first insulating layer A5 and the organic resin layer A6, and the conductive layer A7 is electrically connected to the capacitive electrode layer A9 through a via hole penetrating the third insulating layer A8.

[0089] In a specific implementation, the gates of the driving transistor, the switching transistor, and the gate line can be disposed on the same metal layer on the substrate; the active layer patterns of the driving transistor and the switching transistor can be disposed above the metal layer where the gate is located; the source and drain of the driving transistor, the source and drain of the switching transistor are all disposed on the same layer; the power supply line and the capacitive electrode layer are disposed on the same layer, the power supply line is located above the source of the driving transistor, and the anode is disposed above the power supply line and the capacitive electrode layer;

[0090] The drain of the driving transistor is electrically connected to the anode through the capacitive electrode layer, and the positive projection of the capacitive electrode layer on the substrate has an overlapping area with the positive projection of the extension of the gate of the driving transistor relative to the active layer on the substrate, forming a capacitor;

[0091] The drain of the switching transistor is electrically connected to the gate of the driving transistor through an extension extending in the direction of the power supply line.

[0092] In the embodiment of the present invention, as Figure 2 、 Figure 3 、 Figure 4 and Figure 14 shown, the gate G1 of the driving transistor, the gate G2 of the switching transistor, the first gate line G01 and the second gate line G02 can be arranged in the gate metal layer A1; as Figure 2 、 Figure 3 、 Figure 6 and Figure 14 shown, the active layer pattern 51 of the driving transistor and the active layer pattern of the switching transistor are arranged in the active layer A3; as Figure 2 、 Figure 3 、 Figure 7 and Figure 14 shown, the source S1 of the driving transistor, the drain D1 of the driving transistor, the source S2 of the switching transistor and the drain D2 of the switching transistor are all arranged in the source-drain metal layer A4; as Figure 2 、 Figure 3 、 Figure 10 and Figure 14 shown, the power supply line V1 and the capacitive electrode layer A9 are arranged on the same layer and made of the same material; as Figure 2 、 Figure 3 、 Figure 11 and Figure 14 shown, the anode is located in the anode layer A11;

[0093] The gate metal layer A1, the active layer A3, the source-drain metal layer A4, the capacitive electrode layer A9 and the anode layer A11 can be sequentially arranged on the substrate.

[0094] The drain of the driving transistor located in the source-drain metal layer A4 is electrically connected to the anode located in the anode layer A11 through the capacitive electrode layer A9. As Figure 2 、 Figure 4 、 Figure 5 and Figure 10 shown, the positive projection of the capacitive electrode layer on the substrate has an overlapping area with the positive projection of the extension 40 of the gate G1 of the driving transistor relative to the active layer on the substrate, forming a capacitor.

[0095] In specific implementation, adjacent pixel structures in the same row are mirror - arranged on both sides of the power line;

[0096] Two pixel structures mirror - arranged on both sides of the power line share one power line, and the power line is located between the two driving transistors arranged in mirror; the sources of the two driving transistors arranged in mirror extend from one pixel structure to another along the row direction, and the sources of the two driving transistors are an integral structure;

[0097] The power line further includes a first conductive connection part, and the source of the first driving transistor among the two driving transistors arranged in mirror is electrically connected to the source of the second driving transistor among the two driving transistors arranged in mirror through a second conductive connection part;

[0098] At least part of the orthographic projection of the first conductive connection part on the substrate overlaps with the orthographic projection of the second conductive connection part on the substrate, and the first conductive connection part is electrically connected to the second conductive connection part through a via hole, so that the source of the driving transistor is electrically connected to the power line.

[0099] As Figure 2 and Figure 3 shown, the first pixel structure 21 and the second pixel structure 22 are mirror - arranged on both sides of the power line V1;

[0100] The first pixel structure 21 and the second pixel structure 22 share one power line V1, and the power line V1 is located between the driving transistor of the first pixel structure 21 and the driving transistor of the second pixel structure 22; the source S1 of the driving transistor of the first pixel structure 21 extends from the first pixel structure 21 to the second pixel structure 22 along the row direction, and the power line V1 is an integral structure with the driving transistors of the first pixel structure 21 and the second pixel structure 22;

[0101] As Figure 7 shown, the source S1 of the driving transistor of the first pixel structure 21 is electrically connected to the source of the driving transistor of the second pixel structure 22 through a second conductive connection part L2;

[0102] The power line further includes a first conductive connection part L1, at least part of the orthographic projection of the first conductive connection part L1 on the substrate overlaps with the orthographic projection of the second conductive connection part L2 on the substrate, and the first conductive connection part L1 is electrically connected to the second conductive connection part L2 through a via hole, so that the source S1 of the driving transistor is electrically connected to the power line V1.

[0103] In the embodiment of the present invention, the backplane may further include:

[0104] An isolation layer disposed above the active layer pattern of the driving transistor, the isolation layer being used to isolate the influence of impurities on the active layer pattern of the driving transistor; the isolation layer is a single-layer isolation layer or a multi-layer isolation layer, and the single-layer isolation layer or multi-layer isolation layer includes at least one of an organic resin layer, a metal layer or a metal oxide active layer.

[0105] In a specific implementation, an isolation layer is disposed above the active layer of the driving transistor, and the isolation layer can isolate the influence of impurities on the active layer pattern of the driving transistor.

[0106] Optionally, the isolation layer can be a single-layer isolation layer, or the isolation layer can also be a multi-layer isolation layer, and the isolation layer can include at least one of an organic resin layer, a metal layer or a metal oxide active layer.

[0107] Optionally, the multi-layer isolation layer is a double-layer isolation layer, and the double-layer isolation layer includes an organic resin layer and a metal oxide active layer sequentially disposed above the active layer.

[0108] In a specific implementation, the metal oxide active layer or the metal layer in the isolation layer includes an isolation portion disposed above the active layer pattern of the driving transistor in each pixel structure;

[0109] The isolation portions are independent of each other, or the isolation portions are integrally provided.

[0110] When the isolation layer adopts a metal oxide active layer or a metal layer, the isolation layer includes an isolation portion, the isolation portion is disposed above the active layer pattern of the driving transistor, and the multiple isolation portions included in the isolation layer can be independent of each other or integrally provided, and the structure of the isolation portion is not limited thereto.

[0111] In an embodiment of the present invention, the backplane may further include the first insulating layer, an organic resin layer, a conductive layer containing metal, and a third insulating layer sequentially disposed between the drain electrode of the driving transistor and the capacitor electrode layer; a second insulating layer is provided between the capacitor electrode layer and the anode;

[0112] The organic resin layer and the conductive layer serve as a protective layer for the active layer pattern of the driving transistor to block hydrogen; the orthographic projection of the organic resin layer on the substrate covers the orthographic projection of the active layer pattern of the driving transistor on the substrate, and the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the active layer pattern of the driving transistor on the substrate;

[0113] The vias between the first conductive connection part and the second conductive connection part include a first via, a second via, and a third via; the first via is a via penetrating the first insulating layer, the second via is a via penetrating the organic resin layer, and the third via is a via penetrating the third insulating layer;

[0114] The orthographic projection of the first via on the substrate, the orthographic projection of the second via on the substrate, and the orthographic projection of the third via on the substrate at least partially overlap, so that the first conductive connection part and the second conductive connection part are electrically connected.

[0115] In Figure 12 the numbers H01, H02, and H03 are respectively the first via, the second via, and the third via.

[0116] As Figure 14 shown, the orthographic projection of the first via H01 on the substrate is within the orthographic projection of the second via H02 on the substrate, and the orthographic projection of the third via on the substrate is within the orthographic projection of the second via H02 on the substrate.

[0117] As Figure 14 shown, the backplane may include a conductive layer A7 and an organic resin layer A6; the conductive layer A7 is disposed on the side of the capacitive electrode layer A9 away from the substrate 20; the organic resin layer A6 is disposed between the conductive layer A7 and the source-drain metal layer A4; the backplane further includes a first insulating layer A5 disposed between the source-drain metal layer A4 and the organic resin layer A6 and a third insulating layer A8 disposed between the conductive layer A7 and the capacitive electrode layer A9; the vias include a first via H01, a second via H02, and a third via H03.

[0118] In Figure 14 the number A1 is the gate metal layer, the number A2 is the gate insulating layer, the number A3 is the active layer, the number A10 is the second insulating layer, and the number A11 is the anode layer.

[0119] Optionally, both the first insulating layer and the third insulating layer can be passivation layers, but not limited thereto.

[0120] As Figure 12 and Figure 14 shown, the orthographic projection of the first via H01 on the substrate 20 is within the orthographic projection of the second via H02 on the substrate 20, and the orthographic projection of the third via H03 on the substrate 20 is within the orthographic projection of the second via H02 on the substrate 20.

[0121] In an embodiment of the present invention, due to process limitations, the area of the orthographic projection of H02 on the substrate is set to be larger than the area of the orthographic projection of H01 on the substrate, and the area of the orthographic projection of H02 on the substrate is set to be larger than the area of the orthographic projection of H03 on the substrate, so as to ensure that H01 can be completely presented and completely etched.

[0122] In a specific implementation, as Figure 8 shown, the conductive layer may include a plurality of independent conductive patterns 30; the orthographic projection of the conductive pattern 30 on the substrate covers the pixel region provided with the pixel structure. Moreover, the openings between the conductive patterns 30 may expose the first conductive connection portion L1 and the second conductive connection portion L2 to avoid short circuits.

[0123] In a specific implementation, the active layer may be a metal oxide active layer, but is not limited thereto.

[0124] Optionally, the active layer may be an IGZO layer, wherein the atomic ratio of indium, gallium, zinc, and oxygen may be 1:1:1:4, but is not limited thereto.

[0125] Optionally, the active layer may be made of IGZXO, where X is a metal.

[0126] In a specific implementation, the active layer may be made of IGZXO, adding a metal on the basis of IGZO (indium gallium zinc oxide) to enhance the corrosion resistance of the source and drain of the transistor to acid during etching, reduce the damage to the back channel, and improve the stability of the TFT (thin film transistor).

[0127] In an embodiment of the present invention, the backplane may include a gate metal layer, the active layer, the source-drain metal layer, the capacitor electrode layer, and the anode layer sequentially disposed on the substrate. The gate metal layer includes gate lines, the gate of the driving transistor, and the gate of the switching transistor. The gate of the driving transistor is multiplexed as the first electrode plate of the storage capacitor. The active layer includes the active layer pattern of the driving transistor and the active layer pattern of the switching transistor. The capacitor electrode layer includes a power line and the first electrode plate portion of the second electrode plate of the storage capacitor. The source-drain metal layer includes the source of the driving transistor, the drain of the driving transistor, the source of the switching transistor, the drain of the switching transistor, and the second electrode plate portion of the second electrode plate of the storage capacitor. The anode layer includes a plurality of independent anodes.

[0128] In the embodiment of the present invention, a stacked structure of a gate metal layer, a capacitor electrode layer, and a source-drain metal layer is adopted to form a capacitor, so as to solve the problem that the source electrode of the driving transistor, the drain electrode of the driving transistor, the source electrode of the switching transistor, the drain electrode of the switching transistor, and the second electrode plate of the storage capacitor cannot be disposed only on the same layer due to the small area of the pixel structure.

[0129] As Figure 2 and Figure 3 shown, the first pixel structure 21 and the second pixel structure 22 are mirror-symmetrically disposed on both sides of a power line V1 extending in the column direction; the first pixel structure 21 and the second pixel structure 22 are disposed in the same row; the first pixel structure 21 includes a driving transistor, a switching transistor, and a first data line D01; the second pixel structure 22 includes a driving transistor, a switching transistor, and a second data line D02;

[0130] The first pixel structure 21 and the second pixel structure 22 share the first gate line G01 and the power line V1; pixel structures in the same column can share the same data line.

[0131] As Figure 2 shown, the backplane includes a gate metal layer A1, an active layer A3, a source-drain metal layer A4, a capacitor electrode layer A9, and an anode layer A11 that are sequentially disposed above a substrate 20;

[0132] Figure 4 and Figure 5 is Figure 2 a top view of the gate metal layer in Figure 6 is Figure 2 a top view of the active layer in Figure 7 is Figure 2 a top view of the source-drain metal layer in Figure 10 is Figure 2 a top view of the capacitor electrode layer in Figure 11 is Figure 2 a top view of the anode layer in

[0133] Figure 3 The embodiment of the backplane shown in Figure 2 is different from the embodiment of the backplane shown in

[0134] In Figure 4 and Figure 5 , the one labeled G01 is the first gate line, the one labeled G02 is the second gate line, and the one labeled G1 is the gate of the driving transistor in the first pixel structure 21. The gate G1 of the driving transistor in the first pixel structure 21 is multiplexed as the first electrode plate of the storage capacitor; in Figure 4 and Figure 5Among them, the gate labeled G2 is the gate of the switching transistor in the first pixel structure 21, and the gate G2 of the switching transistor in the first pixel structure 21 is the protrusion of G01; in Figure 6 Among them, the one labeled 51 is the active layer pattern of the driving transistor in the first pixel structure 21; the one labeled 52 is the active layer pattern of the switching transistor in the first pixel structure 21; in Figure 7 Among them, the one labeled S1 is the source of the driving transistor in the first pixel structure 21, the one labeled D1 is the drain of the driving transistor in the first pixel structure 21, the one labeled S2 is the source of the switching transistor in the first pixel structure 21, the one labeled D2 is the drain of the switching transistor in the first pixel structure 21, and the one labeled L3 is the extension part, and the extension part L3 is electrically connected to D2; in Figure 7 Among them, S2 is the protrusion of D01. In Figure 8 Among them, the one labeled 30 is the conductive pattern included in the conductive layer. In Figure 10 Among them, the one labeled L1 is the first conductive connection part, and the one labeled V1 is the power supply line arranged along the column direction. In Figure 11 Among them, the one labeled 10 is the anode.

[0135] As Figure 4 and Figure 5 shown, the main body part of G01 is a linear part extending along the row direction, G2 and the main body part of G01 are an integral structure and protrude from the main body part of G01. As Figure 7 shown, the main body part of D01 is a linear part extending along the column direction, S2 and the main body part of D01 are an integral structure and protrude from the main body part of D01.

[0136] In the embodiment of the present invention, the column direction can be the vertical direction, the row direction can be the horizontal direction, the first side can be the left side, and the second side can be the right side, but it is not limited thereto.

[0137] As Figure 2 and Figure 3 shown, the first pixel structure 21 and the second pixel structure are mirror - set on the opposite sides of the power supply line V1. Symmetrical pixel structures are adopted to save pixel area. In the embodiment of the present invention, the power supply line is arranged in the capacitive electrode layer to further save pixel area and achieve better resolution; moreover, in the embodiment of the present invention, low - resistance metal is used to make the power supply line, and the line width of the power supply line is enlarged as much as possible to reduce the IR drop (IR drop is a phenomenon of voltage drop or rise in the power supply and ground networks in an integrated circuit) under large current and improve the uniformity of large - size backplanes.

[0138] As Figure 2 、 Figure 3 、 Figure 4 、Figure 5 , Figure 6 and Figure 7 As shown in Figure 7 , the active layer pattern of the driving transistor includes a first channel portion 511, a first electrode contact portion 512, and a second electrode contact portion 513;

[0139] The positive projection of the source S1 of the driving transistor on the substrate at least partially overlaps with the positive projection of the first electrode contact portion 512 on the substrate, and the positive projection of the drain D1 of the driving transistor on the substrate at least partially overlaps with the positive projection of the second electrode contact portion 513 on the substrate;

[0140] The source S1 of the driving transistor is in direct contact with the first electrode contact portion 512, and the drain D1 of the driving transistor is in direct contact with the second electrode contact portion 513;

[0141] The first channel portion 511 is disposed between the first electrode contact portion 512 and the second electrode contact portion 513;

[0142] The first channel portion 511 extends in the row direction.

[0143] As Figure 6 shown, the ratio between the width of the first channel portion 511 in the row direction and the length of the first channel portion 511 in the column direction (this ratio is also the aspect ratio of the driving transistor) is greater than a predetermined ratio.

[0144] In an embodiment of the present invention, the power supply line and the capacitor electrode layer are provided on the same layer and made of the same material, so that there is enough space in the source-drain metal layer to set the source of the driving transistor and the drain of the driving transistor, thereby enabling the aspect ratio of the driving transistor to be set to a larger value to improve the driving ability.

[0145] In Figure 2 and Figure 3 the embodiment shown, the aspect ratio of the driving transistor can be greater than or equal to 4 and less than or equal to 8. For example, the aspect ratio of the driving transistor can be equal to 5, but not limited thereto.

[0146] In an embodiment of the present invention, the predetermined ratio can be greater than or equal to 1 and less than or equal to 12.5, but not limited thereto.

[0147] As Figure 7 shown, the drain D1 of the driving transistor and the second plate portion C1b2 are an integral structure;

[0148] As Figure 2 , Figure 3 , Figure 7 and Figure 10As shown, there is a first overlapping region between the orthographic projection of the first electrode plate portion C1b1 on the substrate and the orthographic projection of the second electrode plate portion C1b2 on the substrate; the first electrode plate portion C1b1 is independent of the power supply line V1;

[0149] The first electrode plate portion C1b1 is electrically connected to the second electrode plate portion C1b2 through a connection via; the connection via is disposed in the first overlapping region;

[0150] As Figure 2 、 Figure 3 、 Figure 10 、 Figure 11 and Figure 12 As shown, there is a second overlapping region between the orthographic projection of the first electrode plate portion C1b1 on the substrate and the orthographic projection of the anode 10 on the substrate;

[0151] The first electrode plate portion C1b1 is electrically connected to the anode 10 through a fourth via H04 disposed in the second overlapping region.

[0152] In Figure 14 the fourth via with the label H04 is a through via penetrating the second insulating layer A10.

[0153] As Figure 3 、 Figure 7 、 Figure 8 and Figure 10 As shown, the second electrode plate portion C1b2 is electrically connected to the conductive pattern 30 through a first connection via H1 and a second connection via H2; the conductive pattern 30 is electrically connected to the first electrode plate portion C1a through the third connection via H3.

[0154] As Figure 12 shown, the connection via may include a first connection via H1, a second connection via H2, and a third connection via; the orthographic projection of the first connection via H1 on the substrate is within the orthographic projection of the second connection via H2 on the substrate, and the orthographic projection of the third connection via on the substrate is within the orthographic projection of the second connection via H2 on the substrate.

[0155] In Figure 12 the corresponding embodiment, the orthographic projection of the first connection via H1 on the substrate overlaps with the orthographic projection of the third connection via on the substrate, but not limited thereto. In actual operation, the orthographic projection of the first connection via on the substrate may also at least partially overlap with the orthographic projection of the third connection via on the substrate.

[0156] As Figure 14As shown, the first connection via H1 is a via penetrating the first insulating layer A5, the second connection via H2 is a via penetrating the organic resin layer A6, and the third connection via H3 is a via penetrating the third insulating layer A8;

[0157] The orthographic projection of the first connection via H1 on the substrate is within the orthographic projection of the second connection via H2 on the substrate, and the orthographic projection of the third connection via H3 on the substrate is within the orthographic projection of the second connection via H2 on the substrate.

[0158] In the embodiment of the present invention, due to process limitations, the area of the orthographic projection of H2 on the substrate is set to be larger than the area of the orthographic projection of H1 on the substrate, and the area of the orthographic projection of H2 on the substrate is set to be larger than the area of the orthographic projection of H3 on the substrate to ensure that H1 can be completely presented and etched.

[0159] As Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 7 As shown, the gate G1 of the driving transistor is multiplexed as the first electrode plate of the storage capacitor; the second electrode plate portion C1b2 and the second electrode D1 of the driving transistor are of an integral structure;

[0160] In Figure 10 , the one labeled C1b1 is the first electrode plate portion;

[0161] As Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 7 and Figure 10 As shown, the orthographic projection of the first electrode plate C1a on the substrate, the orthographic projection of the first electrode plate portion C1b1 on the substrate, and the orthographic projection of the second electrode plate portion C1b2 on the substrate at least partially overlap to form a storage capacitor.

[0162] As Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 As shown, the active layer pattern of the switching transistor includes a second channel portion 521 (i.e., the channel of the active layer pattern of the switching transistor), a third electrode contact portion 522, and a fourth electrode contact portion 523;

[0163] The positive projection of the source S2 of the switching transistor on the substrate substantially overlaps with the positive projection of the third electrode contact portion 522 on the substrate, and the positive projection of the drain D2 of the switching transistor on the substrate substantially overlaps with the positive projection of the fourth electrode contact portion 523 on the substrate;

[0164] The source S2 of the switching transistor is in direct contact with the third electrode contact portion 522, and the drain D2 of the switching transistor is in direct contact with the fourth electrode contact portion 523;

[0165] The second channel portion 521 is disposed between the third electrode contact portion 522 and the fourth electrode contact portion 523.

[0166] In a specific implementation, the second electrode of the switching transistor is electrically connected to the extension portion. There is a third overlapping region between the positive projection of the extension portion on the substrate and the positive projection of the first plate of the storage capacitor on the substrate. The first plate of the storage capacitor is electrically connected to the extension portion through a fourth connection via disposed in the third overlapping region, so that the first plate of the storage capacitor is electrically connected to the second electrode of the switching transistor;

[0167] The backplane further includes a gate insulating layer disposed between the gate metal layer and the active layer;

[0168] The fourth connection via is a via penetrating the gate insulating layer.

[0169] As Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 7 shown, the drain D2 of the switching transistor is electrically connected to the extension portion L3. There is a third overlapping region between the positive projection of the extension portion L3 on the substrate and the positive projection of the first plate of the storage capacitor (i.e., the gate G1 of the driving transistor) on the substrate. The first plate of the storage capacitor is electrically connected to the extension portion L3 through a fourth connection via H4 disposed in the third overlapping region, so that the first plate of the storage capacitor is electrically connected to the second electrode D2 of the switching transistor.

[0170] In Figure 14 the fourth connection via labeled H4 is a via penetrating the gate insulating layer A2.

[0171] In an embodiment of the present invention, as Figure 9As shown, the conductive layer includes a plurality of independent conductive patterns 30, and the orthographic projection of the conductive patterns 30 on the substrate covers the pixel regions where pixel structures are disposed; and, as Figure 9 shown, the conductive layer has openings between the plurality of independent conductive patterns 30 to expose the first conductive connection portion and the second conductive connection portion, preventing short circuits.

[0172] Optionally, the backplane according to the embodiment of the present invention may include a gate metal layer, an active layer, an etching stop layer, a source-drain metal layer, a capacitor electrode layer, and an anode layer that are sequentially disposed on the substrate; the etching stop layer is used to protect the active layer from being etched;

[0173] The active layer is electrically connected to the source-drain metal layer through vias penetrating the etching stop layer; the gates of the driving transistor and the switching transistor are disposed on the gate metal layer; the active layer patterns of the driving transistor and the switching transistor are disposed on the active layer; the source electrode of the driving transistor, the drain electrode of the driving transistor, the source electrode of the switching transistor, and the drain electrode of the driving transistor are all disposed on the source-drain metal layer; the power supply line is disposed on the capacitor electrode layer, and the anode is disposed on the anode layer; the anodes included in different pixel structures are independent of each other;

[0174] The drain electrode of the driving transistor is electrically connected to the anode through the capacitor electrode layer, and the orthographic projection of the capacitor electrode layer on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate; the drain electrode of the switching transistor is electrically connected to the gate of the driving transistor through an extension extending in the direction of the power supply line.

[0175] In specific implementation, an etching stop layer may be provided between the active layer and the source-drain metal layer, and the active layer is electrically connected to the source-drain metal layer through vias penetrating the etching stop layer; the etching stop layer is used to protect the active layer from being etched, and the etching stop layer can protect the back channel and prevent damage to the back channel during the etching process for forming the source and drain electrodes.

[0176] As Figure 15A and Figure 15B shown, the backplane according to the embodiment of the present invention includes a gate metal layer A1, a gate insulating layer A2, an active layer A3, an etching stop layer A4, a source-drain metal layer A5, a first insulating layer A6, a capacitor electrode layer A7, a second insulating layer A8, and an anode layer A9 that are sequentially disposed above the substrate 20.

[0177] In Figure 15AAmong them, the one labeled 10 is the anode, the one labeled V1 is the power line extending in the column direction, the one labeled G01 is the first gate line, the one labeled G02 is the second gate line, the one labeled D01 is the first data line, and the one labeled D02 is the second data line.

[0178] Figure 15A The layout of the backplane shown is different from Figure 2 the layout of the backplane described in that: an etching barrier layer A4 is provided, and the source electrode of the driving transistor is electrically connected to the active layer pattern of the driving transistor through the first electrode via, the drain electrode of the driving transistor is electrically connected to the active layer pattern of the driving transistor through at least one second electrode via, the source electrode of the switching transistor is electrically connected to the active layer pattern of the switching transistor through the third electrode via, and the drain electrode of the switching transistor is electrically connected to the active layer pattern of the switching transistor through the second electrode via; the size and position of each via; and the shape of the power line.

[0179] As Figure 15A and Figure 15B shown, the first electrode via H11, the second electrode via H12, the third electrode via H13, and the fourth electrode via H14 are vias penetrating the etching barrier layer.

[0180] As Figure 15A shown, the first conductive connection portion included in the power line labeled L1, as Figure 15A and Figure 15B shown, L1 is electrically connected to the second conductive connection portion (the second conductive connection portion is disposed in the source-drain metal layer) through the first via H01 penetrating the first insulating layer A6;

[0181] In Figure 15A and Figure 15B the embodiment shown, the gate of the driving transistor is multiplexed as the first electrode plate of the storage capacitor; the drain of the driving transistor and the second electrode plate portion are an integral structure; the second electrode plate portion is electrically connected to the first electrode plate portion through the second via H02; the first electrode plate portion is electrically connected to the anode 10 through the third via H03 provided.

[0182] As Figure 15A and Figure 15B shown, the orthographic projection of the second via H02 on the substrate does not overlap with the orthographic projection of the third via H03 on the substrate, to avoid wire breakage, but not limited thereto.

[0183] When manufacturing the backplane according to the embodiments of the present invention, during the deposition of the capacitive electrode layer, a depression will occur at the position of the second via hole H02. If the orthographic projection of H03 on the substrate overlaps with the orthographic projection of H02 on the substrate, it may occur that the first plate portion C1b1 cannot be electrically connected to the anode 10 through the third via hole H03 provided in the third overlapping region. Therefore, during actual operation, the orthographic projection of the second via hole H02 on the substrate is set not to overlap with the orthographic projection of the third via hole H03 on the substrate.

[0184] In Figure 15A and Figure 15B In the embodiment shown, the drain of the switching transistor is electrically connected to the extension portion, and the gate of the driving transistor (i.e., the first plate of the storage capacitor) is electrically connected to the extension portion through a fourth via hole H04 (H04 is a via hole penetrating the gate insulating layer and the etching stop layer), so that the first plate of the storage capacitor is electrically connected to the drain of the switching transistor.

[0185] In Figure 3 In the embodiment of the backplane shown, the structure of the conductive layer can be replaced with the structure shown in Figure 16 shown.

[0186] As Figure 16 shown, the conductive layer may include a plurality of first openings K1 and a plurality of second openings K2, and the third connection via hole H3 passes through the first opening K1; the first opening K1 exposes the first conductive connection portion L1 and the second conductive connection portion L2 to avoid short circuit.

[0187] Adopting Figure 16 the structure of the conductive layer shown, the second plate portion can be directly electrically connected to the first plate portion through the first connection via hole, the second connection via hole, and the third connection via hole, without being transferred through the conductive layer. Therefore, when manufacturing the substrate according to the embodiments of the present invention, the first insulating layer and the organic resin layer can be sequentially manufactured on the side of the source-drain metal layer away from the substrate, and then the second connection via hole penetrating the organic resin layer is manufactured. Then, the third insulating layer is manufactured on the side of the organic resin layer away from the first insulating layer, and then the first connection via hole penetrating the first insulating layer and the third connection via hole penetrating the third insulating layer are manufactured by using the same dry etching process. In this way, one mask can be saved and the production cost can be reduced.

[0188] As Figure 16 shown, the conductive patterns 30 included in the conductive layer can be interconnected, which can improve pixel uniformity.

[0189] In actual operation, to avoid ESD (Electro-Static discharge) problems, the conductive pattern can be connected to an appropriate potential. For example, the conductive pattern can be grounded, but not limited thereto.

[0190] In an embodiment of the present invention, without affecting the characteristics of the TFT (Thin Film Transistor), the conductive pattern can also be electrically connected to other voltage signal lines in the display panel.

[0191] In an embodiment of the present invention, the conductive layer is not used as an inter-metal transfer layer, and the capacitive electrode layer is directly electrically connected to the anode layer through a via, which can reduce the contact resistance.

[0192] In an embodiment of the present invention, as Figure 2 、 Figure 3 Figure 15A shown, the power line labeled V21 is the first power line extending along the row direction included in the power line, and the power line labeled V22 is the second power line extending along the row direction included in the power line. The power line in the embodiment of the present invention can be arranged in a grid shape. The first conductive connection portion L1 is disposed between V21 and V22, and the length of L1 along the row direction is greater than the length of V1 along the row direction, the length of L1 along the column direction is greater than the length of V21 along the column direction, and the length of L1 along the column direction is greater than the length of V22 along the column direction, but not limited thereto. Among them, L1, V21, V22, and V1 are electrically connected.

[0193] In the embodiment of the present invention, the power line is arranged in a grid shape to expand the line width as much as possible, and a low-resistance metal can be used to make the power line to reduce the IR drop (IR drop is a phenomenon of voltage drop or rise on the power supply and ground networks in an integrated circuit) under a large current, and improve the uniformity of the large-size backplane.

[0194] The 3D printing system described in the embodiment of the present invention includes a printing box and the above-mentioned backplane; an electrolyte is accommodated in the printing box; the printing box includes a first cover plate and a second cover plate arranged opposite to each other;

[0195] The above-mentioned backplane is disposed on the side of the first cover plate facing the second cover plate, so that each anode of the backplane faces the electrolyte;

[0196] A cathode for printing is disposed on the side of the second cover plate facing the first cover plate.

[0197] In specific implementation, the backplane includes a pixel structure and an anode disposed on a substrate; the pixel structure is configured to control, under the control of a gate driving signal on a corresponding row gate line, the connection or disconnection between a power supply line and the anode according to a data voltage on a corresponding column data line, so as to control the position where metal ions to be printed in the electrolyte are deposited on the second cover plate, and finally form a 3D pattern, thereby achieving high-precision printing.

[0198] In an embodiment of the present invention, the 3D printing system may further include a cathode backplane; the backplane and the cathode backplane are disposed opposite to each other;

[0199] The cathode backplane is disposed on a side of the second cover plate facing the first cover plate, and a cathode is disposed on a side of the cathode backplane facing the backplane.

[0200] In an embodiment of the present invention, the anode may be an electrochemical anode, and the backplane may be a TFT (Thin Film Transistor) array substrate. By controlling the on and off of a driving transistor in the pixel structure in the backplane, the current conduction path is controlled, so as to control the position where metal ions to be printed in the electrolyte are deposited on the cathode backplane, and finally form a 3D pattern.

[0201] In an embodiment of the present invention, the power supply line may be electrically connected to the positive electrode of an electrochemical DC power supply, but not limited thereto.

[0202] The backplane described in an embodiment of the present invention may include an array of pixel structures disposed on a substrate, and the pixel structures may be as Figure 1 shown.

[0203] As Figure 1 shown, when the pixel structure embodiment works, under the control of a gate driving signal provided by the gate line G0, T2 is turned on to provide the data voltage on the data line D0 to the gate of T1. T1 controls the connection or disconnection between the power supply line V1 and the anode 10 under the control of the potential of its gate; C1 is used to maintain the potential of the gate of T1.

[0204] In an embodiment of the present invention, the anode and the cathode may be disposed in the same sealed cavity structure. The sealed cavity structure contains an electrolyte, and the electrolyte is a metal salt solution to be printed. For example, when the printed metal is copper, the electrolyte may be a copper sulfate solution or other copper metal salt solutions; and, in the sealed cavity structure, the backplane and the cathode backplane (the cathode is disposed on the cathode backplane) are disposed opposite to each other, and the electrolyte, the anode, and the cathode form an electrochemical circuit; a voltage is applied between the anode and the cathode, and copper ions move to the vicinity of the cathode and are deposited on the cathode backplane to form a 3D solid figure.

[0205] In the embodiments of the present invention, the pixel structure is not the pixel structure in the display module, but the pixel structure in the electrochemical anode array, but not limited thereto.

[0206] In the embodiments of the present invention, the cathode may be an electrochemical cathode, the cathode may be electrically connected to the negative electrode of the electrochemical DC power supply, and the cathode may be made of the metal to be printed, but not limited thereto.

[0207] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art to which this disclosure belongs. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0208] It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there may be intermediate elements.

[0209] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0210] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A backplane, characterized in that, it includes a substrate and pixel structures arranged in an array on the substrate; the pixel structure includes a power line, gate lines and data lines that intersect in rows and columns, an anode of the backplane located on the substrate, a driving transistor electrically connected to the anode, and a switching transistor electrically connected to the driving transistor; the gate lines extend along the row direction of the array and are located on one side of the pixel structure close to the next row of pixel structures; the data lines extend along the column direction of the array, and the power line includes a power line extending along the column direction; the data line and the power line extending along the column direction are located on opposite sides of the pixel structure; in the pixel region where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction; the gate of the driving transistor extends from the data line to the power line direction in the row direction, and the gate of the driving transistor extends from the gate line of the previous row of pixel structures to the direction of the switching transistor in the column direction; the width direction of the channel in the active layer pattern of the driving transistor is the row direction, and the channel extends from the data line on one side of the pixel structure to the power line on the other side of the pixel structure in the row direction; the source and the drain of the driving transistor extend along the row direction respectively, and the source and the drain of the driving transistor are arranged in sequence along the column direction; the gate of the driving transistor is connected to the drain of the switching transistor, the source of the driving transistor is electrically connected to the power line, and the drain of the driving transistor is electrically connected to the anode; the source of the switching transistor is electrically connected to the data line, and the gate of the switching transistor is electrically connected to the gate line.

2. The backplane according to claim 1, characterized in that, the gate line has a first protrusion, and the data line has a second protrusion; the width direction of the channel in the active layer pattern of the switching transistor is perpendicular to the width direction of the channel of the driving transistor, the gate of the switching transistor is the first protrusion, and the source of the switching transistor is the second protrusion; the drain and the extension of the switching transistor are of an integral structure, the extension extends towards the power line direction, and a part of the orthographic projection of the extension on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate, and the drain of the switching transistor is electrically connected to the gate of the driving transistor through a via hole.

3. The backplane according to claim 1, characterized in that, adjacent two columns of pixel structures in the same row of pixel structures are arranged in a mirror image.

4. The backplane according to claim 3, characterized in that, adjacent two columns of pixel structures in the same row of pixel structures are arranged in a mirror image on both sides of the power line; Two pixel structures mirror - arranged on both sides of the power supply line share one power supply line, and the power supply line is located between two driving transistors which are mirror - arranged; the data lines in the two pixel structures mirror - arranged on both sides of the power supply line are located on the side of the pixel structure far from the power supply line.

5. The backplane according to claim 4, characterized in that, the sources of the two driving transistors in the two pixel structures which are mirror - arranged are connected together and are of an integral structure.

6. The backplane according to claim 2, characterized in that, the length of the gate of the driving transistor in the column direction is greater than the length of the active layer pattern of the driving transistor in the column direction, such that the gate of the driving transistor extends towards the switching transistor relative to the active layer, and there is no overlapping area between the extended part of the gate of the driving transistor and the projection of the active layer pattern of the driving transistor on the substrate; the drain of the driving transistor is electrically connected to the anode through a capacitive electrode layer; the capacitive electrode layer and the extended part of the gate have an overlapping area on the substrate, and the capacitive electrode layer and at least the extended part of the gate form a capacitor.

7. The backplane according to claim 6, characterized in that, the capacitive electrode layer is located between the drain of the driving transistor and the anode, a first insulating layer is provided between the capacitive electrode layer and the drain of the driving transistor, and a second insulating layer is provided between the capacitive electrode layer and the anode; the capacitive electrode layer is electrically connected to the drain of the driving transistor through a via provided in the first insulating layer, and the capacitive electrode layer is electrically connected to the anode through a via in the second insulating layer; wherein, the orthographic projection of the capacitive electrode layer on the substrate and the orthographic projection of the gate of the driving transistor on the substrate have an overlapping area.

8. The backplane according to claim 6, characterized in that, the power supply line and the capacitive electrode layer are formed of the same layer and the same material.

9. The backplane according to claim 6, characterized in that, it further includes a first insulating layer, an organic resin layer, a conductive layer and a third insulating layer which are sequentially arranged between the drain of the driving transistor and the capacitive electrode layer; the organic resin layer and the conductive layer are used to block hydrogen; the orthographic projection of the organic resin layer on the substrate covers the orthographic projection of the active layer pattern on the substrate, and the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the active layer pattern on the substrate; the drain of the driving transistor is electrically connected to the conductive layer through a via penetrating the first insulating layer and the organic resin layer, and the conductive layer is electrically connected to the capacitive electrode layer through a via penetrating the third insulating layer.

10. The backplane according to claim 1, characterized in that, The gate of the driving transistor, the gate of the switching transistor, and the gate line are disposed on the same metal layer on the substrate; the active layer patterns of the driving transistor and the switching transistor are disposed above the metal layer where the gate is located; the source and drain of the driving transistor and the source and drain of the switching transistor are all disposed on the same layer; the power supply line and the capacitor electrode layer are disposed on the same layer, the power supply line is located above the source of the driving transistor, and the anode is disposed above the power supply line and the capacitor electrode layer; The drain of the driving transistor is electrically connected to the anode through the capacitor electrode layer; The positive projection of the capacitor electrode layer on the substrate overlaps with the positive projection of the extension of the gate of the driving transistor relative to the active layer on the substrate to form a capacitor; The drain of the switching transistor is electrically connected to the gate of the driving transistor through an extension extending in the direction of the power supply line.

11. The backplane according to claim 10, wherein, Adjacent two-column pixel structures in the same row are mirror-symmetrically disposed on both sides of the power supply line; Two pixel structures mirror-symmetrically disposed on both sides of the power supply line share one power supply line, and the power supply line is located between two driving transistors disposed in a mirror image; the sources of the two driving transistors disposed in a mirror image extend from one pixel structure to another pixel structure along the row direction, and the sources of the two driving transistors are an integral structure; The power supply line further includes a first conductive connection portion, and the source of the first driving transistor among the two driving transistors disposed in a mirror image is electrically connected to the source of the second driving transistor among the two driving transistors disposed in a mirror image through a second conductive connection portion; At least a part of the positive projection of the first conductive connection portion on the substrate overlaps with the positive projection of the second conductive connection portion on the substrate, and the first conductive connection portion is electrically connected to the second conductive connection portion through a via hole so that the source of the driving transistor is electrically connected to the power supply line.

12. The backplane according to claim 1, 10 or 11, wherein, further comprising: An isolation layer disposed above the active layer pattern of the driving transistor, and the isolation layer is used to isolate the influence of impurities on the active layer pattern of the driving transistor; The isolation layer is a single-layer isolation layer or a multi-layer isolation layer, and the single-layer isolation layer or the multi-layer isolation layer includes at least one of an organic resin layer, a metal layer or a metal oxide active layer.

13. The backplane according to claim 12, wherein, The multi-layer isolation layer is a double-layer isolation layer, and the double-layer isolation layer includes an organic resin layer and a metal oxide active layer sequentially disposed above the active layer; The metal oxide active layer or the metal layer in the isolation layer includes an isolation portion disposed above the active layer pattern of the driving transistor of each pixel structure; The isolation portions are independent of each other, or the isolation portions are integrally disposed.

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