Fully differential pwm / pfm power converter control

Abstract

A differential control circuit is configured to control operation of a power converter. The control circuit of the present disclosure is configured to receive two differential feedback signals from a fully differential amplifier. The amplifier receives an output voltage (Vout) from a switch mode power supply and receives a reference voltage (Vref). When Vout is less than Vref, the control circuit can output a pulse width modulation (PWM) control signal to the switch mode power supply based on a relative difference between a positive differential voltage and a negative differential voltage in a duty cycle of the PWM control signal. When Vout is greater than Vref, the control circuit can output a pulse frequency modulation (PFM) control signal to the switch mode power supply based on a relative difference between the positive differential voltage and the negative differential voltage in a switching time of the PFM control signal.

Description

Technical Field

[0001] This disclosure relates to power converters, and more particularly to control circuitry for power converters. Background Technology

[0002] Buck switching mode power converters, such as buck converters, can use a control loop to regulate the output voltage. The control loop compares the output voltage to a reference voltage and uses pulse modulation to adjust the output voltage. In some examples, the control loop can use pulse width modulation and change the duty cycle, for example, by changing the pulse on-time while maintaining an approximately constant frequency or switching time. In other examples, the control loop can use pulse frequency modulation and change the switching frequency while maintaining a roughly constant pulse on-time. Summary of the Invention

[0003] This disclosure describes a control circuit arrangement configured to control the operation of a switch-mode power supply. Unlike other such control circuit arrangements, the control circuit arrangement of this disclosure is configured to receive two differential feedback signals from a differential amplifier. The differential amplifier receives an output voltage (Vout) and a reference voltage (Vref) from the switch-mode power supply. Based on the difference between Vout and Vref, the differential amplifier outputs two differential feedback signals, such as a "positive" differential voltage and a "negative" differential voltage.

[0004] In operation, when Vout is less than Vref, the positive differential voltage is greater than the negative differential voltage. In response, the control circuit of this disclosure can output a pulse width modulation (PWM) control signal to the switch-mode power supply based on the relative difference between the positive and negative differential voltages, using the duty cycle of the PWM control signal. When Vout is greater than Vref, the positive differential voltage is less than the negative differential voltage. In response, the control circuit of this disclosure can output a pulse frequency modulation (PFM) control signal to the switch-mode power supply based on the relative difference between the positive and negative differential voltages, using the switching time of the PFM control signal.

[0005] In one example, this disclosure describes a circuit including: a first input terminal configured to receive a first differential input signal; a second input terminal configured to receive a second differential input signal; a current sink input terminal configured to sink current based on the relative amplitude between the first and second differential input signals; a peak detection input terminal configured to receive a logic signal from a peak detection circuit; and an output terminal configured to control a power converter. The circuit can be configured to: sink current at the current sink input terminal in response to the first differential input signal being greater than the second differential input signal, and output a pulse width modulation (PWM) control signal at the output terminal. The duty cycle of the PWM control signal is based on the relative amplitude between the first and second differential input signals. In response to the first differential input signal being less than the second differential input signal, the circuit can be configured to: output a pulse frequency modulation (PFM) control signal at the output terminal, wherein the switching time of the PFM control signal is based on the relative amplitude between the first and second differential input signals.

[0006] In another example, this disclosure describes a system including a power converter and a dual-output differential amplifier configured to: receive an output voltage from the power converter; receive a reference voltage; output a first differential signal; and output a second differential signal. The system also includes differential control circuitry with a first input terminal and a second input terminal, configured to: receive the first differential signal at the first input terminal; receive the second differential signal at the second input terminal; and control the operation of the power converter. In response to the first differential signal being greater than the second differential input signal, the differential control circuitry outputs a pulse-width modulation (PWM) control signal to the power converter. The duty cycle of the PWM control signal is based on the relative amplitude between the first and second differential signals. In response to the first differential signal being less than the second differential signal, a pulse-frequency modulation (PFM) control signal is output to the power converter, wherein the switching time of the PFM control signal is based on the relative amplitude between the first and second differential signals.

[0007] In another example, this disclosure describes a method comprising: receiving an output voltage from a power converter via a dual-output differential amplifier; receiving a reference voltage via the dual-output differential amplifier; and outputting a first differential signal and a second differential signal via the dual-output differential amplifier. The amplitude of the first differential signal is based on the relative difference between the output voltage from the power converter and the reference voltage, and the amplitude of the second differential signal is based on the relative difference between the output voltage from the power converter and the reference voltage. The first differential signal is greater than the second differential signal when the reference voltage is greater than the output voltage from the power converter. In response to the first differential signal being greater than the second differential signal, a pulse width modulation (PWM) control signal is output to the power converter, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first and second differential signals.

[0008] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the description and the drawings. Attached Figure Description

[0009] Figure 1A This is a block diagram illustrating an example of a control circuit device for a power converter according to one or more technologies of this disclosure.

[0010] Figure 1B This is a schematic diagram illustrating an example embodiment of a control circuit device for a power converter according to one or more technologies of this disclosure.

[0011] Figure 2 This is a conceptual diagram illustrating an example operation of the power converter control circuit device of this disclosure.

[0012] Figures 3A-3C This is a schematic diagram illustrating an example compensation circuit device used in conjunction with a power control circuit device.

[0013] Figure 3D Includes diagrams illustrating example operation of the differential amplifier of this disclosure.

[0014] Figure 4A This is a schematic diagram illustrating an example driver and switching circuit arrangement for a buck power converter.

[0015] Figure 4B It is shown that it is used for Figure 4A The timing diagram of the example gate signals of the switching circuit device depicted in the figure.

[0016] Figure 5 This is a timing diagram illustrating an example pulse width modulation operation of the control circuit device of this disclosure.

[0017] Figure 6This is a timing diagram illustrating an example pulse frequency modulation operation of the control circuit device of this disclosure.

[0018] Figure 7 This is a timing diagram illustrating an example operation of the control circuit device of this disclosure switching from pulse frequency modulation to pulse width modulation mode.

[0019] Figure 8 This is a schematic diagram illustrating an example control circuit device for a power converter.

[0020] Figure 9 This is a conceptual diagram illustrating an example operation of a power converter control circuit device that includes the gap between pulse frequency modulation and pulse width modulation modes.

[0021] Figure 10 This is a flowchart illustrating an example operation of a control circuit device according to one or more technologies of this disclosure. Detailed Implementation

[0022] This disclosure describes a control circuit arrangement configured to control the operation of a switch-mode power supply. Unlike other such control circuit arrangements, the control circuit arrangement of this disclosure is configured to receive two differential feedback signals from a differential amplifier. The differential amplifier receives an output voltage (Vout) from the switch-mode power supply and a reference voltage (Vref). Based on the difference between Vout and Vref, the differential amplifier outputs two differential feedback signals, such as a "positive" differential voltage (ve_p) and a "negative" differential voltage (ve_n). In other words, the control circuit arrangement uses inputs from a fully differential amplifier to control a DC-DC converter.

[0023] In operation, when Vout is less than Vref, the positive differential voltage is greater than the negative differential voltage. In response, the control circuit device of this disclosure can output a pulse width modulated (PWM) control signal to the switch-mode power supply based on the relative difference between the positive and negative differential voltages, using the duty cycle of the PWM control signal. When Vout is greater than Vref, the positive differential voltage is less than the negative differential voltage. In response, the control circuit device of this disclosure can output a pulse frequency modulated (PFM) control signal to the switch-mode power supply based on the relative difference between the positive and negative differential voltages, using the switching time of the PFM control signal.

[0024] The technology disclosed herein can provide several advantages over other switch-mode power supply control circuit devices, including improved signal-to-noise ratio (SNR), reduced control circuit jitter, improved DC output voltage quality, simplified control logic requiring less area when implemented on an integrated circuit (IC), a single oscillator that can reduce current consumption, and improved compensation networks.

[0025] The control circuit device of this disclosure can be implemented using a variety of techniques, including processor-executed software, logic circuit devices, and similar techniques. In some examples, the control circuit device of this disclosure can be implemented using transconducting circuits, which can provide a simpler circuit than that achievable by other techniques, and offer lower current consumption, circuit area, and cost compared to other techniques.

[0026] Figure 1A This is a block diagram illustrating an example control circuit arrangement for a power converter according to one or more techniques of the present disclosure. The control circuit arrangement 180A of system 100A uses inputs from a dual-output, fully differential amplifier 102 to control a DC-DC converter 160.

[0027] In the example of Figure 1, the differential control circuit device 180A includes a first input terminal ve_p 108, a second input terminal ve_n 110, a current sink input terminal i_sink 182, a peak detection input terminal 184, and an output terminal PM 146. Input terminal ve_p 108 is connected to the positive output of differential amplifier 102 and configured to receive a first differential input signal ve_p from differential amplifier 102. Input terminal ve_n 110 is connected to the negative output of differential amplifier 102 and configured to receive a second differential input signal ve_n from differential amplifier 102. In this disclosure, when described from the perspective of differential control circuit device 180, the differential input signal ve_p from differential amplifier 102 can be described as a "differential input signal". When described from the perspective of differential amplifier 102, the differential input signals ve_p and ve_n can also be described as "differential signals" or "differential output signals". However, the terms “differential input signal,” “differential output signal,” and “differential signal” are used interchangeably and should be considered in the context in which they are used in this disclosure.

[0028] The current sink input terminal i_sink 182 is connected to the current summing node 186. The current summing node 186 can also be referred to as the current summing node. The current sink input terminal i_sink 182 can be configured to sink current based on the relative amplitude between the first differential input signal ve_p and the second differential input signal ve_n. The current summing node 186 is also connected to the output of the slope compensation circuit 142, the output of the current sensing circuit 144, and the input of the peak detector 140. The output of the slope compensation circuit 142 is the current.

[0029] Peak detection input terminal 184 is connected to the output of peak detector 140. In some examples, peak detector 140 may also be referred to as a current comparator. Peak detector 140 outputs a logic signal based on the current amplitude at current summing node 186. Peak detection input terminal 184 is configured to receive a logic signal from peak detector circuitry 140.

[0030] The output terminal PM 146 of the differential control circuit device 180A is connected to the switching and driver circuit device 150 of the power converter 160. The output terminal PM 146 outputs a pulse-modulated signal, such as a pulse width modulation (PWM) and pulse frequency modulation (PFM) signal, to control the operation of the power converter 160 based at least in part on the difference between the amplitude of the output voltage at the output terminal Vout 156 and the reference voltage Vref 104.

[0031] exist Figure 1A In the example, power converter 160 includes a DC-DC buck converter. Power converter 160 can also be described as a DC-DC power converter and a switch-mode power converter. Power converter 160 includes a switch and driver circuit 150 that receives a control signal at an input terminal connected to the output terminal PM 146 of differential control circuit 180A. Switch and driver circuit 150 is connected to a first terminal of inductor L1 152 at switching node SW 148. A second terminal of inductor L1 152 is connected to the output terminal Vout 156 and the first terminal of output capacitor C1 154. The second terminal of C1 154 is connected to ground. Vout 156 is connected to the inverting input, such as the negative input terminal, of differential amplifier 102. Differential amplifier 102 may also be referred to as differential amplifier 102 in this disclosure.

[0032] The output of differential amplifier 102 is connected to a compensation network comprising capacitor C2 112, resistor R2 114, capacitor C3 115, and resistor R3 116. The non-inverting, for example, positive output of differential amplifier 102 is connected to system ground via a series connection of capacitor C2 112 and resistor R2 114. The inverting, for example, negative output of differential amplifier 102 is connected to system ground via a series connection of capacitor C3 115 and resistor R3 116. The compensation network is configured to control the response time and stability of the circuit based on selected values ​​of capacitor C2 112, resistor R2 114, capacitor C3 115, and resistor R3 116. In this disclosure, the compensation network may also be referred to as a compensation unit. The function of the slope compensation circuit 142, for example as part of peak current control during the PWM mode of the differential control circuit 180A, should not be confused with the compensation unit which includes capacitor C2 112, resistor R2 114, capacitor C3 115 and resistor R3 116.

[0033] In operation, the pulse-modulated output from the output terminal PM 146 of the differential control circuitry 180A can control the power converter 160 to increase Vout 156 when it is too low, for example, less than Vref 104, and to decrease Vout 156 when it is too high, for example, greater than Vref 104. The differential amplifier 102 receives the output voltage Vout 156 from the switch-mode power supply as a feedback voltage, for example, Vfb 106, and receives a reference voltage Vref 104. The amplitude of the first differential input signal ve_p 108 can be based on the relative difference between the output voltage, for example, Vout 156 from the power converter 160, and the reference voltage Vref 104. Similarly, the amplitude of the second differential input signal ve_n 110 can be based on the relative difference between the output voltage Vout 156 and the reference voltage Vref 104. In some examples, when the reference voltage Vref 104 is greater than Vfb 106, for example, when the output voltage Vout 156, ve_p 108 is greater than ve_n 110.

[0034] The differential control circuit arrangement 180A can receive a first differential input signal ve_p 108 and a second differential input signal ve_n 110 from the differential amplifier 102. In some examples, ve_p 108 is greater than the second differential input signal ve_n 110. In other words, ve_p 108>ve_n 110 because Vref 104>Vfb 106, that is, the output voltage Vout 156 is too low. In response to ve_p 108 being greater than ve_n 110, the differential control circuit arrangement can sink current from the current summing node 186 at the current sinking input terminal i_sink 182. The magnitude of the current can depend on the relative difference between ve_p 108 and ve_n 110.

[0035] The differential control circuit arrangement 180A can also output a pulse width modulation control signal at the output terminal PM 146. In some examples, the duty cycle of the PWM control signal is based on the relative magnitude between ve_p 108 and ve_n 110.

[0036] In other examples, ve_p 108 can be less than ve_n 110. In other words, ve_p 108<ve_n 110 because Vref 104<Vfb 106, for example, Vout 156 is too high. In response to ve_p 108<ve_n 110, the differential control circuit arrangement 180A can output a pulse frequency modulation control signal at the output terminal PM 145. The switching time of the PFM control signal to the power converter 160 can be based on ve_p 108 and ve_n 110. Stated differently, the PFM switching time can be based on the magnitude of the difference between ve_p 108 and ve_n 110.

[0037] In some examples, the differential control circuit arrangement 180A can also prevent the current sinking input terminal i_sink 182 from sinking current from the current summing node 186. In other words, the current from the current summing node 186 to i_sink 182 can be set to approximately zero amperes. In the present disclosure, "approximately zero" means no current or zero current, except for some possible small leakage currents that have no effect on circuit operation. In other words, "approximately zero" means no current within manufacturing and measurement tolerances. In response to zero current from the current summing node 186 into i_sink 182, the logic signal output from the peak detector circuit 140 can be set to logic "1".

[0038] In some examples, the functionality of the differential control circuitry 180A can be implemented using processing circuitry. In other examples, the aforementioned functionality can be implemented in hardware, software, firmware, or any combination thereof. For example, the various components of FIG1, including slope compensation 142, peak detector 140, etc., can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored on a tangible computer-readable storage medium and executed by a processor or hardware-based processing unit.

[0039] Instructions can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other equivalent integrated or distributed logic circuit devices. Therefore, the terms "processor" and "processing circuit device" as used herein can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be fully implemented in one or more circuit or logic elements. For example, the differential control circuit device 180 can be implemented by a combination of a microprocessor, a clock, switches, and passive components in various combinations.

[0040] Figure 1B This is a schematic diagram illustrating an example embodiment of a control circuit device for a power converter according to one or more technologies of this disclosure. System 100B is the above-mentioned... Figure 1A An example of the described system 100A. The differential amplifier 102, current sensing circuit 144, summing node 186, slope compensation circuit 142, peak detector 140, differential control circuit device 180B, ve_p 108, ve_n 110, and power converter 160 may have the same characteristics as described above. Figure 1A The same functions and features are described.

[0041] for Figure 2 In the example, the differential control circuit device 180B has an input terminal ve_p 108 connected to the positive output of differential amplifier 102 and configured to receive a first differential input signal ve_p from differential amplifier 102. An input terminal ve_n 110 is connected to the negative output of differential amplifier 102 and configured to receive a second differential input signal ve_n from differential amplifier 102. A current sink input terminal connected to current summing node 186 is connected to the input of the first transconductance unit gm2 118. The peak detection input terminal is a non-inverting input to AND gate 138 and connected to the output of peak detector 140. The output terminal PM 146 is the Q output of RS flip-flop 132.

[0042] The transconductance unit gm2118 is a circuit device configured to absorb current at the current sink input terminal connected to the current summing node 186. The transconductance unit gm2118 and the transconductance unit gm3122 are transconducting circuits, which may also be referred to as transconductor gm2118 and transconductor gm3122 in this disclosure.

[0043] The non-inverting or positive input terminal of the transconductance unit gm2118 is connected to ve_p 108, and the inverting or negative input terminal of the transconductance unit gm2118 is connected to ve_n 110. In response to a first differential input signal from ve_p 108 being greater than a second differential input signal from ve_n 110, the transconductance unit gm2118 draws current i_gm2120 from the current summing node 186. In response to a first differential input signal from ve_p 108 being less than a second differential input signal from ve_n 110, the transconductance unit gm2118 is turned off and does not draw current from the current summing node 186, for example, i_gm2120 = 0. When the transconductance unit gm2118 is activated and draws current i_gm2120, the duty cycle of the PWM control signal at the output terminal 146 is based on the amplitude of the current i_gm2120 passing through the first transconductance unit gm2118. The amplitude of i_gm2120 depends on the relative difference between the first differential input signal from ve_p 108 and the second differential input signal from ve_n 110, for example,

[0044] ve_diff = ve_p - ve_n.

[0045] The transconductance unit GM3122 is also a circuit device configured to absorb current i_GM3124. The non-inverting or positive input terminal of the transconductance unit GM3122 is connected to VE_N 110, and the inverting or negative input terminal of the transconductance unit GM3122 is connected to VE_P 108. Therefore, the transconductance unit GM3122 is configured to conduct i_GM3124 when the transconductance unit GM2118 is deactivated, and vice versa. In other words, the second transconductance unit GM3122 is configured to absorb current i_GM3124 in response to a first differential input signal from VE_P 108 being less than a second differential input signal from VE_N 110. Similar to GM2118, the magnitude of the second current i_GM3124 is based on the relative magnitude between VE_P 108 and VE_N 110. When the first differential input signal from ve_p 108 is greater than the second differential input signal from ve_n 110, the amplitude of the second current i_gm3124 is 0. Similar to the transconductance unit gm2118, in some examples, the transconductance unit gm3122 can conduct a small amount of current caused by circuit leakage or other physical factors when deactivated, which may not affect circuit function.

[0046] The output terminal of the transconductance unit gm3122 is connected to the current-controlled oscillator CCO 128 and the constant current source i_clock 126. The current at the input of CCO 128 is a combination of the current from i_clock 126 and the current through i_gm3124 of the transconductance unit gm3 122. In the example of system 100B, CCO 128 includes two output terminals: logic output t ON_MIN 134 and clock 130. The amplitude of i_gm3 124 modulates the frequency of the clock signal from clock 130. In other words, if i_gm3 124 is greater than i_clock 126, then the transconductance unit gm3 modulates the frequency of the clock signal from clock 130 to 0Hz. Clock 130 is connected to the set input (S) of RS flip-flop 132.

[0047] In the example of system 100B, CCO 128 is also configured to... ON_MIN The output of AND gate 134 is connected to the inverting input of AND gate 138. The output of AND gate 138 is connected to the reset (R) input of RS flip-flop 132. Signal t ON_MIN 134 can be implemented in various ways, such as digital delay circuit devices, RC circuit timing, and other techniques. In other examples, it is used to generate t ON_MIN The circuit arrangement of 134 can be implemented in the differential control circuit arrangement 180B through a circuit separate from CCO 128. For the minimum on-time at the output terminal PM 146 of the converter 160, the signal t... ON_MIN 134 provides a constant value.

[0048] As mentioned above Figure 1A As described, the output of differential amplifier 102 is connected to a compensation network including capacitor C2 112, resistor R2 114, capacitor C3 115, and resistor R3 116. The non-inverting, for example, positive output of differential amplifier 102 is connected to system ground via the series connection of capacitor C2 112 and resistor R2 114. The inverting, for example, negative output of differential amplifier 102 is connected to system ground via the series connection of capacitor C3 115 and resistor R3 116.

[0049] In operation, the two transconductance units gm2 118 and gm3 122 may be connected with opposite polarities. When ve_diff is positive (Vout 156 is too low), ve_p > ve_n, so gm2 118 uses peak current control to generate a current that provides a reference for the PWM control of the power converter 160. At the peak detection section of the differential control circuit 180B, peak current control is provided by a signal from the peak detector 140, for example, the peak 136. The signal, that is, the peak 136, is determined by the peak detector based on the current provided by the slope compensation circuit 142 at the summing node 186, the current provided by the current sensing circuit 144, and i_gm2 120 entering the current sinking input terminal, and can help avoid subharmonic oscillation in the PWM control signal.

[0050] Furthermore, when ve_diff is positive, the transconductance unit gm3 122 receives a negative input voltage, and its current i_gm3 124 is equal to 0. In this case, the CCO 128 outputs a constant frequency clock, which is determined by the constant current from i_clock 126 connected to the control terminal of the CCO 128. Since the clock frequency at clock 130 to the S input of the RS flip-flop 132 is fixed, and the duty cycle at the R input of the flip-flop 132 is modulated by peak current control, the differential control circuit 180B operates the DC-DC power converter 160 in PWM mode.

[0051] When ve_diff is negative, for example, ve_p < ve_n and Vout 156 is greater than Vref 104, gm2 118 will receive a negative input voltage from ve_p 108 and ve_n 110, such that i_gm2 120 is zero amperes. Therefore, the peak detector output signal 140 that monitors the current at the summing node 186 will always output a logic "1" to the AND gate 138 via the peak 136. The transconductance unit gm3 122 will receive a positive input voltage, and sink i_gm3 124 proportionally to the magnitude of the difference between the first differential input signal ve_p and the second differential input signal ve_n. Because the input current of the CCO is the difference between i_clock 126 and i_gm3 124, the clock frequency at clock 130 for the S input of the RS flip-flop 132 is modulated to 0 Hz by the transconductance unit gm3 122 when i_gm3 124 > i_clock 126. In other words, the transconductance unit gm3 122 modulates the clock frequency output at clock 130, and the magnitude of i_gm3 124 dominates the input current of the CCO 128 over the constant current from i_clock 126. Since from the CCO 128 via t on_minThe constant on-time of gates 134 to 138 is equal, and the switching frequency from clock 130 is modulated, so the differential control circuit device 180B operates the DC-DC power converter 160 in PFM mode.

[0052] Figure 2 This is a conceptual diagram illustrating an example operation of the power converter control circuit device of this disclosure. Figure 2 The example describes the above about Figure 1A and Figure 1B The operation of the differential control circuit devices 180A and 180B is described, and will be in accordance with Figure 1B Description, unless otherwise stated.

[0053] If ve_diff 206 is greater than zero, that is, ve_p is greater than ve_n, because Vfb 106 is less than Vref 104 at differential amplifier 102, then the differential control circuit device 180B can operate in pulse width modulation mode, for example in Figure 2 In region PWM 202, if ve_diff 206 is less than zero, i.e., ve_p is less than ve_n, because Vfb 106 is greater than Vref 104 at differential amplifier 102, then the differential control circuit device 180B can operate power converter 160 in pulse frequency modulation mode, for example in region PFM 204. The output range 215 or output voltage swing of ve_diff 206 can depend on the architecture and design of differential amplifier 102 and can be limited to the range between the power supply inputs to differential amplifier 102, such as Vdd 208 and -Vdd 210.

[0054] Figures 3A-3C This is a schematic diagram illustrating an example compensation circuit arrangement used with a power control circuit. In some examples, a fully differential architecture can allow the use of half the capacitors and twice the resistors compared to a single-ended approach. On an integrated circuit, capacitance may be larger than resistance. Therefore, by reducing the number of capacitors, the fully differential approach can result in less area being consumed on the integrated circuit used for the compensation network.

[0055] exist Figure 3A In this amplifier, 302A includes an inverting input, a non-inverting input, and a single output. Figure 3A The compensation circuit device includes a capacitor C4 316 with a capacitance of C farads, which is connected in series to ground through a resistor R4 315 with an impedance of R ohms.

[0056] Figure 3BThe differential amplifier 302B, similar to the one described above, may include a compensation network comprising capacitor C2312, resistor R2314, capacitor C3315, and resistor R3316. Differential amplifiers 302B and 302C are examples of the differential amplifier 102 described above with respect to Figures 1 and 2. The non-inverting, for example, positive output of differential amplifier 102 is connected to system ground via a series connection of capacitor C2112 (with a capacitance of C farads) and resistor R2114 (with a resistance of R ohms). The inverting, for example, negative output of differential amplifier 102 is connected to system ground via a series connection of capacitor C3115 (also with a capacitance of C farads) and resistor R3116 (also with a resistance of R ohms). Because the compensation circuitry of differential amplifier 302B is grounded, therefore... Figure 3B The equivalent circuit can be described as follows: Figure 3C As shown.

[0057] The positive output of the differential amplifier 302C is connected to the negative output via a series connection of capacitor C5 318 and resistor R5 319. This series connection of components means that C5 318 can be used in… Figure 3A and 3B The capacitors C4 316 and C2 312 shown in the diagram can be implemented using half their capacitance, for example, a 1 / 2C farad capacitor. Resistor R5 319 can be implemented using twice the capacitance of resistors R4 315 and R2 314, for example, a 2R ohm resistor. In this way, with... Figure 3A and 3B compared to, Figure 3C The compensation circuit can consume less area on the integrated circuit while still providing the same compensation performance within manufacturing and measurement tolerances.

[0058] Figure 3D Includes diagrams illustrating example operation of the differential amplifier of this disclosure. Figure 3D The differential amplifier 302 mentioned above is... Figure 1A , 1B Example of differential amplifier 102 described in section 2. The inputs to differential amplifier 102 are Vref at the non-inverting input terminal and Vout or feedback voltage Vfb at the inverting input terminal.

[0059] The common-mode voltage v_cm 328 is a design parameter for differential amplifier 302. The common-mode voltage v_cm 328, along with the gain (g) of differential amplifier 302, can depend on the differential amplifier topology and can be selected to suit the design constraints of the application using the amplifier. The common-mode voltage v_cm 328 does not affect the differential output of differential amplifier 302.

[0060] Figure 3DThe graphs depict the characteristics of ve_p 320 and ve_n 322 as a function of the differential voltage (ve_diff = Vref - Vout). In some examples, ve_diff can be referred to as the error voltage, such as the error of Vout compared to Vref. Figure 3D The chart drawn in the middle can be described by the following equation:

[0061] ve_p = v_cm + g*(Vref - Vout)

[0062] ve_n = v_cm + g*(Vout - Vref)

[0063] ve_diff=(ve_p-ve_n)=g*(Vref-Vout).

[0064] Figure 4A This is a schematic diagram illustrating an example driver and switching circuit arrangement for a buck power converter. In some examples, the power converter 460 may correspond to the above description. Figure 1A and 1B The power converter 160 is described.

[0065] exist Figure 4A In the example, power converter 460 includes driver and switching circuitry 450 and an LC filter 455, the LC filter including an inductor L1452 connected in series with capacitor C1454. Output voltage 456 is located at the node between L1452 and C1454. LC filter 455 connects driver and switching circuitry 450 at a switching node 448 located between high-side switch 402 and low-side switch 404. Drivers 406 and 408 may include amplifiers and other circuitry configured to drive high-side switch 402 and low-side switch 404. High-side switch 402 and low-side switch 404 are connected in series between input voltage 410 and ground circuitry.

[0066] The driver and switching circuit device 450 can receive a pulse-modulated control signal from the control circuit output 446, which can correspond to the above-mentioned... Figure 1B The output terminal PM 146 is described above. Refer to the above description. Figure 1A-2 When Vout is less than Vref, the control signal can be a pulse width modulation signal. When Vout is greater than Vref, for example, when ve_diff is less than zero, the control signal can be a pulse frequency modulation signal.

[0067] Figure 4B It is shown Figure 4A The timing diagram of the example gate signals of the switching circuit device depicted in the figure. Figure 4BExample low-side door control signal 426 and high-side door control signal 424 are depicted. High-side door control signal 424 depicts the duty cycle d, denoted as t. ON 422 divided by the period t SW 420. The average output voltage Vout 456 can be described by the following equation:

[0068]

[0069] Vout=average(SW)=Vin×d.

[0070] Figure 5 This is a timing diagram illustrating an example pulse width modulation operation of the control circuit device of this disclosure. Figure 5-7 The chart above describes the above about Figure 1A and 1B The working principles of systems 100A and 100B are described. Figure 5 The example describes the operation when ve_diff > 0, for example, Vout is less than Vref.

[0071] For a fixed input voltage, for example Figure 4A As depicted in Vin 410, the system can reach equilibrium when vfb 504 is slightly lower than vref 502. In this case, the fully differential error amplifier comparing vref 502 and vfb 504 can output a positive differential voltage 506. Because ve_diff 506 is positive, transconductor gm3 is disabled, and the output current i_gm3508 is zero amperes. Therefore, the CCO provides a clock output 520 with a fixed switching period, which is determined only by i_clock, as described above. Figure 1B As described.

[0072] The transconductor gm2 can detect a positive input voltage equal to ve_diff 506, and in this case, the output current i_gm2510 is equal to ve_diff * gm2. This current is the reference current for the peak current control circuit, which includes a current sensing circuit 144, a slope compensation circuit device 142, a peak detector 140, and an AND gate 138, as described above. Figure 1A As stated above.

[0073] Therefore, the duty cycle of the power converter is controlled by i_gm2. The PWM signal 518 from the differential control circuit 180B is set high by the rising edge of the clock 520, and a reset occurs when the sensed current 514 equals i_gm2 510 minus the slope compensation current 512.

[0074] Figure 6This is a timing diagram illustrating an example pulse frequency modulation operation of the control circuit arrangement of this disclosure. If external conditions force the power converter to operate at a very low duty cycle, peak detection may occur at the very beginning of the clock cycle, and therefore for the duration of ton_min. If this occurs, the circuit will ignore the peak detection and will no longer modulate the duty cycle by changing the on-time. Instead, the on-time of the output control signal can be fixed and equal to ton_min, but the circuit modulates the switching frequency, for example, in PFM mode.

[0075] As in Figure 6 As shown, the system finds itself balanced when the feedback voltage vfb 602 is slightly higher than the reference voltage vref 604. Under these conditions, the fully differential error amplifier can output a negative voltage ve_diff 606. In other words, as mentioned above regarding... Figure 1A-2 As stated, ve_n is higher than ve_p. Because ve_diff 606 is negative, i_gm2 610 equals zero, forcing peak detection to occur at the beginning of each switching cycle. Transconductor gm3 can receive a positive input voltage and therefore output a current i_gm3 608 greater than 0A. The input current of the current-controlled oscillator is the difference between the fixed current i_clock and i_gm3 608. Under these conditions, the CCO can output a clock 614 with a lower frequency relative to the PWM 620 because of the lower input current. Therefore, the fully differential error amplifier can now control ve_diff 606 to modify the switching period tsw, thereby using a duty cycle (equal to ton_min / tsw) to keep the output voltage of the power converter constant.

[0076] In some examples, if external conditions change, such as a decrease in the load current demand of the power converter, the differential control circuit can react and adjust the i_gm3 608 to output a new switching frequency that provides an appropriate duty cycle to keep the output voltage constant.

[0077] Figure 7 This is a timing diagram illustrating an example operation of the control circuit device of this disclosure switching from pulse frequency modulation to pulse width modulation mode. Figure 7 In the example, the load current i_load 702 increases with time in a steady ramp. As i_load 702 increases towards time T1, ve_diff 704 increases from a negative value towards zero, i_gm3 708 decreases towards zero, and the switching frequency increases. Before time T1, the differential control circuitry, such as the one described above... Figure 1B The described differential control circuit device 180B can control the power converter circuit in a pulse frequency modulation mode.

[0078] At approximately time T1, ve_diff 704 may be approximately equal to zero and begin to become positive, which could cause i_gm3 to turn off and output zero amperes. (As mentioned above...) Figure 1B The constant current from i_clock causes the switching frequency from CCO to reach a steady-state value after time T1. As i_load 702 continues to increase after time T1, ve_diff 704 becomes positive, and as... Figure 1B and 2 As described above, the differential control circuitry begins to control the power converter in pulse-width modulation (PWM) mode. As i_gm2 706 increases, peak current control circuitry components, such as current sensing circuitry 144, slope compensation circuitry 142, and peak detector 140, begin to modulate the PWM output of the differential control circuitry.

[0079] Figure 8 This is a schematic diagram illustrating an example control circuit arrangement for a power converter. Compared to the fully differential amplifier and differential control circuit arrangement of this disclosure, Figure 8 The system 800 in the example includes a single-output differential amplifier 802 with a compensation unit comprising a resistor R4 814 and a capacitor C4 812. Amplifier 802 is connected to system ground and powered by Vdd 803. In addition to CCO 828, system 800 also includes a second oscillator 845. Oscillator 845 generates t ON_MIN 846 and clock 848 for PWM mode. CCO 828 generates clock 852 for PFM mode based on the amplitude of i_gm3 824 controlled by error voltage ve 808. Error voltage ve 808 can be based on the relative amplitude difference between Vref 804 and feedback voltage Vfb 806.

[0080] Similar to the above about Figure 1A and 1B Systems 100A and 100B are described. System 800 includes a peak current control circuitry comprising a current sensing circuitry 844, a slope compensation circuitry 842, and a peak detector 840. Transconductor gm2 818 can draw current i_gm2 820 from current summing node 886. The amplitude of i_gm2 820 can also be based on the relative amplitude difference between Vref 804 and feedback voltage Vfb 806. However, system 800 may include logic circuitry 860 to manage input signals, such as the output of peak detector 840, t... ON_MIN846, PWM clock 848, and PFM clock 852, so when ve 808 is below the threshold voltage, the output signal from the output terminal PM 846 controls the power converter circuit 160 to be in PFM mode, and when ve 808 is positive and above the second threshold voltage, it controls the power converter circuit to be in PWM mode.

[0081] Figure 9 This is a conceptual diagram illustrating an example operation of the power converter control circuitry of system 800, including the gap between pulse frequency modulation and pulse width modulation modes. Figure 9 According to Figure 8 Unless otherwise specified, in operation, the error amplifier 802 of system 800 compares the output voltage Vout 156 of the power converter with a reference current Vref 804 and an output error voltage ve 808. Vfb 806 can be electrically connected to Vout 156 ( Figure 8 (Not shown in the image).

[0082] The error signal VE 808 drives two transconductors GM2 818 and GM3 822. Transconductor GM2 generates a reference current for peak current control, as described above. Figure 8 As described, the transconductor GM3 822 drives the current-controlled oscillator CCO 828 for PFM mode operation, while the oscillator 845 provides the PWM clock 848 for PWM mode operation.

[0083] Power supply Vdd 928 (which corresponds to) Figure 8 The Vdd 803 and system ground 924 shown in the diagram define the operating voltage range 915 of the error amplifier. The error amplifier 802 can operate within a voltage range 915 between a maximum value ve 910 and a minimum value ve 926, which falls within the range of Vdd 928 and system ground 924. In some examples, the maximum value ve 910 and the minimum value ve 926 can be predetermined operating thresholds where the error amplifier itself can function normally, and may depend on the error amplifier topology. Within this permissible range 915, the error amplifier 802 can operate in three distinct regions: one for PWM 902, one for PFM 904, and one for gap 903.

[0084] When ve 808 is in the PWM 902 region, the PFM clock 852 can have a higher frequency relative to the PWM clock 848, so logic 860 can make the signal at the output terminal PM 846 use the PWM clock 848 to control the power converter 160. The duty cycle of the PWM clock 848 is modulated by i_gm2 820 (which is the reference current for peak current control).

[0085] When ve 808 is within the PFM 904 region, the PFM clock 852 can have a lower frequency relative to the PWM clock 848, so logic 860 can make the signal at output terminal PM 846 use the PFM clock 852 to control the power converter 160. When ve 808 is within the PFM 904 region, i_gm2 820 may be at a very low amplitude, for example, drawing a small current from the summing node 883. Therefore, peak detection by peak detector 840 may occur at the beginning of the switching cycle, for example, within the minimum on-time ton_min 846. When peak detection is within the duration of ton_min 846, logic 860 can ignore the peak detection signal output by peak detector 840 and set the on-time of the PFM signal at output terminal PM 846 to be equal to ton_min. Then, by changing the switching cycle, for example t SW 420 is used to modulate the duty cycle of the DC-DC power converter 160, as mentioned above. Figure 4B As described.

[0086] If ve 808 is within the gap 903 region, there is no duty cycle modulation. When within the gap 903 region, the PFM clock 852 can have a higher switching frequency relative to the PWM clock 848. Therefore, logic 860 can select the PWM clock 848 to control the power converter, and the switching period t SW It can be constant. On the other hand, i_gm2 818 may be at a low amplitude, causing peak detection to occur during the minimum on-time, causing logic 860 to ignore the peak detection signal output by peak detector 840. Since the on-time and switching period are constant, the duty cycle is constant, so the output voltage of the power converter may not be controllable within the gap 903 region.

[0087] In contrast, a system with the fully differential amplifier and differential control circuitry of this disclosure can offer advantages over System 800 and other power converter control techniques. For example, the signal-to-noise ratio (SNR) of the differential control circuitry of this disclosure can be an improvement over the SNR of System 800 because the allowable voltage swing of the error voltage ve 808 must be split across the three regions of System 800, rather than as described above. Figure 2 The two regions described are for the differential control circuit. Assuming in system 800 and the above regarding Figure 1 and... Figure 2The noise levels are the same during operation of the differential control circuits in systems 100A and 100B, and ideally, the maximum swing of the error amplifier output is equal to the power supply range of the error amplifier. For system 800, the PWM signal swing begins to vary from one-third of the operating range 915 between Vdd 928 and system ground 924. Conversely, the operating range of the PWM for the differential control circuit device is the entire range between Vdd 208 and zero volts, or system ground, as described above. Figure 2 As described. Therefore, the SNR of the differential control circuit device of this disclosure can ideally be three times higher than that of the PWM operation in system 800. A similar SNR will be obtained for the comparison of the PFM operation. Furthermore, for the differential control circuit device of this disclosure, the gap 903 between the PWM and PFM modes can be at zero volts and approximately zero volts wide. In the differential control circuit device, the transition from one mode to another, such as from PFM to PWM, occurs when ve_diff crosses zero volts, regardless of the outputs of the i_clock, gm2, and gm3 transconductance units and other parameters.

[0088] Other advantages may include the fact that the control logic may be very simple, as mentioned above. Figure 1B The AND gate 138 and RS flip-flop 132 are described. Furthermore, system 100B includes only one oscillator, such as oscillator CCO 128, which reduces cost and complexity, improves reliability, and consumes less area for control circuitry implemented on integrated circuits.

[0089] Figure 10 This is a flowchart illustrating an example operation of a control circuit device according to one or more technologies of this disclosure. (The following text is incomplete and likely refers to a separate process:) Figure 1B and 2 describe Figure 10 Unless otherwise specified, the boxes are marked with boxes.

[0090] The dual-output differential amplifier 102 can receive the output voltage Vout 156 (90) from the switch-mode power converter at the feedback voltage terminal Vfb 106. Vfb 106 is the inverting input terminal of the differential amplifier 102. The differential amplifier 102 can also receive the reference voltage Vref 104 (92) at the non-inverting input terminal.

[0091] Differential amplifier 102 can output two differential signals ve_p 108 and ve_n 110 (94). The amplitudes of ve_p 108 and ve_n 110 can depend on the relative difference between the output voltage from the power converter and the reference voltage, as mentioned above. Figure 3DAs described. For example, when the reference voltage Vref 104 is greater than Vfb 106 coupled to the output of the power converter 160, the first differential signal ve_p 108 can be greater than the second differential signal ve_n 110.

[0092] In response to the first differential signal ve_p 108 being greater than the second differential input signal ve_n 110, the differential control circuit device 180B can output a pulse width modulation (PWM) control signal to the switch-mode power converter 160 (96). The duty cycle of the PWM control signal can be based on the relative amplitude between ve_p 108 and ve_n 110.

[0093] Furthermore, in response to the first differential signal ve_p 108 being less than the second differential signal ve_n 110, the differential control circuit 180B can output a pulse frequency modulation (PFM) control signal to the power converter 160 (98). The switching time of the PFM control signal can be based on the relative amplitude between ve_p 108 and ve_n 110.

[0094] The technology disclosed herein can also be described in the following examples:

[0095] Example 1: A circuit includes: a first input terminal configured to receive a first differential input signal; a second input terminal configured to receive a second differential input signal; a current sink input terminal configured to sink current based on the relative amplitude between the first differential input signal and the second differential input signal; a peak detection input terminal configured to receive a logic signal from a peak detection circuit; and an output terminal configured to control a power converter, wherein the circuit is configured to: sink the current at the current sink input terminal in response to the first differential input signal being greater than the second differential input signal; and output a pulse width modulation (PWM) control signal at the output terminal, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first differential input signal and the second differential input signal; and output a pulse frequency modulation (PFM) control signal at the output terminal in response to the first differential input signal being less than the second differential input signal, wherein the switching time of the PFM control signal is based on the relative amplitude between the first differential input signal and the second differential input signal.

[0096] Example 2: The circuit of claim 1 further includes a dual-output differential amplifier configured to: receive an output voltage from a power converter; receive a reference voltage; output a first differential input signal to a first input terminal; and output a second differential input signal to a second input terminal, wherein: the amplitude of the first differential input signal is based on the relative difference between the output voltage from the power converter and the reference voltage, the amplitude of the second differential input signal is based on the relative difference between the output voltage from the power converter and the reference voltage, and the first differential input signal is greater than the second differential input signal when the reference voltage is greater than the output voltage from the power converter.

[0097] Example 3: A circuit according to any combination of Examples 1-2, wherein in response to the first differential input signal being less than the second differential input signal, the circuit is further configured to prevent the current sink input terminal from absorbing the current, and wherein absorbing approximately zero current at the current sink input terminal causes the logic signal on the peak detector circuit to be set to logic 1.

[0098] Example 4: A circuit according to any combination of Examples 1-3, wherein the circuit further includes a first transconductance unit configured to: absorb current at a current-absorbing input terminal in response to a first differential input signal being greater than a second differential input signal, wherein the amplitude of the current is based on the relative amplitude between the first differential input signal and the second differential input signal, wherein the duty cycle of the PWM control signal is based on the amplitude of the current through the first transconductance unit, and wherein the amplitude of the current is approximately zero in response to a first differential input signal being less than a second differential input signal.

[0099] Example 5: A circuit according to any combination of Examples 1-4 further includes a slope compensation unit coupled to a peak detector and a current sink input terminal, wherein the peak detector is configured to output a logic signal to the peak detection input terminal.

[0100] Example 6: The circuit according to any combination of Examples 1-5 further includes a current sensing circuit coupled to a peak detector and a current sink input terminal, wherein the logic signal from the peak detector is based on the current amplitude at the current sink input terminal.

[0101] Example 7: A circuit according to any combination of Examples 1-6, wherein the current is a first current, wherein the circuit arrangement further includes a second transconductance unit configured to: absorb a second current separated from the first current in response to a first differential input signal being less than a second differential input signal, wherein the amplitude of the second current is based on the relative amplitude between the first differential input signal and the second differential input signal, and wherein the amplitude of the second current is approximately zero in response to a first differential input signal being greater than the second differential input signal.

[0102] Example 8: A circuit based on any combination of Examples 1-7, wherein the switching time of the PFM control signal is based on the amplitude of the second current.

[0103] Example 9: A circuit according to any combination of Examples 1-8, wherein the circuit further includes a current-controlled oscillator configured to: receive an input current comprising the difference between a third current and a second current from a current source; and output a clock signal, wherein the frequency of the clock signal is based on the difference between the third current and the second current, and wherein the switching time of the PFM control signal is based on the frequency of the clock signal.

[0104] Example 10: A circuit according to any combination of Examples 1-9, further comprising a compensation unit coupled to the first input terminal and the second input terminal, wherein the compensation unit is used to control the response time and stability of the circuit.

[0105] Example 11: A system comprising: a power converter; a dual-output differential amplifier configured to: receive an output voltage from the power converter; receive a reference voltage; output a first differential signal; and output a second differential signal; and differential control circuitry including a first input terminal and a second input terminal, the differential control circuitry being configured to: receive the first differential signal at the first input terminal; receive the second differential signal at the second input terminal; and control operation of the power converter, wherein: in response to the first differential signal being greater than the second differential input signal, a pulse width modulation (PWM) control signal is output to the power converter, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first differential signal and the second differential signal; and in response to the first differential signal being less than the second differential signal, a pulse frequency modulation (PFM) control signal is output to the power converter, wherein the switching time of the PFM control signal is based on the relative amplitude between the first differential signal and the second differential signal.

[0106] Example 12. The system according to Example 11 also includes a slope compensation circuit.

[0107] Example 13. A system according to any combination of Examples 11-12, wherein the differential control circuit device further includes a first transconductance unit and a second transconductance unit, wherein the first transconductance unit is configured to: absorb a first current from a current absorption terminal in response to a first differential signal being greater than a second differential signal, wherein the amplitude of the first current is based on the relative amplitude between the first differential signal and the second differential signal, wherein the amplitude of the first current is approximately zero in response to a first differential signal being less than a second differential signal, wherein the second transconductance unit is configured to: absorb a second current separate from the first current in response to a first differential signal being less than a second differential signal, wherein the amplitude of the second current is based on the relative amplitude between the first differential signal and the second differential signal, and wherein the amplitude of the second current is approximately zero in response to a first differential signal being greater than a second differential signal.

[0108] Example 14. A system according to any combination of Examples 11-13, wherein the differential control circuit device further includes a current-controlled oscillator configured to: receive an input current comprising the difference between a third current and a second current from a current source; and output a clock signal, wherein the frequency of the clock signal is based on the difference between the third current and the second current, and wherein the switching time of the PFM control signal is based on the frequency of the clock signal.

[0109] Example 15. A system according to any combination of Examples 11-14, wherein in response to a first differential input signal being less than a second differential input signal, a first transconductance unit is configured to absorb approximately zero current, and thus a first current from the current absorption input terminal is approximately zero, and wherein absorbing approximately zero current at the current absorption input terminal causes a logic signal to be set to logic 1.

[0110] Example 16. A system according to any combination of Examples 11-15, wherein the power converter includes a buck converter.

[0111] Example 17. A method comprising: receiving an output voltage from a power converter via a dual-output differential amplifier; receiving a reference voltage via the dual-output differential amplifier; outputting a first differential signal and a second differential signal via the dual-output differential amplifier, wherein: the amplitude of the first differential signal is based on the relative difference between the output voltage from the power converter and the reference voltage, the amplitude of the second differential signal is based on the relative difference between the output voltage from the power converter and the reference voltage, and the first differential signal is greater than the second differential signal when the reference voltage is greater than the output voltage from the power converter; and in response to the first differential signal being greater than the second differential signal, outputting a pulse width modulation (PWM) control signal to the power converter, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first differential signal and the second differential signal.

[0112] Example 18. The method of Example 1 further includes outputting a pulse frequency modulation (PFM) control signal to a power converter in response to the first differential signal being less than the second differential signal, wherein the switching time of the PFM control signal is based on the relative amplitude between the first differential signal and the second differential signal.

[0113] Example 19. The method according to Example 18 further includes: absorbing a first current through a first transconductance unit in response to a first differential signal being greater than a second differential signal, wherein the amplitude of the first current is based on the relative amplitude between the first differential signal and the second differential signal, wherein the amplitude of the first current is approximately zero in response to a first differential signal being less than the second differential signal; and absorbing a second current separated from the first current through a second transconductance unit in response to a first differential signal being less than the second differential signal, wherein the amplitude of the second current is based on the relative amplitude between the first differential signal and the second differential signal, and wherein the amplitude of the second current is approximately zero in response to a first differential signal being greater than the second differential signal.

[0114] Example 20. The method according to any combination of Examples 17-19 further includes: receiving an input current via a current-controlled oscillator, the input current including the difference between a third current from a current source and a second current; and outputting a clock signal via the current-controlled oscillator, wherein the frequency of the clock signal is based on the difference between the third current and the second current, and wherein the switching time of the PFM control signal is based on the frequency of the clock signal.

[0115] Various examples of this disclosure have been described. These and other examples are within the scope of the following claims.

Claims

1. A circuit for controlling a power converter, comprising: The first input terminal is configured to receive a first differential input signal; The second input terminal is configured to receive a second differential input signal; The current absorption input terminal is configured to absorb current based on the relative amplitude between the first differential input signal and the second differential input signal; The peak detection input terminal is configured to receive logic signals from the peak detector circuit. as well as The output terminal is configured to control the power converter, wherein the circuitry is configured as follows: In response to the first differential input signal being greater than the second differential input signal: The current is absorbed at the current absorption input terminal; and A pulse width modulation (PWM) control signal is output at the output terminal, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first differential input signal and the second differential input signal, and In response to the first differential input signal being less than the second differential input signal, a pulse frequency modulation (PFM) control signal is output at the output terminal, wherein the switching time of the PFM control signal is based on the relative amplitude between the first differential input signal and the second differential input signal.

2. The circuit according to claim 1 further includes a dual-output differential amplifier configured as follows: Receive the output voltage from the power converter; Receive reference voltage; Output the first differential input signal to the first input terminal; and Output the second differential input signal to the second input terminal. in: The amplitude of the first differential input signal is based on the relative difference between the output voltage from the power converter and the reference voltage. The amplitude of the second differential input signal is based on the relative difference between the output voltage from the power converter and the reference voltage, and When the reference voltage is greater than the output voltage from the power converter, the first differential input signal is greater than the second differential input signal.

3. The circuit of claim 1, wherein in response to the first differential input signal being less than the second differential input signal, the circuit is further configured to prevent the current sink input terminal from absorbing the current, and wherein absorbing approximately zero current at the current sink input terminal causes the logic signal on the peak detector circuit to be set to logic one.

4. The circuit according to claim 1, The circuit further includes a first transconductance unit configured to absorb current at the current-absorbing input terminal in response to the first differential input signal being greater than the second differential input signal. The amplitude of the current is based on the relative amplitude between the first differential input signal and the second differential input signal. The duty cycle of the PWM control signal is based on the amplitude of the current through the first transconductance unit, and When the first differential input signal is less than the second differential input signal, the amplitude of the current is approximately zero.

5. The circuit of claim 4 further includes a slope compensation unit coupled to the peak detector and the current absorption input terminal, wherein the peak detector is configured to output the logic signal to the peak detection input terminal.

6. The circuit of claim 5 further includes a current sensing circuit coupled to the peak detector and the current absorption input terminal, wherein the logic signal from the peak detector is based on the current amplitude at the current absorption input terminal.

7. The circuit according to claim 4, The current mentioned therein is the first current. The circuit arrangement further includes a second transconductance unit configured to absorb a second current separated from the first current in response to the first differential input signal being less than the second differential input signal. The amplitude of the second current is based on the relative amplitude between the first differential input signal and the second differential input signal, and In response to the first differential input signal being greater than the second differential input signal, the amplitude of the second current is approximately zero.

8. The circuit of claim 7, wherein the switching time of the PFM control signal is based on the amplitude of the second current.

9. The circuit of claim 7, wherein the circuit further comprises a current-controlled oscillator configured to: Receives an input current including the difference between a third current from a current source and a second current; and Output clock signal, The frequency of the clock signal is based on the difference between the third current and the second current, and The switching time of the PFM control signal is based on the frequency of the clock signal.

10. The circuit of claim 1, further comprising a compensation unit coupled to the first input terminal and the second input terminal, wherein the compensation unit is configured to control the response time and stability of the circuit.

11. A power converter system, comprising: Power converter; A dual-output differential amplifier is configured as follows: Receive the output voltage from the power converter; Receive reference voltage; Output the first differential signal; as well as Output the second differential signal; as well as A differential control circuit includes a first input terminal and a second input terminal, and the differential control circuit is configured to: The first differential signal is received at the first input terminal; The second differential signal is received at the second input terminal; as well as Controlling the operation of the power converter, wherein: In response to the first differential signal being greater than the second differential signal, a pulse width modulation (PWM) control signal is output to the power converter, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first differential signal and the second differential signal; and In response to the first differential signal being less than the second differential signal, a pulse frequency modulation (PFM) control signal is output to the power converter, wherein the switching time of the PFM control signal is based on the relative amplitude between the first differential signal and the second differential signal.

12. The power converter system according to claim 11 further includes a slope compensation circuit.

13. The power converter system according to claim 11, The differential control circuit further includes a first transconductance unit and a second transconductance unit. The first transconductance unit is configured to absorb a first current from the current absorption terminal in response to the first differential signal being greater than the second differential signal. The amplitude of the first current is based on the relative amplitude between the first differential signal and the second differential signal. In response to the first differential signal being smaller than the second differential signal, the amplitude of the first current is approximately zero. The second transconductance unit is configured to absorb a second current separated from the first current in response to the first differential signal being less than the second differential signal. The amplitude of the second current is based on the relative amplitude between the first differential signal and the second differential signal, and In response to the first differential signal being greater than the second differential signal, the amplitude of the second current is approximately zero.

14. The power converter system of claim 13, wherein the differential control circuit further comprises a current-controlled oscillator configured to: Receives an input current including the difference between a third current from a current source and a second current; and Output clock signal, The frequency of the clock signal is based on the difference between the third current and the second current, and The switching time of the PFM control signal is based on the frequency of the clock signal.

15. The power converter system according to claim 13, In response to the first differential signal being less than the second differential signal, the first transconductance unit is configured to absorb approximately zero current, and therefore the first current from the current absorption input terminal is approximately zero. The absorption of approximately zero current at the current absorption input terminal causes the logic signal to be set to logic one.

16. The power converter system of claim 11, wherein the power converter includes a buck converter.

17. A method for controlling a power converter, comprising: The output voltage from the power converter is received through a dual-output differential amplifier; The reference voltage is received through a dual-output differential amplifier; The first differential signal and the second differential signal are output through a dual-output differential amplifier, wherein: The amplitude of the first differential signal is based on the relative difference between the output voltage from the power converter and the reference voltage. The amplitude of the second differential signal is based on the relative difference between the output voltage of the power converter and the reference voltage, and When the reference voltage is greater than the output voltage from the power converter, the first differential signal is greater than the second differential signal, and In response to the first differential signal being greater than the second differential signal, a pulse width modulation (PWM) control signal is output to the power converter, wherein the duty cycle of the PWM control signal is based on the relative amplitude between the first differential signal and the second differential signal.

18. The method of claim 17, further comprising, in response to the first differential signal being less than the second differential signal, outputting a pulse frequency modulation (PFM) control signal to the power converter, wherein the switching time of the PFM control signal is based on the relative amplitude between the first differential signal and the second differential signal.

19. The method of claim 18, further comprising: In response to the first differential signal being greater than the second differential signal, the first current is absorbed through the first transconductance unit. The amplitude of the first current is based on the relative amplitude between the first differential signal and the second differential signal. In response to the first differential signal being smaller than the second differential signal, the amplitude of the first current is approximately zero. In response to the first differential signal being less than the second differential signal, the second transconductance unit absorbs the second current separated from the first current. The amplitude of the second current is based on the relative amplitude between the first differential signal and the second differential signal, and In response to the first differential signal being greater than the second differential signal, the amplitude of the second current is approximately zero.

20. The method of claim 19, further comprising: The input current is received by a current-controlled oscillator, the input current including the difference between a third current from a current source and a second current; and The clock signal is output by controlling the oscillator with current. The frequency of the clock signal is based on the difference between the third current and the second current, and The switching time of the PFM control signal is based on the frequency of the clock signal.

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