Power supply noise suppression circuit and image sensor

Abstract

The present invention relates to a power supply noise suppression circuit and an image sensor, comprising a pixel circuit, a comparison signal generating circuit and a comparator, wherein the pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input end of the comparator, and the comparison signal generating circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input end of the comparator, wherein the second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise of the pixel circuit; the comparison signal generating circuit comprises a capacitance adjustment module, a buffer transistor and a bias transistor, the capacitance adjustment module comprises a variable capacitor and a bias capacitor, and the gate of the bias transistor is connected to a bias voltage node and is connected to a first end of the bias capacitor. The present invention introduces noise through a comparator to suppress the power supply noise in the pixel circuit, and can effectively resist power supply noise interference, reduce image noise and improve image quality.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits of image sensors, and in particular to a power supply noise suppression circuit and an image sensor. Background Art

[0002] Image sensors are commonly used in a variety of electronic devices, such as video surveillance systems, smart phones, digital cameras, and smart AI, face recognition and other electronic products to capture and identify image information of people or scenes. As an important part of digital cameras, they provide the function of converting optical images into electrical signals. Image sensors can be divided into CMOS (Complementary Metaloxide Semiconductor), CCD (Charge Coupled Device) and image sensors according to different components.

[0003] CMOS image sensors have the advantages of high integration, low power consumption, programmable random readout of local pixels, high speed and low cost, and can be applied to digital cameras, PC cameras and mobile communication products. In addition to being widely used in digital cameras, CCD image sensors are also widely used in scanners and industrial fields. Both CMOS image sensors and CCD image sensors use photoelectric conversion areas, generally using photodiodes (Photodiode or Photodetector) to collect incident light and convert it into photocharges that can be used for image processing. In existing CMOS image sensors, a pixel array composed of several pixel units often adopts a 3T, 4T or 5T structure. Taking 4T as an example, it is composed of a transfer transistor, a reset transistor, a source follower transistor and a row selection transistor. The pixel unit forms photogenerated carriers through photoelectric conversion by a photodiode, generates an analog signal, and reads the analog signal of each column by selecting and reading the row of the pixel array, and performs subsequent signal processing processes such as operation gain amplification and analog-to-digital conversion.

[0004] In actual operation, the noise sources of CMOS image sensors include pixel power line noise and noise coupled from the pixel control signal line related to the power supply. The noise of the power supply of the source follower transistor (SF tube) of the pixel circuit will be coupled to the floating diffusion node (FD) of the pixel unit through capacitance, and then the signal will be amplified by the source follower transistor. After the digital-to-analog conversion module converts it, it will be reflected in the output data, affecting the signal-to-noise ratio of the image. The existing processing method is to set a LDO (Low Dropout Regulator) for the pixel circuit separately to reduce the impact of the external power supply noise on the image quality. If the output of the LDO is affected, the power supply noise will still be reflected in the image. Therefore, when the LDO is used to solve the power supply noise, when the chip interference is large, the stabilization speed of this method is limited. During its stabilization process, the power supply noise will still be reflected in the image. In addition, the LDO also occupies a large layout area, consumes power and limits the use of power supply by other modules, which may lead to a decrease in the performance of the image sensor chip. Summary of the invention

[0005] In view of this, the present invention provides a power supply noise suppression circuit and an image sensor, which can effectively suppress the power supply noise interference of the image sensor, reduce image noise and improve image quality.

[0006] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present invention provides a power supply noise suppression circuit. As one implementation mode thereof, a power supply noise suppression circuit is characterized in that the circuit includes a pixel circuit, a comparison signal generating circuit and a comparator;

[0007] The pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, and the comparison signal generating circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, wherein the second power supply noise signal has the same amplitude as the first power supply noise signal, so as to offset the power supply noise in the pixel circuit;

[0008] Wherein, the comparison signal generating circuit includes a capacitance adjustment module, a buffer transistor and a bias transistor, and the capacitance adjustment module includes a variable capacitor and a bias capacitor;

[0009] The first end of the variable capacitor is connected to the noise power supply, the second end of the variable capacitor is connected to the first end of the bias capacitor, and the second end of the bias capacitor is grounded;

[0010] The buffer transistor and the bias transistor are connected in series between the noise power supply and ground, the gate of the buffer transistor receives a ramp voltage reference signal, and the gate of the bias transistor is connected to a bias voltage node and to a first end of the bias capacitor;

[0011] The value of the variable capacitor is adjusted to make the second power supply noise signal have the same amplitude as the first power supply noise signal, so as to offset the power supply noise in the pixel circuit.

[0012] As one implementation mode, the buffer transistor is a first NMOS tube, and the bias transistor is a second NMOS tube; the drain of the first NMOS tube is connected to the noise power supply, the gate of the first NMOS tube is connected to the voltage reference signal node, the voltage reference signal is a ramp voltage reference signal, and the source of the first NMOS tube is connected to the second input terminal of the comparator; the drain of the second NMOS tube is connected to the second input terminal of the comparator, the gate of the second NMOS tube is connected to the bias voltage node and connected to the first end of the bias capacitor, and the source of the second NMOS tube is grounded.

[0013] As one of the implementation modes, the buffer transistor is a first PMOS tube, and the bias transistor is a second PMOS tube; the source of the second PMOS tube is connected to the noise power supply, the gate of the second PMOS tube is connected to the bias voltage node and connected to the first end of the bias capacitor, and the drain of the second PMOS tube is connected to the second input end of the comparator; the source of the first PMOS tube is connected to the second input end of the comparator, the gate of the first PMOS tube is connected to the voltage reference signal node, the voltage reference signal is a ramp voltage reference signal, and the drain of the first PMOS tube is grounded. Ramp voltage reference signal As one of the implementation modes, the bias voltage node is connected to a current mirror circuit to provide a bias voltage.

[0014] As one embodiment, the variable capacitor includes a capacitor with variable size.

[0015] As one implementation manner, the variable capacitor includes a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control the conduction of each constant capacitor.

[0016] As one implementation manner, the first input terminal of the comparator is an inverting input terminal, and the second input terminal of the comparator is a non-inverting input terminal.

[0017] As one implementation manner, the bias capacitor is a variable capacitor.

[0018] As one embodiment, the pixel circuit includes a first capacitor connected between the drain and gate of the source follower transistor and a second capacitor connected between the gate of the source follower transistor and ground, the first capacitor is the total coupling capacitance between the pixel power line, the pixel control signal line related to the power supply and the floating diffusion node, and the second capacitor is all parasitic capacitances on the floating diffusion node minus the first capacitor.

[0019] As one implementation manner, the image signal superimposed with the first power supply noise signal is:

[0020]

[0021] The comparison signal with the second power supply noise signal superimposed is:

[0022]

[0023] Among them, v noise is the noise supply voltage, C p is the first capacitor, C fd is the second capacitor, C bias is the total capacitance of the bias voltage node, M buf is the buffer transistor, M bias is the bias transistor, W and L are the width and length of the MOS tube respectively, gmb sf is the small signal bulk transconductance that characterizes the source follower transistor, gm sf , gm buf , gm bias They are the transconductance of the source follower transistor, buffer transistor, and bias transistor. By adjusting C c Make the difference Minimize noise suppression.

[0024] To achieve the above objective, a second aspect of an embodiment of the present invention provides an image sensor. As one implementation manner, the image sensor includes the power supply noise suppression circuit described in any one of the above implementation manners.

[0025] In summary, the present invention is provided with a pixel circuit, a comparison signal generating circuit and a comparator, wherein the pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, and the comparison signal generating circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, and the second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise in the pixel circuit; wherein the comparison signal generating circuit comprises a capacitance adjustment module, a buffer transistor and a bias transistor, and the capacitance adjustment module comprises a variable capacitor and a bias capacitor; the first end of the variable capacitor is connected to the noise power supply, the second end of the variable capacitor is connected to the first end of the bias capacitor, and the second end of the bias capacitor is grounded; the ramp voltage reference signal, the buffer transistor and the bias transistor are connected in series between the noise power supply and the ground, the gate of the buffer transistor receives a ramp voltage reference signal, and the gate of the bias transistor is connected to the bias voltage node and connected to the first end of the bias capacitor; wherein the second power supply noise signal is made to have the same amplitude as the first power supply noise signal by adjusting the value of the variable capacitor to offset the power supply noise in the pixel circuit. Therefore, the present invention introduces noise into the comparison signal generating circuit through a comparator, so that the power supply noise appears as the common mode noise of the comparator, thereby suppressing the power supply noise in the pixel circuit, and can effectively resist power supply noise interference, reduce image noise and improve image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A structural block diagram of a power supply noise suppression circuit provided by an embodiment of the present invention is shown.

[0027] Figure 2 A specific structural schematic diagram of a power supply noise suppression circuit provided by an embodiment of the present invention is shown.

[0028] Figure 3 A specific structural schematic diagram of a power supply noise suppression circuit provided by another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments, and are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In this patent specification, "one embodiment" or "an implementation method" refers to the specific features, structures or characteristics described in the example included in at least one embodiment of the present invention.

[0030] First of all, the inventive concept of the present invention is to solve the row noise of the image sensor manifested by the pixel power line noise in the pixel unit and the noise coupled from the pixel control signal line related to the power supply, by transmitting the power supply noise coupled in the pixel unit to one input end of the comparator or amplifier through a source follower (source follower transistor and current source), and at the same time introducing the power supply noise with the same amplitude into the other input end of the comparator or amplifier, so that the power supply noise of the pixel unit becomes the common mode noise of the comparator, thereby suppressing the power supply noise of the pixel unit, making the output of the comparator less affected by the power supply noise, and achieving the purpose of reducing image noise and improving image quality.

[0031] Specifically, please refer to Figure 1 , Figure 1 FIG. 2 shows a structural block diagram of a power supply noise suppression circuit provided by an embodiment of the present invention. Figure 1 As shown, the power supply noise suppression circuit includes a pixel circuit 11, a comparison signal generating circuit 12 and a comparator 13. The pixel circuit 11 outputs an image signal of a first power supply noise signal superimposed with a noise power supply vnoise to a first input terminal of the comparator 13. The comparison signal generating circuit 12 outputs a comparison signal of a second power supply noise signal superimposed with a noise power supply vnoise to a second input terminal of the comparator 13. The second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise in the pixel circuit. The comparison signal generating circuit 12 includes a capacitance adjustment module, a buffer transistor and a bias transistor. The buffer transistor and the bias transistor are connected in series between the noise power supply vnoise and the ground. The gate of the buffer transistor receives a voltage reference signal. The capacitance is adjusted by the capacitance adjustment module so that the second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise in the pixel circuit.

[0032] Combined with reference Figure 2 , Figure 2 FIG. 2 is a schematic diagram showing a specific structure of a power supply noise suppression circuit provided by an embodiment of the present invention. Figure 2 As shown, the pixel circuit 11 includes a first capacitor Cp connected between the drain and gate of the source follower transistor Msf and a second capacitor Cfd connected between the gate of the source follower transistor Msf and the ground. The first capacitor Cp is the total coupling capacitance between the pixel power line, the pixel control signal line related to the power supply and the floating diffusion node, and the second capacitor Cfd is all the parasitic capacitance on the floating diffusion node minus the first capacitor Cp.

[0033] The comparison signal generating circuit 12 in the power supply noise suppression circuit includes a capacitance adjustment module, a first NMOS tube Mbuf (cache transistor) and a second NMOS tube Mbias (bias transistor), and the capacitance adjustment module includes a variable capacitor Cc and a bias capacitor Cbias; wherein, the first end of the variable capacitor Cc is connected to the noise power supply vnoise, the second end of the variable capacitor Cc is connected to the first end of the bias capacitor Cbias, and the second end of the bias capacitor Cbias is grounded; the drain of the first NMOS tube Mbuf is connected to the noise power supply vnoise, the gate of the first NMOS tube Mbuf is connected to the ramp voltage reference signal node vref, and the source of the first NMOS tube Mbuf is connected to the second input end of the comparator 13; the drain of the second NMOS tube Mbias is connected to the second input end of the comparator 13, the gate of the second NMOS tube Mbias is connected to the bias voltage node vbias and connected to the first end of the bias capacitor Cbias, and the source of the second NMOS tube Mbias is grounded.

[0034] Specifically, the pixel circuit can be a 3T, 4T, 5T or other structure. Regardless of the structure, the power supply voltage in the pixel circuit will generate power supply noise, affecting the signal-to-noise ratio of the image. The common 4T structure pixel circuit includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor, a current source and a row selection transistor. The photodiode is connected to the source of the transfer transistor, the drains of the reset transistor and the source follower transistor are commonly connected to the noise power supply, the drain of the transfer transistor, the source of the reset transistor and the gate of the source follower transistor are connected to the floating diffusion node, the source of the source follower transistor is connected to the drain of the row selection transistor, and the source of the row selection transistor is grounded through a current source. Among them, Figure 2 As shown, the pixel unit includes a connection to a noise power supply vnoise and a floating diffusion node FD (the voltage of FD is expressed as Figure 2 The first capacitor Cp connected to the floating diffusion node FD (the voltage of FD is expressed as Figure 2 The first capacitor Cp is the total coupling capacitance between the pixel power line, the pixel control signal line related to the power supply and the floating diffusion node FD, and the second capacitor Cfd is all the parasitic capacitance on the floating diffusion node FD minus the first capacitor Cp.

[0035] When the image sensor is working, the first capacitor Cp couples the power supply noise of the noise power supply vnoise to the floating diffusion node FD, and outputs it to the first input terminal of the comparator 13 through the source follower transistor Msf, that is, the source of the source follower transistor Msf is connected to the node visg, and the first input terminal of the comparator 13 is connected to the node vsig. Therefore, the first power supply noise signal of the noise power supply vnoise in the pixel circuit 11 is superimposed on the image signal and input to the first input terminal of the comparator 13. Then the second power supply noise signal of the noise power supply vnoise in the comparison signal generating circuit 12 is superimposed on the comparison signal and input to the second input terminal of the comparator 13 to cancel each other out, thereby eliminating the power supply noise of the noise power supply vnoise in the pixel circuit 11. Among them, in the comparison signal generating circuit 12, the bias voltage node vbias provides a bias voltage to the second NMOS tube Mbias to generate a bias current, which can also be understood as providing a working voltage to the second NMOS tube Mbias, and the first NMOS tube Mbuf is used to suppress the influence of the reverse noise at the comparator end on the ramp voltage reference signal vref and provide gain.

[0036] Specifically, in this embodiment, the image signal superimposed with the first power supply noise signal is:

[0037]

[0038] The comparison signal with the second power supply noise signal superimposed is:

[0039]

[0040] Among them, v noise is the noise supply voltage, C p is the first capacitor, C fd is the second capacitor, C bias is the total capacitance of the bias voltage node, M buf is the buffer transistor, M bias is the bias transistor, W and L are the width and length of the MOS tube respectively, gmb sf It is the small signal body transconductance that characterizes the source follower transistor. It is related to the voltage difference between the body terminal and the source terminal. When the body terminal and the source terminal are connected together, gmb sf =0, then the capacitance adjustment can be more effective, gm sf , gm buf , gm bias They are the transconductance of the source follower transistor, buffer transistor, and bias transistor. By adjusting C c Make the difference Minimize noise suppression.

[0041] It is worth mentioning that the optimal situation is that the amplitude of the second power supply noise signal is equal to the amplitude of the first power supply noise signal, and the amplitude difference between the two noise signals can be minimized by adjusting the variable capacitor Cc.

[0042] In one implementation, the first input terminal of the comparator 13 is an inverting input terminal, and the second input terminal of the comparator 13 is a non-inverting input terminal.

[0043] In one embodiment, the bias voltage node vbias is connected to a current mirror circuit to provide a bias voltage.

[0044] In one embodiment, the variable capacitor Cc includes a variable-sized capacitor.

[0045] Specifically, the variable capacitor Cc includes a capacitor with a variable size, and the image sensor can control the amplitude of the second noise signal by adjusting the size of the variable capacitor.

[0046] In one embodiment, the variable capacitor Cc includes a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control the conduction of each constant capacitor.

[0047] Specifically, the variable capacitor Cc can be implemented by a plurality of constant capacitors connected in parallel and a plurality of corresponding switches, and the capacitance value is changed by controlling the on / off of each switch to adjust the size of the variable capacitor to control the amplitude of the second noise signal.

[0048] In one embodiment, the bias capacitor Cbias is a variable capacitor.

[0049] In summary, the power supply noise suppression circuit provided by the embodiment of the present invention is provided by setting a pixel circuit, a comparison signal generating circuit and a comparator, wherein the pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, and the comparison signal generating circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, and the second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise in the pixel circuit; wherein the comparison signal generating circuit includes a capacitance adjustment module, a first NMOS tube and a second NMOS tube, and the capacitance adjustment module includes a variable capacitor and a bias capacitor; the first end of the variable capacitor is connected to the noise power supply, the second end of the variable capacitor is connected to the first end of the bias capacitor, and the second end of the bias capacitor is grounded; the drain of the first NMOS tube is connected to the noise power supply, the gate of the first NMOS tube is connected to the ramp voltage reference signal node, and the source of the first NMOS tube is connected to the second input terminal of the comparator; the drain of the second NMOS tube is connected to the second input terminal of the comparator, the gate of the second NMOS tube is connected to the bias voltage node and connected to the first end of the bias capacitor, and the source of the second NMOS tube is grounded. The present invention introduces noise into the comparison signal generating circuit through a comparator, so that the power supply noise appears as the common mode noise of the comparator, thereby suppressing the power supply noise in the pixel circuit, and can effectively resist power supply noise interference, reduce image noise and improve image quality.

[0050] Please refer to Figure 3 , Figure 3 FIG. 2 is a schematic diagram showing a specific structure of a power supply noise suppression circuit provided by another embodiment of the present invention. Figure 3As shown, the power supply noise suppression circuit includes a pixel circuit 11, a comparison signal generating circuit 12 and a comparator 13. The pixel circuit 11 outputs an image signal of a first power supply noise signal superimposed with a noise power supply vnoise to a first input terminal of the comparator 13. The comparison signal generating circuit 12 outputs a comparison signal of a second power supply noise signal superimposed with a noise power supply vnoise to a second input terminal of the comparator 13. The second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise in the pixel circuit. The comparison signal generating circuit 12 includes a capacitance adjustment module, a first PMOS tube Mbias and a second PMOS tube Mbuf. The capacitance adjustment module includes a variable capacitor Cc and a bias capacitor Cbias. A first end of the variable capacitor Cc is connected to a noise power supply vnoise, a second end of the variable capacitor Cc is connected to a first end of a bias capacitor Cbias, and a second end of the bias capacitor Cbias is grounded; a source of the first PMOS tube Mbias is connected to the noise power supply vnoise, a gate of the first PMOS tube Mbias is connected to a bias voltage node vbias and to the first end of the bias capacitor Cbias, and a drain of the first PMOS tube Mbias is connected to a second input end of the comparator 13; a source of the second PMOS tube Mbuf is connected to the second input end of the comparator 13, a gate of the second PMOS tube Mbuf is connected to a ramp voltage reference signal node vref, and a drain of the second PMOS tube Mbuf is grounded.

[0051] Specifically, in this embodiment,

[0052] The image signal superimposed with the first power supply noise signal is:

[0053]

[0054] The comparison signal with the second power supply noise signal superimposed is:

[0055]

[0056] Among them, v noise is the noise supply voltage, C p is the first capacitor, C fd is the second capacitor, C bias is the total capacitance of the bias voltage node, M buf is the buffer transistor, M bias is the bias transistor, W and L are the width and length of the MOS tube respectively, gmb sf It is the small signal body transconductance that characterizes the source follower transistor. It is related to the voltage difference between the body terminal and the source terminal. When the body terminal and the source terminal are connected together, gmb sf =0, then the capacitance adjustment can be more effective, gm sf , gm buf, gm bias They are the transconductance of the source follower transistor, buffer transistor, and bias transistor. By adjusting C c Make the difference Minimize noise suppression.

[0057] It is worth mentioning that the optimal situation is that the amplitude of the second power supply noise signal is equal to the amplitude of the first power supply noise signal, and the amplitude difference between the two noise signals can be minimized by adjusting the variable capacitor.

[0058] In one implementation, the first input terminal of the comparator 13 is an inverting input terminal, and the second input terminal of the comparator 13 is a non-inverting input terminal.

[0059] In one embodiment, the bias voltage node vbias is connected to a current mirror circuit to provide a bias voltage.

[0060] In one embodiment, the variable capacitor Cc includes a variable-sized capacitor.

[0061] Specifically, the variable capacitor Cc includes a capacitor with a variable size, and the image sensor can control the amplitude of the second noise signal by adjusting the size of the variable capacitor.

[0062] In one embodiment, the variable capacitor Cc includes a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control the conduction of each constant capacitor.

[0063] Specifically, the variable capacitor Cc can be implemented by a plurality of parallel constant capacitors and a plurality of corresponding switches, and the capacitance value is changed by controlling the on / off of each switch to adjust the size of the variable capacitor to control the amplitude of the second noise signal.

[0064] In one embodiment, the bias capacitor Cbias is a variable capacitor.

[0065] In summary, the power supply noise suppression circuit provided by the embodiment of the present invention is provided by setting a pixel circuit, a comparison signal generating circuit and a comparator, wherein the pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, and the comparison signal generating circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, and the second power supply noise signal has the same amplitude as the first power supply noise signal to offset the power supply noise in the pixel circuit; wherein the comparison signal generating circuit includes a capacitance adjustment module, a first PMOS tube and a second PMOS tube, and the capacitance adjustment module includes a variable capacitor and a bias capacitor; the first end of the variable capacitor is connected to the noise power supply, the second end of the variable capacitor is connected to the first end of the bias capacitor, and the second end of the bias capacitor is grounded; the source of the first PMOS tube is connected to the noise power supply, the gate of the first PMOS tube is connected to the bias voltage node and connected to the first end of the bias capacitor, and the drain of the first PMOS tube is connected to the second input terminal of the comparator; the source of the second PMOS tube is connected to the second input terminal of the comparator, the gate of the second PMOS tube is connected to the ramp voltage reference signal node, and the drain of the second PMOS tube is grounded. The present invention introduces noise into the comparison signal generating circuit through a comparator, so that the power supply noise appears as the common mode noise of the comparator, thereby suppressing the power supply noise in the pixel circuit, and can effectively resist power supply noise interference, reduce image noise and improve image quality.

[0066] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the present invention. The various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

Claims

1. A power supply noise suppression circuit, characterized in that: The circuit includes a pixel circuit, a comparison signal generating circuit and a comparator; The pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, and the comparison signal generating circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, wherein the second power supply noise signal has the same amplitude as the first power supply noise signal, so as to offset the power supply noise in the pixel circuit; Wherein, the comparison signal generating circuit includes a capacitance adjustment module, a buffer transistor and a bias transistor, and the capacitance adjustment module includes a variable capacitor and a bias capacitor; The first end of the variable capacitor is connected to the noise power supply, the second end of the variable capacitor is connected to the first end of the bias capacitor, and the second end of the bias capacitor is grounded; The buffer transistor and the bias transistor are connected in series between the noise power supply and the ground, the gate of the buffer transistor receives a voltage reference signal, the voltage reference signal is a ramp voltage reference signal, the buffer transistor is used to suppress the influence of the reverse noise of the comparator end on the ramp voltage reference signal, and the gate of the bias transistor is connected to the bias voltage node and connected to the first end of the bias capacitor; The comparison signal with the second power supply noise signal superimposed is: Among them, v noise is the noise supply voltage, C bias is the total capacitance of the bias voltage node, C c is the value of the variable capacitor; M buf is the buffer transistor, M bias is the bias transistor, W and L are the width and length of the transistor respectively, gm buf , gm bias They are the transconductance of the buffer transistor and the bias transistor respectively; The value of the variable capacitor is adjusted to make the second power supply noise signal have the same amplitude as the first power supply noise signal, so as to cancel the power supply noise in the pixel circuit.

2. The power supply noise suppression circuit according to claim 1, characterized in that: The buffer transistor is a first NMOS transistor, and the bias transistor is a second NMOS transistor; the drain of the first NMOS transistor is connected to the noise power supply, the gate of the first NMOS transistor is connected to the voltage reference signal node, and the source of the first NMOS transistor is connected to the second input terminal of the comparator; the drain of the second NMOS transistor is connected to the second input terminal of the comparator, the gate of the second NMOS transistor is connected to the bias voltage node and connected to the first end of the bias capacitor, and the source of the second NMOS transistor is grounded.

3. The power supply noise suppression circuit according to claim 1, characterized in that: The bias transistor is a first PMOS tube, and the buffer transistor is a second PMOS tube; the source of the first PMOS tube is connected to the noise power supply, the gate of the first PMOS tube is connected to the bias voltage node and connected to the first end of the bias capacitor, and the drain of the first PMOS tube is connected to the second input end of the comparator; the source of the second PMOS tube is connected to the second input end of the comparator, the gate of the second PMOS tube is connected to the voltage reference signal node, and the drain of the second PMOS tube is grounded.

4. The power supply noise suppression circuit according to claim 1, characterized in that: The bias voltage node is connected to a current mirror circuit to provide a bias voltage.

5. The power supply noise suppression circuit according to claim 1, characterized in that: The variable capacitor includes a capacitance whose size can be changed.

6. The power supply noise suppression circuit according to claim 1, characterized in that: The variable capacitor includes a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control the conduction of each constant capacitor.

7. The power supply noise suppression circuit according to claim 1, characterized in that: The first input terminal of the comparator is an inverting input terminal, and the second input terminal of the comparator is a non-inverting input terminal.

8. The power supply noise suppression circuit according to claim 1, characterized in that: The bias capacitor is a variable capacitor.

9. The power supply noise suppression circuit according to claim 1, characterized in that: The pixel circuit includes a first capacitor connected between the drain and gate of the source follower transistor and a second capacitor connected between the gate of the source follower transistor and ground. The first capacitor is the total coupling capacitance between the pixel power line, the pixel control signal line related to the power supply and the floating diffusion node, and the second capacitor is all the parasitic capacitance on the floating diffusion node minus the first capacitor.

10. The power supply noise suppression circuit according to claim 9, characterized in that: The image signal superimposed with the first power supply noise signal is: Among them, C p is the first capacitor, C fd is the second capacitor, gmb sf is the small signal bulk transconductance that characterizes the source follower transistor, gm sf is the transconductance of the source follower transistor, by adjusting C c Make the difference Minimize noise suppression.

11. An image sensor, characterized in that: The invention comprises a power supply noise suppression circuit as described in any one of claims 1 to 10.

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