Low power display driving circuit performing internal encoding and decoding and operating method thereof

Abstract

A low-power display driving circuit performing internal encoding and decoding and an operating method thereof are provided. The display driving circuit includes a memory configured to store an input bitstream encoded by an encoder, and a controller configured to determine a data path through which output frame data in a second frame period passes according to whether internal encoding in a first frame period is successful, wherein, when the internal encoding is successful, the controller performs the internal encoding in the second frame period, stores a generated internal bitstream in the memory, allows the internal bitstream to pass through a low-power path to generate the output frame data, and, when the internal encoding fails, the controller generates the output frame data in the second frame period by allowing the input bitstream to pass through a normal path, changes an encoding setting of the internal encoder, and repeats the internal encoding.

Description

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0123322, filed with the Korean Intellectual Property Office on September 23, 2020, and Korean Patent Application No. 10-2021-0061644, filed with the Korean Intellectual Property Office on May 12, 2021, the subject matter of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a display driving circuit, and more specifically, to a display driving circuit and its operation method implemented with low power by performing internal encoding and decoding. Background Technology

[0004] The display device includes a display panel for displaying images and a display driving circuit for driving the display panel. The display driving circuit can receive image data from the outside and perform multiple image processing steps.

[0005] Meanwhile, the display driver circuit can receive still images, and even when holding a still image, it must output an image signal every set frame period. In this case, power consumption may increase because image processing is repeatedly performed on the same image data every frame period. Summary of the Invention

[0006] The present invention provides a display driving circuit and its operation method that achieve low power by repeatedly executing internal encoding while changing encoding settings.

[0007] According to one aspect of the present invention, a display driving circuit for outputting a still image is provided. The display driving circuit includes a memory and a controller. The memory is configured to store an input bitstream encoded by a first encoder based on the still image. The controller is configured to determine the data path traversed by output frame data in a second frame period based on whether internal encoding in a first frame period is successful. When internal encoding is successful, the controller is configured to perform internal encoding in the second frame period, store the generated internal bitstream in the memory, allow the internal bitstream to traverse a low-power path to generate output frame data, and when internal encoding fails, the controller is configured to generate output frame data in the second frame period by allowing the input bitstream to traverse a normal path, changing the encoding settings of the internal encoder, and repeating the internal encoding.

[0008] According to another aspect of the present invention, a method is provided for operating a display driving circuit that outputs a still image, the method comprising: generating multiple frame data segments based on an input bit stream in a first frame period; determining at least one of the multiple frame data segments as data to be encoded; performing internal encoding on the data to be encoded; changing at least one of the data to be encoded or the encoding settings when the internal encoding fails; and repeating the internal encoding in a second frame period.

[0009] According to another aspect of the present invention, a display driving circuit is provided, comprising: a memory configured to store an input bitstream; a first decoder configured to decode the input bitstream to generate a first frame of data; a plurality of image processors configured to perform image processing on the first frame of data to generate multiple segments of processed data; an internal encoder configured to perform internal encoding on at least one of the multiple segments of processed data; an internal decoder configured to decode the internal bitstream stored in the memory and output a decoded bitstream when the internal encoding is successful; and a controller configured to change the encoding settings of the internal encoder and control the internal encoder to repeat the internal encoding when the internal encoding fails. Attached Figure Description

[0010] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the concept of the present invention;

[0012] Figure 2 This is a block diagram illustrating a host processor according to an exemplary embodiment of the concept of the present invention;

[0013] Figure 3 This is a block diagram illustrating a display driving circuit according to an exemplary embodiment of the concept of the present invention;

[0014] Figure 4A and Figure 4B This is a diagram illustrating a data path according to an example embodiment of the concept of the present invention;

[0015] Figure 5 This is a timing diagram of a display driving circuit according to an exemplary embodiment of the present invention;

[0016] Figure 6 and Figure 7 This is a flowchart illustrating a method for operating a display driving circuit according to an exemplary embodiment of the present invention;

[0017] Figure 8A and Figure 8B This is a flowchart illustrating a lossless encoding method for a repeating display driving circuit according to an exemplary embodiment of the present invention;

[0018] Figure 9 This is a block diagram illustrating a display driving circuit according to an exemplary embodiment of the concept of the present invention;

[0019] Figure 10 This is a conceptual diagram illustrating a method for operating a display driving circuit according to an exemplary embodiment of the present invention;

[0020] Figure 11 This is a timing diagram of a display driving circuit according to an exemplary embodiment of the present invention;

[0021] Figure 12 This is a flowchart illustrating a method for internal encoding of a repeating display driving circuit according to an exemplary embodiment of the present invention;

[0022] Figure 13 This is a flowchart illustrating a method for operating a display driving circuit according to an exemplary embodiment of the present invention;

[0023] Figure 14 This is a block diagram illustrating a portion of a display driving circuit according to an exemplary embodiment of the present invention; and

[0024] Figure 15 This is a timing diagram of a display driving circuit according to an exemplary embodiment of the present invention. Detailed Implementation

[0025] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 This is a block diagram illustrating an example embodiment of an electronic device 10 according to a concept of the present invention.

[0027] Reference Figure 1 The electronic device 10 may include a host processor 100, a display driver circuit (or display driver (DDI)) 200, and a display panel 300.

[0028] According to various embodiments, electronic device 10 may include a device with image display capabilities. For example, electronic device 10 may include a smartphone, tablet PC, portable multimedia player (PMP), camera, wearable device, Internet of Things (IoT) device, television, digital video disc (DVD) player, refrigerator, air conditioner, air purifier, set-top box (STB), robot, drone, various medical devices, navigation device, global positioning system (GPS) receiver, advanced driver assistance system (ADAS), vehicle device, furniture, or various measuring instruments.

[0029] The host processor 100 can control the electronic device 10 as a whole. The host processor 100 can generate image data (IMAGE DATA) to be displayed on the display panel 300 and send the image data (IMAGE DATA) to the display driver circuit 200. As an example, the host processor 100 can encode the image data (IMAGE DATA) and send the encoded image result as an input bitstream to the display driver circuit 200.

[0030] The host processor 100 can display moving images (or videos) on the display panel 300, and a portion of the moving image can be stationary for a specific period of time. In this case, the host processor 100 can send the stationary image data (IMAGE DATA) to the display driver circuit 200, and will not send the image data (IMAGE DATA) to the display driver circuit 200 for a certain period of time thereafter. The display driver circuit 200 can output the received image data (IMAGE DATA) to the display panel 300 for the specific period of time.

[0031] Subsequently, when the static state of the moving image ends, the host processor 100 can send new image data IMAGEDATA to the display driver circuit 200.

[0032] In some embodiments, the host processor 100 may correspond to an application processor. However, the inventive concept is not limited thereto, and the host processor 100 may be implemented as various types of processors, such as a central processing unit (CPU), a microprocessor, a multimedia processor, and a graphics processing unit. For example, the host processor 100 may be implemented as an integrated circuit (IC), or as a mobile application processor (AP) or a system-on-a-chip (SoC).

[0033] The display driver circuit 200 can receive image data IMAGE DATA from the host processor 100, convert the image data IMAGE DATA into frame data FD_OUT, and send the frame data result to the display panel 300 to drive the display panel 300.

[0034] In some embodiments, in order to periodically output still images within a specific time period, the display driving circuit 200 may store image data IMAGE DATA received from the host processor 100 and periodically output the stored image data IMAGE DATA to the display panel 300.

[0035] To output image data, the display driver circuit 200 can encode and store the processed data results after multiple image processing operations, and periodically decode and output the decoded data results, instead of repeatedly performing image processing operations. Therefore, when maintaining a still image, image processing operations can be avoided to reduce the power consumption of the display driver circuit 200.

[0036] According to an embodiment of the present invention, the display driving circuit 200 may include an encoding controller 210. The success of encoding the processed data result can be determined based on the encoding environment or settings, and when encoding of the processed data result fails, the encoding controller 210 can re-encode while changing the encoding settings to increase the probability of successful encoding.

[0037] In some embodiments, the encoding controller 210 can modify the processed data to be encoded. For example, as the image complexity of the processed data increases, the probability of encoding failure increases. Therefore, the encoding controller 210 can determine processed data with low image complexity as the data to be encoded. (See below for further details.) Figures 3 to 8B This embodiment is described.

[0038] In some embodiments, the encoding controller 210 can change the bit depth of the data to be encoded. (See below for further details.) Figures 9 to 13 This embodiment is described.

[0039] In some embodiments, the encoding controller 210 may change the time period used to store the bitstream generated as a result of encoding in memory. (See below for further details.) Figure 14 and Figure 15 This embodiment is described.

[0040] Display panel 300 is a display unit that displays an actual image. It may include a display device that displays a two-dimensional (2D) image upon receiving an electrically transmitted image signal IS, such as a thin-film transistor liquid crystal display (TFT-LCD), an organic light-emitting diode (OLED) display, a field emission display, and a plasma display panel (PDP). Display panel 300 may be implemented as another type of flat panel display or flexible display panel.

[0041] Figure 2 This is a block diagram illustrating a host processor according to an exemplary embodiment of the concept of the present invention.

[0042] Reference Figure 2 The host processor 100 may include a first encoder 110 and an interface circuit (I / F) 120.

[0043] The first encoder 110 can perform encoding on image data IMAGE DATA. According to an embodiment, the first encoder 110 can generate an input bitstream by encoding the image data IMAGE DATA corresponding to a still image. The first encoder 110 can perform encoding on the first frame of the still image, and may not perform encoding on the image data IMAGE DATA in subsequent frame periods. Hereinafter, the image data IMAGE DATA generated by the first encoder 110 is referred to as the input bitstream (e.g., Figure 3 (BS_IN). The first encoder 110 can be implemented as a Display Stream Compression (DSC) encoder, but is not limited thereto.

[0044] The I / F 120 can send the encoded image data result (IMAGE DATA) to the display driver circuit 200 via a channel. In an exemplary embodiment, the I / F 120 can support RGB interfaces, CPU interfaces, serial interfaces, Mobile Display Digital Interface (MDDI), Internal Integrated Circuit (I2C) interfaces, Serial Peripheral Interface (SPI), Microcontroller Unit (MCU) interfaces, Mobile Industrial Processor Interface (MIPI), Embedded Display Port (eDP) interfaces, D-sub interfaces, optical interfaces, High Definition Multimedia Interface (HDMI), etc. Furthermore, in one example embodiment, the I / F 120 can also support Mobile High Definition Link (MHL) interfaces, Secure Digital (SD) card / Multimedia Card (MMC) interfaces, or Infrared Data Association (IrDA) standard interfaces.

[0045] Figure 3 This is a block diagram illustrating a display driving circuit 400 according to an exemplary embodiment of the present invention.

[0046] Reference Figure 3 The display driving circuit 400 may include a host I / F 401, a graphics memory (GRAM) 403, a first decoder 405, multiple image processors 406, 408, and 410 (including a first image processor 406, a second image processor 408, and a third image processor 410), a second encoder 413, a second decoder 414, first to fifth multiplexers (MUX) 402, 407, 409, 411, and 412, a first demultiplexer (DEMUX) 404, and an encoding controller 415. Furthermore, the display driving circuit 400 may also include a source driver that generates a driving signal based on the output frame data FD_OUT and sends the generated driving signal to the display panel 300.

[0047] The host I / F 401 can receive the input bitstream BS_IN from the host processor 100 and send the received bitstream BS_IN to other components of the display driver circuit 400, including the encoding controller 415. The host I / F 401 can correspond to... Figure 2 I / F 120.

[0048] GRAM 403 can store the input bitstream BS_IN compressed by the first encoder 110 of the host processor 100. Furthermore, GRAM 403 can store at least one of the processing data results generated by image processors 406, 408, and 410, and a bitstream compressed by the second encoder 413. GRAM 403 can output the stored data under the control of the encoding controller 415.

[0049] GRAM 403 includes volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM)) or non-volatile memory (such as ROM or flash memory, resistive random access memory (ReRAM) and magnetic random access memory (MRAM)).

[0050] The first decoder 405 can decode the input bitstream BS_IN encoded by the first encoder 110 of the host processor 100. The decoding method of the first decoder 405 can correspond to the encoding method of the first encoder 110, therefore, it can only decode data encoded by the first encoder 110.

[0051] Image processors 406, 408, and 410 can perform various image processing required to display the input bitstream BS_IN received from host processor 100 on display panel 300, and can include commands for it.

[0052] For example, image processors 406, 408, and 410 may include a vertex shader module, a geometry shader module, a pixel shader module, a rasterizer module, a blending module, a tessellation module, an interpolation module, a dithering module, and a subpixel rendering module.

[0053] At least one of the image processors 406, 408, and 410 can be powered off depending on the operating mode and / or data path of the display driving circuit 400. For example, when the display driving circuit 400 operates in low-power mode, the image processors other than the dithering module and the subpixel rendering module can be powered off.

[0054] The second encoder 413 can encode the data IP1_FD, IP2_FD, and IP3_FD generated by components within the display driving circuit 400. For example, the second encoder 413 can encode the frame data FD generated by the first decoder 405 and the processing data results output from each of the image processors 406, 408, and 410.

[0055] In some embodiments, the second encoder 413 can encode data in a lossless manner, and therefore, the second encoder 413 can be referred to as a lossless encoder. Hereinafter, the second encoder 413 is referred to as a lossless encoder, and the bitstream generated by the second encoder 413 is referred to as a lossless bitstream (LLBS), but is not limited thereto. As an example, because the second encoder 413 is located inside the display driver circuit 400, the second encoder 413 can also be referred to as an internal encoder.

[0056] The second decoder 414 may correspond to the second encoder 413 and decodes the data encoded by the second encoder 413. In some embodiments, because the second decoder 414 can decode the bitstream BS_IN in a lossless manner, the second decoder 414 may be referred to as a lossless decoder, and the frame data generated as a result of lossless decoding may be referred to as lossless frame data LLFD. The LLFD may be the same as the data before the LLBS was encoded. In some embodiments, since the second decoder 414 is located inside the display driver circuit 400, the second decoder 414 may also be referred to as an internal decoder.

[0057] According to an embodiment of the present invention, because the still image is maintained for a specific time period, the input bitstream BS_IN may not be received from the host I / F 401 during this specific time period. Therefore, when the input bitstream BS_IN constituting the first frame of the still image is received, the encoding controller 415 can store the received input bitstream BS_IN. During the frame period when no bitstream BS_IN is received from the outside, the encoding controller 415 can periodically output the input bitstream BS_IN from the GRAM 403 to generate output frame data FD_OUT. Therefore, the display panel 300 can output the still image to the screen at predetermined intervals.

[0058] The encoding controller 415 can determine the data path traversed by the input bit stream BS_IN in order to generate output frame data FD_OUT based on the input bit stream BS_IN stored in GRAM 403.

[0059] The encoding controller 415 can control the operation of the components of the display driver circuit 400 according to the data path, and can generate control signals SEL1 to SEL6 to determine, for example, the outputs of the first to fifth multiplexers MUX 402, MUX 407, MUX 409, MUX 411 and MUX 412 and the first demultiplexer DEMUX 404.

[0060] The encoding controller 415 can generate output frame data FD_OUT by allowing the input bitstream BS_IN received from the host processor 100 to pass through a normal path or by allowing the LLBS generated via the second encoder 413 to pass through a low-power path. The normal path refers to the path through which the input bitstream BS_IN is output by all the image processors of the display driver circuit 400, and the low-power path refers to the path through which the stored bitstream is output only by some components. See below for further details. Figure 4A and Figure 4B Describe the normal path and the low-power path.

[0061] While periodically generating output frame data FD_OUT, the encoding controller 415 can generate LLBS and lossless frame data LLFD to perform a low-power path. That is, the second encoder 413 and the second decoder 414 can be operated. As an example, lossless encoding can be performed on any of the frame data output from the first decoder 405 and the multiple segments of processed data output from image processors 406, 408, and 410, respectively. This lossless encoding can be performed in parallel with the operation of generating the output frame data.

[0062] According to embodiments of the present invention, since the processed data generated after the completion of specific image processing is internally compressed and stored, and the stored data (i.e., LLBS) is decoded and output, it is not necessary to repeat the specific image processing in each cycle of the output frame.

[0063] In other words, it is possible to power on only the second decoder 414 that decodes the stored data and the image processor that has not yet processed the data, while powering off other components that have already processed the data (e.g., the first decoder 405 and the image processor).

[0064] Furthermore, since lossless coding is a variable bit rate (VBR) method, the size of the output LLBS is non-uniform. If the LLBS size is irregular, in some cases the LLBS cannot be stored in GRAM 403, and it may be difficult to implement low-power paths.

[0065] Therefore, according to embodiments of the present invention, the data to be encoded or the encoding settings can be changed to enable successful lossless encoding. In embodiments, lossless encoding can be performed repeatedly while changing the processing data and encoding settings input to the second encoder 413. Thus, a low-power path can be implemented under various conditions, such as the characteristics of still images and uncertainties in lossless encoding methods.

[0066] Figure 4A and Figure 4B This is a diagram illustrating a data path according to an example embodiment of the concept of the present invention.

[0067] Hereinafter, it is assumed that the host processor 100 receives the input bitstream BS_IN corresponding to the first frame of the still image and completes the storage of the input bitstream BS_IN in GRAM 403. Figure 4A The diagram illustrates the normal path 400a in the first frame period and the lossless encoding performed in parallel with the normal path 400a. Figure 4B The low-power path 400b in the second frame period is shown when lossless encoding is successful.

[0068] refer to Figure 4A The input bitstream BS_IN stored in GRAM 403 can be provided to the first decoder 405 via the first DEMUX 404. The first decoder 405 can perform decoding corresponding to the encoding method of the first encoder 110 to generate frame data FD.

[0069] While the frame data FD passes through the first to third image processors 406, 408, and 410, various image processing techniques can be applied to the frame data FD. The data output from each image processor is called processed data. In the normal path 400a, the third processed data IP3_FD that has passed through the first image processor 406, the second image processor 408, and the third image processor 410 can be identified as the output frame data FD_OUT and can be provided to the source driver.

[0070] In parallel with the implementation of normal path 400a, the first to third processed data IP1_FD, IP2_FD, and IP3_FD output from the first to third image processors 406, 408, and 410, respectively, can be provided to the second encoder 413 via the fifth MUX 412. The second encoder 413 can perform lossless encoding on any of the first to third processed data IP1_FD, IP2_FD, and IP3_FD under the control of the encoding controller 415.

[0071] When the lossless encoding of the second encoder 413 is successful, the generated LLBS can be stored in GRAM 403 through the first MUX 402.

[0072] When lossless encoding by the second encoder 413 fails, lossless encoding can be repeated in the next frame period. As an example, the second encoder 413 can perform lossless encoding on the third processed data IP3_FD in the first frame period, and if lossless encoding fails, the second encoder 413 can perform lossless encoding on the second processed data IP2_FD in the second frame period.

[0073] refer to Figure 4B The second encoder 413 can perform lossless encoding on the first processed data IP1_FD and store the resulting LLBS in GRAM 403.

[0074] Subsequently, the LLBS stored in GRAM 403 can be provided to the second decoder 414 via the first DEMUX 404. The second decoder 414 can perform decoding corresponding to the encoding method of the second encoder 413 to generate lossless frame data LLFD. In any case, the lossless frame data LLFD is the same as the first processed data IP1_FD in terms of the characteristics of the lossless encoding method, and therefore the lossless frame data LLFD can be output to the source driver via the second image processor 408 and the third image processor 410.

[0075] Therefore, the power to the first decoder 405 and the first image processor 406 can be turned off because the first processed data IP1_FD has already passed through the first decoder 405 and the first image processor 406.

[0076] Therefore, the electronic device 10, including the display driving circuit 400, can operate in a low-power mode. For example, the low-power mode could be an always-on display (AoD) mode that displays a preset image on the screen.

[0077] In AoD mode, the normal path 400a may include only the necessary image processors from image processors 406, 408, and 410, and in this case, the non-essential image processors may be in a powered-off state. For example, the necessary image processors may include a subpixel rendering module and a dithering module. Because the non-essential image processors are not operating, the image quality of the AoD image may be degraded.

[0078] According to embodiments of the present invention, even in the normal path of AoD mode, non-essential image processors can be operated and lossless encoding can be performed. When lossless encoding is successful, not only can non-essential image processors be powered off, but essential image processors can also be powered off, thereby reducing power consumption and improving output image quality.

[0079] Figure 5This is a timing diagram of a display driver circuit according to an exemplary embodiment of the present invention. Data input to each component is shown, and output data is omitted. However, the timing of data input to each component is not limited to this timing diagram. Each of t1 to t6 can refer to the time when the vertical synchronization signal Vsync is logic high. Output frame data FD_OUT can be generated five times when the normal path 400a or low-power path 400b is executed five times during the first frame period t1 to t2 to the fifth frame period t5 to t6. When a still image is output during t1 to t6, the host I / F 401 can receive the input bitstream BS_IN corresponding to the first frame of the still image only once.

[0080] Please refer to the above. Figure 3 and Figure 5 During the first frame period t1 to t2, the host I / F 401 can receive the input bitstream BS_IN and store the received input bitstream BS_IN in GRAM 403. The received input bitstream BS_IN can correspond to the first frame of the still image.

[0081] Through normal path 400a, the first decoder 405 can decode the input bitstream BS_IN to generate frame data FD, the first image processor 406 can perform image processing to generate first processed data IP1_FD, the second image processor 408 can perform image processing to generate second processed data IP2_FD, and the third image processor 410 can perform image processing to generate third processed data IP3_FD. Thereafter, the third processed data IP3_FD can be provided to the source driver.

[0082] Here, the second encoder 413 can receive the third processing data IP3_FD and perform lossless encoding on it. In some cases, lossless encoding may fail because the image complexity of the third processing data IP3_FD is high, or the data generated as a result of lossless encoding may be too large to be stored in GRAM 403.

[0083] During the second frame period t2 to t3, the input bitstream BS_IN stored in GRAM 403 can be output. As in the first frame period t1 to t2, through normal path 400a, the first decoder 405 can generate frame data FD, the first image processor 406 can generate first processing data IP1_FD, the second image processor 408 can generate second processing data IP2_FD, and the third image processor 410 can generate third processing data IP3_FD, and the third processing data IP3_FD can be provided to the source driver.

[0084] Here, the second encoder 413 can receive the second processed data IP2_FD and perform lossless encoding on it. For example, the lossless encoding of the second processed data IP2_FD may fail, and the lossless encoding can be repeated as the encoding settings are changed in the next frame period.

[0085] During the third frame period t3 to t4, the input bitstream BS_IN, which was stored in GRAM 403 during the first frame period t1 to t2, can be output. The input bitstream BS_IN can pass through the normal path 400a, and the third processing data IP3_FD can be provided to the source driver.

[0086] Here, the second encoder 413 can receive the first processed data IP1_FD and perform lossless encoding on it. Because the image complexity of the first processed data IP1_FD can be lower than that of the second processed data IP2_FD and the third processed data IP3_FD, the lossless encoding can be successful.

[0087] In the fourth frame period t4 to t5, based on information about the successful lossless encoding in the third frame period t3 to t4, lossless encoding can be performed using the same settings as the lossless encoding performed in the third frame period t3 to t4. That is, the second encoder 413 can encode the first processed data IP1_FD, and the resulting LLBS can be stored in GRAM 403. In this case, depending on the performance of GRAM 403, the LLBS can be directly stored in GRAM 403 in the fourth frame period t4 to t5.

[0088] The source driver can receive the third-processed data IP3_FD generated when the input bitstream BS_IN passes through the normal path 400a.

[0089] During the fifth frame period t5 to t6, a low-power path 400b for LLBS can be executed, replacing the normal path 400a for the input bitstream BS_IN. Therefore, the first decoder 405, the first image processor 406, and the second encoder 413 can be powered down.

[0090] Through low-power path 400b, the second decoder 414 can decode the LLBS to generate lossless frame data LLFD. Since the LLBS is generated based on the first processed data IP1_FD, the lossless frame data LLFD can be the same as the first processed data IP1_FD. Therefore, the second image processor 408 can receive the lossless frame data LLFD and perform image processing to generate second processed data IP2_FD, and the third image processor 410 can perform image processing to generate third processed data IP3_FD. The third processed data IP3_FD can then be provided to the source driver.

[0091] Subsequently, while maintaining a still image, the system can enter low-power path 400b and provide the third processing data IP3_FD to the source driver. Simultaneously, when the still image terminates, the host I / F 401 can receive a new input bitstream BS_IN, thus terminating low-power path 400b and re-entering normal path 400a.

[0092] Figure 6 and Figure 7 This is a flowchart illustrating a method for operating a display driving circuit according to an exemplary embodiment of the present invention. Figure 6 The operation in the first frame period is shown. Figure 7 The operation during the second frame period is shown.

[0093] Please refer to the above. Figure 3 and Figure 6 The normal path can be executed in the first frame period (S110), and output frame data FD_OUT can be generated (S120). As an example, the normal path may include a first decoder 405 and a plurality of image processors 406, 408 and 410, and the output frame data FD_OUT may be third processing data IP3_FD.

[0094] In parallel with entering the normal path, lossless encoding can be performed on at least one of the frame data generated in the normal path and the multi-segment processed data (S130).

[0095] When lossless encoding is successful, the generated LLBS can be stored in GRAM 403 (S140), and when lossless encoding fails, the first frame period can be terminated. Meanwhile, to improve the operating speed and stability of GRAM 403, LLBS can be stored in GRAM 403 in subsequent frame periods after the first frame period.

[0096] Please refer to the above. Figure 3 and Figure 7 The result of the lossless encoding performed in the first frame period is confirmed (S210), and thus the path for generating the output frame data FD_OUT in the second frame period can be determined. The second frame period is not limited to the frame period immediately following the first frame period, but can represent, for example, the frame period after the LLBS is stored in GRAM 403.

[0097] When lossless encoding fails and only the input bitstream BS_IN is stored in GRAM 403, the input bitstream BS_IN can enter the normal path (S220). In parallel with the normal path, lossless encoding can be repeated as the encoding environment or settings change (S230). As a result of the normal path, output frame data FD_OUT can be generated and output (S240).

[0098] As an example of changing encoding settings, refer to the above. Figures 3 to 5 As mentioned above, the data to be processed through lossless encoding can be changed. Furthermore, several embodiments for changing the encoding settings will be described later.

[0099] When lossless encoding is successful and the LLBS is stored in GRAM 403, the components that the LLBS passed before encoding can be powered off (S250).

[0100] As the LLBS passes through the low-power path 400b (S260), output frame data FD_OUT can be generated (S240). The low-power path 400b may include components other than the components that are powered off (e.g., the second decoder 414 and image processors 406, 408 and 410), and the output frame data FD_OUT may be third processed data IP3_FD.

[0101] Figure 8A and Figure 8B This is a flowchart illustrating an exemplary embodiment of a method for repeated lossless encoding via a display driving circuit according to a concept of the present invention. (Refer to the above) Figures 3 to 5 As described above, the encoding settings can be changed, and lossless encoding can be repeated. Hereinafter, it is assumed that the display driver circuit 400 includes n+1 image processors.

[0102] Reference Figure 8A Lossless encoding can be performed on the nth processed data generated by the first to nth image processors in the first frame period (S310). If lossless encoding fails (S320), lossless encoding is repeated on the (n-1)th processed data generated by the first to n-1th image processors in the second frame period, which is the subsequent frame period (S330).

[0103] Reference Figure 8B Lossless encoding can be performed on the nth processed data generated by the first to nth image processors in the first frame period (S410). If the lossless encoding fails (S420), lossless encoding can be repeated on the (n+1)th processed data generated by the first to n+1th image processors in the second frame period, which is the subsequent frame period (S430). At this time, the first to nth image processors can be connected to the front end of the (n+1)th image processor. That is, the operation of the first to nth image processors can be performed before the operation of the (n+1)th image processor.

[0104] Changing the order of the data to be encoded is not limited to this; for example, lossless encoding can be performed on the determined processing data according to a predetermined order.

[0105] Figure 9This is a block diagram illustrating a display driving circuit 500 according to an exemplary embodiment of the concept of the present invention, and Figure 10 This is a conceptual diagram illustrating a method of operating a display driving circuit according to an exemplary embodiment of the present invention. Since the display driving circuit 500 is similar to... Figure 3 The display driver circuit 400 is omitted here, so its redundant description will be omitted.

[0106] refer to Figure 9 The encoding controller 510 can change the bit depth of the data to be encoded (i.e., the data E_DATA to be encoded) by providing a first control signal CTRL_BD1 and / or a second control signal CTRL_BD2, thereby changing the encoding settings. Additionally, the bit depth of the bitstream to be decoded (i.e., the data D_DATA to be decoded) can be changed to correspond to it. That is, with... Figure 3 Unlike lossless methods, the second encoder 508 and the second decoder 509 can perform internal encoding and decoding in a manner different from lossless methods. Therefore, the data input to the second encoder 508 and the data output from the second decoder 509 may not be exactly the same. Thus, in the following text, the output from the second encoder 508 is referred to as the Internal Bit Stream (IBS), while the output from the second decoder 509 is referred to as the Internal Frame Data (IFD).

[0107] Reference Figure 10 The image data generated by the host processor 100 can be an RGB image, and Figure 10 This indicates the bit depth of any one of the RGB channels. The frame data FD can be generated from the input bitstream BS_IN via the normal path, and the bit depth of the frame data FD can be 8 bits. The bit depth can increase as the frame data FD undergoes multiple image processing steps. For example, the bit depth of the processed data IP_FD after undergoing multiple image processors can be 10 bits.

[0108] If the bit depth of the data to be encoded, E_DATA, is large, the probability of internal encoding failure may increase. Therefore, the encoding controller 510 can increase the probability of successful internal encoding by reducing the bit depth of the processed data, IP_FD. The encoding controller 510 can change the number of bits to be reduced by providing a first control signal, CTRL_BD1, to the second encoder 508.

[0109] The following description, as an example, illustrates how successful internal encoding can be achieved by reducing the bit depth of the processed data IP_FD by one bit. That is, an IBS with a bit depth of 9 bits can be generated. The encoding controller 510 can recover the reduced bit depth by providing a second control signal CTRL_BD2 to the second decoder 509.

[0110] The second decoder 509 can generate the data to be decoded, D_DATA, by decoding the IBS, and can generate the internal frame data, IFD, by restoring one bit of the data to be decoded, D_DATA.

[0111] Meanwhile, the method for reducing the bit depth of the processed data IP_FD and the method for restoring the bit depth of IBS executed by the encoding controller 510 are not limited to any one of them. As an example, the encoding controller 510 can generate the data to be encoded E_DATA by deleting the least significant bit or a bit at a preset position of the processed data IP_FD. Although one bit is deleted as presented and shown in the accompanying drawings, the number of bits to be deleted is not limited to this.

[0112] As an example, the encoding controller 510 can generate internal frame data IFD by restoring bits at deleted positions or predetermined positions. For example, when deleting the least significant bit of processed data IP_FD and generating data to be encoded E_DATA with a bit depth of 9 bits, the encoding controller 510 can generate internal frame data IFD with a bit depth of 10 bits by adding 1 bit to the least significant bit of the data to be decoded D_DATA. Various restoration methods can be used, such as "0" padding, "1" padding, extended jitter, etc.

[0113] Meanwhile, the bit depth of the processed data IP_FD can be the same as the bit depth of the input bit stream BS_IN. That is, even after image processing, the bit depth may not increase, and in this case, the encoding controller 510 can omit the operations of reducing the bit depth and restoring the bit depth.

[0114] According to an embodiment of the present invention, the encoding controller 510 can increase the probability of successful encoding by reducing the bit depth of the data to be encoded, E_DATA, and can reduce data corruption by restoring the bit depth and performing decoding.

[0115] Figure 11 This is a timing diagram of a display driving circuit according to an exemplary embodiment of the present invention. Figure 11 The timing diagram can be similar to Figure 5 The timing diagram shows that the normal path is executed from the first frame period t1 to t2 to the fourth frame period t4 to t5, and the low-power path can be executed from the fifth frame period t5 to t6.

[0116] Refer to together Figure 9 , Figure 10 and Figure 11 During the first frame period t1 to t2, the host I / F 501 can receive the input bitstream BS_IN and store the received bitstream BS_IN in GRAM 503. The received input bitstream BS_IN can correspond to the first frame of the still image.

[0117] Through the normal path, the first decoder 505 can decode the input bitstream BS_IN to generate frame data FD, and multiple image processors 506 can perform image processing to generate processed data IP_FD, which can then be provided to the source driver. The second encoder 508 can receive the processed data IP_FD and perform internal encoding on it, although this internal encoding may fail.

[0118] During the second frame period t2 to t3, the input bitstream BS_IN stored in GRAM 503 can be output. As in the first frame period, through the normal path, the first decoder 505 can generate frame data FD, and the image processor 506 can generate processing data IP_FD and provide the generated processing data IP_FD to the source driver.

[0119] The encoding controller 510 can send the first control signal CTRL_BD1 to the second encoder 508, thereby generating data E_DATA to be encoded with a bit depth reduced by 1 bit from the processed data IP_FD. The number of bits reduced is not limited to this. The second encoder 508 can perform internal encoding on the data E_DATA to be encoded based on the first control signal CTRL_BD1, but internal encoding may fail.

[0120] During the third frame period t3 to t4, the normal path can be entered. Here, the encoding controller 510 can send the first control signal CTRL_BD1 to the second encoder 508, thereby generating data E_DATA to be encoded with a bit depth reduced by 2 bits from the processed data IP_FD. The number of bits reduced is not limited to this, and can be different from the number of bits reduced during the second frame period t2 to t3. The second encoder 508 can perform internal encoding based on the first control signal CTRL_BD1, and the internal encoding can be successful.

[0121] During the fourth frame period t4 to t5, internal encoding can be performed with the same settings as the internal encoding performed during the third frame period t3 to t4. That is, the second encoder 508 can generate the IBS by performing internal encoding based on the first control signal CTRL_BD1. The IBS can be stored in GRAM 503. Simultaneously, the IBS can be directly stored in GRAM 503 during the third frame period t3 to t4. The input bitstream BS_IN travels through the normal path, and the resulting processed data IP_FD can be sent to the source driver.

[0122] During the fifth frame period t5 to t6, the first decoder 505, the image processor 506, and the second encoder 508 can be powered off, and the IBS stored in GRAM 503 can enter a low-power path.

[0123] The encoding controller 510 can recover the reduced bit depth of the IBS by sending the second control signal CTRL_BD2 to the second decoder 509. For example, the second decoder 509 can generate the data to be decoded D_DATA by decoding the IBS, and generate the internal frame data IFD by restoring or adding 2 bits to the data to be decoded D_DATA. The second decoder 509 can provide the internal frame data IFD to the source driver.

[0124] Subsequently, while maintaining a still image, a low-power path can be entered, and the internal frame data IFD can be provided to the source driver. Simultaneously, when the still image terminates, the host I / F 501 can receive a new input bitstream BS_IN, and therefore, the low-power path can be terminated and the system can re-enter the normal path.

[0125] Figure 12 This is a flowchart illustrating a method for internal encoding of a repeating display driving circuit according to an exemplary embodiment of the present invention. (Refer to the above) Figures 9 to 11 As mentioned above, the bit depth of the data to be encoded, E_DATA, can be changed, and the internal encoding can be repeated. This can correspond to changing... Figure 7 An embodiment of the encoding environment or settings described in operation S230.

[0126] Reference Figure 12 Internal encoding can be performed on the processed data IP_FD, which is the result of processing by the image processor 506 and has a bit depth N, during the first frame period (S510). If the internal encoding fails (S520), the bit depth of the processed data IP_FD can be changed during the second frame period, which is the next frame period, so that the internal encoding can be repeated (S530). For example, the bit depth can be reduced by 1 bit.

[0127] Figure 13 This is a flowchart illustrating a method for operating a display driving circuit according to an exemplary embodiment of the present invention.

[0128] Reference Figure 13 In the first frame period, the data to be encoded, E_DATA, can be generated by deleting N bits from the bit depth of the processed data IP_FD (S610). If the internal encoding is successful (S620), the IBS is stored in GRAM 503 in the second frame period (S630). For the sake of the operating speed and stability of GRAM 403, the frame period for performing internal encoding can be different from the frame period for storing the IBS.

[0129] In the third frame period, the IBS can be decoded to generate the decoded data result D_DATA (S640). The bit depth corresponding to the deleted bits in the decoded data result D_DATA can be recovered to generate the inner frame data IFD (S650). For example, N bits can be added. As the inner frame data IFD is output to the source driver, a low-power path can be executed. Furthermore, the number of bits added is not limited to this, and a number different from the number of bits deleted can be added.

[0130] Figure 14 This is a block diagram illustrating a portion of a display driving circuit 600 according to an exemplary embodiment of the present invention.

[0131] Reference Figure 14 The display driving circuit 600 may include a second encoder 610 with a buffer 611, a GRAM 620, and an encoding controller 630. The components are similar to those described above, and therefore repeated descriptions are omitted. The buffer 611 may temporarily store LLBS generated through lossless encoding. As an example, the buffer 611 may be an asynchronous buffer or a first-in-first-out (FIFO) buffer.

[0132] Due to the characteristics of lossless coding methods, the size and output period of LLBS can be irregular. Therefore, during a predetermined frame period, the operation of the second encoder 610 can be stopped when buffer 611 is full. Furthermore, due to the bandwidth limitation of GRAM 620, even if buffer 611 is not full, the LLBS stored in buffer 611 may not be stored in GRAM 620.

[0133] Therefore, according to embodiments of the present invention, by changing the encoding settings through altering the output frequency of buffer 611 and the operating frequency of GRAM 620, the success rate of lossless encoding can be increased. As an example, when lossless encoding by the second encoder 610 fails, the encoding controller 630 can generate a first control signal CTRL_FR1 controlling the operating frequency of buffer 611 and a second control signal CTRL_FR2 controlling the operating frequency of GRAM 620, and provide the generated first control signal CTRL_FR1 and the generated second control signal CTRL_FR2 to buffer 611 and GRAM 620. Therefore, even with irregularities in the lossless encoder, buffer 611 can be prevented from becoming fully filled.

[0134] The period of the input encoded LLBS can be different from the period of the output encoded LLBS, and the operating frequency of the components of the display driver circuit can be different from the operating frequency of the GRAM 620. Meanwhile, although in Figure 14 The buffer 611 is shown inside the second encoder 610, but the location of the buffer 611 is not limited thereto.

[0135] Figure 15 This is a timing diagram of a display driving circuit according to an exemplary embodiment of the present invention. Figure 15 The timing diagram can be similar to Figure 5 and Figure 11 The timing diagram shows that the normal path can be entered during the first frame period t1 to t2 to the fourth frame period t4 to t5, and the low-power path can be entered during the fifth frame period t5 to t6.

[0136] Refer to together Figure 14 and Figure 15 During the first frame period t1 to t2, the host I / F 501 can receive the input bitstream BS_IN and store the received input bitstream BS_IN in GRAM 620. The received input bitstream BS_IN can correspond to the first frame of the still image.

[0137] Through the normal path, the first decoder 505 can decode the input bitstream BS_IN to generate frame data FD, the image processor 506 can perform image processing to generate processed data IP_FD, and the processed data IP_FD can be provided to the source driver. The second encoder 610 can receive the processed data IP_FD and perform lossless encoding.

[0138] The operating frequency of GRAM 620 can be a primary frequency, such as 100MHz. In this case, due to the low operating frequency, buffer 611 may be full, and therefore, LLBS may not be stored.

[0139] During the second frame period t2 to t3, the input bitstream BS_IN stored in GRAM 620 can be output. As in the first frame period, through the normal path, the first decoder 505 can generate frame data FD, and the image processor 506 can generate processing data IP_FD and provide the generated processing data IP_FD to the source driver.

[0140] The encoding controller 630 can send a first control signal CTRL_FR1 to the buffer 611 and a second control signal CTRL_FR2 to the GRAM 620, thereby setting each operating frequency to a second frequency. The second frequency can be, for example, 110MHz. Despite the increased operating frequency, lossless encoding may fail because the buffer 611 is full.

[0141] During the third frame period t3 to t4, the normal path can be entered. The encoding controller 630 can set the operating frequency of the buffer 611 and GRAM 620 to a third frequency via the first control signal CTRL_FR1 and the second control signal CTRL_FR2. The third frequency can be, for example, 150MHz. Because the bandwidth of GRAM 620 is increased, the generated LLBS can be sufficiently stored in GRAM 620. LLBS can be directly stored in GRAM 620 during the corresponding frame period, or LLBS can be stored in the next frame period for stable operation.

[0142] During the fourth frame period t4 to t5, lossless encoding can be performed using the same settings as the lossless encoding performed during the third frame period t3 to t4. That is, the operating frequencies of buffer 611 and GRAM 620 can be set to a third frequency using each of the first control signal CTRL_FR1 and the second control signal CTRL_FR2. Lossless encoding can be successful, and the resulting LLBS can be stored in GRAM 620. Furthermore, a normal path can be executed to generate processing data IP_FD, and the processing data IP_FD can be provided to the source driver.

[0143] Subsequently, during the fifth frame period t5 to t6, the first decoder 505, the image processor 506, and the second encoder 610 can be powered off, and the LLBS stored in the GRAM 620 can enter a low-power path.

[0144] Although it has been referenced Figures 1 to 15 Each embodiment has been described individually, but two or more embodiments may be combined. As an example, the encoding controller (e.g., Figure 3 (415) can change the bit depth of the data to be encoded in the first to third frame periods, and if the result is an internal encoding failure, the data to be encoded in the fourth frame period can be changed to other processed data in the fourth frame period. Furthermore, as an embodiment, the encoding controller (e.g., Figure 14 The 630 can perform internal encoding by changing the data to be encoded in the first to third frame cycles, and can change the operating frequency of the buffer 611 and GRAM 620 in the fourth frame cycle. Furthermore, when internal encoding is successfully achieved by combining the various embodiments, an image with improved image quality can be output even in low-power mode.

[0145] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display driving circuit for outputting still images, the display driving circuit comprising: A memory configured to store an input bitstream encoded by a first encoder based on the still image; as well as A controller is configured to determine the data path traversed by the output frame data in a second frame period based on whether the internal encoding in the first frame period was successful, wherein the controller determines whether the internal encoding was successful based on whether the first internal bitstream generated in the first frame period can be stored in the memory. Specifically, when the internal encoding is successful, the controller is configured to perform internal encoding in the second frame period to generate a second internal bitstream, store the second internal bitstream in the memory, allow the second internal bitstream to pass through a low-power path to generate the output frame data, and when the internal encoding fails, the controller is configured to generate the output frame data in the second frame period by allowing the input bitstream to pass through a normal path, changing the encoding settings of the internal encoder, and repeating the internal encoding. The normal path includes: a first decoder configured to decode the input bitstream to generate a first frame of data; and a plurality of image processors configured to perform image processing on the first frame of data to generate multiple segments of processed data. The low-power path includes a second decoder configured to decode the second internal bitstream to generate second frame data, and the low-power path is configured to bypass at least one of the plurality of image processors, namely a first image processor.

2. The display drive circuit of claim 1, wherein, The controller is configured to perform the internal encoding on at least one of the multi-segment processed data and the frame data.

3. The display driving circuit according to claim 2, wherein, When the internal encoding of the first processed data that has passed through the first, second, and third image processors of the plurality of image processors fails in the first frame period, the controller is configured to repeat the internal encoding of the second processed data that has passed through the first and second image processors of the plurality of image processors in the second frame period.

4. The display driving circuit according to claim 2, wherein, When the internal encoding of the first processed data of the first to third image processors among the plurality of image processors fails in the first frame period, the controller is configured to repeat the internal encoding of the second processed data of the first to fourth image processors among the plurality of image processors in the second frame period.

5. The display driving circuit according to claim 1, wherein, When the internal encoding of the processed data generated via the normal path is successful in the first frame period, the controller is configured to disconnect power to the normal path in the second frame period.

6. The display driving circuit according to claim 1, wherein, The second internal bitstream is generated based on the data processed by at least one of the plurality of image processors, namely the first image processor.

7. The display driving circuit according to claim 6, wherein, The operation of the at least one first image processor is performed before the operation of at least one second image processor among the plurality of image processors, in addition to the at least one first image processor.

8. The display driving circuit according to claim 6, wherein, The controller is configured to disconnect power to the at least one first image processor during the second frame period.

9. The display driving circuit according to claim 2, wherein, When the internal encoding of the first processed data fails in the first frame period, the controller is configured to generate data to be encoded by changing the bit depth of the first processed data, and repeat the internal encoding of the data to be encoded in the second frame period.

10. The display driving circuit according to claim 9, wherein, The controller is configured to generate the data to be encoded by reducing the bit depth of the first processed data.

11. The display driving circuit according to claim 10, wherein, The controller is configured to: The third internal bitstream, generated as a result of repeating the internal encoding in the second frame period, is stored in the memory. Internal decoding is performed on the third internal bitstream to generate data to be decoded, and the bit depth of the data to be decoded is restored.

12. The display driving circuit according to claim 1, further comprising: An asynchronous buffer, configured to temporarily store the received internal bit stream, In the second frame period, if the internal encoding fails, the controller is configured to change the output frequency of the asynchronous buffer.

13. A method for operating a display driving circuit that outputs a still image, the method comprising: In the first frame period, the input bitstream is decoded to generate the first frame data, and multiple image processors perform image processing on the first frame data to generate multiple frame data segments, each of which is output from a corresponding image processor among the multiple image processors; At least one of the multiple frame data segments is determined as the data to be encoded, and internal encoding is performed on the data to be encoded. When the internal encoding is successful, in the second frame period, the internal bitstream generated by performing the internal encoding is decoded, and the decoded bitstream is allowed to bypass at least one of the plurality of image processors to generate output frame data. When the internal encoding fails, during the second frame period, at least one of the data to be encoded and the encoding settings is changed, and the internal encoding is repeated.

14. The method according to claim 13, wherein, The plurality of image processors includes a first image processor, a second image processor, and a third image processor. During the repeated internal encoding, the first frame data generated by the first image processor and the second image processor is designated as the data to be encoded. When making the change, the data to be encoded is changed to second frame data generated by the first image processor to the third image processor.

15. The method according to claim 13, wherein, The plurality of image processors includes a first image processor, a second image processor, and a third image processor. During the repeated internal encoding, the first frame data generated by the first image processor, the second image processor, and the third image processor is designated as the data to be encoded. When making the change, the data to be encoded is changed to second frame data generated by the first image processor and the second image processor.

16. The method according to claim 13, wherein, The change includes changing the bit depth of the data to be encoded.

17. The method of claim 16, further comprising: The internal bitstream generated by repeating the internal encoding in the second frame period is stored; as well as The bit depth of the internal bitstream is recovered in the third frame period.

18. The method according to claim 13, wherein, The display driving circuit operates in low-power mode, and The method further includes: The internal bitstream generated by repeating the internal encoding in the second frame period is stored in memory; and The decoder and the at least one image processor through which the internal bitstream passes are turned off.

19. A display driving circuit, comprising: A memory configured to store the input bit stream; A first decoder is configured to decode the input bitstream to generate a first frame of data; Multiple image processors are configured to perform image processing on the first frame of data to generate multiple segments of processed data; An internal encoder is configured to perform internal encoding on at least one of the multiple segments of processed data; An internal decoder is configured to decode an internal bitstream stored in the memory when the internal encoding is successful, and to allow the decoded bitstream from the internal decoder to bypass at least one of the plurality of image processors to generate output frame data. as well as A controller is configured to change the encoding settings of the internal encoder and control the internal encoder to repeat the internal encoding when the internal encoding fails.

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