Power-based adaptive allocation of sram

Abstract

A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having rows and blocks that are selectively powered based on clustering criteria; and placing the instruction state memory entry in the identified slot.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. nonprovisional application No. 16 / 556,139, filed August 29, 2019, entitled “ADAPTABLE ALLOCATION OF SRAM BASE DONPOWER (Power-based Adaptive Allocation of SRAM)”, the entire contents of which are incorporated herein by reference. Background Technology

[0003] In computer systems, volatile memory (such as static random access memory) consumes power when powered on. Techniques for improving the power consumption of volatile memory are constantly being developed. Attached Figure Description

[0004] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings:

[0005] Figure 1 This is a block diagram of an exemplary apparatus that can implement one or more features of this disclosure;

[0006] Figure 2 The example is shown. Figure 1 Details of the device;

[0007] Figure 3 This is a block diagram of the instruction dispatch unit based on the example;

[0008] Figure 4 This is a block diagram of the instruction state memory based on the example;

[0009] Figure 5 This is an illustration based on an example showing an entry insertion operation for the instruction state memory;

[0010] Figure 6 This is a block diagram of an exemplary implementation of an instruction state memory; and

[0011] Figure 7 This is a flowchart of a method for placing an entry into the instruction state memory, based on an example. Detailed Implementation

[0012] A technique for processing computer instructions is provided. The technique includes: obtaining information about instruction state memory entries for an instruction; identifying, based on clustering criteria, slots in the instruction state memory that have rows and blocks that can be selectively powered; and placing the instruction state memory entries into the identified slots.

[0013] Figure 1This is a block diagram of an exemplary device 100 that can implement one or more features of this disclosure. Device 100 may be, but is not limited to, a computer, gaming device, handheld device, set-top box, television, mobile phone, tablet computer, or other computing device. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 also includes one or more input drivers 112 and one or more output drivers 114. Any of the input drivers 112 is embodied in hardware, a combination of hardware and software, or software, and is used for the purpose of controlling the input device 112 (e.g., controlling operations, receiving input from the input driver 112, and providing data to the input driver 112). Similarly, any of the output drivers 114 is embodied in hardware, a combination of hardware and software, or software, and is used for the purpose of controlling the output device 114 (e.g., controlling operations, receiving input from the output driver 114, and providing data to the output driver 114). It should be understood that device 100 may include... Figure 1 Other components not shown.

[0014] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102, or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0015] Storage device 106 includes fixed or removable storage devices, such as, but not limited to, hard disk drives, solid-state drives, optical disks, or flash drives. Input device 108 includes, but is not limited to, keyboards, keypads, touchscreens, touchpads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes, but is not limited to, displays, speakers, printers, haptic feedback devices, one or more lights, antennas, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals).

[0016] Input driver 112 and output driver 114 include one or more hardware, software, and / or firmware components configured to interface with and drive input device 108 and output device 110, respectively. Input driver 112 communicates with processor 102 and input device 108 and allows processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110 and allows processor 102 to send output to output device 110. Output driver 114 includes an accelerated processing unit (“APD”) 116 coupled to display device 118, which in some examples is a physical display device or analog device that uses a remote display protocol to display output. APD 116 is configured to accept computation commands and graphics rendering commands from processor 102, process those commands, and provide pixel output to display device 118 for display. As described in further detail below, APD 116 includes one or more parallel processing units configured to perform computations according to the Single Instruction Multiple Data (“SIMD”) paradigm. Therefore, while various functions are described herein as being performed by or in conjunction with APD 116, in various alternatives, the functions described as being performed by APD 116 may additionally or alternatively be performed by other computing devices with similar functionality that are not driven by a host processor (e.g., processor 102) and are not configured to provide graphics output to display device 118. For example, it is contemplated that any processing system performing processing tasks according to the SIMD paradigm could be configured to perform the functions described herein. Alternatively, it is contemplated that a computing system not performing processing tasks according to the SIMD paradigm could perform the functions described herein.

[0017] Figure 2 Details of the device 100 and APD 116 according to the example are shown. Processor 102 ( Figure 1 The operating system 120, driver 122, and application program 126 are executed, and alternatively or additionally, other software may also be executed. The operating system 120 controls various aspects of the device 100, such as managing hardware resources, processing service requests, scheduling and controlling process execution, and performing other operations. The APD driver 122 controls the operation of the APD 116, sending tasks such as graphics rendering tasks or other work to the APD 116 for processing. In some embodiments, the APD driver 122 also includes a just-in-time (JIT) compiler that compiles programs for execution by the processing units of the APD 116 (such as the SIMD unit 138, discussed further in detail below).

[0018] APD 116 executes commands and procedures related to selected functions, such as graphics and non-graphics operations suitable for parallel processing. APD 116 can be used to perform graphics pipeline operations based on commands received from processor 102, such as pixel manipulation, geometric calculations, and rendering images to display device 118. APD 116 also performs computational processing operations not directly related to graphics operations based on commands received from processor 102, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks.

[0019] APD 116 includes a computation unit 132 comprising one or more SIMD units 138 configured to perform operations in parallel upon request from processor 102 (or another unit) according to a SIMD paradigm. A SIMD paradigm is one in which multiple processing elements share a single program control flow unit and program counter, and thus execute the same program, but are able to execute that program with different data. In one example, each SIMD unit 138 includes sixteen channels, where each channel executes the same instruction simultaneously with other channels in the SIMD unit 138, but can execute that instruction with different data. If not all channels need to execute a given instruction, assertions can be used to shut down channels. Assertions can also be used to execute programs with divergent control flow. More specifically, for programs with conditional branches or other instructions, where control flow is based on computation performed by a single channel, assertions for a channel correspond to currently unexecuted control flow paths, and serial execution of different control flow paths allows for arbitrary control flow.

[0020] APD 116 includes one or more caches 142 that can be accessed by compute unit 132. Cache 142 implements a cache coherence protocol to allow data stored in any individual cache 142 to be accessed by any of compute units 132.

[0021] The parallelism provided by computing unit 132 is suitable for graphics-related operations, such as pixel value calculation, vertex transformation, and other graphics operations. Therefore, in some instances, graphics pipeline 134, which receives graphics processing commands from processor 102 (or another entity), provides computational tasks to computing unit 132 for parallel execution.

[0022] The computing unit 132 is also used to perform computational tasks that are unrelated to graphics or are not part of the “normal” operation of the graphics pipeline 134 (e.g., custom operations performed to supplement the processing performed for the operation of the graphics pipeline 134). The application program 126 or other software executing on the processor 102 transfers the program (“core program”) that defines such computational tasks to the APD 116 for execution.

[0023] The basic unit of execution in computing unit 132 is a work item. Each work item represents a single instance of a program (sometimes referred to as a “core program”) that will be executed in parallel on a specific channel. Work items can be executed simultaneously (or partially simultaneously and partially sequentially) as “wavefronts” on a single SIMD processing unit 138. One or more wavefronts are included in a “workgroup,” which comprises a set of work items designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that constitute the workgroup. Alternatively, wavefronts can be executed on a single SIMD unit 138 or on different SIMD units 138. APD scheduler 136 is configured to perform operations related to scheduling various workgroups and wavefronts on computing unit 132 and SIMD unit 138. In an example of use, application 126 instructs APD 116 how to execute the core program in terms of the “size” of the core program execution, where “size” indicates the number of work items. In some operating modes, application 126 also specifies how work items are divided into workgroups. In other operating modes, APD 116 and / or driver 122 determine how work items are divided into workgroups. The size of the core program execution and the number of work items to be executed in each workgroup determine how many workgroups to execute for a given core program execution. These workgroups are executed by APD 116. APD scheduler 136 allocates workgroups to computing unit 132 for execution based on the availability of computing resources (e.g., how many workgroups are allocated to a particular computing unit 132, and whether other resources (such as memory, registers, or other resources) are available).

[0024] Figure 3 This is a block diagram of an instruction dispatch unit 300 according to an example. The instruction dispatch unit 300 is included in a processor, such as SIMD unit 138, processor 102, or another processor not described herein.

[0025] The instruction dispatch unit 300 includes an instruction fetch block 302, a decoding block 304, and an instruction state memory 310. The instruction dispatch unit 300 also includes a low-latency block 306 and a high-latency block 308. Upon request from the decoding unit 304, the low-latency block provides low-latency data to the instruction state memory 310. This low-latency data is data necessary for instruction execution, and its fetch latency is lower than that of the high-latency data. Upon request from the decoding unit 304, the high-latency block provides high-latency data to the instruction state memory 310. Generally, low-latency data is data that can be retrieved from a structure close to the decoding unit 304 in terms of signal propagation latency. One example of such a structure includes custom computing circuitry that receives operations from the decoding unit 304 to compute specific values, computes those values, and provides those values ​​to the instruction state memory 310. Another example of a low-latency structure includes memory "close" to the decoding unit 304 and the instruction state memory 310, such that the access latency to those memories is lower than the fastest access latency to any memory of the high-latency data unit 308. Low-latency data block 306 includes a collection of any structures (including processing circuitry, low-latency memory, etc.) that provide such low-latency data. High-latency data is data retrieved from a structure with a latency longer than the longest latency of low-latency data unit 306. Examples of high-latency data structures include caches (including lowest-level caches, such as L0 caches), system memory, non-volatile memory devices, or other structures. High-latency data block 308 includes all such structures, or, where such structures are physically located outside instruction dispatch unit 300, includes an interface within instruction dispatch unit 300 to such structures (i.e., hardware circuitry that sends requests for high-latency data and receives high-latency data in response).

[0026] In operation, instruction fetch unit 302 fetches the instructions to be executed and provides those instructions to decoding unit 304. Decoding unit 304 analyzes and generates instructions for micro-operations to be executed by functional units, which are not shown in detail. A functional unit is any of a variety of units that perform instruction processing, such as an arithmetic logic unit (“ALU”), a load / store unit for reading from or writing to memory, or other units. In fact, all processors that execute programs consisting of instructions selected from the instruction set architecture have both decoding and functional units.

[0027] The instructions to be executed consume one or both of low-latency data and high-latency data. Various processors have instruction sets that include some instructions that consume low-latency data but not high-latency data, some instructions that consume high-latency data but not low-latency data, some instructions that consume both high-latency and low-latency data, and some instructions that consume neither high-latency nor low-latency data.

[0028] After decoding the instruction by decoding unit 304, if the instruction requires low-latency data, decoding unit 304 retrieves low-latency data from low-latency data block 306. Once the low-latency data is obtained, decoding unit 304 places an entry including micro-operations on the instruction and the low-latency data in instruction state memory 310. Decoding unit 304 also triggers the retrieval of high-latency data from high-latency data block 308. When high-latency data is retrieved from high-latency data block 308, the instruction is ready for execution, and instruction state memory 310 sends the instruction to the functional unit. In instruction state memory 310, a single instruction set architecture instruction can generate multiple entries. In other words, decoding unit 304 can generate multiple micro-operations for each instruction set architecture instruction and generate an entry for each micro-operation in instruction state memory 310.

[0029] In addition to sending micro-operations and low-latency data (if any) to the instruction state memory 310, the decoding unit 304 also sends information about power control to the instruction state memory 310. The instruction state memory 310 includes multiple individually powered blocks that are powered on and off according to the contents of the instruction state memory 310 and the power control information received from the decoding unit 304.

[0030] Figure 4 This is a detailed block diagram of the instruction state memory 310 according to the example. The instruction state memory 310 includes multiple blocks 402 organized in multiple rows 404. Each row 404 includes one or more entries. Within a row 404, the data type stored in each block 402 is different from that of the other blocks 402. Specifically, a block 402 either stores "core instruction state"—data that identifies the micro-operation to which the entry is targeted—or stores some type of low-latency data. Each block 402 can be powered on or off independently of each other block. The term "power on or off" uniformly refers to execution clock gating (pausing or resuming the clock to retain data in memory elements but preventing reads or writes) or power gating (turning the power on or off to block 402). Each row 404 can also be powered on or off individually. The controller 401 powers on and off the rows in response to the contents of the memory 400 (whether an entry is placed in or removed from a particular row 404) and in response to information received from the decoding unit 204 regarding power control.

[0031] exist Figure 4In the instruction state memory 310, blocks 402 at the same position in each row store data of the same type. In the example, blocks 402 for state 1 all store data of the same type, blocks 402 for state 2 all store data of the same type, and so on. A particular instruction may require any subset of the data types that can be stored in line 404. More specifically, an instruction of a certain type may require data that would be stored in the block for state 1 and data that would be stored in the block for state 3, but not data that would be stored in other blocks (such as the block for state 2). Therefore, the entry for that instruction in the instruction state memory 310 will store data in the blocks for state 1 and state 2, but not in any other blocks.

[0032] In some cases, if there is no entry in row 404 storing data of type 402 in that row, the controller 401 powers down the block. In some embodiments, the controller immediately powers down the block 402 after detecting that the last entry in row 404 using data for a specific block 402 has been deleted from row 404. In some embodiments, the controller enters a waiting period after detecting that the last entry in row 404 using data for a specific block 402 has been deleted from row 404. If, during the waiting period, the controller 401 determines that another entry is to be placed in row 404 using data associated with block 402, the controller 401 does not power down the block 402. If, during the waiting period, the controller 401 determines that no entry is to be placed in row 404 using data associated with block 402, the controller 401 powers down the block 402.

[0033] The latency period for a power outage of block 402 can be determined in any technically feasible manner. Regardless of the state of instruction state memory 310, the latency period can be constant or vary depending on the state of instruction state memory 310 and / or the state of the instructions decoded by decoding unit 304. In some embodiments, the latency period for a power outage of block 402 is based on a comparison between the power consumed by energizing block 402 during an idle period and the power saved by turning block 402 off and then on again during an idle period. The idle period is the number of cycles between when block 402 becomes empty and when a new entry is placed in block 402. In some examples, the idle period is determined from the state of instruction dispatch unit 300. Specifically, when block 402 becomes empty, if there is an instruction being processed in instruction dispatch unit 300, but no entry for using block 402 has yet been generated in instruction state memory 310 (e.g., low-latency data is being fetched), but it is known that the instruction will need an entry in block 402 within a certain number of cycles after block 402 becomes empty, then the certain number of cycles is the duration of the idle period. If there is no instruction in instruction dispatch unit 300, the idle period is a default idle period, which in some embodiments is the minimum number of cycles from when the instruction dispatch unit receives an instruction that will need space in block 402 until that instruction actually occupies the block 402. In some embodiments, the amount of power consumed by opening block 402 during the idle period versus de-energizing and then energizing block 402 during the idle period is predetermined by the designer. In this scenario, if the idle period exceeds a threshold, the instruction state memory 310 is configured to be powered down and then powered on again, and if the idle period is less than or equal to the threshold, it is configured to remain powered on, where the threshold is a crossover point at which it would be more power-consuming to power on block 402 rather than powering it down and then powering it on again. In some examples, the threshold is programmable, for example, via a configuration register.

[0034] In some cases, if row 404 has no stored entries, controller 401 powers down the row. In some embodiments, the controller immediately powers down row 404 after detecting that the last entry in row 404 has been deleted. In some embodiments, after detecting that the last entry in row 404 has been deleted, the controller enters a waiting period. If, during the waiting period, controller 401 determines that another entry needs to be placed in row 404, controller 401 does not power down row 404. If, during the waiting period, the controller determines that no other entry needs to be placed in row 404, controller 401 powers down row 404.

[0035] The latency for power-down of line 404 can be determined in any technically feasible manner. The latency can be constant regardless of the state of instruction state memory 310, or it can vary depending on the state of instruction state memory 310 and / or the state of the instruction decoded by decoding unit 304. In some embodiments, the latency for power-down of line 404 is based on the number of lines 404 that are powered on. Specifically, the more lines that are powered on, the shorter the latency 404. In some embodiments, the latency for power-down of line 404 is based on the number of released entries in other lines 404 that are powered on. The more released entries in other lines 404 that are powered on, the shorter the latency. In some embodiments, the latency is based on how many entries are required for the flight command. In some embodiments, instruction state memory 310 determines how to power down line 404 in a manner similar to the above description regarding whether to power down block 402, wherein the term "line 404" is used instead of the term "block 402".

[0036] Figure 5 The operation for placing a new entry into instruction state memory 310 is illustrated according to an example. Controller 401 attempts to cluster entries in row 404 together to maximize the number of rows 404 that can be turned off. Specifically, when controller 401 receives a new entry to place in instruction state memory 310, controller 401 determines that row 404 has the fewest empty entry slots while still having at least one empty entry slot, and places the new entry into one of the empty entry slots in the identified row 404. In the example, if two rows 404 have the same number of empty entries, controller 401 selects the row 404 with the most recent entry. Selecting the row 404 with the fewest empty entry slots to receive the new entry results in a reduction in the total number of active rows 404, which allows more rows 404 to be turned off.

[0037] In some cases, when it is determined that a new entry requires a specific type of low-latency data, and therefore a particular block 402 needs to be energized in the row 404 where the entry is located, the controller 401 selects the row 404 where the block 402 is already energized, rather than the row 404 where the block 402 is de-energized. In some implementations, if two rows 404 have the same number of empty entries, but one row energizes the block 402 required for the new entry while the other row does not, the controller 401 selects the row 404 where the required block 402 is energized. In some implementations, the controller 401 selects the row 404 where the required block 402 is energized even if that row 404 has more empty entries than the other row 404, as long as the selected row 404 has the lowest number of empty entries where the required block 402 is also energized. In some implementations, if the row 404 that powers the desired block 402 has more empty entries than another row 404 that powers the desired block 402, the controller 401 selects that row, provided that the number of empty entries in the row 404 to be selected is within a threshold number or a threshold percentage of the number of empty entries in the row 404 where the desired block 402 is powered off.

[0038] Figure 6 This is a block diagram of an exemplary implementation of the instruction state memory 310 (SIMD unit instruction state memory 600). The SIMD unit instruction state memory 600 includes a block 602 for core instruction states, a block 604 for filter weights, and a block 606 for reference data.

[0039] As described above, the SIMD unit 138 executes a shader program that includes a sequence of instructions. The instruction dispatch unit 300, which includes an instruction state memory 310, fetches instructions, decodes the instructions, and places the decoded instructions and state data into the instruction state memory 310.

[0040] The core instruction state is a piece of information that identifies the operation that needs to be performed on the instruction to be executed. In the example, the instruction is an `add` instruction, and the core instruction state indicates that an `add` operation needs to be performed. Block 604 stores the filter weights for texture instructions. More specifically, some instructions require the application of filters to manipulate texture data. Filters can include weights determined based on instruction identifiers, and these weights can be applied to operands such as texture elements (texels). In this example, the filter weights are low-latency data, and the texture elements are high-latency data. The filter weights are placed in block 604 for filter weights in response to being retrieved from low-latency data block 306.

[0041] Block 606, designated for reference data, stores the reference data to be used by the instructions. Reference data is data to be compared with another value, such as an item of high-latency data. In the example, block 606 stores the depth value of the pixel used for z-testing (sometimes also called depth testing). In some examples, the pixel shader program performs a depth test on the value stored in the depth buffer. Specifically, the pixel shader compares the depth value of the pixel being processed with the value in the depth buffer, and may therefore discard the pixel and / or modify the depth buffer. The reference data is the depth value of the pixel, and the operand is the value retrieved from the depth buffer.

[0042] Instructions typically use block 602 for core instruction states. Therefore, in some embodiments, block 602 for core instruction states is not de-energized when line 404 is energized. Instructions may use one or both of block 604 for filter weights or block 606 for reference data, depending on the instruction's identifier. Therefore, when an instruction is located in a particular line 404, the block for low-latency data used by that instruction is opened. In various embodiments, when controller 401 determines that an instruction using one or both of filter weights or reference data should be placed in line 404 where those blocks are de-energized, controller 401 energizes those blocks.

[0043] Figure 7 This is a flowchart of method 700 for placing an entry in instruction state memory 310, based on an example. Although regarding... Figures 1 to 6 The system described herein is intended to perform the steps of method 700 in any technically feasible order, but those skilled in the art will understand that any system configured to perform the steps of method 700 in any technically feasible order falls within the scope of this disclosure.

[0044] Method 700 begins at step 702, where the controller 401 of the instruction state memory 310 receives information about an instruction state memory entry for an instruction. This information is received from the decoder 304 and indicates which type of low-latency data the instruction associated with the instruction state memory entry uses. If the instruction requests to fetch low-latency data, the decoder 304 requests this information from the low-latency data block 306. The decoder 304 also requests high-latency data from the high-latency data block 308. It should be noted that the decoder 304 may expand the instruction into multiple micro-operations, and each micro-operation may require an instruction state memory entry. In this case, aspects of method 700 (such as steps 704 and 706) or all aspects of method 700 may repeat for each micro-operation generated from the instruction. In some implementations, the clustering criterion considers the total number of slots required by the instruction, rather than just one slot.

[0045] At step 704, controller 401 identifies slots in instruction state memory 310 based on clustering criteria. The clustering criteria exist to cluster more entries into fewer rows 404, allowing more rows 404 to be de-energized. In some embodiments, the clustering criteria also cluster entries into rows 404 where the same block 402 is energized and the same block 402 is de-energized.

[0046] In some implementations, the clustering criterion is as follows. Controller 401 attempts to place a new entry in row 404, which has the lowest, non-zero number of empty entries. This action results in a clustering of entries in row 404.

[0047] In some implementations, the clustering criteria also consider the blocks 402 that have been energized in the used rows 404. In one example, if there are multiple rows 404 with the minimum number of entries (i.e., if two or more rows 404 have the same number of empty entries, which is also the minimum number of empty entries), the controller 401 selects the row 404 that results in the minimum number of blocks 402 being energized. For example, if a new entry for an instruction requires low-latency data for block 2, and if the row 404 with the minimum number of entries energizes block 2 and the row 404 with the minimum number of entries de-energizes block 2, the controller 401 selects the row 404 where block 2 is energized to place the new entry. In some implementations, rows 404 need not have the same number of empty entries—if the number of empty entries in row 404 is within a percentage of a threshold number of empty entries or a minimum number of empty entries in row 404, and that row 404 powers the required block, while no other row 404 with fewer empty entries powers the required block, then controller 401 selects the row 404 whose required block is powered, rather than the row 404 with fewer empty entries. In some implementations, controller 401 powers a row 404 for each possible combination of blocks 402 that can be powered, or for a subset of combinations of blocks 402 that can be powered. In this implementation, for a new entry, controller 401 selects a row 404 that has the minimum number of entries and powers at least the required block 402, or requires the minimum number of blocks 402 to be powered. If no row 404 has empty entries, controller 401 powers row 404. Similarly, if no row 404 powers the block 402 required by the entry, controller 401 powers at least one block 402. At step 706, the controller 401 places the instruction status memory entry into the identified slot.

[0048] When all high-latency data has entered for the instruction in instruction state memory 310, instruction state memory 310 sends the instruction to the functional unit. Furthermore, if the instruction is the last instruction in line 404, or the last instruction in line 404 using a specific block 402, controller 401 powers down line 404 or block 402. The power-down may occur after a delay, as described elsewhere herein. Furthermore, if a new instruction for line 404 or block 402 is required to enter during the delay, no power-down occurs. Additionally, in some embodiments, when instruction information is sent to the functional unit for execution, reading is only performed from the block 402 that is actually powered for the instruction, and therefore reading from unpowered blocks does not consume power.

[0049] It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0050] The various functional units shown in the figures and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, accelerated processing device 116, scheduler 136, graphics processing pipeline 134, computing unit 132, SIMD unit 138, instruction dispatch unit 300, instruction fetch unit 302, decoding unit 304, low-latency data unit 306, high-latency data unit 308, instruction state memory 310, or controller 401) may be implemented as a general-purpose computer, processor, or processor core, or implemented as a program, software, or firmware, stored in a non-transitory computer-readable medium or another medium, executable by a general-purpose computer, processor, or processor core. The provided methods may be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such instructions can be stored on a computer-readable medium). The result of this processing can be a mask, which is then used in a semiconductor manufacturing process to manufacture a processor embodying the features of this disclosure.

[0051] The methods or flowcharts provided herein can be implemented in computer programs, software, or firmware incorporated into non-transitory computer-readable storage media for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROM discs and digital versatile discs (DVDs)).

Claims

1. A method for processing computer instructions, the method comprising: The instruction is received by the processor's instruction dispatch unit. The instruction specifies the core instruction state of the instruction, wherein the instruction references low-latency data. The instruction dispatch unit stores the core instruction state into a first selectively powered portion of the instruction state memory, which is configured to store the core instruction state of one or more micro-operations that identify the instruction rather than low-latency data. The instruction dispatch unit stores the low-latency data into a powered row, which includes at least one entry of a type matching the low-latency data. This row belongs to a second selectively powered portion of the instruction state memory, which is configured to store the core instruction state of the low-latency data rather than the instructions.

2. The method of claim 1, further comprising: Upon receiving high-latency data for the instruction state memory, the instruction dispatch unit transmits the data for the instruction in the instruction state memory and the high-latency data to one or more functional units for execution, wherein the access latency of the high-latency data is higher than that of the low-latency data.

3. The method of claim 2, further comprising: After the data is transferred from the instruction state memory to the one or more functional units for execution, it is determined that the row from which the data is transferred is not occupied by any slot. as well as Power off the line.

4. The method of claim 3, wherein the power failure occurs after the waiting period.

5. The method of claim 1, further comprising identifying slots in the instruction state memory for the core instruction state based on clustering criteria: Identify the row in the instruction state memory that has the lowest, non-zero number of empty slots from the rows in the instruction state memory; and The empty slots of the identified rows are used as the slots of the core instruction state.

6. The method of claim 1, wherein: Within the instruction state memory, a first power-on row includes a first block of data of a first type, wherein the first block is powered on, and a second power-on row includes a second block of data of the first type, wherein the second block is de-powered; and Storing the core instruction state includes identifying the slots in the first energized row as the first selectively energized portion.

7. The method of claim 6, wherein the second energized row comprises more empty slots than the first energized row.

8. The method of claim 1, further comprising identifying the first selectively powered portion by: It was determined that there were no energized rows with empty slots; and To turn off the power and then on the power, The first selectively powered portion includes the de-energized section that has already been energized.

9. An instruction status memory, comprising: Multiple selectable power supply sections; as well as The processor's controller, the controller being configured to: Receive an instruction that specifies the core instruction state, wherein the instruction references low-latency data; The core instruction state is stored in a first selectively powered portion of the plurality of selectively powered portions, the first selectively powered portion being configured to store the core instruction state of instructions rather than low-latency data; and The low-latency data is stored in a row that has been powered on, the row including at least one entry of a type that matches the low-latency data, the row belonging to a second selectively powered portion of the plurality of selectively powered portions, the second selectively powered portion being configured to store the low-latency data rather than the core instruction state of the instructions.

10. The instruction state memory of claim 9, wherein the controller is further configured to: Upon receiving high-latency data for the instruction state memory, the data in the instruction state memory for the instruction and the high-latency data are transferred to one or more functional units for execution, wherein the access latency of the high-latency data is higher than that of the low-latency data.

11. The instruction state memory of claim 10, wherein the controller is further configured to: After the data is transferred from the instruction state memory to the one or more functional units for execution, it is determined that the rows from which the data is transferred are not occupied by slots; and Power off the line.

12. The instruction state memory of claim 11, wherein the power failure occurs after a waiting period.

13. The instruction state memory of claim 9, wherein the controller is further configured to identify slots in the instruction state memory for the core instruction state based on a clustering criterion: Identify the row in the instruction state memory that has the lowest, non-zero number of empty slots from the rows in the instruction state memory; and The empty slots of the identified rows are used as the slots of the core instruction state.

14. The instruction state memory as claimed in claim 9, wherein: Within the instruction state memory, a first power-on row includes a first block of data of a first type, wherein the first block is powered on, and a second power-on row includes a second block of data of the first type, wherein the second block is de-powered; and Storing the core instruction state includes identifying the slots in the first energized row as the first selectively energized portion.

15. The instruction state memory of claim 14, wherein the second power row includes more empty slots than the first power row.

16. The instruction state memory of claim 9, wherein the controller is further configured to identify the first selectively powered portion in such a way that: It was determined that there were no energized rows with empty slots; and To turn off the power and then on the power, The first selectively powered portion includes the de-energized section that has already been energized.

17. A processor comprising: Instruction state memory, the instruction state memory comprising: Multiple selectable power supply sections; and The controller is configured to: Receive an instruction that specifies the core instruction state of the instruction, the core instruction state identifying one or more micro-operations of the instruction, wherein the instruction references low-latency data; The core instruction state is stored in a first selectively powered portion of the plurality of selectively powered portions, the first selectively powered portion being configured to store the core instruction state of instructions rather than low-latency data; and The low-latency data is stored in a row that has been powered on, the row including at least one entry of a type that matches the low-latency data, the row belonging to a second selectively powered portion of the plurality of selectively powered portions, the second selectively powered portion being configured to store the low-latency data rather than the core instruction state of the instructions.

18. The processor of claim 17, wherein the controller is further configured to: Upon receiving high-latency data for the instruction state memory, the data in the instruction state memory for the instruction and the high-latency data are transferred to one or more functional units for execution, wherein the access latency of the high-latency data is higher than that of the low-latency data.

19. The processor of claim 18, wherein the controller is further configured to: After data is transferred from the instruction state memory to the one or more functional units for execution, the rows from which the data is transferred have unoccupied slots; and Power off the line.

20. The processor of claim 19, wherein the power failure occurs after a waiting period.

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