Semiconductor devices having super-mutant junction regions with spaced superlattices and related methods

Abstract

A semiconductor device can include a substrate and a superabrupt junction region carried by the substrate. The superabrupt region can include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different from the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device can also include a gate dielectric layer on the second superlattice layer of the superabrupt junction region, a gate electrode on the gate dielectric layer, and a spaced apart source region and a drain region adjacent the superabrupt junction region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor devices including super-transition junctions and related methods. Background Technology

[0002] Structures and techniques for enhancing the performance of semiconductor devices have been proposed, such as by enhancing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416, granted to Currie et al., discloses a strained material layer of silicon, silicon-germanium, and relaxed silicon, and also includes impurity-free regions (impurities would otherwise cause performance degradation). The biaxial strain generated in the upper silicon layer alters the carrier mobility, thereby enabling higher speed and / or lower power devices. Published U.S. Patent Application No. 2003 / 0034529, granted to Fitzgerald et al., discloses a CMOS inverter also based on a similar strained silicon technique.

[0003] U.S. Patent No. 6,472,685B2, granted to Takagi, discloses a semiconductor device comprising silicon and a carbon layer sandwiched between the silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. Since electrons with smaller effective mass and already induced by the electric field applied to the gate electrode are confined within the second silicon layer, it is asserted that the n-channel MOSFET has higher mobility.

[0004] U.S. Patent No. 4,937,204, granted to Ishibashi et al., discloses a superlattice in which multiple layers, comprising fewer than eight monolayers and including fractional or binary or binary compound semiconductor layers, are alternately and epitaxially grown. The direction of the main current flow is perpendicular to the layers of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short-period superlattice with higher mobility obtained by reducing alloy scattering in the superlattice. Following these ideas, U.S. Patent No. 5,683,934 to Candelaria discloses a MOSFET with enhanced mobility, comprising a channel layer comprising a silicon alloy and a second material alternately present in the silicon lattice in percentages that place the channel layer under tensile strain.

[0006] U.S. Patent No. 5,216,262 granted to Tsu discloses a quantum well structure comprising two barrier regions and an epitaxially grown thin semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating SiO2 / Si layers, typically ranging in thickness from two to six monolayers. A much thicker silicon portion is sandwiched between the barrier layers.

[0007] Also published online on September 6, 2000, in Applied Physics and Materials Science & Processing, pp. 391-402, is a paper titled "Phenomena in silicon nanostructure devices," authored by Tsu. A silicon / oxygen semiconductor atomic superlattice (SAS) was disclosed. The Si / O superlattice was revealed to be useful in silicon quantum and light-emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. Current flow in the diode structure was vertical, i.e., perpendicular to the layers of the SAS. The disclosed SAS can comprise semiconductor layers separated by adsorbed substances such as oxygen atoms and CO molecules. Silicon growth beyond the adsorbed oxygen monolayer was described as epitaxial growth with a considerably low defect density. One SAS structure includes a 1.1 nm thick silicon portion, approximately eight atomic silicon layers, while another structure has a silicon thickness twice that of the 1.1 nm portion. The article titled “Chemical Design of Direct-Gap Light-Emitting Silicon” by Luo et al., published in Physical Review Letters, Volume 89, Issue 7 (August 12, 2002), further discusses Tsu’s luminescent SAS structure.

[0008] U.S. Patent No. 7,105,895 to Wang et al. discloses a barrier layer construct consisting of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby further reducing the current flowing vertically through the lattice by more than four orders of magnitude. The insulating / barrier layer allows for the deposition of low-defect epitaxial silicon next to the insulating layer.

[0009] UK Patent Application 2,347,520, granted to Mears et al., discloses that the principles of aperiodic photonic bandgap (APBG) structures can be applied to electronic bandgap engineering. Specifically, the application discloses that material parameters (e.g., the location of band minimums, effective mass, etc.) can be adjusted to produce novel aperiodic materials with desired bandgap structure characteristics. It also discloses that other parameters (such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability) may also be designed into the material.

[0010] Furthermore, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices, the method comprising depositing a silicon layer and at least one additional element on a silicon substrate, thereby creating a substantially defect-free deposited layer that allows for the deposition of substantially defect-free epitaxial silicon on the deposited layer. Alternatively, a monolayer of one or more elements (preferably including oxygen) is absorbed onto the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon layers form a barrier composite.

[0011] Despite the existence of such methods, further enhancements may be expected to improve the performance of semiconductor devices by using advanced semiconductor materials and processing techniques. Summary of the Invention

[0012] A semiconductor device may include a substrate and a super-abrupt junction region supported by the substrate. The super-abrupt junction region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer having a second conductivity type different from the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may also include a gate dielectric layer on the second superlattice layer of the super-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced-apart source and drain regions adjacent to the super-abrupt junction region.

[0013] According to one example embodiment, the spaced-apart source and drain regions may have a second conductivity type. Furthermore, the first and second semiconductor layers, as well as the first and second superlattice layers, may be parallel to the bottom portion of the substrate. According to another example embodiment, the first and second semiconductor layers, as well as the first and second superlattice layers, may be U-shaped.

[0014] As an example, the first semiconductor layer and the second semiconductor layer may each have a thickness in the range of 50 nm to 300 nm. Also as an example, the base semiconductor monolayer may contain at least one of silicon and germanium, and at least one non-semiconductor monolayer may contain at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

[0015] A method for manufacturing a semiconductor device may include forming a superjunction region over a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer having a second conductivity type different from the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the superjunction region, forming a gate electrode on the gate dielectric layer, and forming spaced-apart source and drain regions adjacent to the superjunction region. Each of the first and second superlattices may include a plurality of stacked layer groups, each layer group including a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent basic semiconductor portion.

[0016] More specifically, the spaced-apart source and drain regions may have a second conductivity type. In one example embodiment, the first and second semiconductor layers, as well as the first and second superlattice layers, may be parallel to the bottom portion of the substrate. According to another example embodiment, the first and second semiconductor layers, as well as the first and second superlattice layers, may be U-shaped.

[0017] As an example, the first semiconductor layer and the second semiconductor layer may each have a thickness in the range of 50 nm to 300 nm. Also as an example, the base semiconductor monolayer may contain at least one of silicon and germanium, and at least one non-semiconductor monolayer may contain at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. Attached Figure Description

[0018] Figure 1 This is a very enlarged schematic cross-sectional view of a superlattice used in a semiconductor device according to an example embodiment.

[0019] Figure 2 yes Figure 1 A perspective atomic diagram of a portion of the superlattice shown.

[0020] Figure 3 This is a very enlarged schematic cross-sectional view of another embodiment of the superlattice according to the example embodiment.

[0021] Figure 4A This refers to bulk silicon in existing technologies and, for example, Figure 1-2 The 4 / 1Si / O superlattices shown are all band structure curves calculated from the gamma point (G).

[0022] Figure 4B This refers to bulk silicon in existing technologies and, for example, Figure 1-2 The 4 / 1Si / O superlattices shown are all band structure curves calculated from the Z point.

[0023] Figure 4C This refers to bulk silicon in existing technologies and, for example, Figure 3 The 5 / 1 / 3 / 1Si / O superlattices shown are all band structure curves calculated from gamma and Z-point.

[0024] Figure 5 This is a schematic cross-sectional view of a JFET including a super-abrupt junction incorporated into a superlattice, according to an example embodiment.

[0025] Figure 6 This is a schematic cross-sectional view of an IGFET including a super-abrupt junction incorporated into a superlattice, according to an example embodiment.

[0026] Figure 7This is a schematic cross-sectional view of another IGFET, including a super-abrupt junction incorporated into a single superlattice, according to an example embodiment.

[0027] Figure 8 This is a schematic cross-sectional view of a varactor diode including a super-abrupt junction incorporated into a superlattice, according to an example embodiment.

[0028] Figure 9A and Figure 9B This is a schematic cross-sectional view of other varactor diodes including a super-abrupt junction incorporated into a single superlattice, according to an example embodiment.

[0029] Figure 10 It is a diagram and Figure 5-7 A flowchart of the methods associated with the manufacture of the device.

[0030] Figure 11 It is a diagram and Figure 8 A flowchart illustrating the methods associated with the manufacture of the -9 device. Detailed Implementation

[0031] Example embodiments will now be described more fully below with reference to the accompanying drawings, in which example embodiments are illustrated. However, embodiments may be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Throughout, similar numbers indicate similar elements, and apostrophes and multiple apostrophes are used in different embodiments to indicate similar elements.

[0032] Generally, this disclosure relates to devices having an enhanced semiconductor superlattice. In this disclosure and the accompanying drawings, the enhanced semiconductor superlattice is also referred to as an "MST" layer or "MST technology".

[0033] More specifically, MST technology involves advanced semiconductor materials, such as superlattices 25 further described below. The applicant theoretically does not wish to be limited by this, arguing that certain superlattices described herein reduce the effective mass of charge carriers, and that this leads to higher charge carrier mobility. Effective mass has various definitions in the literature. As a measure to improve effective mass, the applicant uses the "inverse conductivity effective mass tensor," and specifically for electrons and holes. and For electrons, the definitions are respectively:

[0034]

[0035] And the location of the hole is as follows:

[0036]

[0037] Where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to the wave vector k and the nth energy band, and the indices i and j refer to the Cartesian coordinates x, y and z. The integral is obtained in the Brillouin zone (BZ), and the sum is obtained in the energy bands of electrons and holes with energies higher and lower than the Fermi energy, respectively.

[0038] The applicant's definition of the inverse effective mass tensor of conductivity states that the larger the value of the corresponding component of the inverse effective mass tensor of conductivity, the larger the tensor component of the material's conductivity. Hoping not to be limited thereto, the applicant again theoretically argues that the superlattice described herein sets the value of the inverse effective mass tensor of conductivity to enhance the material's conductivity properties, such as, typically, the preferred direction of charge carrier transport. The inverse of the appropriate tensor element is called the effective mass of conductivity. In other words, to characterize the structure of semiconductor materials, the effective mass of electron / hole conductivity, calculated as described above and in the expected direction of charge carrier transport, is used to distinguish improved materials.

[0039] The applicant has identified improved materials or structures for use in semiconductor devices. More specifically, the applicant has identified materials or structures having band structures for which the effective mass of appropriate conductivity for electrons and / or holes is substantially less than the corresponding values ​​for silicon. In addition to the enhanced mobility characteristics of these structures, they can also be formed or used in a manner that provides piezoelectric, thermoelectric, and / or ferroelectric properties favorable for use in a wide variety of device types, as will be discussed further below.

[0040] Now for reference Figure 1 and 2 The material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 comprises multiple layers 45a-45n arranged in a stacked relationship, as detailed in a specific reference. Figure 1 A schematic cross-sectional view may be best understood.

[0041] Each layer group 45a-45n of the superlattice 25 illustratively includes multiple stacked base semiconductor monolayers 46 (which define corresponding base semiconductor portions 46a-46n) and band-modification layers 50 thereon. For clarity, in Figure 1 The dotted line in the middle indicates the bandgap modification layer 50.

[0042] The bandgap modification layer 50 illustratively includes a non-semiconductor monolayer confined within the lattice of an adjacent base semiconductor portion. "Confined within the lattice of an adjacent base semiconductor portion" means that at least some semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together through the intervening non-semiconductor monolayer 50, such as... Figure 2 As seen in the diagram. Generally, this construction is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition (ALD) technology, such that not all (i.e., less than all or 100% coverage) available semiconductor bonding sites are filled with bonds to non-semiconductor atoms, as will be discussed further below. Therefore, when another monolayer 46 of semiconductor material is deposited on or above the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining empty bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0043] In other embodiments, it is possible to have more than one such non-semiconductor monolayer. It should be noted that the references herein to non-semiconductor or semiconductor monolayers mean that if the material used for the monolayer is formed in a bulk form, then it will be non-semiconductor or semiconductor. That is, as those skilled in the art will recognize, a single monolayer of a material (such as silicon) does not necessarily exhibit the same properties as if it were formed in a bulk form or as a relatively thick layer.

[0044] The applicant theoretically believes that the band-modified layer 50 and the adjacent base semiconductor portions 46a-46n enable the superlattice 25 to have an effective mass of appropriate conductivity for charge carriers in the parallel layer direction than would otherwise exist. Alternatively, this parallel direction is orthogonal to the stacking direction. The band-modified layer 50 also enables the superlattice 25 to have a common band structure, while advantageously serving as an insulator between layers or regions vertically above and below the superlattice.

[0045] Furthermore, this superlattice structure can advantageously act as a barrier to dopant and / or material diffusion between layers vertically above and below the superlattice 25. These properties can therefore advantageously allow the superlattice 25 to provide an interface for a high-k dielectric that not only reduces the diffusion of high-k material into the channel region but also advantageously reduces undesirable scattering effects and improves device mobility, as those skilled in the art will recognize.

[0046] Theoretically, it is also believed that semiconductor devices including superlattice 25 can enjoy higher charge carrier mobility based on a lower effective conductivity mass than would exist in other cases. In some embodiments, and as a result of the bandgap design achieved by the present invention, superlattice 25 can also have a substantially direct bandgap, which can be particularly advantageous for, for example, optoelectronic devices.

[0047] The superlattice 25 also illustratively includes a capping layer 52 on the upper group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46. The capping layer 52 may have 2 to 100 monolayers of base semiconductors, and more preferably 10 to 50 monolayers.

[0048] Each base semiconductor portion 46a-46n may include a base semiconductor selected from group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, as those skilled in the art will recognize, the term "group IV semiconductor" also includes group IV-IV semiconductors. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

[0049] Each bandgap modification layer 50 may include, for example, a non-semiconductor selected from oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. It is also desirable to thermally stabilize the non-semiconductor by depositing the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor processing, as will be recognized by those skilled in the art. More particularly, for example, the base semiconductor may include at least one of silicon and germanium.

[0050] It should be noted that the term monolayer means including both a single atomic layer and a single molecular layer. It should also be noted that the band-modification layer 50 provided by a single monolayer also means including a monolayer in which not all possible sites are occupied (i.e., less than full or 100% coverage). For example, see special reference. Figure 2 The atomic diagram illustrates a 4 / 1 repeating structure where silicon serves as the base semiconductor material and oxygen as the bandgap modifier. In the example shown, only half of the possible sites for oxygen are occupied.

[0051] In other embodiments and / or for different materials, as those skilled in the art will recognize, this half-occupancy will not necessarily be the case. Indeed, even in this schematic diagram, it is evident that the individual oxygen atoms in a given monolayer are not precisely aligned along a flat plane, as those skilled in the art of atomic deposition will recognize. For example, a preferred occupancy range is approximately one-eighth to one-half of the possible oxygen sites filled, but other amounts may be used in some embodiments.

[0052] Silicon and oxygen are currently widely used in conventional semiconductor processing; therefore, manufacturers will be able to readily use these materials described herein. Atomic or monolayer deposition is also now widely used. Consequently, as those skilled in the art will recognize, semiconductor devices incorporating the superlattice 25 according to the invention can be readily adopted and implemented.

[0053] The applicant theoretically believes that, for example, for superlattices (such as Si / O superlattices), the number of silicon monolayers should ideally be seven or fewer so that the energy bands of the superlattice are always common or relatively homogeneous to achieve the desired advantages. For Si / O, Figure 1 and 2 The 4 / 1 repeating structure shown has been modeled as indicating enhanced electron and hole mobility in the X direction. For example, the calculated effective conductivity mass is 0.26 for electrons (for the isotropic bulk silicon) and 0.12 for the 4 / 1 SiO superlattice in the X direction, resulting in a ratio of 0.46. Similarly, the calculated value for holes is 0.36 for bulk silicon and 0.16 for the 4 / 1 Si / O superlattice, resulting in a ratio of 0.44.

[0054] While such directional preference may be desirable in some semiconductor devices, others can benefit from a more uniform increase in mobility in any direction parallel to the layer set. As those skilled in the art will recognize, increased mobility for both electrons and holes, or only one of these types of charge carriers, can also be beneficial.

[0055] The lower effective conductivity mass of the 4 / 1Si / O embodiment of superlattice 25 can be less than two-thirds of the effective conductivity mass that would otherwise occur, and this applies to both electrons and holes. Of course, as those skilled in the art will recognize, superlattice 25 can also include at least one type of conductivity dopant.

[0056] In fact, now additional reference Figure 3 Now, another embodiment of the superlattice 25' according to the invention, with different properties, is described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is shown. More specifically, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. The band-modification layers 50' may each comprise a single monolayer. For this superlattice 25' comprising Si / O, the enhancement of charge carrier mobility is independent of the orientation of the layers in the plane. Figure 3 Other components not specifically mentioned above are related to the above references. Figure 1 The components discussed are similar and need not be discussed further here.

[0057] In some device embodiments, all the base semiconductor portions of the superlattice can be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions can be of different numbers of monolayers thick.

[0058] exist Figures 4A-4C The diagram presents the band structure calculated using density functional theory (DFT). It is well known in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands above the gap can be shifted using appropriate "scissor correction." However, the band shape is known to be much more reliable. The vertical energy axis should be interpreted in this angle.

[0059] Figure 4A This shows the results for bulk silicon (represented by continuous lines) and for... Figure 1 The 4 / 1Si / O superlattice 25 shown (indicated by dotted lines) represents the band structure calculated from the gamma point (G). These directions relate to the unit cell of the 4 / 1Si / O structure, not the conventional unit cell of Si, but the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, thus showing the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will recognize that the bands of Si in the figure are folded to represent them in the appropriate reciprocal lattice directions for the 4 / 1Si / O structure.

[0060] It can be seen that, compared to bulk silicon (Si), the conduction band minimum for the 4 / 1Si / O structure is located at the gamma point, while the valence band minimum appears at the edge of the Brillouin zone in the (001) direction, which we call the Z point. It can also be noted that, due to band splitting caused by perturbations introduced by the additional oxygen layer, the conduction band minimum for the 4 / 1Si / O structure exhibits greater curvature than that for Si.

[0061] Figure 4B The band structure calculated from the Z point is shown for both bulk silicon (continuous line) and 4 / 1Si / O superlattice 25 (dotted line). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

[0062] Figure 4C This shows the results for bulk silicon (continuous line) and for... Figure 3The band structure of the 25' superlattice 5 / 1 / 3 / 1Si / O structure (dotted line) is calculated from both gamma and Z-point measurements. Due to the symmetry of the 5 / 1 / 3 / 1Si / O structure, the band structures calculated in the (100) and (010) directions are equivalent. Therefore, the effective mass of conductivity and mobility are expected to be isotropic in a plane parallel to the layers (i.e., perpendicular to the (001) stacking direction). Note that in the 5 / 1 / 3 / 1Si / O example, both the conduction band minimum and the valence band maximum are at or near the Z-point.

[0063] Although increased curvature indicates a decrease in effective mass, this can be appropriately compared and discriminated by calculations using the inverse of the conductivity-effective mass tensor. This leads the applicant to further theoretically consider that the 5 / 1 / 3 / 1 superlattice 25' should be essentially a direct bandgap. As those skilled in the art will understand, the appropriate matrix elements used for optical transitions are another indicator of the difference between direct and indirect bandgap behavior.

[0064] Now for reference Figure 5 The aforementioned superlattice structure can be advantageously used to provide super-junctions in a variety of different semiconductor devices. In typical super-junction devices, thin (e.g., 50 nm–300 nm) P and N layers are grown adjacent to each other to form a superjunction channel. However, a problem with this configuration is that adjacent thin P and N layers will tend to compensate for each other through diffusion, and will limit the mobility and amount of charge that can be effectively incorporated into the layers without degradation.

[0065] In the example embodiments presented herein, one or more diffusion-blocking superlattice layers, such as the MST superlattice layers discussed above, are advantageously incorporated into the super-abrupt junction stack. The superlattice layers advantageously block interdiffusion and thus correspondingly increase the available charge with higher mobility due to less ionized impurity scattering. According to a first example, the JFET 100 illustratively includes a semiconductor substrate 101 having a back gate 102 therein. Spaced-apart source and drain regions 104, 105 with corresponding contacts 106, 107 are formed on the back gate 102, and a super-abrupt junction region 108 is also formed on the back gate between the source and drain regions. Furthermore, a back gate through-region 109 with contacts 110 is coupled to the back gate 102, and an isolation region 111 (e.g., oxide) spaces the back gate through-region from the source and drain regions 104, 105. It should be noted that in some embodiments, the back gate through region 109 may instead extend from the back side of the substrate 101 instead of from the top / front side as shown, in which case (one or more) contacts 110 will be on the back side of the substrate.

[0066] More specifically, the super-abrupt junction region 108 illustratively includes a first semiconductor layer 112 having a first conductivity type (N or P), a first superlattice layer 125a on the first semiconductor layer, a second semiconductor layer 113 on the first semiconductor layer having a second conductivity type (P or N) different from the first conductivity type, and a second superlattice layer 125b on the second semiconductor layer. Furthermore, a gate electrode 115 is illustratively included overlying the second superlattice layer 125b, which will generally have the same conductivity type as the back gate 102 and the first semiconductor layer 112 (i.e., the first conductivity type), while the semiconductor layer 113 and the source / drain regions 104, 105 will be of the same conductivity type (here, the second conductivity type). The second semiconductor layer 113 of the super-abrupt junction region 108 defines the super-abrupt channel of the JFET 100. The superlattice layers 125a, 125b effectively block interdiffusion and thus increase the available charge with higher mobility within the channel due to less ionized impurity scattering.

[0067] For further reference Figure 10 Flowchart 120 begins at block 121. At block 122, semiconductor layers 112, 113 and superlattices 125a, 125b can be formed alternately as blanket layers across substrate 101, or selectively at desired locations on the substrate to form super-abrupt junction regions 108. In the illustrated example, superlattices 125a, 125b extend into source and drain regions 104, 105 and into back gate pass-through region 109, but in some embodiments, the superlattices may be confined only to the channel region if desired. Then at block 123, a gate electrode layer 115 can be formed over superlattice 125b, followed by a gate contact 116. At block 125, source and drain regions 106, 107 can be formed by doping with a dopant of an appropriate conductivity type (P-type for P-channels and vice versa), and the back gate pass-through region 109 can be similarly formed. An isolation region 117 is also formed to isolate the source and drain contacts 106, 107 from the gate contacts. Figure 10 The method is explained illustratively at box 126.

[0068] Go to Figure 6The above-described technology can also be used to fabricate other FET structures, such as IGFET 200. IGFET 200 illustratively includes a substrate 201 and a semiconductor layer 202 on the substrate. A superjunction region 208 is located within the semiconductor layer 202 and extends partially into the substrate 201. The superjunction region 208 illustratively includes a first semiconductor layer 212 having a first conductivity type (N or P), a first superlattice layer 225a on the first semiconductor layer, a second semiconductor layer 213 on the first superlattice layer and having a conductivity type (P or N) different from the first conductivity type, and a second superlattice layer 225b on the second semiconductor layer. Furthermore, the superjunction region 208 is U-shaped and can be formed as a filled trench structure by continuously depositing the aforementioned layers in a trench extending through the semiconductor layer 202 into the substrate 201.

[0069] Overlying the superjunction region 208 are a drain extension region 230 and a dielectric layer 228. Furthermore, a gate electrode layer 215 is overlying the dielectric layer 228 and surrounded by a gate dielectric layer 214. A body region 233 surrounds the gate dielectric layer and defines a conductive channel 240 adjacent to the gate dielectric layer 232. Overlying the body region 233 is a source region 234, and overlying the source region and the gate are first and second dielectric layers 235 and 236. Additionally, a source contact layer 237 (e.g., a semiconductor) may be formed over the top side of the device 200 (i.e., overlying the gate structure and the semiconductor layer 202), and a drain contact layer 238 (e.g., a metal layer) may be formed on the back side of the substrate 201.

[0070] Now go to Figure 7 According to another example embodiment of the IGFET 200', the super-abrupt junction region 208' illustratively includes a single superlattice layer 225'. More specifically, in this example, the super-abrupt junction region 208' illustratively includes a first semiconductor layer 212' having a first conductivity type (N or P), a superlattice layer 225', a second semiconductor layer 213' having a second conductivity type (P or N) opposite to the first conductivity type, and an optional intrinsic semiconductor layer 239'. The remaining components of the IGFET 200' can be similar to those described above. Figure 6 The components described.

[0071] Now go to Figure 8 and Figure 11Flowchart 130 now describes a varactor diode 300 incorporated into a super-abrupt junction layer 308 and an associated manufacturing method. The varactor diode 300 illustratively includes a substrate 301 having a cathode layer 302 and a collector layer 303 on the cathode layer. Starting at block 131, a super-abrupt junction region 308 (block 132) may be grown on the collector layer 303 of the substrate 301. More specifically, the super-abrupt junction region 308 illustratively includes a first semiconductor layer 312 having a first conductivity type (P or N), a first superlattice 325a on the first semiconductor layer, a second semiconductor layer 313 on the first superlattice layer having a second conductivity type (N or P) different from (i.e., opposite to) the first conductivity type, and a second superlattice layer 325b on the second semiconductor layer.

[0072] Furthermore, at box 133, an anode region 340 and an associated metal layer 341 (i.e., a first contact) are formed on the superjunction region 308. Additionally, (box 134) a through-hole implant 342 and an associated metal layer 343 (i.e., a second contact) are also formed to contact the cathode layer 302 of the substrate 301 (it should be noted that in some embodiments this can be replaced by a back-side contact if desired). The through-hole implant 342 is laterally spaced from the superjunction 308 and extends from the surface of the collector layer 303 to the cathode layer 302. More specifically, the through-hole implant 342 may have a conductivity type opposite to that of the cathode layer 302 and the collector layer 303, and the collector layer and the first semiconductor layer 312 may have the same conductivity type. Furthermore, an isolation region 311 (e.g., a dielectric) may be formed around the superjunction region 308 and the through-hole implant 342. Figure 11 The method ends at box 135.

[0073] Now for reference Figure 9A Another similar varactor diode 330' is described, wherein the super-abrupt junction 308' illustratively includes a single semiconductor layer 325'. More specifically, the super-abrupt junction 308' illustratively includes a first semiconductor layer 312', a superlattice 325', an intrinsic semiconductor layer 339', and a second semiconductor layer 340' (which also serves as the anode region). Figure 9B The diagram shows another similar varactor diode 330", in which all components are identical to those in varactor diode 330', except that the intrinsic layer 339" is below rather than above the superlattice layer 325". The remaining components of varactor diodes 330' and 330" can be similar to those described above. Figure 8 The components described.

[0074] Further details regarding the JFET, IGFET, and varactor diode structures can be found in U.S. Patent No. 7,825,441 to Eshun et al.; U.S. Publication No. 2007 / 0278565 to Tu et al.; and U.S. Patent No. 7,183,628 to Coolbaugh et al., which are incorporated herein by reference in their entirety.

[0075] Many modifications and other embodiments of the invention will arise for those skilled in the art from the teachings presented in the foregoing description and the accompanying drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: substrate; The super-abrupt junction region supported by the substrate includes: A first semiconductor layer having a first conductivity type, The first superlattice layer on the first semiconductor layer, A second semiconductor layer, having a second conductivity type different from the first conductivity type, is disposed on a first superlattice layer. The second semiconductor layer defines a superjunction with respect to the first semiconductor layer. A second superlattice layer on the second semiconductor layer; Gate dielectric layer on the second superlattice layer in the super-abrupt junction region; The gate electrode on the gate dielectric layer; and Source and drain regions spaced apart on opposite sides of the super-mutation junction region; The first and second superlattices each include multiple stacked layers, each layer including multiple stacked basic semiconductor monolayers defining a basic semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent basic semiconductor portion. The first superlattice layer and the second superlattice layer block the diffusion of dopants between the first semiconductor layer and the second semiconductor layer.

2. The semiconductor device of claim 1, wherein the spaced-apart source region and drain region have the second conductivity type.

3. The semiconductor device of claim 1, wherein the first semiconductor layer and the second semiconductor layer, as well as the first superlattice layer and the second superlattice layer, are parallel to the bottom portion of the substrate.

4. The semiconductor device of claim 1, wherein the first semiconductor layer and the second semiconductor layer, as well as the first superlattice layer and the second superlattice layer, are U-shaped.

5. The semiconductor device of claim 1, wherein the first semiconductor layer and the second semiconductor layer each have a thickness in the range of 50 nm to 300 nm.

6. The semiconductor device of claim 1, wherein the basic semiconductor monolayer comprises a silicon monolayer.

7. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.

8. The semiconductor device of claim 1, wherein the basic semiconductor monolayer comprises germanium.

9. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

10. A method for manufacturing a semiconductor device, comprising: A super-abrupt junction region is formed above the substrate, and the super-abrupt junction region includes... A first semiconductor layer having a first conductivity type, The first superlattice layer on the first semiconductor layer, A second semiconductor layer having a second conductivity type different from the first conductivity type on a first superlattice layer, and A second superlattice layer on the second semiconductor layer; A gate dielectric layer is formed on the second superlattice layer in the super-abrupt junction region; A gate electrode is formed on the gate dielectric layer; as well as Forming spaced-apart source and drain regions adjacent to the super-mutation junction region; The first and second superlattices each include multiple stacked layers, each layer including multiple stacked basic semiconductor monolayers defining a basic semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent basic semiconductor portion. The first superlattice layer and the second superlattice layer block the diffusion of dopants between the first semiconductor layer and the second semiconductor layer.

11. The method of claim 10, wherein the spaced-apart source region and drain region have the second conductivity type.

12. The method of claim 10, wherein the first semiconductor layer and the second semiconductor layer, as well as the first superlattice layer and the second superlattice layer, are parallel to the bottom portion of the substrate.

13. The method of claim 10, wherein the first semiconductor layer and the second semiconductor layer, as well as the first superlattice layer and the second superlattice layer, are U-shaped.

14. The method of claim 10, wherein the first semiconductor layer and the second semiconductor layer each have a thickness in the range of 50 nm to 300 nm.

15. The method of claim 10, wherein the basic semiconductor monolayer comprises a silicon monolayer.

16. The method of claim 10, wherein the at least one non-semiconductor monolayer comprises oxygen.

17. The method of claim 10, wherein the basic semiconductor monolayer comprises germanium.

18. The method of claim 10, wherein the at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

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