Integrated chip with substrate via and method of forming the same

Abstract

An integrated chip (IC) comprising: a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate; an insulating structure disposed along an inner sidewall of the semiconductor substrate, the inner sidewall of the semiconductor substrate extending through the semiconductor substrate; a barrier layer disposed along an inner sidewall of the insulating structure; and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewall of the insulating structure, the second portion extending from the first portion to the conductive structure, and a maximum width of the second portion is less than a maximum width of the first portion.

Description

Technical Field

[0001] This invention relates to an integrated chip with a substrate through-hole and a method for forming the same. Background Technology

[0002] A through-substrate via (TSV) is a conductive structure that passes through a semiconductor substrate. TSVs are used to electrically couple conductive structures located on opposite sides of a semiconductor substrate. TSVs are used in many modern integrated chip structures, such as back-side illuminated (BSI) image sensors, multidimensional integrated chips (e.g., 3DIC), or the like. Summary of the Invention

[0003] This invention provides an integrated chip (IC) comprising: a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate; an insulating structure disposed along an inner sidewall of the semiconductor substrate, wherein the inner sidewall of the semiconductor substrate extends through the semiconductor substrate; a barrier layer disposed along the inner sidewall of the insulating structure; and a substrate through-hole (TSV) comprising a first portion and a second portion, wherein the first portion extends along a horizontally extending surface of the insulating structure protruding outward from the inner sidewall of the insulating structure, and wherein the second portion extends from the first portion to the conductive structure, and the maximum width of the second portion is less than the maximum width of the first portion.

[0004] This invention provides a method for constructing an integrated circuit (IC), comprising: forming a conductive structure within a dielectric structure along a first side of a semiconductor substrate; performing a first etching process on a second side of the semiconductor substrate to form a sidewall of the semiconductor substrate, the sidewall defining a first via extending into the dielectric structure; forming an insulating structure above the second side of the semiconductor substrate and along the sidewall of the semiconductor substrate; performing a second etching process on the dielectric structure to form a sidewall of the dielectric structure, the sidewall defining a second via extending into the conductive structure, wherein the maximum width of the second via is less than the maximum width of the first via; and forming a substrate through-hole (TSV) within the first via and the second via.

[0005] This invention provides a method for forming an integrated circuit (IC), comprising: forming an interconnect structure within a dielectric structure along a first side of a semiconductor substrate; performing a first etching process on a second side of the semiconductor substrate to form a sidewall of the semiconductor substrate, the sidewall defining a first via extending into the dielectric structure; forming an insulating structure above the second side of the semiconductor substrate and along the sidewall of the semiconductor substrate; forming a barrier layer along the sidewall of the insulating structure; forming a temporary barrier layer along the sidewall of the barrier layer and the sidewall of the insulating structure; performing a second etching process on the dielectric structure to form a sidewall of the dielectric structure, the sidewall defining a second via extending into the interconnect structure; and forming a conductive material within the first and second vias. Attached Figure Description

[0006] The various aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip (IC) are shown, the integrated chip including the disclosed substrate through-hole (TSV) structure having multiple portions of different widths.

[0008] Figure 2 Cross-sectional views of some additional embodiments of an image sensor IC including the disclosed TSV structure are shown.

[0009] Figure 3 Cross-sectional views of some additional embodiments of an IC including the disclosed TSV structure are shown.

[0010] Figure 4A Cross-sectional views of some additional embodiments of an IC including the disclosed TSV structure are shown.

[0011] Figure 4B Show Figure 4A Some embodiments of IC top view.

[0012] Figures 5 to 13 A series of cross-sectional views are shown illustrating some embodiments of methods for forming an IC including the disclosed TSV structure.

[0013] Figure 14 Showing with Figures 5 to 13 Flowcharts of some embodiments of the consistent method. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0016] A substrate through-vessel (TSV) can be formed by selectively exposing a first side of a semiconductor substrate to an etchant according to a mask layer to form an opening extending through the semiconductor substrate and reaching a conductive structure disposed along a second side of the semiconductor substrate. After forming the opening, a dielectric layer can be formed along the inner sidewall of the semiconductor substrate defining the opening, and a conductive material can be formed within the opening, above the dielectric layer, and on the conductive features. A planarization process is then performed to remove excess conductive material from above the first side of the semiconductor substrate, forming the TSV extending from the first side of the semiconductor substrate to the conductive structure.

[0017] As the size of integrated chip components shrinks, the size of the openings used to form TSVs can also decrease. Reducing the opening size can improve the reliability of the integrated chip. For example, a smaller opening size allows the TSV size to correspond to the conductive structure below, thereby mitigating over-etching and corresponding electrical short circuits. It also allows less etchant to enter the opening, thus reducing damage to smaller and / or thinner conductive structures. However, a smaller opening size can affect the ability of the plating process to effectively form conductive material within the opening. For example, as the opening size decreases, it may become more difficult for metal ions to enter the opening, creating voids in the resulting TSV. Voids increase the resistance of the TSV, thus reducing its efficiency in conducting charge through the semiconductor substrate.

[0018] This disclosure presents a method for manufacturing a TSV (Through-Substrate Via) to produce more efficient integrated circuits. The method includes performing a first etching process to form a first opening through a semiconductor substrate, and lining the sidewalls of the semiconductor substrate defining the first opening with a dielectric layer. A barrier layer and a temporary barrier layer are then formed along the sidewalls of the dielectric layer. A second etching process is then performed with the barrier layer and temporary barrier layer in place to form a second opening through the dielectric layer extending to an underlying conductive structure. The barrier layer and temporary barrier layer block some of the etchant used in the second etching process, such that the etchant is confined away from the dielectric layer, and the second opening is formed to have a maximum width smaller than that of the first opening. A conductive material is then formed within the first and second openings to define the substrate via (TSV). Using a temporary barrier layer to reduce the width of the second opening allows the first opening to be formed with a relatively large width to reduce voids in the TSV, while the smaller width of the second opening can improve the reliability of the associated integrated chip by reducing over-etching of the TSV opening and / or damage to the conductive structure.

[0019] Figure 1 Cross-sectional view 100 shows some embodiments of integrated chips (ICs) including substrate through-hole (TSV) structures.

[0020] The IC includes a dielectric structure 102 disposed along a first side 106a of a semiconductor substrate 106. The dielectric structure 102 surrounds a conductive structure 104. In some embodiments, the dielectric structure 102 may include an inter-level dielectric (ILD) structure, and the conductive structure 104 may include conductive interconnects. A substrate through-hole (TSV) 108 extends through an opening 103 defined by a sidewall of the semiconductor substrate 106. In some embodiments, the TSV 108 extends from a second side 106b of the semiconductor substrate 106 to the conductive structure 104. An insulating structure 110 covers the semiconductor substrate 106 and laterally separates the semiconductor substrate 106 from the TSV 108. The insulating structure 110 includes a horizontally extending surface 110h located below a horizontally extending surface 108h of the TSV 108. A barrier layer 112 covers the semiconductor substrate 106 and is disposed along the inner sidewall of the insulating structure 110, thereby providing another layer of isolation between the TSV 108 and the semiconductor substrate 106. In some embodiments, TSV 108 may include a diffusion barrier layer 114 disposed along one or more outer surfaces of TSV 108.

[0021] In some embodiments, the bottom surface of the barrier layer 112 may directly cover the TSV 108. In some embodiments, the height of the insulating structure 110 may be greater than the height of the barrier layer 112. In some embodiments, the barrier layer 112 directly covers the horizontally extending surface 110h of the insulating structure 110.

[0022] In some embodiments, the TSV 108 includes a plurality of different portions 109a to 109c with different widths. For example, in some embodiments, the TSV 108 may include a first portion 109a, a second portion 109b, and a third portion 109c, each with a different width. The first portion 109a is disposed between the inner sidewalls of the barrier layer 112, the second portion 109b is disposed between the inner sidewalls of the insulating structure 110, and the third portion 109c is disposed between the inner sidewalls of the dielectric structure 102. In some embodiments, the maximum width of the first portion 109a of the TSV 108 is less than the maximum width of the second portion 109b of the TSV 108. In some embodiments, the maximum width of the third portion 109c of the TSV 108 is less than the maximum width of the second portion 109b of the TSV 108. This allows the TSV 108 to extend wider through the semiconductor substrate 106 while maintaining a smaller width at the point where the TSV 108 contacts the conductive structure 104.

[0023] In some embodiments, the innermost sidewall of the insulating structure 110 is aligned with the inner sidewall of the dielectric structure 102 along a line, and in a further embodiment, the inner sidewall is inclined inward. In some embodiments, the first portion 109a of the TSV 108 directly covers the horizontally extending surface 110h of the insulating structure 110. In some embodiments, the outer sidewall of the third portion 109c of the TSV 108 is inclined at an angle different from 90 degrees relative to the first side 106a of the semiconductor substrate 106. The third portion 109c of the TSV 108 may have a bottom surface recessed below the top surface of the conductive structure 104. In such embodiments, the innermost sidewall of the insulating structure 110 and the inner sidewall of the dielectric structure 102 may be inclined inward.

[0024] The width of TSV 108 and the corresponding opening 103 corresponds to the ability of the electroplating process to effectively form conductive material within the opening 103. For example, as the width of opening 103 decreases, it may become more difficult for metal ions to enter the opening 103, thus creating voids in TSV 108. Furthermore, the width of TSV 108 and the corresponding opening 103 also corresponds to the reliability of the integrated chip. For example, as the width of opening 103 increases, over-etching and / or damage to conductive structure 104 may increase. The different widths of the various portions 109a to 109c of TSV 108 allow opening 103 to have both a first width that reduces voids within TSV 108 and a second width that limits over-etching and / or damage to conductive structure 104, thereby providing good electrical properties and good reliability for TSV 108.

[0025] Figure 2 A cross-sectional view 200 is shown for some embodiments of an IC including a substrate through-hole (TSV) structure.

[0026] The IC includes a first interlayer dielectric (ILD) structure 202 disposed along a first side 206a of a first semiconductor substrate 206. The first ILD structure 202 surrounds a first plurality of interconnects 204. A substrate through-hole (TSV) 108 extends through the first semiconductor substrate 206. In some embodiments, the TSV 108 extends from a second side 206b of the first semiconductor substrate 206 to one of the first plurality of interconnects 204. In some embodiments, the TSV 208 may extend to an interconnect wire, the interconnect wire being the one closest to the first semiconductor substrate 206.

[0027] In some embodiments, the TSV 108 includes a plurality of different portions 109a to 109c with different widths. For example, the TSV 108 may include a first portion 109a, a second portion 109b, and a third portion 109c, each with a different width. In some embodiments, the width of the first portion 109a may be substantially equal to the width of the third portion 109c. In some embodiments, the minimum width of the first portion 109a may be greater than the minimum width of the third portion 109c (due to a temporary barrier layer used during etching the openings of the TSV 108).

[0028] An insulating structure 110 is disposed along a second side 206b of the first semiconductor substrate 206 and laterally separates the first semiconductor substrate 206 from the TSV 108. The insulating structure 110 includes a horizontally extending surface extending outward from a sidewall of the insulating structure 110 beneath the TSV 108. A barrier layer 112 covers the first semiconductor substrate 206 and is disposed along an inner sidewall of the insulating structure 110, thereby providing another layer of isolation between the TSV 108 and the first semiconductor substrate 206. In some embodiments, the bottom surface of the barrier layer 112 is higher than the bottom surface of the insulating structure 110.

[0029] In some embodiments, the first semiconductor substrate 206 may be or otherwise comprise, for example, a bulk silicon substrate, a bulk germanium substrate, a group III to V substrate, or some other suitable semiconductor substrate. In some embodiments, the first ILD structure 202 may comprise a plurality of stacked ILD layers, each comprising silicon dioxide, silicon nitride, some other suitable low dielectric constant dielectric material(s), or any combination thereof. In some embodiments, the barrier layer 112 and / or the insulating structure 110 may comprise or be nitrides, oxides, carbides, or the like. The TSV 108 and / or the first plurality of interconnects 204 are conductive and may be or otherwise comprise, for example, tungsten, aluminum-copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s).

[0030] The redistribution layer 216 contacts the upper surface of the TSV 108. A first dielectric material 218 is disposed above the upper surface of the barrier layer 112, such that it contacts the outer sidewall of the redistribution layer 216. A second dielectric material 220 is disposed above the first dielectric material 218, such that it contacts the top surface and the inner sidewall of the redistribution layer 216. In some embodiments, the bottom surface of the second dielectric material 220 is recessed below the top surface of the first dielectric material 218.

[0031] In some embodiments, under-bump metallization 232 is disposed above the top surface of redistribution layer 216. Further embodiments include solder bumps 248 electrically coupled to under-bump metallization 232. Redistribution layer 216, under-bump metallization 232, and solder bumps 248 are conductive and may be, or otherwise comprise, for example, tungsten, aluminum-copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s). First dielectric material 218 and second dielectric material 220 may be, or otherwise comprise, for example, silicon dioxide, silicon nitride, or any combination thereof.

[0032] In some embodiments, a photodiode 228 is disposed within a first semiconductor substrate 206. The photodiode 228 has a first region 228a of a first doping type (e.g., n-type) and an adjacent second region 228b of a second doping type different from the first doping type (e.g., p-type). A first transistor 256 is disposed along a first side 206a of the first semiconductor substrate 206. The first transistor 256 includes a first gate dielectric layer 224 disposed along the first side 206a of the first semiconductor substrate 206 and a first gate electrode 226 below the first gate dielectric layer 224. In some embodiments, a first pair of sidewall spacers 230 are disposed on opposite sides of the first gate electrode 226. A floating diffusion well 234 is disposed within the first semiconductor substrate 206, and the first transistor 256 is laterally located between the floating diffusion well 234 and the photodiode 228. The first gate dielectric layer 224 may be or otherwise comprise, for example, silicon dioxide, silicon nitride, or any combination thereof. The first pair of sidewall spacers 230 may be or otherwise comprise, for example, nitride, oxide, or any combination thereof. The first gate electrode 226 may be or otherwise comprise, for example, doped polysilicon, metal, or some other suitable conductive material(s).

[0033] A color filter 242 covers the barrier layer 112 and is configured to transmit incident radiation of a specific wavelength. In some embodiments, the color filter 242 is disposed within a mesh structure 244 disposed on the barrier layer 112. A microlens 246 is disposed above the color filter 242. In some embodiments, the microlens 246 may have a substantially flat bottom surface adjacent to the color filter 242 and a curved upper surface configured to focus incident radiation toward a photodiode 228. The color filter 242 may have sidewalls defined by sidewalls of a first dielectric material 218 and a second dielectric material 220.

[0034] In some embodiments, a second ILD structure 252 is disposed below a first ILD structure 202. The second ILD structure 252 surrounds a second plurality of interconnects 254. In a further embodiment, a second semiconductor substrate 250 is disposed below the second ILD structure 252. The second semiconductor substrate 250 may be or otherwise comprise, for example, a bulk silicon substrate, a bulk germanium substrate, a group III to V substrate, or some other suitable semiconductor substrate. The second ILD structure 252 may be or otherwise comprise, for example, silicon dioxide, silicon nitride, some other suitable low dielectric constant dielectric material(s), or any combination thereof. The second plurality of interconnects 254 are conductive and may be or otherwise comprise, for example, tungsten, aluminum-copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s).

[0035] A second transistor 258 is disposed on a second semiconductor substrate 250. The second transistor 258 includes a second gate dielectric layer 236 disposed above the upper surface of the second semiconductor substrate 250 and a second gate electrode 240 disposed above the second gate dielectric layer 236. In some embodiments, a second pair of sidewall spacers 238 are disposed on opposite sides of the second gate electrode 240. A second diffusion well 264a and a third diffusion well 264b are disposed within the second semiconductor substrate 250 and below the second transistor 258. In some embodiments, the second gate dielectric layer 236 may be or otherwise comprise, for example, silicon dioxide, silicon nitride, or any combination thereof. The second pair of sidewall spacers 238 may be or otherwise comprise, for example, nitride, oxide, or any combination thereof. The second gate electrode 240 may be or otherwise comprise, for example, doped polysilicon, metal, or some other suitable conductive material(s).

[0036] Figure 3 A cross-sectional view 300 is shown of some embodiments of an IC including a substrate through-hole (TSV) structure.

[0037] The IC includes a dielectric structure 102 (e.g., an ILD structure) disposed along a first side 106a of a semiconductor substrate 106. The dielectric structure 102 surrounds a plurality of conductive structures 104a to 104b. In some embodiments, the plurality of conductive structures 104a to 104b includes a first conductive structure 104a (e.g., a first interconnect) and a second conductive structure 104b (e.g., a second interconnect). A plurality of TSVs 108a to 108b extend through the semiconductor substrate 106. In some embodiments, the plurality of TSVs 108a to 108b extend from a second side 106b of the semiconductor substrate 106 to the plurality of conductive structures 104a to 104b. For example, a first TSV 108a may extend from the second side 106b of the semiconductor substrate 106 to the first conductive structure 104a, and a second TSV 108b may extend from the second side 106b of the semiconductor substrate 106 to the second conductive structure 104b.

[0038] An insulating structure 110 is disposed along a second side 106b of a semiconductor substrate 106 and extends continuously along the sidewall of the semiconductor substrate 106. The insulating structure 110 laterally separates the semiconductor substrate 106 from the plurality of TSVs 108a to 108b. In some embodiments, the insulating structure 110 may include a plurality of different dielectric layers 110a to 110c. For example, the insulating structure 110 may include a first dielectric layer 110a and a second dielectric layer 110b stacked on the second side 106b of the semiconductor substrate 106. In some embodiments, the insulating structure 110 may further include a third dielectric layer 110c disposed over the second dielectric layer 110b and extending along the first dielectric layer 110a, the second dielectric layer 110b, and the sidewall of the semiconductor substrate 106. The insulating structure 110 may have a horizontally extending surface directly beneath the plurality of TSVs 108a to 108b. In some embodiments, the first dielectric layer 110a may comprise an oxide, the second dielectric layer 110b may comprise a nitride, and the third dielectric layer 110c may comprise an oxide.

[0039] A barrier layer 112 covers the insulating structure 110 and lines part, but not all, of the inner sidewalls of the insulating structure 110. The barrier layer 112 may further extend over the plurality of TSVs 108a to 108b such that an imaginary vertical line perpendicular to the first side 106a of the semiconductor substrate 106 extends through the barrier layer 112 and the plurality of TSVs 108a to 108b.

[0040] The plurality of TSVs 108a to 108b each include a plurality of different portions 109a to 109c with different widths. For example, the plurality of TSVs 108a to 108b may include a first portion 109a, a second portion 109b, and a third portion 109c with different widths. The third portion 109c may include a first width W1 between the inner sidewalls of the insulating structure 110 and a second width W2 at the bottommost surface of the plurality of TSVs 108a to 108b. In some embodiments, the first width W1 may be greater than the second width W2. In some embodiments, the first width W1 may be between approximately 500 nanometers and approximately 700 nanometers, between approximately 550 nanometers and approximately 650 nanometers, or other suitable values. In some embodiments, the second width W2 may be between approximately 400 nanometers and approximately 600 nanometers, between approximately 450 nanometers and approximately 550 nanometers, or other suitable values. In some embodiments, the second portion 109b may include a third width W3 between the outermost sidewalls of the TSV 108. The third width W3 may be greater than the second width W2. In some embodiments, the third width W3 may be between 110% and 150% larger than the second width W2, thereby allowing sufficient space to reduce voids in the TSV while preventing over-etching and / or damage to the plurality of conductive structures 104a to 104b. In some embodiments, the third width W3 may be between approximately 700 nm and approximately 800 nm, between approximately 725 nm and approximately 775 nm, or other suitable values.

[0041] The plurality of TSVs 108a to 108b may be laterally separated from each other by a first distance D1. In some embodiments, the first distance D1 may be between approximately 550 nm and approximately 650 nm, between approximately 575 nm and approximately 625 nm, or other suitable values. In some embodiments, the plurality of TSVs 108a to 108c may be disposed within an opening defined by sidewalls separating a second distance D2. In some embodiments, the second distance D2 may be between 750 nm and 850 nm, between approximately 775 nm and approximately 825 nm, or other suitable values. In some embodiments, the first distance D1 may be greater than the second width D2. The horizontally extending surface of the insulating structure 110 may extend a third distance D3. In some embodiments, the third distance D3 may be between 70 nm and 90 nm, between approximately 75 nm and approximately 85 nm, or other suitable values. Each of the plurality of conductive structures 104a to 104b may have a fourth width W4, and each of the plurality of conductive structures 104a to 104b may be separated by a fourth distance D4. The fourth width W4 may be between approximately 750 nm and approximately 1000 nm, between approximately 800 nm and approximately 900 nm, or other suitable values. The fourth distance D4 may be between approximately 400 nm and approximately 600 nm, between approximately 450 nm and approximately 550 nm, or other suitable values.

[0042] Figure 4A Cross-sectional view 400A shows some embodiments of an IC including a substrate through-hole (TSV) structure.

[0043] The IC includes a conductive structure 104 disposed within a dielectric structure 102 along a first side 106a of a semiconductor substrate 106. The semiconductor substrate 106 surrounds a substrate through-hole (TSV) 108. In some embodiments, the TSV 108 extends through the semiconductor substrate 106 to the top surface of the conductive structure 104. An insulating structure 110 covers the semiconductor substrate 106 and laterally separates the semiconductor substrate 106 from the TSV 108. The insulating structure 110 includes a horizontally extending surface 110h located below the TSV 108. A barrier layer 112 covers the semiconductor substrate 106 and is disposed along the inner sidewall of the insulating structure 110. In some embodiments, the barrier layer 112 may include an inner sidewall extending from the top surface of the barrier layer 112 to the inner sidewall of the insulating structure 110. In some embodiments, the barrier layer 112 may have a thickness that gradually decreases between a first value at the top surface of the barrier layer 112 and a second value at the bottom surface of the barrier layer 112.

[0044] TSV 108 includes a plurality of distinct portions 109a to 109c. In some embodiments, the plurality of distinct portions 109a to 109c include a first portion 109a disposed along a second side 106b of the semiconductor substrate 106, a second portion 109b covering a horizontally extending surface 110h of the insulating structure 110, and a third portion 109c located directly below the second portion 109b. In some embodiments, the maximum width of the second portion 109b is greater than the maximum width of the third portion 109c. In some embodiments, the second portion 109b of TSV 108 may include a lower surface in direct contact with the horizontally extending surface 110h of the insulating structure 110. In some embodiments, the lower surface of the second portion 109b of TSV 108 may extend horizontally into a vertical portion of the insulating structure 110 by a fifth distance D5. In some embodiments, a portion of the semiconductor substrate 106 may be disposed directly below the horizontally extending surface 110h of the insulating structure 110.

[0045] In some embodiments, the second portion 109b of the TSV 108 has a sidewall at a first angle θ1 relative to the first side 106a of the semiconductor substrate 106, and the third portion 109c of the TSV 108 includes a sidewall at a second angle θ2 relative to the first side 106a of the semiconductor substrate 106. The first angle θ1 is different from the second angle θ2.

[0046] Figure 4B A cross-section 400B is shown for some embodiments of an IC including a TSV structure. In some embodiments, the IC may be... Figure 4A The IC described herein. TSV 108 is surrounded by an insulating structure 110. A semiconductor substrate 106 surrounds the insulating structure 110. The third portion 109c of TSV 108 may be smaller than the second portion 109b of TSV 108. In some embodiments, the surface area of ​​the third portion 109c of TSV 108 may be less than half the surface area of ​​the second portion 109b of TSV 108. In some embodiments, TSV 108 and insulating structure 110 may each have a square profile. In other embodiments (not shown), TSV 108 and insulating structure 110 may each have a circular profile or a square profile with rounded edges.

[0047] Reference Figures 5 to 13 A series of cross-sections 500 to 1300 illustrate some embodiments of methods for forming an IC including a TSV. The IC may, for example, correspond to... Figure 1 IC. Although the method is described. Figures 5 to 13 However, it should be understood that Figures 5 to 13 The structure disclosed herein is not limited to this method, but can exist independently of the method.

[0048] like Figure 5 As shown in the cross-sectional view 500, a dielectric structure 102 and a conductive structure 104 are formed along a first side 106a of a semiconductor substrate 106. In some embodiments, the conductive structure 104 may be formed within the dielectric structure 102. In some embodiments, the semiconductor substrate 106 may be or otherwise comprise, for example, a bulk silicon substrate, a bulk germanium substrate, a group III to V substrate, or some other suitable semiconductor substrate. The dielectric structure 102 may be or otherwise comprise, for example, silicon dioxide, silicon nitride, some other suitable low dielectric constant dielectric material(s), or any combination thereof. The conductive structure 104 is conductive and may be or otherwise comprise, for example, tungsten, aluminum-copper, copper, aluminum, some other suitable metal(s), or some other suitable conductive material(s).

[0049] In some embodiments, the dielectric structure 102 may be formed by a deposition process (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition, physical vapor deposition, or similar deposition processes). In some embodiments, the conductive structure 104 may include interconnects (e.g., interconnect wires). In various embodiments, the interconnects may be formed by a damascene process (e.g., single damascene, double damascene), wherein the dielectric structure 102 is selectively patterned to define openings subsequently filled with a conductive material.

[0050] like Figure 6 As shown in the cross-sectional view 600, a first hole 602 is etched in the semiconductor substrate 106 by a first etching process. The first hole 602 is defined by the inner sidewalls 106s of the semiconductor substrate 106 and exposes a portion of the dielectric structure 102. In some embodiments (not shown), the first etching process can be performed by forming a mask (e.g., a hard mask, photoresist, or the like) over the semiconductor substrate 106 and then exposing the semiconductor substrate 106 to a first etchant according to the mask to define the first hole 602.

[0051] like Figure 7 As shown in the cross-sectional view 700, an insulating structure 110 is formed over a semiconductor substrate 106. The insulating structure 110 is further formed along the inner sidewalls 106s of the semiconductor substrate 106 and over the exposed portion of the dielectric structure 102. The insulating structure 110 can be formed by, for example, physical vapor deposition, chemical vapor deposition, or some other suitable formation process. The insulating structure 110 can be or otherwise comprises, for example, oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), or any combination thereof.

[0052] In some embodiments (not shown), the insulating structure 110 may include a plurality of dielectric layers. For example, the insulating structure 110 may include a first dielectric layer and / or a second dielectric layer formed over the semiconductor substrate 106 before etching the first hole 602, and a third dielectric layer formed over the first and second dielectric layers and along the inner sidewall of the semiconductor substrate 106 after etching the first hole 602. In this embodiment, the first dielectric layer and / or the second dielectric layer may be used as part of a mask to etch the first hole 602.

[0053] like Figure 8 As shown in the cross-sectional view 800, a barrier layer 112 is formed above the insulating structure 110 and along the inner sidewall of the insulating structure 110. The barrier layer 112 reduces the width of the first hole 602 along the second side of the semiconductor substrate 106.

[0054] The barrier layer 112 can be formed by a deposition process (e.g., physical vapor deposition, chemical vapor deposition, or some other suitable formation process). In some embodiments, the formation process causes material to accumulate at the edges of the barrier layer 112. The accumulation includes the surface of the barrier layer 112, which protrudes outward as a protrusion from the sidewall of the barrier layer 112. The barrier layer 112 reduces the width of the first aperture 602 along the second side of the semiconductor substrate 106 from a first width 802 to a second width 804.

[0055] In some embodiments, the formation process of the barrier layer 112 may not completely fill the first via 602, but may form the barrier layer 112 to contact a portion of the inner sidewall of the insulating structure 110, thereby serving as a barrier layer for subsequent etching of the dielectric structure 102. The barrier layer 112 may be or additionally comprise, for example, silicon dioxide, silicon nitride, or any combination thereof.

[0056] like Figure 9 As shown in the cross-sectional view 900, a temporary barrier layer 902 is provided above the barrier layer 112, along the inner sidewall of the barrier layer 112, along the inner sidewall of the insulating structure 110, and above the exposed surface of the insulating structure 110. The temporary barrier layer 902 further reduces the width of the first hole 602 along the second side of the semiconductor substrate 106 from a second width 804 to a third width 904.

[0057] In some embodiments, the formation process causes material to deposit at the edge of the temporary barrier layer 902. The temporary barrier layer 902 may be, or additionally comprise, for example, silicon dioxide, silicon nitride, titanium nitride, or any combination thereof. In some embodiments, the temporary barrier layer 902 may comprise a different material than the barrier layer 112. Using different materials for the barrier layer 112 and the temporary barrier layer 902 improves etching resistance (e.g., by providing different etching selectivity to the etchant). By improving etching resistance, the different materials of the barrier layer 112 and the temporary barrier layer 902 can increase the subsequent formation of a second via (e.g., Figure 10 The second hole 1002 is recessed from the sidewall of the semiconductor substrate 106. In other embodiments, the temporary barrier layer 902 may contain the same material as the barrier layer 112.

[0058] like Figure 10 As shown in the cross-sectional view 1000, a second hole 1002 is etched in the temporary barrier layer 902, the insulating structure 110, and the dielectric structure 102 by a second etching process to define an opening 103 extending through the semiconductor substrate 106 to the conductive structure 104. The second etching process exposes the temporary barrier layer 902, the insulating structure 110, and the dielectric structure 102 to a second etchant 1004. Because the barrier layer 112 and the temporary barrier layer 902 overhang over a portion of the first hole 602, the barrier layer 112 and the temporary barrier layer 902 reduce the amount of second etchant 1004 reaching the outer wall of the temporary barrier layer 902, thereby creating a second hole 1002 that recedes from the sidewall of the temporary barrier layer 902. In some embodiments, the overhang of the barrier layer 112 and the temporary barrier layer 902 also prevents damage to the sidewall of the insulating structure 110, thereby improving the interaction between the semiconductor substrate 106 and the subsequently formed TSV (e.g., Figure 14 Electrical isolation between TSV 108 in the middle.

[0059] In some embodiments, the second etchant 1004 may remove a temporary barrier layer 902 from above a second side 106b of the semiconductor substrate 106, while simultaneously causing the temporary barrier layer 902 along the sidewalls of the semiconductor substrate 106 to define a first via 602. In some embodiments, the second etchant 1004 may include a dry etchant (e.g., a plasma etchant, an ion bombardment etchant, or a similar etchant). In some embodiments, the second via 1002 extends into the conductive structure 104. The second etching process causes the insulating structure 110 to have a horizontally extending surface surrounding the second via 1002.

[0060] like Figure 11As shown in the cross-sectional view 1100, the remaining portion of the temporary barrier layer 902 is removed by a removal process. The removal process may be, or may additionally include, for example, a wet etching process. In various embodiments, the wet etching process may utilize a wet etchant including hydrofluoric acid (HF), potassium hydroxide (KOH), alkaline wet etchants, or the like. In some embodiments, the wet etchant may reduce the size of the protrusions in the barrier layer 112, thereby increasing the width of the opening 103 along the second side 106b of the semiconductor substrate 106 and reducing the subsequently formed TSV (e.g., Figure 13 The resistor in the TSV 108).

[0061] like Figure 12 As shown in the cross-sectional view 1200, a diffusion barrier layer 114 is formed along the inner sidewall of the barrier layer 112, the inner sidewall of the insulating structure 110, the dielectric structure 102, and the inner sidewall of the insulating structure 110, and over the exposed portion of the conductive structure 104. The diffusion barrier layer 114 may be, or may additionally comprise, for example, tantalum, titanium, titanium nitride, tantalum nitride, some other suitable metal(s), or some other suitable conductive material(s). The diffusion barrier layer 114 may be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, or some other suitable formation process.

[0062] like Figure 13 As shown in the cross-sectional view 1300, TSV 108 is formed within the first hole 602 and the second hole 1002 by a forming process. TSV 108 is thinned to the top surface of the barrier layer 112 by a thinning process. The thinning process can be, or may additionally include, for example, chemical-mechanical planarization, polishing, etching, or some other suitable thinning process. In some embodiments, TSV 108 is laterally separated from the insulating structure 110, the barrier layer 112, and the dielectric structure 102 by the diffusion barrier layer 114. TSV 108 can be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, and / or plating processes (e.g., electroplating, electroless plating).

[0063] about Figure 14 The flowchart 1400 shows some embodiments of a method for forming an IC including a TSV structure.

[0064] Although the disclosed flowchart 1400 is shown and illustrated herein as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or illustrated herein. Furthermore, not all actions shown may be necessary for implementing one or more aspects or embodiments described herein. Additionally, one or more actions illustrated herein may be performed in one or more separate actions and / or phases.

[0065] At action 1402, a conductive structure is formed within the dielectric structure along the first side of the semiconductor substrate. Figure 5 A cross-sectional view 500 is shown, corresponding to some embodiments of action 1402.

[0066] At action 1404, a first hole extending into the dielectric structure is etched in the semiconductor substrate. Figure 6 A cross-sectional view 600 is shown, corresponding to some embodiments of action 1404.

[0067] At action 1406, an insulating structure is formed above the second side of the substrate, thereby lining the inner sidewalls of the substrate and the exposed portions of the dielectric structure. Figure 7 A cross-sectional view 700 is shown, corresponding to some embodiments of action 1406.

[0068] At action 1408, a barrier layer is formed above the insulating structure and along the inner wall of the insulating structure. Figure 8 A cross-sectional view 800 is shown, corresponding to some embodiments of action 1408.

[0069] At action 1410, a temporary barrier layer is formed above the barrier layer and along the inner wall of the insulation structure. Figure 9 A cross-sectional view 900 is shown, corresponding to some embodiments of action 1410.

[0070] At action 1412, a second hole is etched in the dielectric structure based on the barrier layer and the temporary barrier layer. The second hole extends from the top surface of the dielectric structure to the conductive structure. Figure 10 A cross-sectional view 1000 is shown, corresponding to some embodiments of action 1412.

[0071] At action 1414, remove the temporary blocking layer. Figure 11 A cross-sectional view 1100 is shown, corresponding to some embodiments of action 1414.

[0072] At action 1416, a substrate through-hole (TSV) is formed in the first trench and the second trench, such that the TSV is electrically coupled to the conductive structure. Figures 12 to 13Cross-sectional views 1200 to 1300 are shown for some embodiments corresponding to action 1416.

[0073] Therefore, in some embodiments, this disclosure relates to an integrated chip (IC) comprising: a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate; an insulating structure disposed along an inner sidewall of the semiconductor substrate, the inner sidewall of the semiconductor substrate extending through the semiconductor substrate; a barrier layer disposed along the inner sidewall of the insulating structure; and a substrate through-hole (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally extending surface of the insulating structure projecting outward from the inner sidewall of the insulating structure, the second portion extending from the first portion to the conductive structure, and the maximum width of the second portion being less than the maximum width of the first portion.

[0074] In some embodiments, the dielectric structure includes an inner sidewall at a first angle relative to the first side of the semiconductor substrate. In some embodiments, the first portion of the substrate via directly covers the horizontally extending surface of the insulating structure. In some embodiments, the barrier layer has a bottom surface perpendicularly separated from the horizontally extending surface of the insulating structure by the first portion of the substrate via. In some embodiments, the horizontally extending surface of the insulating structure has a width between approximately 70 nanometers and approximately 90 nanometers. In some embodiments, the substrate via further includes a third portion separated from the second portion by the first portion; and wherein the maximum width of the third portion is less than the maximum width of the first portion. In some embodiments, the bottom surface of the barrier layer is directly above the upper surface of the substrate via. In some embodiments, the first portion of the substrate via has a sidewall at a first angle relative to the first side of the semiconductor substrate, and the second portion of the substrate via includes a sidewall at a second angle relative to the first side of the semiconductor substrate, the first angle being different from the second angle. In some embodiments, the barrier layer has a height less than that of the insulating structure.

[0075] In other embodiments, this disclosure relates to a method for forming an integrated circuit (IC), the method comprising: forming a conductive structure within a dielectric structure along a first side of a semiconductor substrate; performing a first etching process on a second side of the semiconductor substrate to form a sidewall of the semiconductor substrate, the sidewall defining a first via extending into the dielectric structure; forming an insulating structure over the second side of the semiconductor substrate and along the sidewall of the semiconductor substrate; performing a second etching process on the dielectric structure to form a sidewall of the dielectric structure, the sidewall defining a second via extending into the conductive structure, the maximum width of the second via being less than the maximum width of the first via; and forming a substrate through-hole (TSV) within the first via and the second via.

[0076] In some embodiments, the method further includes forming a barrier layer over the insulating structure and along the inner sidewall of the insulating structure prior to the second etching process. In some embodiments, the method further includes forming a temporary barrier layer along the sidewall of the barrier layer and the inner sidewall of the insulating structure prior to the second etching process. In some embodiments, the method further includes removing the temporary barrier layer from the sidewall of the barrier layer and the inner sidewall of the insulating structure prior to forming the substrate via. In some embodiments, after performing the second etching process, the barrier layer, the insulating structure, and the dielectric structure share a common inner sidewall. In some embodiments, the horizontally extending surface of the insulating structure is laterally located between the second via and the sidewall of the barrier layer. In some embodiments, the barrier layer has a thickness that varies between the top surface of the insulating structure and the horizontally extending surface of the insulating structure.

[0077] In other embodiments, this disclosure relates to a method of forming an integrated chip (IC), the method comprising: forming a conductive structure within a dielectric structure along a first side of a semiconductor substrate; performing a first etching process on a second side of the semiconductor substrate to form a sidewall of the semiconductor substrate, the sidewall defining a first via extending into the dielectric structure; forming an insulating structure over the second side of the semiconductor substrate and along the sidewall of the semiconductor substrate; forming a barrier layer along the sidewall of a dielectric layer; forming a temporary barrier layer along the sidewall of the barrier layer and the sidewall of the insulating structure; performing a second etching process on the dielectric structure to form a sidewall of the dielectric structure, the sidewall defining a second via extending into the conductive structure; and forming a conductive material within the first via and the second via.

[0078] In some embodiments, the method further includes removing the temporary barrier layer after the second etching process. In some embodiments, the method further includes stating that the temporary barrier layer comprises titanium nitride. In some embodiments, the second etching process removes a portion of the temporary barrier layer, and after the second etching process is completed, the temporary barrier layer remains along the sidewall of the insulating structure.

[0079] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: A conductive structure is disposed within a dielectric structure on the first side of a semiconductor substrate; An insulating structure includes a main body portion and a horizontal protrusion portion, the main body portion being disposed along an inner sidewall of a semiconductor substrate and extending to cover a second side of the semiconductor substrate, the horizontal protrusion portion being embedded in the semiconductor substrate near a first side of the semiconductor substrate and laterally protruding from the inner sidewall of the main body portion, wherein the inner sidewall of the semiconductor substrate extends through the semiconductor substrate. A barrier layer is disposed along the inner sidewall of the insulating structure and extends to cover the second side of the semiconductor substrate; as well as A substrate via includes a first portion and a second portion, wherein the first portion extends along the inner sidewall of the insulating structure and covers the horizontally extending surface of the horizontally protruding portion of the insulating structure, and wherein the second portion extends from the first portion to the conductive structure, and the maximum width of the second portion is less than the maximum width of the first portion. The barrier layer has a droop that protrudes from the sidewall of the barrier layer toward the substrate perforation. The substrate via further includes a third portion, which is separated from the second portion by the first portion, and the minimum width of the portion of the third portion adjacent to the overhang of the barrier layer is greater than the minimum width of the second portion.

2. The integrated chip of claim 1, wherein the dielectric structure includes an inner sidewall at a first angle relative to the first side of the semiconductor substrate.

3. The integrated chip according to claim 1, wherein the integrated chip further comprises: A photodiode is disposed within the semiconductor substrate; A color filter is disposed on the blocking layer and corresponds to the photodiode; as well as A microlens is disposed on the color filter.

4. The integrated chip of claim 1, wherein the barrier layer has a bottom surface that is perpendicularly separated from the horizontally extending surface of the insulating structure through the first portion of the substrate via.

5. The integrated chip of claim 1, wherein the horizontally extending surface of the insulating structure has a width between 70 nanometers and 90 nanometers.

6. The integrated chip according to claim 1, The third portion of the substrate via includes a first sub-portion and a second sub-portion; The maximum width of the third part is less than the maximum width of the first part; and The first sub-part is adjacent to the overhang and separated from the first part by the second sub-part, and the maximum width of the first sub-part is less than the maximum width of the second sub-part.

7. The integrated chip of claim 6, wherein the bottom surface of the barrier layer is directly above the upper surface of the substrate via.

8. The integrated chip of claim 1, wherein the first portion of the substrate via has a sidewall at a first angle relative to the first side of the semiconductor substrate, and the second portion of the substrate via includes a sidewall at a second angle relative to the first side of the semiconductor substrate, the first angle being different from the second angle.

9. The integrated chip according to claim 1, wherein the barrier layer has a height less than that of the insulating structure.

10. A method for constructing an integrated circuit, comprising: A conductive structure is formed within the dielectric structure on the first side of the semiconductor substrate; A first etching process is performed on a second side of the semiconductor substrate to form a sidewall of the semiconductor substrate, the sidewall defining a first hole extending into the dielectric structure; An insulating structure is formed above the second side of the semiconductor substrate and along the sidewall of the semiconductor substrate; A barrier layer is formed above the insulating structure and along the inner sidewall of the insulating structure; A temporary barrier layer is formed along the sidewall of the barrier layer and the inner sidewall of the insulating structure, wherein the barrier layer and the temporary barrier layer have overhangs that protrude from the sidewall of the barrier layer and hang over a portion of the first hole; A second etching process is performed on the temporary barrier layer, the insulating structure, and the dielectric structure to form insulating sidewalls of the insulating structure and dielectric sidewalls of the dielectric structure. The insulating sidewalls are exposed by the temporary barrier layer and together with the dielectric sidewalls define a second hole extending into the conductive structure, wherein the maximum width of the second hole is less than the maximum width of the first hole. Substrate vias are formed in the first and second holes, wherein the overhang of the barrier layer protrudes from the sidewall of the barrier layer toward the substrate via.

11. The method of claim 10, wherein: The barrier layer is formed before the second etching process.

12. The method of claim 10, further comprising: Before forming the substrate vias, the temporary barrier layer is removed from the sidewalls of the barrier layer and the inner sidewalls of the insulating structure.

13. The method of claim 10, wherein after performing the second etching process, the barrier layer, the insulating structure, and the dielectric structure share a common inner sidewall.

14. The method of claim 13, wherein the horizontally extending surface of the insulating structure is laterally located between the second hole and the sidewall of the barrier layer.

15. The method of claim 11, wherein the barrier layer has a thickness that varies between the top surface of the insulating structure and the horizontally extending surface of the insulating structure.

16. A method for forming an integrated chip, comprising: An interconnect structure is formed within the dielectric structure on the first side of the semiconductor substrate; A photodiode is formed within the semiconductor substrate; A first etching process is performed on a second side of the semiconductor substrate to form a sidewall of the semiconductor substrate, the sidewall defining a first hole extending into the dielectric structure, and the first hole being laterally separated from the photodiode; An insulating structure is formed above the second side of the semiconductor substrate and along the sidewall of the semiconductor substrate; A barrier layer is formed above the insulating structure and along the sidewall of the insulating structure; A temporary barrier layer is formed along the sidewall of the barrier layer and the sidewall of the insulation structure, wherein the barrier layer and the temporary barrier layer have overhangs that protrude from the sidewall of the barrier layer and hang over a portion of the first hole; A second etching process is performed on the temporary barrier layer, the insulating structure, and the dielectric structure to form insulating sidewalls of the insulating structure and dielectric sidewalls of the dielectric structure, the insulating sidewalls being exposed by the temporary barrier layer and together with the dielectric sidewalls defining a second hole extending into the interconnect structure; Conductive material is formed in the first hole and the second hole, wherein the overhang of the barrier layer protrudes from the sidewall of the barrier layer toward the conductive material; A color filter is formed on the barrier layer to correspond to the photodiode; as well as Microlenses are formed on the color filter.

17. The method of claim 16, further comprising: The temporary barrier layer is removed after the second etching process.

18. The method of claim 17, further comprising: The temporary barrier layer contains titanium nitride.

19. The method of claim 16, wherein the second etching process removes a portion of the temporary barrier layer, and after the second etching process is completed, the temporary barrier layer remains along the sidewall of the insulating structure.

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