半导体存储装置
By setting notches on the side of semiconductor chips and optimizing wiring configuration, the problem of high integration in memory chip stack-up structures is solved, achieving higher integration and electrical characteristic uniformity, and improving the reliability and manufacturing efficiency of semiconductor memory devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2021-08-11
- Publication Date
- 2026-07-17
AI Technical Summary
In the existing technology, it is difficult to achieve high integration of the memory chip stacking structure of semiconductor memory devices, resulting in uneven wiring length and inconsistent electrical characteristics, which affects reliability and manufacturing efficiency.
By creating notches on the sides of semiconductor chips and optimizing the configuration of leads and pads to avoid contact between leads and chips, a layered structure without intermediaries is adopted to achieve tight stacking and uniform electrical connection of multiple chips.
It improves the reliability and manufacturing efficiency of semiconductor memory devices, achieves higher integration and electrical characteristic uniformity, reduces wiring length non-uniformity, and enhances product design flexibility.
Smart Images
Figure CN114267646B_ABST