Semiconductor package structure

Abstract

The semiconductor package structure provided by the present disclosure maintains signal lines on the substrate and designs power / ground lines on the redistribution layer (RDL) in the circuit design between the RDL and the substrate. Compared with the conventional fan-out substrate (FOSub) structure in which part of the signal lines are designed on the RDL with a smaller line width than the substrate, the present disclosure maintains the signal lines on the substrate with a larger line width than the RDL to maintain the high-speed signal layout, and there is no signal transmission loss, so the integrity of the signal transmission can be maintained.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures. Background Technology

[0002] like Figure 1 In the conventional fan-out substrate (FOSub) structure shown, the wiring design between the redistribution layer 2 (RDL) and the substrate 1 typically places signal lines on the redistribution layer 2 and power / ground lines on the substrate 1. However, when a signal is transmitted from the substrate 1 to the redistribution layer 2, the line width of the redistribution layer 2 is smaller than that of the substrate 1, resulting in significant signal transmission loss, which is detrimental to high-speed signal transmission. Summary of the Invention

[0003] This disclosure provides a semiconductor packaging structure, including:

[0004] The first line structure includes signal lines;

[0005] The second line structure includes a power / ground line, the second line structure is disposed on the first line structure, and the second line structure includes a redistribution layer.

[0006] Electronic components are mounted on the second circuit structure;

[0007] In some alternative implementations, the line density of the first line structure is greater than the line density of the second line structure.

[0008] In some alternative implementations, the thickness of the second circuit structure is less than the thickness of the first circuit structure.

[0009] In some alternative implementations, the linewidth of the second line structure is greater than the thickness of the second line structure.

[0010] In some optional implementations, the line width of some lines in the second line structure is greater than or equal to the line width of the first line structure.

[0011] In some alternative implementations, the second circuit structure includes a chip bonding region, and the linewidth of the lines located outside the chip bonding region in the second circuit structure is greater than the linewidth of the first circuit structure.

[0012] In some alternative implementations, the external wiring of the chip bonding area is the power / ground wiring.

[0013] In some alternative implementations, a line in the second circuit structure has a linewidth of a different size, with the linewidth being smaller the closer it is to the chip bonding region.

[0014] In some alternative implementations, the power / grounding line is in a power / grounding plane.

[0015] In some alternative implementations, the electrical connection path between the first circuit structure and the second circuit structure is in the vertical direction.

[0016] In some alternative implementations, the first circuit structure is electrically connected to the second circuit structure via a via.

[0017] In some alternative implementations, the electronic component includes active and passive components.

[0018] In some alternative implementations, the passive element is a capacitor.

[0019] In some alternative implementations, it also includes:

[0020] A molding layer is disposed on the second circuit structure and covers the electronic components.

[0021] The semiconductor packaging structure disclosed herein includes a core substrate in the circuit design between the redistribution layer (RDL) and the substrate. Signal lines are retained on the core substrate, while power / ground lines are designed on the redistribution layer. Compared to the conventional fan-out substrate (FOSub) structure, which places some signal lines on the redistribution layer with a linewidth smaller than the substrate, this disclosure retains signal lines on the substrate with a linewidth larger than the redistribution layer to maintain high-speed signal layout without signal transmission loss, thus preserving signal transmission integrity. Attached Figure Description

[0022] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0023] Figure 1 It is a circuit design based on a traditional fan-out substrate structure;

[0024] Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;

[0025] Figure 3 This is a top view of the power supply line structure.

[0026] Figure 4 This is a top view of the grounding line structure.

[0027] Figure 5 This is a top view of the signal line structure.

[0028] Symbol explanation:

[0029] 1-First circuit structure, 11-Signal line, 2-Second circuit structure, 21-Power supply line, 22-Chip bonding area, 23-Ground line, 24-Planet, 3-Electronic component, 31-Active component, 32-Passive component, 4-Molding layer, 5-Substrate, 6-Rewiring layer. Detailed Implementation

[0030] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0031] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0032] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0033] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0034] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 2 The semiconductor package structure shown includes a first circuit structure 1, a second circuit structure 2, and an electronic component 3. The second circuit structure 2 can be disposed on the first circuit structure 1. The electronic component 3 can be disposed on the second circuit structure 2.

[0036] In this embodiment, the first line structure 1 may include signal lines for transmitting signals, such as high-speed signal lines. The second line structure 2 may include power / ground lines. The power / ground lines can serve as a reference ground plane for the high-speed signal lines, thereby achieving the effects of impedance control and ensuring signal integrity. In one embodiment, the second line structure 2 may not include high-speed line signals. By retaining the signal lines in the first line structure 1 and designing the power / ground lines on the second line structure 2, this semiconductor packaging structure can reduce signal transmission loss during signal transmission between the first line structure 1 and the second line structure 2 compared to the circuit design of a conventional fan-out substrate (FOSub) structure.

[0037] In this embodiment, the signal lines and power / ground lines can be made of conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0038] In one embodiment, the line density of the first line structure 1 can be greater than the line density of the second line structure 2. The linewidth of some lines in the second line structure 2 can be greater than or equal to the linewidth of the first line structure 1. The second line structure 2 may include a redistribution layer (RDL). The first line structure 1 may include a substrate. The substrate includes a core substrate, specifically, as follows:Figure 3 The power line 21 in the second circuit structure 2 shown Figure 4 The grounding line 23 in the second line structure 2 shown and Figure 5 As shown in the first circuit structure 1, the line width of signal line 11 in the second circuit structure 2, excluding the chip bonding area 22, is significantly greater than or equal to the line width of signal line 11 in the first circuit structure 1. The number of lines in the first circuit structure 1 is significantly greater than or equal to the number of lines in the second circuit structure; therefore, the line density of the first circuit structure 1 can be greater than the line density of the second circuit structure 2.

[0039] In one embodiment, such as Figure 3 As shown, the second circuit structure 2 may include a chip bonding area 22. The line width of the lines in the second circuit structure 2 located outside the chip bonding area 22 may be greater than the line width of the first circuit structure 1. A single line in the second circuit structure 2 may have different line widths, with the line width decreasing as it approaches the chip bonding area 22. Some low-speed signal lines may be arranged on the chip bonding area 22.

[0040] In one embodiment, the linewidth of the second circuit structure 2 can be greater than the thickness of the second circuit structure 2. Specifically, viewed from a top view, as... Figure 3 As shown, the power line 21 can be in the form of a strip. For example... Figure 4 As shown, the grounding line 23 can be in the form of a strip or a plane 24. From Figure 4 As can be seen from the planar structure design of the second line structure 2 shown, the line width of the second line structure 2 can be greater than the thickness of the second line structure 2. The thickness of the second line structure 2 is small, which can result in higher capacitance efficiency, effectively improve the power supply capability of the electronic component 3, and maintain signal transmission efficiency.

[0041] In this embodiment, electronic component 3 may include active components 31 and passive components 32. Electronic component 3 may be connected to a power supply / grounding line. Active components 31 may be, for example, various chips (power management chips, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips). Passive components 32 may be, for example, capacitors, resistors, inductors, etc.

[0042] In one embodiment, the passive component 32 can be at least one capacitor. The capacitor is, for example, a decoupling capacitor. A decoupling capacitor can provide a more stable power supply while also reducing noise coupled from the component to the power supply. The decoupling capacitor can be placed as close as possible to the active component 31 to increase its effectiveness.

[0043] In one embodiment, the power / ground lines in the second circuit structure 2 are designed directly below the electronic components 3. Compared to the power / ground lines being designed in the first circuit structure 1, this can shorten the power supply path, improve power supply efficiency, and maintain a more stable signal transmission.

[0044] In one embodiment, the electrical connection path between the first circuit structure 1 and the second circuit structure 2 can be vertical. This can be achieved, for example, by providing vias in the first circuit structure 1 / second circuit structure 2. Thus, signals can flow vertically from the electronic component 3 through the second circuit structure 2 to the first circuit structure 1. Similarly, power can flow vertically from the first circuit structure 1 through the second circuit structure 2 to the electronic component 3.

[0045] In one embodiment, the semiconductor package structure may further include a molding layer 4. The molding layer 4 may encapsulate the electronic component 3. The molding layer 4 may be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0046] The semiconductor package structure disclosed herein retains the signal lines on the first line structure 1 while designing the power / ground lines on the second line structure 2. Compared to the circuit design of a conventional fan-out substrate (FOSub) structure, this semiconductor package structure can reduce signal transmission loss during signal transmission between the first line structure 1 and the second line structure 2, thus maintaining the integrity of signal transmission.

[0047] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package structure, comprising: The first circuit structure includes a substrate and signal lines, wherein the substrate includes a core substrate and the signal lines include high-speed signal lines. The second line structure includes a power / ground line, the second line structure is disposed on the first line structure, and the second line structure includes a redistribution layer. The linewidth of the second line structure is greater than the thickness of the second line structure; The power supply / grounding line serves as the reference ground plane for the high-speed signal line; Electronic components are mounted on the second circuit structure.

2. The semiconductor packaging structure according to claim 1, wherein, The line density of the first line structure is greater than the line density of the second line structure.

3. The semiconductor packaging structure according to claim 1, wherein, The thickness of the second circuit structure is less than the thickness of the first circuit structure.

4. The semiconductor packaging structure according to claim 1, wherein, In the second line structure, the line width of some lines is greater than or equal to the line width of the first line structure.

5. The semiconductor packaging structure according to claim 4, wherein, The second circuit structure includes a chip bonding area, and the linewidth of the lines located outside the chip bonding area in the second circuit structure is greater than the linewidth of the first circuit structure.

6. The semiconductor packaging structure according to claim 5, wherein, The external wiring of the chip bonding area is the power / ground wiring.

7. The semiconductor packaging structure according to claim 5, wherein, One line of the second circuit structure has a linewidth of different dimensions, and the linewidth of one line of the second circuit structure is smaller the closer it is to the chip bonding area.

8. The semiconductor packaging structure according to claim 2 or 6, wherein, The power supply / grounding line is in the power supply / grounding plane.

9. The semiconductor packaging structure according to claim 1, wherein, The electrical connection path between the first circuit structure and the second circuit structure is in the vertical direction.

10. The semiconductor packaging structure according to claim 9, wherein, The first circuit structure is electrically connected to the second circuit structure through a via.

11. The semiconductor packaging structure according to claim 1, wherein, The electronic components include active components and passive components.

12. The semiconductor packaging structure according to claim 11, wherein, The passive component is a capacitor.

13. The semiconductor packaging structure according to claim 1, further comprising: A molding layer is disposed on the second circuit structure and covers the electronic components.

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