Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a gate line extending in a first direction parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed under the gate line and including a first-conductivity-type impurity; a second active region disposed apart from the first active region in the first direction, including a second channel region disposed under the gate line, and including the first-conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one of the plurality of metal wirings is directly electrically connected to the first active region, no metal wiring is electrically connected to the second active region at the first height level, and at least one of the plurality of metal wirings is connected to receive a signal applied to the gate line.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0118842, filed on September 16, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor device. Background Technology

[0003] Semiconductor devices can be classified as semiconductor memory devices for storing data, semiconductor logic devices for operating and processing data, or hybrid semiconductor devices that include both memory and logic elements. Typically, semiconductor devices can be manufactured to include transistors and antenna devices within a predetermined region of a semiconductor substrate. During the manufacturing process of a semiconductor device, the antenna device can naturally emit plasma ions into the semiconductor substrate to protect the transistors from plasma damage. However, typically, additional regions are used to accommodate the antenna devices, depending on variations in transistor thickness, to improve the operating speed of the semiconductor device. Therefore, there are issues with increased semiconductor device size and reduced freedom of metal wiring. Summary of the Invention

[0004] One aspect of the present invention is to provide an integrated semiconductor device that utilizes empty space to increase the channel region without setting up antenna devices.

[0005] According to one aspect of the present invention, a semiconductor device includes: a gate line extending along a first direction parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity type impurity; a second active region disposed separately from the first active region in a first direction, including a second channel region disposed below the gate line and including a first conductivity type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one of the plurality of metal wirings is directly electrically connected to the first active region, the plurality of metal wirings at the first height level are electrically separated from the second active region, and at least one of the plurality of metal wirings is connected to receive a signal applied to the gate line.

[0006] According to one aspect of the present invention, a semiconductor device includes: a plurality of gate lines, including a plurality of first gate lines extending along a first direction parallel to an upper surface of a semiconductor substrate and a second gate line extending along the first direction and having a length different from that of each of the plurality of first gate lines in the first direction; a first active region including a plurality of first channel regions disposed below the plurality of gate lines and including impurities of a first conductivity type; a second active region disposed separately from the first active region in the first direction, including a second channel region disposed below the second gate lines and including impurities of the first conductivity type; and a third active region including a plurality of third channel regions disposed below the plurality of gate lines and including impurities of a second conductivity type, wherein the structure of the second gate line above each of the plurality of first channel regions is different from the structure of the second gate line above the second channel region.

[0007] According to one aspect of the present invention, a semiconductor device includes: a gate line extending along a first direction parallel to an upper surface of a semiconductor substrate; a plurality of active regions including a plurality of channel regions below the gate line, the plurality of channel regions including all channel regions of the semiconductor device, the plurality of channel regions being configured to be separated from each other in the first direction; a plurality of metal wirings disposed at a first height level for electrically connecting to the gate line and a group of active regions including at least two of the plurality of active regions, the plurality of metal wirings including all metal wirings at the first height level of the semiconductor device; and a plurality of contacts connected to the group of the plurality of active regions. The semiconductor device is arranged such that the ratio of the total area of ​​the plurality of metal wirings to the total area of ​​the plurality of channel regions is a value of 0.4 or greater and 400 or less. Attached Figure Description

[0008] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0009] Figure 1 It is a layout diagram of a semiconductor device including antenna components.

[0010] Figure 2 This is a layout diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 3 This is a schematic circuit diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0012] Figures 4 to 6 This is a cross-sectional view illustrating an embodiment of a semiconductor device according to the present invention.

[0013] Figures 7 to 21 This is a layout diagram of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 22 and Figure 23 This is a cross-sectional view illustrating an embodiment of a semiconductor device according to the present invention.

[0015] Figures 24 to 28 This is a layout diagram of a semiconductor device according to an embodiment of the present invention.

[0016] Figure 29 and Figure 30 This is a cross-sectional view illustrating an embodiment of a semiconductor device according to the present invention.

[0017] Figure 31 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention. Detailed Implementation

[0018] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0019] Figure 1 It is a layout diagram of a semiconductor device including antenna components.

[0020] Typically, a semiconductor device may include transistors, lower metal wirings, and other elements arranged on a semiconductor substrate along a first direction (e.g., the Y direction) and a second direction (e.g., the X direction). Depending on the embodiment, the layout of the layers formed on the semiconductor substrate can be provided in various ways. For example, in one example layout, three (3) lower metal wirings spaced apart in the second direction may be positioned above one (1) transistor (e.g., in the Z direction). For example, one (1) of the three (3) lower metal wirings may be connected to an antenna device. The antenna device can naturally emit plasma ions accumulated during the process of manufacturing the semiconductor device to form various patterns into the semiconductor substrate to protect the transistor from plasma damage. For example, the antenna device may be an antenna diode.

[0021] To improve the performance of a semiconductor chip comprising multiple semiconductor devices, each performing various operations, it is important to reduce the size of the components included in each of the multiple semiconductor devices or to change their layout to reduce the size of the semiconductor chip. However, the size of the components included in a semiconductor device directly affects the performance of the semiconductor device, thus there are limitations to reducing its size. For example, recently, to increase operating speed and improve the performance of the semiconductor device, semiconductor devices comprising transistors that are thinner than conventional transistors in a second direction can be used; therefore, the arrangement of antenna devices may be problematic.

[0022] Reference Figure 1The semiconductor device 1, including the antenna device AD, may include two (2) lower metal wirings ML spaced apart in a second direction above a transistor (1). For example, in the semiconductor device 1 using transistors that are thinner in the second direction than conventional transistors, unlike conventional semiconductor devices, the lower metal wirings ML may not be disposed above the channel regions CH1 and CH3 of the transistor, thus requiring additional regions. Due to the arrangement of the antenna device AD ​​using additional regions, including Figure 1 The semiconductor chip size of the semiconductor device 1 shown increases, reducing the freedom of arrangement of the lower metal wiring ML. Furthermore, when using transistors thinner than conventional transistors, the lower metal wiring ML can be positioned above the channel regions CH1 and CH3 of the transistor. In this case, the performance degradation of the semiconductor device 1 due to the reduced thickness of the lower metal wiring ML may be more problematic than the increased semiconductor chip size caused by the arrangement of the antenna device AD.

[0023] Reference Figure 1 A semiconductor device 1, described as a general semiconductor device including an antenna device AD, may include a gate line GL, a first active region ACT1, a third active region ACT3, multiple lower metal wirings ML (shown as having the same shade as the single line labeled ML) arranged in the X and Y directions, and multiple contacts CNTs. For example, the first active region ACT1 and the third active region ACT3, which are in a continuous pattern, may extend in a direction intersecting the gate line GL. The multiple contacts CNTs may electrically connect the gate line GL and / or the active regions ACT1 and ACT3 to the multiple lower metal wirings ML.

[0024] Semiconductor device 1 can provide multiple transistors from gate line GL and active regions ACT1 and ACT3. As described above, the lower metal wiring ML may not be disposed above the channel regions CH1 and CH3 of each of the multiple transistors. Therefore, an antenna device AD ​​for protecting the transistors from plasma damage can be disposed on a laterally disposed surface of semiconductor device 1. The antenna device AD ​​can be electrically connected to semiconductor device 1 via the lower metal wiring ML and contact CNT. For example, semiconductor device 1 may include a first region A1 in which multiple transistors are disposed and a second region A2 in which the antenna device AD ​​is disposed. The second region A2 may be an additional region for the use of the antenna device AD. Therefore, the size of the semiconductor chip increases, and the degree of freedom in arranging the lower metal wiring ML decreases. Ordinal numbers such as "first," "second," "third," etc., can simply be used as labels for certain elements, steps, etc., to distinguish these elements, steps, etc. from each other. Terms such as "first," "second," etc., not used in the specification, may still be referred to as "first" or "second" in the claims. In addition, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0025] exist Figure 1 In the general semiconductor device 1 shown, each gate line GL may extend along a first direction (e.g., the Y direction). Although in Figure 1 The diagram shows only one (1) gate line GL (e.g., shown as having an insulating gap between a first portion and a second portion of the gate line GL), but a typical semiconductor device 1 may include multiple gate lines. Additionally, Figure 1 The characteristics of the semiconductor device 1 shown can be present in at least a portion of multiple gate lines. The multiple gate lines can have different shapes, and, as needed, a group of gate lines can be dummy gate lines arranged to be separate from and / or arranged together with other peripheral semiconductor devices. Depending on the process, the thickness, arrangement, and shape of the gate lines GL are not limited to... Figure 1 The semiconductor device 1 shown is shown.

[0026] exist Figure 1 In the semiconductor device 1 shown, at least a portion of the active regions ACT1 and ACT3 can be configured to overlap with the gate line GL. For example, the active regions ACT1 and ACT3 can be configured to be spaced apart in a first direction along which the gate line GL extends. Transistors can be respectively disposed based on the regions of the active regions ACT1 and ACT3 overlapping with the gate line GL. For example, the regions of the active regions ACT1 and ACT3 overlapping with the gate line GL may include the channel regions CH1 and CH3 of the transistor. Figure 1The semiconductor device 1 shown may include a gate line GL and two (2) active regions ACT1 and ACT3, and may thereby provide two (2) transistors. However, this is merely illustrative and the present disclosure is not limited thereto.

[0027] Multiple lower metal wirings ML (also described as multiple first horizontal metal wirings ML) may be wirings disposed at a first height level above the active regions ACT1 and ACT3 and the gate line GL (e.g., the horizontal metal wiring closest to the gate line GL in the Z direction) and may extend longitudinally in the Y direction. An object, layer, or part of an object or layer described as extending "longitudinally" in a particular direction has a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width. However, according to embodiments, the directions in which the multiple lower metal wirings ML extend may be different. For example, at least a portion of the lower metal wirings ML connected to the antenna device AD ​​may extend longitudinally in a second direction perpendicular to the first direction (e.g., both the first and second directions are horizontal directions on the same plane). The power line PL may be disposed at a second height level greater than the first height level on which the multiple lower metal wirings ML are disposed. At least a portion of the multiple lower metal wirings ML may be connected to the power line PL via contacts. However, this is merely illustrative, and the present disclosure is not limited thereto.

[0028] Power lines PL can be directed to... Figure 1 The semiconductor device 1 shown is supplied with different first and second voltages and can be electrically connected to source / drain regions formed on active regions ACT1 and ACT3 via multiple contacts CNTs. For example, a high power line can supply the first voltage, and a low power line can supply a second voltage lower than the first voltage. For example, the first voltage can be a power supply voltage, and the second voltage can be ground voltage. However, this is merely illustrative, and the present disclosure is not limited thereto.

[0029] Figure 2 This is a layout diagram of a semiconductor device according to an embodiment of the present invention. Figure 3 This is a schematic circuit diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0030] Typically, the presence or absence of an antenna device can be determined based on the area of ​​the transistor's channel region and the area of ​​the metal wiring connected to it, thus preventing transistor damage due to plasma during semiconductor chip manufacturing. For example, according to antenna rules, an antenna device can be placed in a semiconductor device when the ratio of the total area of ​​the metal wiring to the total area of ​​the channel region is not within permissible limits. For instance, the ratio of the total area of ​​the metal wiring (e.g., the area occupied by the metal wiring, such as the area of ​​the top surface of the metal wiring) to the total area of ​​the channel region (e.g., from a plan view) can be defined as the antenna ratio (A / R). Antenna devices arranged according to antenna rules can emit accumulated plasma charge. The absence of an antenna device results in defects in the semiconductor device.

[0031] The sum of the areas included in the denominator and numerator of the antenna ratio can be calculated based on the electrical connection network. For example, assuming the process has progressed to the target layer for measuring the antenna ratio, the sum of the areas of the metal wiring can be calculated by summing the areas of the electrical connection network. For instance, if the layers have levels M0, M1, M2, etc., starting from the lowest level, then when the target layer for measuring the antenna ratio is at level M0, the sum of the areas of the metal wiring can be the sum of the areas of metal wiring at level M0 or smaller. When the target layer for measuring the antenna ratio is at level M1, the sum of the areas of the metal wiring can be the sum of the areas of metal wiring at levels M1 or smaller. In this case, metal wiring at level M0 can be included. However, the value used to calculate the sum of the areas of the metal wiring is not limited to the areas of the metal wiring arranged at each level, but can also include, in addition to the sum of the areas of the metal wiring, the areas of, for example, the areas of the contacts used to connect the metal wiring between the layers.

[0032] Figure 2 This shows that in order to solve including Figure 1 The diagram shows a semiconductor device 1 for the antenna device AD, which has a problem, and therefore provides an additional transistor instead of a semiconductor device 2 for the antenna device AD. (Refer to...) Figure 2 Compared to semiconductor device 1 which uses antenna device AD, semiconductor device 2 according to an embodiment of the present invention does not additionally use a second region A2. Additional transistors can be disposed in the empty space of the first region A1. Similar to... Figure 1The semiconductor device 1 shown, and the semiconductor device 2 according to an embodiment of the present invention, may include a gate line GL, a first active region ACT1, a third active region ACT3, multiple lower metal wirings ML, and multiple contacts CNT. Compared with semiconductor device 1, the semiconductor device 2 according to an embodiment of the present invention may be characterized in that: the length of the gate line GL may be different; it may also include a second active region ACT2 superimposed on the extended gate line GL; and as described above, a second region including antenna devices is not used. In the semiconductor device 2 according to an embodiment of the present invention, the multiple lower metal wirings ML may be disposed in a layer having a horizontal level M0, and the power lines PL may be disposed in a layer having a horizontal level M1.

[0033] Reference Figure 3 The semiconductor device 2 according to an embodiment of the present invention may include an inverter. The inverter may include one (1) PMOS transistor TR1 and one (1) NMOS transistor TR2, and transistors TR1 and TR2 may be arranged in series between a power supply voltage VDD and a ground voltage VSS. The gates of each of transistors TR1 and TR2 included in the inverter may be connected to each other to provide an input node IN. One of the source / drain regions of each of transistors TR1 and TR2 included in the inverter may be connected to each other to provide an output node OUT. The inverter can invert an input signal input to the input node IN and can output an inverted signal to the output node OUT. However, this is merely illustrative, and the present disclosure is not limited thereto. The semiconductor device 2 according to an embodiment of the present invention may include components for protecting the transistors from plasma damage.

[0034] Refer to together Figure 2 and Figure 3According to embodiments of the present invention, a semiconductor device 2 may include a first channel region CH1 superimposed with a gate line GL and a first active region ACT1, and a third channel region CH3 superimposed with a gate line GL and a third active region ACT3. The term "semiconductor device" can be used to describe individual semiconductor components (such as inverters or transistors), or more generally to describe an integrated circuit formed on a die and comprising multiple components. For example, the semiconductor device 2 may provide a plurality of first transistors and a plurality of third transistors, each comprising a first channel region CH1 and a third channel region CH3. For example, the plurality of first transistors and the plurality of third transistors may include general-purpose transistors relevant to the operation of the semiconductor device 2. For example, the plurality of first transistors may all be PMOS transistors TR1, and the plurality of third transistors may all be NMOS transistors TR2. In the process of manufacturing the semiconductor device 2, transistors may be damaged by plasma damage, and the semiconductor device 2 may include structures for preventing defects in the semiconductor chip on which the semiconductor device 2 is formed.

[0035] Semiconductor device 2 according to an embodiment of the present invention may use gate line GL and a second active region ACT2 while maintaining a lower metal wiring ML, the size of which may be difficult to adjust, to additionally provide a second channel region CH2. The additionally provided second channel region CH2 can increase the total area of ​​the channel regions and can reduce the antenna ratio between the total area of ​​the lower metal wiring ML and the total area of ​​the channel regions. For example, by reducing the antenna ratio, transistors can be protected from plasma damage without antenna devices. For example, in semiconductor device 2 according to an embodiment of the present invention, by adding the second channel region CH2, the antenna ratio can have a value of about 0.4 or greater and 400 or less (e.g., between 0.4 and 400, depending on whether only one level or multiple levels of metal wiring are used to calculate the ratio). However, this is merely illustrative, and the present disclosure is not limited thereto. The antenna ratio can vary depending on the area of ​​the further added second channel region CH2 and / or the layout of semiconductor device 2. It can be seen that semiconductor device 2 according to an embodiment of the present invention does not require antenna devices. Therefore, the size of the semiconductor chip can be reduced, and the degree of freedom in arranging the lower metal wiring ML can be improved.

[0036] In some embodiments, the second channel region CH2 is a region in which at least a portion of the gate line GL extending along a first direction overlaps with the second active region ACT2. The second active region ACT2 may be configured to be spaced apart from active regions ACT1 and ACT3 in the first direction, and may be located in an empty space of the first region A1. Within the active regions, the second active region ACT2 may be adjacent to the first active region ACT1 in the first direction. Therefore, with... Figure 1Unlike the semiconductor device 1 including the antenna device AD ​​shown, which requires a second region A2 to arrange the antenna device AD, the antenna device AD ​​can be improved without the need for an additional region to protect the transistor from plasma damage.

[0037] In the semiconductor device 2 according to an embodiment of the present invention, active regions ACT1 and ACT3 may include impurities formed in the semiconductor layer, each doped with a different conductivity type. For example, the first active region ACT1 may include impurities of a first conductivity type, and the third active region ACT3 may include impurities of a second conductivity type different from the first conductivity type impurities. The second active region ACT2 may include impurities of the same first conductivity type as its adjacent first active region ACT1. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type. However, this is merely illustrative, and the present disclosure is not limited thereto. Depending on the location of the second active region ACT2, the impurities included in the second active region ACT2 may have different conductivity types.

[0038] Similar to the first active region ACT1 and the third active region ACT3, source / drain regions can be formed on the added second active region ACT2. However, the source / drain regions formed on the second active region ACT2 can be floating and, for example, not connected to any wiring layer. For example, in one embodiment, electrical signals and power supply voltages or ground voltages are not applied to the source / drain regions formed in the second active region ACT2. For example, multiple lower metal wirings ML can be electrically isolated and insulated from the second active region ACT2. At least one of the multiple lower metal wirings ML can be directly electrically connected to the first active region ACT1. In addition, the semiconductor device 2 according to an embodiment of the present invention can apply a signal to the gate line GL through at least one of the multiple lower metal wirings ML. As used herein, components described as "electrically connected" are configured such that electrical signals can be transmitted from one component to another (although such electrical signals are attenuated in strength during their transmission and can be selectively transmitted). Furthermore, components with "direct electrical connections" share a common electrical node through electrical connections of one or more conductors (such as wiring, pads, internal wires, through-vias, etc.). Thus, components that are directly electrically connected do not include those that are electrically connected through active elements (such as transistors or diodes).

[0039] In a semiconductor device 2 according to an embodiment of the present invention, a second channel region CH2 added based on a second active region ACT2 can be the channel region of a second transistor. When the source / drain regions of the second active region ACT2 are floating, the second transistor can operate as a dummy transistor with a dummy active region (e.g., the second active region ACT2), and therefore does not transmit signals to or from other components. Thus, the semiconductor device 2 can include active transistors (which communicate with other components) and dummy transistors (which do not communicate with other components). However, this is merely illustrative, and the present disclosure is not limited thereto. The structural features of the second active region ACT2 and the source / drain regions, as well as the structural features of the gate line GL and the second channel region CH2, can also vary. Descriptions of embodiments with various features will be described later.

[0040] Figures 4 to 6 This is a cross-sectional view illustrating an embodiment of a semiconductor device according to the present invention.

[0041] For example, Figures 4 to 6 It shows the respective along Figure 2 The cross-sections of semiconductor device 2 taken by dicing lines I-I', II-II', and III-III'. For ease of description, in Figures 4 to 6 The diagram shows only the main components of semiconductor device 2. For example, although in Figures 4 to 6 The diagram shows a layer with a horizontal plane of M1, but is not limited thereto. Furthermore, the arrangement of the main components and metal wiring shown is merely illustrative, and this disclosure is not limited thereto.

[0042] Reference Figures 4 to 5 A semiconductor device 100 according to an embodiment of the present invention may include a substrate 101, active regions ACT1, ACT2 and ACT3, a device isolation layer 110, a source / drain region 120, a lower interlayer insulating layer 130, a gate insulating layer 142, a gate electrode layer 145, a gate cap layer 148, an upper interlayer insulating layer 150, a plurality of contacts CNTs, and a plurality of metal wirings ML. For example, the plurality of contacts CNTs may include active contacts, gate contacts, lower vias, etc. The cross-section of the gate line ML may include the gate insulating layer 142, the gate electrode layer 145 and the gate cap layer 148. However, this is merely illustrative and the present disclosure is not limited thereto. The construction of the semiconductor device 100 and the construction of the gate line ML included therein may differ from the construction shown.

[0043] Substrate 101 may have an upper surface extending along the X and Y directions. Substrate 101 may include or may be a semiconductor material (such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, a group IV semiconductor may include or may be silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. Substrate 101 may include doped regions (such as N-well regions).

[0044] Device isolation layer 110 can define active regions ACT1, ACT2, and ACT3 in substrate 101. Device isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. Figure 4 As shown, the device isolation layer 110 may include, but is not limited to, a region extending deeper in the lower portion of the substrate 101 between adjacent active regions ACT1, ACT2, and ACT3. The device isolation layer 110 may be formed of an insulating material and may be, or include, for example, oxides, nitrides, or combinations thereof.

[0045] Active regions ACT1, ACT2, and ACT3 may be defined by a device isolation layer 110 in substrate 101 and may be configured to extend along a second direction (e.g., along the X direction). Source / drain regions 120 may be disposed on both sides of the gate line GL on the active regions ACT1, ACT2, and ACT3. According to an embodiment, active regions ACT1, ACT2, and ACT3 may have doped regions including impurities. For example, active regions ACT1, ACT2, and ACT3 may include impurities diffused from the source / drain region 120 in the region contacting the source / drain region 120. As shown, active regions ACT1, ACT2, and ACT3 are not limited to structures having a flat upper surface.

[0046] The source / drain region 120 may be formed of an epitaxial layer and may comprise, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). Furthermore, the source / drain region 120 may further include impurities such as arsenic (As) and / or phosphorus (P). In embodiments, the source / drain region 120 may include multiple regions containing elements and / or dopants of different concentrations.

[0047] Gate lines GL can be disposed above, superimposed on, and extend along the Y direction of active regions ACT1, ACT2, and ACT3. The channel regions of each transistor can be disposed within the active regions ACT1, ACT2, and ACT3 superimposed on the gate lines GL. The cross-section of the gate lines GL may include a gate insulating layer 142, a gate electrode layer 145, a gate spacer layer, and a gate cap layer 148. However, the shape and configuration of the gate lines GL included in each transistor are not limited to those shown.

[0048] For example, the gate insulating layer 142 may be configured as multiple layers, or it may be configured to extend to the lateral surface of the gate electrode layer 145. The gate insulating layer 142 may be or may include an oxide, nitride, or high-k material. A high-k material may refer to a dielectric material having a dielectric constant higher than that of the silicon oxide layer (SiO2). The gate line GL may be formed of two conductive portions, for example, both conductive portions extending longitudinally along a first direction (Y direction), wherein the two conductive portions are separated by an insulating layer or block formed therebetween.

[0049] The gate electrode layer 145 may include or may be a conductive material, such as a metal nitride like a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film, and / or a metallic material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polycrystalline silicon. The gate electrode layer 145 may be formed from a multilayer having two or more layers. The gate electrode layer 145 may be disposed separately from each other in the Y direction between at least some adjacent transistors, depending on the circuitry of the semiconductor device 100. For example, the gate electrode layer 145 may be separated by a separate gate separation layer (e.g., a gate separation layer forming an insulating layer or block).

[0050] A gate spacer layer may be disposed on both lateral surfaces of the gate electrode layer 145. The gate spacer layer may insulate the source / drain regions 120 from the gate electrode layer 145. The gate spacer layer may be configured as a multilayer structure according to embodiments. The gate spacer layer may be formed of oxide, nitride, or oxynitride, and specifically, may be formed of a low-k film. The gate spacer layer may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN, or may be formed of at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0051] A gate cap layer 148 may be disposed on the gate electrode layer 145, and the lower surface and lateral surface of the gate cap layer 148 may be surrounded by the gate electrode layer 145 and the gate spacer layer, respectively. The gate cap layer 148 may be formed of, for example, oxides, nitrides, or oxide oxynitrides.

[0052] The lower interlayer insulating layer 130 may be configured to cover the source / drain region 120 and the gate line GL. The lower interlayer insulating layer 130 may include, for example, at least one of oxides, nitrides, and oxide oxynitrides, or be formed of, for example, at least one of oxides, nitrides, and oxide oxynitrides, and may include a low-k material.

[0053] Multiple contact CNTs can extend through the lower interlayer insulating layer 130 to connect to the source / drain region 120, or they can extend through the lower interlayer insulating layer 130 and the gate cap layer 148 to connect to the gate electrode layer 145, and can apply electrical signals to the source / drain region 120 and the gate electrode layer 145. The multiple contact CNTs can be configured to extend to a predetermined depth, but they are not limited thereto. The multiple contact CNTs can include conductive materials (e.g., metallic materials such as tungsten (W), aluminum (Al), copper (Cu), etc.) or semiconductor materials (e.g., doped polysilicon), or are formed of conductive materials (e.g., metallic materials such as tungsten (W), aluminum (Al), copper (Cu), etc.) or semiconductor materials (e.g., doped polysilicon). According to some embodiments, the multiple contact CNTs can include a barrier metal layer disposed on their outer surface. Furthermore, according to some embodiments, the multiple contact CNTs can also include a metal-semiconductor layer (such as a silicide layer) disposed at the interface between the contact source / drain region 120 and the gate electrode layer 145.

[0054] The upper interlayer insulating layer 150 may cover multiple contact CNTs and may be disposed at the same level as the lower via and multiple metal wirings ML. The upper interlayer insulating layer 150 may include first to third insulating layers with different levels. The upper interlayer insulating layer 150 may be formed of silicon oxide or a low-k material. The upper interlayer insulating layer 150 may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN. An etch stop layer for stopping etching in the etching process for forming the lower via and multiple metal wirings ML may be disposed on the lower surface of each upper interlayer insulating layer 150. The etch stop layer may include a high-k material and may include, for example, silicon nitride or aluminum oxide.

[0055] Figures 4 to 5 The semiconductor device 100 shown is illustrated up to a horizontal layer having a depth of M1, but the semiconductor device 100 is not limited thereto. For example, the semiconductor device 100 may include a lower via, a first wiring, a first via, a second wiring, etc., which may be sequentially stacked and disposed from the bottom of the semiconductor device 100. The first wiring and the second wiring, which are sequentially stacked from the bottom to the top of the semiconductor device 100, may have a relatively large thickness towards the top, but they are not limited thereto. Each wiring structure may include a conductive material. For example, each wiring structure may include or may be at least one of aluminum (Al), copper (Cu), and tungsten (W).

[0056] Reference Figure 6 In the semiconductor device 100 according to an embodiment of the present invention, the cross-section of the second active region ACT2 may have a shape different from that of the first active region ACT1. For example, as Figure 6 As shown, the active contact is not disposed above the second active region ACT2. For example, the second active region ACT2 may be a floating region. However, this is merely illustrative, and the present disclosure is not limited thereto. According to some embodiments, a floating active contact may be disposed above the second active region ACT2.

[0057] As in Figure 6 As can be seen in the embodiments shown in the figures below, each depicted semiconductor device includes a second active region ACT2 superimposed on the first active region ACT1 and the third active region ACT3 in a first direction (e.g., the Y direction). Furthermore, each second active region ACT2 is formed to have a width (or length) in a second direction (e.g., the X direction) that is the same as or less than the width of each of the first active region ACT1 and the third active region ACT3 in the second direction. Additionally, in each example, the second active region ACT2 is vertically superimposed on at least a portion of the gate line GL (e.g., in a top view or in the Z direction). In each example, the gate line GL extends along the first direction (e.g., the Y direction) to be vertically superimposed on both the first active region ACT1 and the second active region ACT2. Furthermore, in various embodiments, the length of the second active region ACT2 in the first direction (e.g., the Y direction) is shorter than the length of either the first active region ACT1 or the third active region ACT3 in the first direction. As used herein, terms such as “identical,” “equal,” “plane,” or “coplanar” imply similarity or include near-identity, for example, due to variations that may occur due to manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “basically” may be used herein to emphasize that meaning.

[0058] Figures 7 to 21 This is a layout diagram of a semiconductor device according to an embodiment of the present invention.

[0059] The effect of the semiconductor device according to an embodiment of the present invention can be determined by the area of ​​the second channel region CH2. For example, the area of ​​the second channel region CH2 can be different from the area of ​​the first channel region CH1. For example, the area of ​​the second channel region CH2 can be smaller than the area of ​​the first channel region CH1. However, this is merely illustrative and not a limitation. The area of ​​the second channel region CH2 can be determined by the shape of the extended gate line GL, the shape of the second active region ACT2, and the shape of the portion of the second channel region CH2 in which the extended gate line GL is superimposed with the second active region ACT2 (e.g., superimposed in the Z direction). The shape of the extended gate line GL, the shape of the second active region ACT2, and the shape of the portion of the second channel region CH2 in which the extended gate line GL is superimposed with the second active region ACT2 are not limited to... Figure 2 Those shown, and can have various structures (e.g., size, shape, and / or layout). For example, the second channel region CH2 can have various structures (such as triangles and other shapes besides rectangles).

[0060] Figures 7 to 21 The diagram illustrates various types of embodiments.

[0061] First, refer to Figure 7 and Figure 8 In the semiconductor devices 3 and 4 according to embodiments of the present invention, the length of the extended gate line GL may not be limited to a specific length. For example, including... Figure 2 The gate line GL in the semiconductor device 2 shown can extend further in the first direction than the lower end of the additionally added second active region ACT2. (Included in...) Figure 7 and Figure 8 The gate line GL in the semiconductor devices 3 and 4 shown can extend in the first direction to a extent that it does not reach the lower end of the second active region ACT2, or it can extend to the lower end of the second active region ACT2. In this case, the boundary of the extended gate line GL can be the boundary of the second channel region CH2. For example, with respect to the same second active region ACT2, when the gate line GL is as shown in... Figure 2 In the semiconductor device 2 shown, when it extends through the lower end of the second active region ACT2, or when the gate line GL is as shown in Figure 8 In the semiconductor device 4 shown, the area of ​​the second channel region CH2 can be maximized when it extends to the lower end of the second active region ACT2. When the area of ​​the second channel region CH2 is maximized, the antenna ratio of the semiconductor device can be minimized. Therefore, even without typical antenna devices, the transistors included in the semiconductor device can be protected from plasma damage.

[0062] For example, in Figure 7 and Figure 8In the semiconductor devices 3 and 4 shown, the length of the second active region ACT2 in the first direction can be H. Figure 7 The length of the second channel region CH2 shown in the first direction can be Y1. Figure 2 and Figure 8 The length of the second channel region CH2 shown can be Y2. For example, Y1 can have a value less than H, and Y2 can be substantially the same as H.

[0063] As described above, multiple contact elements (CNTs) can be disposed above the first active region ACT1 and the third active region ACT3 to apply signals to the source / drain regions of the first active region ACT1 and the third active region ACT3, respectively. The multiple contact elements (CNTs) may include active contacts and under-vias. See reference... Figure 9 and Figure 10 At least one floating contact FCNT, having a shape, for example, identical to that of an active contact, can be disposed laterally above the gate line GL in the upper lateral portion of the second active region ACT2. For example, source / drain regions can be formed within a portion of the second active region ACT2, and the floating active contact can be disposed above at least one of the source / drain regions. The floating contact FCNT can be electrically isolated from multiple lower metal wirings ML (and from any metal wiring). However, Figure 9 and Figure 10 The arrangement and shape of the floating contact FCNTs in semiconductor devices 5 and 6 shown are illustrative only, and the embodiments are not limited thereto. Furthermore, as... Figure 9 and Figure 10 The floating contact shown can be included in various other embodiments disclosed herein.

[0064] The presence or absence of a floating contact FCNT can be determined by considering the ease of semiconductor device manufacturing and / or its arrangement with other components. For example, when including the contact will not cause problems such as the second active region ACT2 being connected to the lower metal wiring ML due to the contact, the contact can be positioned above the second active region ACT2 without distinction from the first active region ACT1. In this case, the contact positioned above the second active region ACT2 can be a floating contact FCNT. When including the contact would cause problems such as the second active region ACT2 being connected to the lower metal wiring ML due to the contact, the contact may not be positioned above at least a portion of the second active region ACT2.

[0065] The size and shape of the second channel region CH2 may differ from the size and shape of each of the plurality of first channel regions CH1 and the plurality of third channel regions CH3. For example, the area or length in the Y direction of the second channel region CH2 may differ from (e.g., be greater than or less than) the area or length in the Y direction of the first channel region CH1 or the third channel region CH3. The size and shape of the second channel region CH2 may be determined by the shape of the extended gate line GL and / or the extension direction of the gate line GL, etc. Figures 11 to 18 This diagram illustrates an embodiment relating to the extension shape and direction of the gate line GL. The gate line GL may extend substantially along a first direction. However, the inventive concept is not limited thereto. The gate line GL may also extend along a second direction in a region superimposed with the second active region ACT2. Furthermore, the gate line GL may extend along a third direction that includes both the first and second directions. Moreover, the second channel region CH2 is not limited to the illustrated embodiment as long as the second channel region CH2 is separately disposed from the first channel region CH1 based on the floating second active region ACT2 (e.g., disposed separately from the first channel region CH1).

[0066] Reference Figures 11 to 14 The gate line GL included in the semiconductor devices 7 to 10 according to embodiments of the present invention can extend in various shapes. For example, at least a portion of the gate line GL can have a first channel region CH1 and a second channel region CH2 with different lengths in a second direction. For example, the length of the first channel region CH1 in the second direction can be W. Figures 11 to 14 In the semiconductor devices 7 to 10 shown, the lengths of the gate lines GL stacked with the second channel region CH2 at any point in the second direction can be W1, W2, W3, and W4, respectively. The length of the extended gate lines GL in the second direction can be determined taking into account processing conditions and arrangement with other components.

[0067] Reference Figure 11 In the semiconductor device 7 according to an embodiment of the present invention, the length of the extended gate line GL in the second direction can be reduced. For example, the length W1 of the second channel region CH2 at a point in the second direction can be a smaller value than the length W of the first channel region CH1 in the second direction. Figure 11 As shown, the length of the second channel region CH2 at different points in the second direction can have values ​​other than W1. However, this is merely illustrative, and this disclosure is not limited thereto.

[0068] Reference Figure 12 and Figure 13In the semiconductor devices 8 and 9 according to embodiments of the present invention, the length of the extended gate line GL in the second direction can be increased. For example, the lengths W2 and W3 of the second channel region CH2 at a point in the second direction can be larger than the length W of the first channel region CH1 in the second direction. Figure 12 As shown, the length of the second channel region CH2 at different points in the second direction can have values ​​other than W2. Additionally, as... Figure 13 As shown, the length of the gate line GL, which extends fully over the second channel region CH2, in the second direction can be W3.

[0069] In addition, refer to Figure 14 In the semiconductor device 10 according to an embodiment of the present invention, the extended gate line GL may have the same length in the second direction as the second active region ACT2. In this case, the length of the extended gate line GL in the second direction and the length of the second active region ACT2 in the second direction may be the same (e.g., W4). For example, the area of ​​the second channel region CH2 may be the same as the area of ​​the second active region ACT2. According to an embodiment, the extended gate line GL may be used to maximize the area of ​​the second channel region CH2, but this is merely illustrative and the present disclosure is not limited thereto. The shape of the gate line GL may be determined considering the overall layout of the semiconductor device.

[0070] Reference Figures 15 to 18 The extension direction of the gate line GL included in the semiconductor devices 11 to 14 according to embodiments of the present invention may not be limited to these examples. For example, at least a portion of the gate line GL may extend in a direction other than the first direction. For example, at least a portion of the gate line GL above the second channel region CH2 may extend in a direction different from the first and second directions and parallel to the upper surface of the semiconductor substrate. For example, when the X and Y directions are taken as axes, the extended gate line GL may have a diagonal shape. Using a gate line GL extended to have a diagonal shape, the semiconductor devices 11 to 14 according to embodiments of the present invention can improve the degree of freedom in arranging the lower metal wiring ML. However, the extension direction of the gate line GL is related to... Figures 15 to 18 Semiconductor devices 11 to 14 are illustrative only and are not limited thereto.

[0071] Reference Figure 15 In the semiconductor device 11 according to an embodiment of the present invention, the gate line GL can extend along a predetermined direction. For example, in Figure 16In the semiconductor device 12 shown, the extension direction of the gate line GL can be changed during the extension. For example, the gate line GL, which extends in a predetermined direction in the portion of the gate line GL that overlaps with the second active region ACT2, can be further extended in a direction different from the predetermined direction.

[0072] Furthermore, according to an embodiment, the gate line GL can be extended to have a diagonal shape while varying its length in the second direction. (See also...) Figure 17 In the semiconductor device 13 according to an embodiment of the present invention, the gate line GL can be extended to gradually increase in length in a second direction. For example, the gate line GL above the second channel region CH2 may include a first region having a first width in the second direction and a second region having a second width different from the first width. For example, the first width may be W5, the second width may be W6, and W5 may be a value less than W6. From a plan view, this can form a conical shape (such as a trapezoidal shape).

[0073] Reference Figure 18 In the semiconductor device 14 according to an embodiment of the present invention, the gate line GL can be extended to gradually decrease in length in the second direction. For example, the gate line GL above the second channel region CH2 may include a first region having a first width in the second direction and a second region having a second width different from the first width. For example, the first width may be W7, the second width may be W8, and W7 may be a value greater than W8. However, Figure 17 and Figure 18 The semiconductor devices 13 and 14 shown are illustrative only and are not intended to be limiting. The length of the gate line GL in the second direction can vary in various ways depending on the embodiment.

[0074] Reference Figures 19 to 21 The size of the second active region ACT2 included in the semiconductor device according to the embodiment can vary. The size of the second active region ACT2 can be determined by considering the relationship between the process and surrounding components. According to the embodiment, the size of the second active region ACT2 can determine the size of the second channel region CH2. Semiconductor devices 15, 16, and 17 according to embodiments of the present invention can include gate lines GL extending the same length and having the same shape. For example, the gate lines GL included in semiconductor devices 15, 16, and 17, respectively, can be consistent with those included in the semiconductor device 17. Figure 2 The gate line GL in the semiconductor device 2 shown is substantially the same (although gate sizes and shapes from other foregoing embodiments can be used as alternatives). Furthermore, semiconductor devices 15, 16, and 17, as well as… Figure 2The semiconductor device 2 shown may include a second channel region CH2 having substantially the same area and shape.

[0075] Reference Figures 19 to 21 In embodiments of the present invention, the length of the second active region ACT2 included in semiconductor devices 15, 16, and 17 in a second direction may differ from the length of the first active region ACT1 included therein. For example, in the second direction, the length of the second active region ACT2 may be smaller than the length of the first active region ACT1. In the second direction, the portion in which the second active region ACT2 is not provided may be a region separated by an STI process. For example, the portion in which the second active region ACT2 is not provided may be defined as an STI region.

[0076] exist Figure 19 In the semiconductor device 15 shown, an STI process can be performed in a second active region ACT2 disposed below a lower metal wiring. For example, the lower metal wiring can be disposed on the STI region. For example, the second active region ACT2 can be non-overlapping with the lower metal wiring in the Z direction perpendicular to the upper surface of the semiconductor substrate. In this way, the STI process can be performed taking into account the arrangement between the floating second active region ACT2 and other components. The STI region formed by the STI process can divide the second active region ACT2 into multiple regions. However, this is merely illustrative, and the present disclosure is not limited thereto. According to an embodiment, the second active region ACT2 can be a region with a reduced length in the second direction, and the lower metal wiring may not be disposed above the STI region.

[0077] For example, Figure 20 The semiconductor device 16 shown may include having a ratio in the second direction to Figure 19 The semiconductor device 15 shown has a long STI region. Therefore, the second active region ACT2 included in the semiconductor device 15 may include a region of the STI region whose length is reduced in the second direction. Additionally, Figure 21 The semiconductor device 17 shown may include STI regions located in the second active region ACT2, respectively formed on the upper surfaces on both sides of the extended gate line GL. In this case, the lower metal wiring may not be disposed above either of the STI regions. For example, the lengths of the second active region ACT2 and the gate line GL in the second direction may be substantially the same.

[0078] Figure 22 and Figure 23 This is a cross-sectional view illustrating an embodiment of a semiconductor device according to the present invention.

[0079] For example, Figure 22 It shows Figure 19The cross-section of the semiconductor device 15 shown is taken along line IV-IV'. Figure 23 It shows Figure 20 The semiconductor device 16 shown is a cross-section taken along line V-V'. For ease of description, in Figure 22 and Figure 23 The diagram shows only the main components of semiconductor devices 15 and 16. Components omitted in the following description may correspond to... Figure 6 The semiconductor device 100 shown includes components similar to those described above. Figure 6 Even in the way, Figure 22 and Figure 23 The diagram shows a layer with a horizontal plane M1, but the semiconductor device is not limited to this. Furthermore, the arrangement of the main components and metal wiring shown is illustrative only and is not a limitation thereof.

[0080] In semiconductor devices 1500 and 1600 according to embodiments of the present invention, the second active region ACT2 may include an STI region formed on at least a portion thereof. The STI region may be device isolation layers 1510 and 1610, and source / drain regions 1520 and 1620 may be replaced by device isolation layers 1510 and 1610 and may be filled with an insulating material. For example, in Figure 22 In the semiconductor device 1500 shown according to an embodiment of the present invention, a device isolation layer 1510 may be formed in a portion of the second active region ACT2. The device isolation layer 1510 may be formed such that a portion of the N-well NWELL is recessed to separate the second active region ACT2. However, this is merely illustrative, and the present disclosure is not limited thereto. Furthermore, in Figure 23 In the semiconductor device 1600 shown according to an embodiment of the present invention, the device isolation layer 1610 may be formed to completely replace a lateral portion of the second active region ACT2. The device isolation layer 1610 may be formed such that a portion of the N-well (NWELL) is recessed to replace the second active region ACT2.

[0081] Reference Figure 22 and Figure 23 In semiconductor devices 1500 and 1600 according to embodiments of the present invention, due to device isolation layers 1510 and 1610, the second active region ACT2 may not include at least a portion of the source / drain regions 1520 and 1620. For example, respectively with Figure 22 and Figure 23 corresponding Figure 19 and Figure 20 The semiconductor devices 15 and 16 shown may not include source or drain regions. Figure 21 The semiconductor device 17 shown may not include all source / drain regions. However, Figures 19 to 21Semiconductor devices 15, 16, and 17 shown are illustrative and not limiting, and the STI region can be formed and configured to have various shapes. For example, the STI region included in the semiconductor device can be configured such that the second active region ACT2 does not include at least one of the source / drain regions, and the second active region ACT2 of the semiconductor device includes source and drain regions with different sizes.

[0082] Figures 24 to 28 This is a layout diagram of a semiconductor device according to an embodiment of the present invention.

[0083] Reference Figures 24 to 28 The embodiments are not limited to those based on Figures 7 to 21 The semiconductor devices shown in the embodiments are examples of semiconductor devices, and can be constructed in various forms to include features combined with each other. For example, the extended gate line GL can be as follows: Figure 15 The semiconductor device 11 shown extends in a diagonal shape, and at the same time, the floating contact FCNT can be as follows: Figure 9 The semiconductor device 5 shown is arranged in a portion of the second active region ACT2.

[0084] Reference Figures 24 to 26 According to embodiments of the present invention, semiconductor devices 18, 19, and 20 may have wherein each of the following is present: Figures 19 to 21 The features of semiconductor devices 15, 16, and 17 shown are the same as those in... Figure 8 The semiconductor device 4 shown in the figure has a combination of features.

[0085] For example, Figure 24 The semiconductor device 18 shown may include a second active region ACT2 divided into multiple regions and a gate line GL extending to the lower end of the second active region ACT2. Due to the second channel region CH2 based on the second active region ACT2, the sum of the areas of channel regions CH1 and CH2 can be increased.

[0086] Figure 25 The semiconductor device 19 shown may include a second active region ACT2 comprising a region whose length decreases in a second direction and a gate line GL extending to the lower end of the second active region ACT2. Due to the second channel region CH2 based on the second active region ACT2, the sum of the areas of channel regions CH1 and CH2 can be increased.

[0087] Figure 26The semiconductor device 20 shown may include a second active region ACT2 that does not contain source / drain regions and a gate line GL extending to the lower end of the second active region ACT2. Due to the second channel region CH2 based on the second active region ACT2, the sum of the areas of channel regions CH1 and CH2 can be increased.

[0088] Reference Figure 27 The semiconductor device 21 according to an embodiment of the present invention may have a combination of Figure 13 , Figure 19 and Figure 21 The semiconductor devices 9, 15, and 17 shown are characterized by their construction. For example, semiconductor device 21 may include a second active region ACT2 divided into multiple regions and not containing source / drain regions, and a gate line GL having an increased length in a second direction and extending further than the lower end of the second active region ACT2. Due to the second channel region CH2 superimposed on the gate line GL of the second active region ACT2, the sum of the areas of the channel regions CH1 and CH2 can be increased.

[0089] Reference Figure 28 The semiconductor device 22 according to an embodiment of the present invention may have a combination Figure 13 The features of the semiconductor device 9 shown are... Figure 21 The semiconductor device 17 shown is characterized by its construction. For example, the semiconductor device 22 may include a second active region ACT2 and a gate line GL. The second active region ACT2 includes a region whose length decreases in a second direction and does not include source / drain regions. The gate line GL has an increased length in the second direction and extends further than the lower end of the second active region ACT2. Due to the second channel region CH2 superimposed on the gate line GL in the second active region ACT2, the sum of the areas of the channel regions CH1 and CH2 can be increased.

[0090] Figure 27 and Figure 28 The semiconductor devices 21 and 22 shown are embodiments that maximize the area of ​​the second channel region CH2, even considering the arrangement with the lower metal wiring ML. However, the layout of the semiconductor devices is not limited to this and can be determined by considering the process of manufacturing the semiconductor devices. In addition, the shape of the extended gate line GL, the shape of the added second active region ACT2, and the shape of the second channel region CH2 are not limited to the illustrated embodiments, and the semiconductor devices according to embodiments of the present invention can be arranged to minimize the ratio of the total area of ​​the multiple metal wirings to the total area of ​​the multiple channel regions.

[0091] Figure 29 and Figure 30 This is a cross-sectional view illustrating an embodiment of a semiconductor device according to the present invention.

[0092] For example, Figure 29 It shows Figure 27 The cross-section of the semiconductor device 21 shown is taken along line VI-VI'. Figure 30 It shows Figure 28 The cross-section of the semiconductor device 22 shown is taken along line VII-VII'. For ease of explanation, in... Figure 29 and Figure 30 The diagram shows only the main components of semiconductor devices 21 and 22. Components omitted in the following description may correspond to... Figure 6 The semiconductor device 100 shown includes components similar to those described above. Figure 6 Even in the way, Figure 29 and Figure 30 The diagram shows a layer with a horizontal M1, but is not limited to this. Furthermore, the arrangement of the main components and metal wiring shown is illustrative only and is not limited to this.

[0093] In semiconductor devices 2100 and 2200 according to embodiments of the present invention, the second active region ACT2 may include device isolation layers 2110 and 2210 formed on the upper surfaces on both sides of the gate line GL. Device isolation layers 2110 and 2210 may include an insulating material and may be formed in regions where source / drain regions of the second active region ACT2 can be formed. For example, in Figure 29 In the semiconductor device 2100 shown according to an embodiment of the present invention, a device isolation layer 2110 may be formed in portions of the two lateral portions of the second active region ACT2. The device isolation layer 2110 may be formed such that a portion of the N-well NWELL is recessed to separate the second active region ACT2. However, this is merely illustrative, and the present disclosure is not limited thereto. Furthermore, in Figure 30 In the semiconductor device 2200 shown according to an embodiment of the present invention, the device isolation layer 2210 may be formed to completely replace the two lateral portions of the second active region ACT2. The device isolation layer 2210 may be formed to recess a portion of the N-well NWELL to replace the second active region ACT2.

[0094] However, Figure 29 and Figure 30 The semiconductor devices 2100 and 2200 shown are illustrative and not limiting, and the device isolation layers 2110 and 2210 can be formed and configured in various forms. For example, the device isolation layers 2110 and 2210 included in the semiconductor device can be configured such that not only does the second active region ACT2 not include source / drain regions, but the second active region ACT2 of the semiconductor device can also include source and drain regions of different sizes.

[0095] Figure 31 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0096] Reference Figure 31 A semiconductor device according to an embodiment of the present invention may include a first gate line GL1 (which may be one of a plurality of first gate lines GL1), a second gate line GL2 (which may be one of a plurality of second gate lines), a plurality of active regions, a plurality of lower metal wirings, and a plurality of contacts. The plurality of first gate lines GL1 and second gate lines GL2 may extend along a first direction, and some gate lines may extend to different lengths (e.g., the first gate line GL1 may extend to different lengths than the second gate line GL2). Furthermore, the plurality of first gate lines GL1 may be connected to at least a portion of the plurality of lower metal wirings and apply signals to at least a portion of the plurality of lower metal wirings, or may be floating. Each second gate line GL2 and a plurality of components directly connected to the second gate line GL2 may correspond to... Figures 2 to 30 The components included in the semiconductor device of the embodiment shown.

[0097] For example, multiple first gate lines GL1, a first active region, and a third active region can be components for the general operation of a semiconductor device. A second active region, spaced apart from the first active region in a first direction, can be a floating region and can be used to protect transistors included in the semiconductor device from plasma damage. For example, multiple first gate lines GL1 can share a first active region, and at least some of the multiple first gate lines GL1 can share a first active region with a second gate line GL2. The second active region can be stacked with the second gate line GL2.

[0098] For example, the second gate line GL2 may extend to a length different from that of the plurality of first gate lines GL1. Furthermore, a portion of the second gate line GL2 may include a gate structure having a shape different from that of the plurality of first gate lines GL1. For example, in a semiconductor device according to an embodiment of the present invention, a dummy region DUMMY may be included, which is adjacent to the plurality of first gate lines GL1 in a first direction and adjacent to a second active region in a second direction. The dummy region DUMMY may not provide transistors for operation of a typical semiconductor device. However, this is merely illustrative, and the present disclosure is not limited thereto. Furthermore, as previously discussed, the second active region may also be considered a dummy region.

[0099] The second gate line GL2 can provide transistors for increasing the area of ​​the channel region as well as transistors for general operation, and therefore can provide a greater number of transistors than the first gate line GL1, which only provides transistors for general operation. For example, the second gate line GL2 may also include transistors disposed based on the second channel region. However, this is merely illustrative and the present disclosure is not limited thereto. The number of transistors disposed may vary depending on the separation state of the first gate line GL1 and the second gate line GL2.

[0100] In a semiconductor device according to an embodiment of the present invention, the extended second gate line GL2 and the added second active region may differ from those in a semiconductor device with an added antenna device. For example, a ground voltage may be applied to the gate line to which the antenna device is connected, and the active region may not be floating. However, in a semiconductor device according to an embodiment of the present invention, a predetermined signal other than a ground voltage may be applied to the second gate line GL2, and the active region may be floating.

[0101] A semiconductor device according to an embodiment of the present invention may include a first active region and a second active region respectively superimposed on an extended gate region. The first active region may provide transistors for operating the semiconductor device. The second active region may increase the area of ​​the channel region to minimize the use of antenna devices. Therefore, the problems of increased semiconductor device size and reduced degrees of freedom in metal wiring due to the use of antenna devices can be solved.

[0102] The various advantages and effects of the present invention are not limited to those described above, and can be more easily understood in the process of describing specific embodiments of the present invention.

[0103] Although embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Gate line, extending along a first direction parallel to the upper surface of the semiconductor substrate; The first active region includes a first channel region disposed below the gate line and includes impurities of a first conductivity type. The second active region is configured to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity type impurity; as well as Multiple metal wirings are disposed at a first horizontal height above the semiconductor substrate. In this configuration, at least one of the plurality of metal wirings is directly electrically connected to the first active region, the plurality of metal wirings at the first height level are electrically separated from the second active region, and at least one of the plurality of metal wirings is connected to receive a signal applied to the gate line. The second active region is floating, and the gate line and the second active region define a dummy transistor.

2. The semiconductor device according to claim 1, wherein, The gate line and the first active region define the first transistor. The plurality of metal wirings are disposed above the first transistor and vertically stacked on top of the first transistor, and include two or fewer metal wirings extending along a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein, The area of ​​the first channel region is larger than the area of ​​the second channel region.

4. The semiconductor device according to claim 1, wherein, The length of the second active region in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate is the same as the length of the first active region in the second direction.

5. The semiconductor device according to claim 1, wherein, The length of the second active region in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate is shorter than the length of the first active region in the second direction.

6. The semiconductor device according to claim 1, wherein, The second active region does not overlap with at least some of the plurality of metal wirings in a third direction perpendicular to the upper surface of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein, The second active region does not include at least one of the source region and the drain region.

8. The semiconductor device according to claim 1, wherein, At least one contact is disposed in the upper lateral portion of the second active region relative to the gate line. The at least one contact is electrically isolated from the plurality of metal wires.

9. The semiconductor device according to claim 1, wherein, At least a portion of the gate line above the first channel region and the second channel region has a different length in a second direction that is perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate.

10. The semiconductor device according to claim 1, wherein, The gate line above the second channel region includes a first region having a first width in a second direction and a second region having a second width different from the first width, the second direction being perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate.

11. The semiconductor device according to claim 1, wherein, At least a portion of the gate line above the second channel region extends along a direction parallel to the upper surface of the semiconductor substrate and different from the first direction and the second direction, wherein the second direction is perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate.

12. The semiconductor device according to claim 1, wherein, The area of ​​the second channel region is the same as the area of ​​the second active region.

13. The semiconductor device of claim 1, further comprising: The third active region is configured to be separated from the first active region and the second active region in the first direction, and includes a third channel region disposed below the gate line and including impurities of the second conductivity type.

14. A semiconductor device, the semiconductor device comprising: Multiple gate lines, including multiple first gate lines extending along a first direction parallel to the upper surface of the semiconductor substrate and a second gate line extending along the first direction and having a length different from that of each of the multiple first gate lines in the first direction. The first active region includes a plurality of first channel regions disposed below the plurality of gate lines and includes impurities of a first conductivity type; The second active region is configured to be separated from the first active region in the first direction, including a second channel region disposed below the second gate line, and including the first conductivity type impurity; as well as The third active region includes a plurality of third channel regions disposed below the plurality of gate lines and includes impurities of a second conductivity type. The structure above each of the plurality of first channel regions of the second gate line is different from the structure above the second channel region of the second gate line.

15. The semiconductor device according to claim 14, wherein, The second gate line and at least one of the plurality of first gate lines share the first active region.

16. The semiconductor device according to claim 14, wherein, The first conductivity type impurity is an N-type impurity, and The second type of conductivity impurity is a P-type impurity.

17. The semiconductor device according to claim 14, wherein, Each of the plurality of gate lines and the first active region defines a first transistor. The second gate line and the second active region define the second transistor, and Each of the plurality of gate lines and the third active region define a third transistor. The second active region is floating, and the second transistor is a dummy transistor.

18. The semiconductor device of claim 14, further comprising a dummy region disposed in a position adjacent to the plurality of first gate lines along a first direction and adjacent to the second active region along a second direction, the second direction being perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate.

19. A semiconductor device, the semiconductor device comprising: Gate line, extending along a first direction parallel to the upper surface of the semiconductor substrate; Multiple active regions, including multiple channel regions below the gate line, the multiple channel regions including all channel regions of the semiconductor device, the multiple channel regions being configured to be separated from each other in the first direction; Multiple metal wirings are disposed at a first height level to be electrically connected to the gate line and a group of active regions including at least two of the multiple active regions, the multiple metal wirings including all metal wirings at the first height level of the semiconductor device; as well as Multiple contacts are connected to a set of active regions among the multiple active regions. The semiconductor device is arranged such that the ratio of the total area of ​​the plurality of metal wirings to the total area of ​​the plurality of channel regions is a value of 0.4 or greater and 400 or less.

20. The semiconductor device of claim 19, wherein, The plurality of active regions further include a first active region connected to at least one of the plurality of contacts and a second active region separate from the plurality of contacts. The gate line and the second active region define a dummy transistor.

Images