Memristor-based balanced ternary univariate logic circuits

Abstract

This invention discloses a balanced three-valued single-variable logic circuit based on memristors, comprising 18 types of single-variable logic circuits. Among them, the output circuits of F4 and F9 are each composed of only one memristor and one NMOS transistor; F5, F... 10 F 13 F 18 F 23 F 26 The output circuits of F3 and F7 are each composed of two memristors and one NMOS transistor; the output circuits of F2 and F7 are each composed of two memristors and two NMOS transistors; 15 The output circuits are all composed of three memristors and two NMOS transistors; F 17 F 21 F 24 The circuits are all composed of three memristors and three NMOS transistors; F 11 F 12 The output circuits of all circuits consist of four memristors and four NMOS transistors; the F8 output circuit consists of five memristors and five NMOS transistors. The circuit structure of this invention is clear, simple, and easy to implement, and it is of great significance for application research in many fields such as multi-valued digital logic circuit design.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology and relates to ternary digital logic circuit structures, specifically to the design and implementation of 18 physically realizable memristor-based balanced ternary single-variable logic circuits. Background Technology

[0002] In 1971, Professor Cai Shaotang, from the perspective of circuit theory completeness, predicted the existence of a fourth missing passive basic circuit element besides resistors, capacitors, and inductors, characterizing the relationship between charge and magnetic flux, and named it the memristor. Memristors are considered the next generation of non-volatile memory technology, possessing advantages such as high speed, low power consumption, easy integration, and compatibility with CMOS processes. Until 2008, HP Labs linked the theoretical concept of memristors with the bipolar switching phenomenon of resistance in TiO2 devices, proposing the HP model of memristors. Furthermore, memristors and CMOS have good compatibility; CMOS-memristor hybrid designs, combining the advantages of both, have very broad application prospects in non-volatile memory, digital logic operations, and neural networks.

[0003] With the continuous development of electronic technology, extensive research has been conducted on multi-valued logic, especially ternary logic. Compared with traditional binary signals, ternary, quaternary, or even higher-valued signals can improve the information density and processing capabilities of transmission lines and integrated circuits. In ternary logic circuit design, existing circuit structures using CMOS, CMOS, and CMOS FET designs are complex and difficult to integrate, failing to demonstrate the significant advantages of ternary logic circuits. Now, with the research on memristors, it has been discovered that using memristors to replace traditional CMOS integrated circuits in ternary logic can better reduce circuit complexity and achieve higher accuracy. Memristors, with their nanometer size, low power consumption, and compatibility with CMOS technology, provide a new direction for the development of ternary logic circuits.

[0004] In the design of ternary logic circuits, single-variable logic functions are widely used. In balanced ternary circuits, the single-variable function f(A) has three possible values: -1, 0, and 1, i.e., A∈{-1,0,1}. When the inputs are -1, 0, and 1 respectively, the output value G of the single-variable logic function is determined as follows: A=-1, A=0, A=1. -1 G0, G1 are categorized into three-digit numbers G. -1 If we sort G0G1 in that order, then the outputs of the balanced three-valued single-variable logic functions can be denoted as F1={-1,-1,-1}, F2={-1,-1,0}, F3={-1,-1,1}, F4={-1,0,-1}, ..., F 26 ={1,1,0}、F 27={1,1,1}, a total of 27 possibilities. By utilizing the resistance switching characteristics of memristors and the switching characteristics of MOSFETs, the above single-variable function was implemented in a circuit, which can provide a certain reference for the research of multi-valued logic circuits. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes several novel designs for balanced ternary single-variable logic circuits based on memristors, all of which can be implemented using a hybrid design combining memristors and CMOS. The technical solutions adopted by this invention to solve the technical problems are as follows:

[0006] This invention includes technical solutions for 18 single-variable logic circuits. Among them, the output circuits of F4 and F9 are each composed of only one memristor and one NMOS transistor; F5, F... 10 F 13 F 18 F 23 F 26 The output circuits of F3 and F7 are each composed of two memristors and one NMOS transistor; the output circuits of F2 and F7 are each composed of two memristors and two NMOS transistors; 15 The output circuits are all composed of three memristors and two NMOS transistors; F 17 F 21 F 24 The circuits are all composed of three memristors and three NMOS transistors; F 11 F 12 The output circuits of all circuits consist of four memristors and four NMOS transistors; the F8 output circuit consists of five memristors and five NMOS transistors.

[0007] The F4 logic circuit consists of a first memristor M1 and a first NMOS transistor T1. The negative terminal of the first memristor M1 is connected to the gate of the first NMOS transistor T1 and serves as the input terminal of the F4 logic circuit; the positive terminal of the first memristor M1 is connected to the drain of the first NMOS transistor T1 and serves as the output terminal F4 of the F4 logic circuit; the source of the first NMOS transistor T1 is connected to the power supply -V. DD Connected.

[0008] The F5 logic circuit consists of a second memristor M2, a third memristor M3, and a second NMOS transistor T2. The negative terminal of the second memristor M2 is connected to the gate of the second NMOS transistor T2 and serves as the input terminal of the F5 logic circuit; the positive terminal of the second memristor M2 is connected to the negative terminal of the third memristor M3 and serves as the output terminal F5 of the F5 logic circuit; the positive terminal of the third memristor M3 is connected to the drain of the second NMOS transistor T2; and the source of the second NMOS transistor T2 is connected to the power supply -V. DD Connected.

[0009] The F9 logic circuit consists of a fourth memristor M4 and a third NMOS transistor T3. The cathode of the fourth memristor M4 and the gate of the third NMOS transistor T3 are connected to the power supply V. DD The positive terminal of the fourth memristor M4 is connected to the drain of the third NMOS transistor T3 and serves as the output terminal F9 of the F9 logic circuit; the source of the third NMOS transistor T3 serves as the input terminal of the F9 logic circuit.

[0010] The F 10 Logic circuits and F 13 The logic circuit structure is consistent and can be constructed using a fifth memristor M5, a sixth memristor M6, and a fourth NMOS transistor T4. The negative terminal of the fifth memristor M5 is connected to the power supply V. DD Connected; the positive terminal of the fifth memristor M5 and the negative terminal of the sixth memristor M6 are connected to the drain of the fourth NMOS transistor T4, and serve as F. 10 The output terminal F of the logic circuit 10 or F 13 The output terminal F of the logic circuit 13 The gate of the fourth NMOS transistor T4 serves as F. 10 Logic circuits or F 13 The input terminals of the logic circuit; the positive terminal of the sixth memristor M6 and the source terminal of the fourth NMOS transistor T4 are connected to the power supply -V. DD Connected.

[0011] The F 18 The logic circuit consists of a seventh memristor M7, an eighth memristor M8, and a fifth NMOS transistor T5. The negative terminal of the seventh memristor M7 and the gate of the fifth NMOS transistor T5 are connected to the power supply V. DD Connected; the positive terminal of the seventh memristor M7 is connected to the negative terminal of the eighth memristor M8, and serves as F. 18 The output terminal F of the logic circuit 18 The positive terminal of the eighth memristor M8 is connected to the drain of the fifth NMOS transistor T5; the source of the fifth NMOS transistor T5 serves as the F... 18 The input terminal of a logic circuit.

[0012] The F 23 Logic circuits and F 26 The logic circuit has a consistent structure and can be composed of the ninth memristor M9 and the tenth memristor M. 10 It is composed of the sixth NMOS transistor T6. The negative terminal of the ninth memristor M9 is connected to the power supply V. DD Connected; the positive terminal of the ninth memristor M9 is connected to the tenth memristor M... 10 The negative terminal is connected and serves as F. 23 The output terminal F of the logic circuit 23 or F 26 The output terminal F of the logic circuit 26 ; 10th memristor M10 The positive terminal is connected to the drain of the sixth NMOS transistor T6; the gate of the sixth NMOS transistor T6 serves as F. 23 Logic circuits or F 26 The input terminal of the logic circuit; the source of the sixth NMOS transistor T6 and the power supply -V DD Connected.

[0013] The F2 logic circuit consists of F 26 The logic circuit and the F4 logic circuit are cascaded together; F 26 The input terminal of the logic circuit serves as the input terminal of the F2 logic circuit; F 26 The output terminal F of the logic circuit 26 It is connected to the input terminal of the F4 logic circuit; the output terminal of the F4 logic circuit serves as the output terminal F2 of the F2 logic circuit.

[0014] The F3 logic circuit is composed of F 25 Logic circuits and F 19 Cascaded logic circuits; F 25 The input terminal of the logic circuit serves as the input terminal of the F3 logic circuit; F 25 The output terminal F of the logic circuit 25 With F 19 The input terminals of the logic circuit are connected; F 19 The output terminal of the logic circuit is used as the output terminal F3 of the F3 logic circuit.

[0015] The F7 logic circuit is composed of cascaded F4 and F9 logic circuits; the input terminal of the F4 logic circuit serves as the input terminal of the F7 logic circuit; the output terminal F4 of the F4 logic circuit is connected to the input terminal of the F9 logic circuit; and the output terminal of the F9 logic circuit serves as the output terminal F7 of the F7 logic circuit.

[0016] The F8 logic circuit consists of F 20 Logic circuits and F 22 Cascaded logic circuits; F 20 The input terminals of the logic circuit serve as the input terminals of the F8 logic circuit; F 20 The output terminal F of the logic circuit 20 With F 22 The input terminals of the logic circuit are connected; F 22 The output terminal of the logic circuit is used as the output terminal F8 of the F8 logic circuit.

[0017] The F 11 The logic circuit consists of the F7 logic circuit and F... 16 Cascaded logic circuits constitute the F7 logic circuit; the input terminal of the F7 logic circuit serves as the F7 logic circuit. 11 The input terminals of the logic circuit; the output terminals of the F7 logic circuit. 16 The input terminals of the logic circuit are connected; F16 The output of the logic circuit is used as F 11 The output terminal F of the logic circuit 11 .

[0018] The F 12 The logic circuit consists of F 16 Logic circuits and F 22 Cascaded logic circuits; F 16 The input terminal of the logic circuit is used as F 12 The input terminal of a logic circuit; F 16 The output terminal F of the logic circuit 16 With F 22 The input terminals of the logic circuit are connected; F 22 The output of the logic circuit is used as F 12 The output terminal F of the logic circuit 12 .

[0019] The F 15 The logic circuit consists of F 25 Logic circuits and F 26 Cascaded logic circuits; F 25 The input terminal of the logic circuit is used as F 15 The input terminal of a logic circuit; F 25 The output terminal F of the logic circuit 25 With F 26 The input terminals of the logic circuit are connected; F 26 The output of the logic circuit is used as F 15 The output terminal F of the logic circuit 15 .

[0020] The F 17 The logic circuit consists of the F4 logic circuit and F... 16 Cascaded logic circuits constitute the F4 logic circuit; the input terminal of the F4 logic circuit serves as the F... 17 The input terminals of the logic circuit; the output terminals of the F4 logic circuit, F4 and F... 16 The input terminals of the logic circuit are connected; F 16 The output of the logic circuit is used as F 17 The output terminal F of the logic circuit 17 .

[0021] The F 21 The logic circuit consists of F 16 Logic circuits and F 25 Cascaded logic circuits; F 16 The input terminal of the logic circuit is used as F 21 The input terminal of a logic circuit; F 16 The output terminal F of the logic circuit 16 With F 25 The input terminals of the logic circuit are connected; F 25The output of the logic circuit is used as F 21 The output terminal F of the logic circuit 21 .

[0022] The F 24 The logic circuit consists of the F4 logic circuit and F... 22 Cascaded logic circuits constitute the F4 logic circuit; the input terminal of the F4 logic circuit serves as the F... 24 The input terminals of the logic circuit; the output terminals of the F4 logic circuit, F4 and F... 22 The input terminals of the logic circuit are connected; F 22 The output of the logic circuit is used as F 24 The output terminal F of the logic circuit 24 .

[0023] This invention provides a novel family of balanced three-valued single-variable logic circuit models based on memristors, which are clear, simple, and easy to implement. This circuit model is of great significance for application research in many fields, including multi-valued digital logic circuit design. Attached Figure Description

[0024] Figure 1 This is a circuit structure diagram of the single-variable logic function F4 implemented by the balanced three-valued single-variable logic circuit based on memristors according to the present invention.

[0025] Figure 2 This is a circuit structure diagram of the single-variable logic function F5 implemented by the balanced three-valued single-variable logic circuit based on memristors according to the present invention.

[0026] Figure 3 This is a circuit structure diagram of the single-variable logic function F9 implemented by the balanced three-valued single-variable logic circuit based on memristors according to the present invention.

[0027] Figure 4 The present invention implements a single-variable logic function F using a memristor-based balanced three-valued single-variable logic circuit. 10 or F 13 The circuit structure diagram.

[0028] Figure 5 The present invention implements a single-variable logic function F using a memristor-based balanced three-valued single-variable logic circuit. 18 The circuit structure diagram.

[0029] Figure 6 The present invention implements a single-variable logic function F using a memristor-based balanced three-valued single-variable logic circuit. 23 or F 26 The circuit structure diagram. Detailed Implementation

[0030] The table below shows the truth tables for all balanced three-valued single-variable logic logic, totaling 3. 3= 27 types, excluding F1 and F2 14 F 27 The three constant logics and the F6 follower logic do not need to be designed; the F6 logic has already been covered in other patents. 16 Upspin logic, F 20 No need to design the downspin logic, and F 19 F 22 F 25 Apart from the three ternary logic NOT operations which require no design, the remaining 18 logic function circuits can all be implemented using a hybrid design of memristors and CMOS. Among them, F... 19 and F 25 The invention patent CN 111667863 A can be found, F 22 It can be found in the invention patent CN111046617 A.

[0031]

[0032] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] In a memristor-based balanced three-valued single-variable logic circuit, the logic state is a voltage value, defined as voltage V. DD 1V corresponds to logic "1"; GND is 0V, corresponding to logic "0"; -V DD It is -1V, corresponding to logic "-1".

[0034] like Figure 1 As shown, the F4 logic circuit consists of a first memristor M1 and a first NMOS transistor T1. The negative terminal of the first memristor M1 is connected to the gate of the first NMOS transistor T1 and serves as the input terminal of the F4 logic circuit; the positive terminal of the first memristor M1 is connected to the drain of the first NMOS transistor T1 and serves as the output terminal F4 of the F4 logic circuit; the source of the first NMOS transistor T1 is connected to the power supply -V. DD Connected.

[0035] For the F4 logic circuit, the threshold voltage of the first NMOS transistor T1 is 1.5V. When input terminal A is connected to -V... DD When the input is grounded (i.e., the input is logic "-1" or logic "0"), the first NMOS transistor T1 is cut off, and the output terminal F4 is directly connected to the input terminal A through the first memristor M1, meaning the outputs correspond to logic "-1" and logic "0" respectively; when the input terminal A is connected to V... DD When the input is logic "1", the first NMOS transistor T1 is turned on, and the output terminal F4 is connected to -V through the first NMOS transistor T1. DD The output is a logical "-1".

[0036] like Figure 2As shown, the F5 logic circuit consists of a second memristor M2, a third memristor M3, and a second NMOS transistor T2. The negative terminal of the second memristor M2 is connected to the gate of the second NMOS transistor T2 and serves as the input terminal of the F5 logic circuit; the positive terminal of the second memristor M2 is connected to the negative terminal of the third memristor M3 and serves as the output terminal F5 of the F5 logic circuit; the positive terminal of the third memristor M3 is connected to the drain of the second NMOS transistor T2; and the source of the second NMOS transistor T2 is connected to the power supply -V. DD Connected.

[0037] For the F5 logic circuit, the threshold voltage of the second NMOS transistor T2 is 1.5V. When input terminal A is connected to -V... DD When the input is grounded (i.e., the input is logic "-1" or logic "0"), the second NMOS transistor T2 is cut off, and the output terminal F5 is directly connected to the input terminal A through the second memristor M2, meaning the outputs correspond to logic "-1" and logic "0" respectively; when the input terminal A is connected to V... DD When the input is logic "1", the second NMOS transistor T2 is turned on, and the current will flow from input terminal A to -V through the second memristor M2 and the third memristor M3. DD Based on the resistance change pattern of the memristors, both the second memristor M2 and the third memristor M3 switch to R at this time. OFF In this state, the output terminal F5 is 0V after being divided by the second memristor M2 and the third memristor M3, and the output is logic "0".

[0038] like Figure 3 As shown, the F9 logic circuit consists of a fourth memristor M4 and a third NMOS transistor T3. The negative terminal of the fourth memristor M4 and the gate of the third NMOS transistor T3 are connected to the power supply V. DD The positive terminal of the fourth memristor M4 is connected to the drain of the third NMOS transistor T3 and serves as the output terminal F9 of the F9 logic circuit; the source of the third NMOS transistor T3 serves as the input terminal of the F9 logic circuit.

[0039] For the F9 logic circuit, the threshold voltage of the third NMOS transistor T3 is 1.5V. When input terminal A is connected to -V... DD When the input is logic "-1", the third NMOS transistor T3 is turned on, and the output terminal F9 is directly connected to the input terminal A through the third NMOS transistor T3, meaning the output corresponds to logic "-1"; when the input terminal A is grounded or V... DD When the input is logic "0" or logic "1", the third NMOS transistor T3 is turned off, and the output terminal F9 is connected to the power supply V through the fourth memristor M4. DD Connected, the output is logic "1".

[0040] like Figure 4 As shown, F 10 Logic circuits and F 13The logic circuit structure is consistent and can be constructed using a fifth memristor M5, a sixth memristor M6, and a fourth NMOS transistor T4. The negative terminal of the fifth memristor M5 is connected to the power supply V. DD Connected; the positive terminal of the fifth memristor M5 and the negative terminal of the sixth memristor M6 are connected to the drain of the fourth NMOS transistor T4, and serve as F. 10 The output terminal F of the logic circuit 10 or F 13 The output terminal F of the logic circuit 13 The gate of the fourth NMOS transistor T4 serves as F. 10 Logic circuits or F 13 The input terminals of the logic circuit; the positive terminal of the sixth memristor M6 and the source terminal of the fourth NMOS transistor T4 are connected to the power supply -V. DD Connected.

[0041] For F 10 In the logic circuit, the threshold voltage of the fourth NMOS transistor T4 is 0.8V. When input terminal A is connected to -V... DD When the input is logic "-1", the fourth NMOS transistor T4 is turned off, and the current will flow from the power supply V through the fifth memristor M5 and the sixth memristor M6. DD Current flows to power supply -V DD Based on the resistance change pattern of the memristors, both the fifth memristor M5 and the sixth memristor M6 switch to R at this time. OFF Status, output terminal F 10 After voltage division by the fifth memristor M5 and the sixth memristor M6, the voltage is 0V, and the output is logic "0"; when input terminal A is grounded or V... DD When the input is logic "0" or logic "1", the fourth NMOS transistor T4 is turned on, and the output terminal F... 10 Connected to -V via the fourth NMOS transistor T4 DD The output is a logical "-1".

[0042] For F 13 Logic circuits, which are related to F 10 The logic circuit structures are the same, but the threshold voltage of the fourth NMOS transistor T4 is 1.5V. When input terminal A is connected to -V... DD When the circuit is grounded, i.e., the input is logic "-1" or logic "0", the fourth NMOS transistor T4 is turned off, and the current will flow from the power supply V through the fifth memristor M5 and the sixth memristor M6. DD Current flows to power supply -V DD Based on the resistance change pattern of the memristors, both the fifth memristor M5 and the sixth memristor M6 switch to R at this time. OFF Status, output terminal F 13 After voltage division by the fifth memristor M5 and the sixth memristor M6, the voltage is 0V, and the output is logic "0"; when input terminal A is connected to V... DDWhen the input is logic "1", the fourth NMOS transistor T4 is turned on, and the output F... 13 Connected to -V via the fourth NMOS transistor T4 DD The output is a logical "-1".

[0043] like Figure 5 As shown, F 18 The logic circuit consists of a seventh memristor M7, an eighth memristor M8, and a fifth NMOS transistor T5. The negative terminal of the seventh memristor M7 and the gate of the fifth NMOS transistor T5 are connected to the power supply V. DD Connected; the positive terminal of the seventh memristor M7 is connected to the negative terminal of the eighth memristor M8, and serves as F. 18 The output terminal F of the logic circuit 18 The positive terminal of the eighth memristor M8 is connected to the drain of the fifth NMOS transistor T5; the source of the fifth NMOS transistor T5 serves as the F... 18 The input terminal of a logic circuit.

[0044] For F 18 In the logic circuit, the threshold voltage of the fifth NMOS transistor T5 is 1.5V. When input terminal A is connected to -V... DD When the input is logic "-1", the fifth NMOS transistor T5 is turned on, and current will flow from the power supply V through the seventh memristor M7 and the eighth memristor M8. DD The current flows to input terminal A. According to the resistance change pattern of the memristors, both the seventh memristor M7 and the eighth memristor M8 switch to R at this time. OFF Status, output terminal F 18 After voltage division by the seventh memristor M7 and the eighth memristor M8, the voltage is 0V, and the output is logic "0"; when input terminal A is grounded or V... DD When the input is logic "0" or logic "1", the fifth NMOS transistor T5 is cut off, and the output terminal F... 18 Through the seventh memristor M7 and V DD Connected, the output is logic "1".

[0045] like Figure 6 As shown, F 23 Logic circuits and F 26 The logic circuit has a consistent structure and can be composed of the ninth memristor M9 and the tenth memristor M. 10 It is composed of the sixth NMOS transistor T6. The negative terminal of the ninth memristor M9 is connected to the power supply V. DD Connected; the positive terminal of the ninth memristor M9 is connected to the tenth memristor M... 10 The negative terminal is connected and serves as F. 23 The output terminal F of the logic circuit 23 or F 26 The output terminal F of the logic circuit 26 ; 10th memristor M 10The positive terminal is connected to the drain of the sixth NMOS transistor T6; the gate of the sixth NMOS transistor T6 serves as F. 23 Logic circuits or F 26 The input terminal of the logic circuit; the source of the sixth NMOS transistor T6 and the power supply -V DD Connected.

[0046] For F 23 In the logic circuit, the threshold voltage of the sixth NMOS transistor T6 is 0.8V. When input terminal A is connected to -V... DD When the input is logic "-1", the sixth NMOS transistor T6 is cut off, and the output F... 23 Through the ninth memristor M9 and V DD When connected, the output is logic "1"; when input A is grounded or V is connected, the output is logic "1"; DD When the input is logic "0" or logic "1", the sixth NMOS transistor T6 is turned on, and current will flow through the ninth memristor M9 and the tenth memristor M1. 10 From power supply V DD Current flows to power supply -V DD According to the resistance change pattern of memristors, at this time, the ninth memristor M9 and the tenth memristor M... 10 Switch all to R OFF Status, output terminal F 23 Through the ninth memristor M9 and the tenth memristor M 10 After voltage division, the voltage is 0V, and the output is logic "0".

[0047] For F 26 Logic circuits, which are related to F 23 The logic circuit structures are the same, but the threshold voltage of the sixth NMOS transistor T6 is 1.5V. When input terminal A is connected to -V... DD When the circuit is grounded, i.e., the input is logic "-1" or logic "0", the sixth NMOS transistor T6 is cut off, and the output terminal F... 26 Through the ninth memristor M9 and V DD When connected, the output is logic "1"; when input A is connected to V... DD When the input is logic "1", the sixth NMOS transistor T6 is turned on, and current will flow through the ninth memristor M9 and the tenth memristor M1. 10 From power supply V DD Current flows to power supply -V DD According to the resistance change pattern of memristors, at this time, the ninth memristor M9 and the tenth memristor M... 10 Switch all to R OFF Status, output terminal F 26 Through the ninth memristor M9 and the tenth memristor M 10 After voltage division, the voltage is 0V, and the output is logic "0".

[0048] For the F2 logic circuit, it consists of F 26It is composed of cascaded logic circuits and F4 logic circuits. 26 The input terminal of the logic circuit serves as the input terminal of the F2 logic circuit; F 26 The output terminal F of the logic circuit 26 It is connected to the input terminal of the F4 logic circuit; the output terminal of the F4 logic circuit serves as the output terminal F2 of the F2 logic circuit.

[0049] When input terminal A is connected to -V DD Or when grounded, F 26 Logic circuit section output terminal F 26 A is logic "1", which is equivalent to inputting logic "1" into the F4 logic circuit section. The output of the F4 logic circuit section is logic "-1", meaning that the output terminal F2 of the F2 logic circuit is logic "-1". When input terminal A is connected to V... DD At that time, F 26 The output of the logic circuit section is logic "0", which is equivalent to inputting logic "0" into the F4 logic circuit section. The output of the F4 logic circuit section is logic "0", which means that the output of the F2 logic circuit is logic "0".

[0050] For the F3 logic circuit, it consists of F 25 Logic circuits and F 19 Cascaded logic circuits. 25 The input terminal of the logic circuit serves as the input terminal of the F3 logic circuit; F 25 The output terminal F of the logic circuit 25 With F 19 The input terminals of the logic circuit are connected; F 19 The output terminal of the logic circuit is used as the output terminal F3 of the F3 logic circuit.

[0051] When input terminal A is connected to -V DD Or when grounded, F 25 Logic circuit section output terminal F 25 The logic value is "1", which is equivalent to sending a signal to F. 19 The logic circuit section inputs logic "1", F 19 The logic circuit output is logic "-1", meaning the output terminal F3 of the F3 logic circuit is logic "-1"; when input terminal A is connected to V... DD At that time, F 25 The output of the logic circuit section is logic "-1", which is equivalent to sending a signal to F. 19 The logic circuit section inputs logic "-1", F 19 The logic circuit output is logic "1", that is, the output terminal F3 of the F3 logic circuit is logic "1".

[0052] The F7 logic circuit is constructed by cascading the F4 and F9 logic circuits. The input terminal of the F4 logic circuit serves as the input terminal of the F7 logic circuit; the output terminal F4 of the F4 logic circuit is connected to the input terminal of the F9 logic circuit; and the output terminal of the F9 logic circuit serves as the output terminal F7 of the F7 logic circuit.

[0053] When input terminal A is connected to -V DD or V DD When the input terminal A is grounded, the output terminal F4 of the F4 logic circuit is logic "-1", which is equivalent to inputting logic "-1" into the F9 logic circuit. The output terminal F9 of the F9 logic circuit is logic "-1", which means that the output terminal F7 of the F7 logic circuit is logic "-1". When the input terminal A is grounded, the output terminal of the F4 logic circuit is logic "0", which is equivalent to inputting logic "0" into the F9 logic circuit. The output terminal F9 of the F9 logic circuit is logic "1", which means that the output terminal F7 of the F7 logic circuit is logic "1".

[0054] For the F8 logic circuit, it consists of F 20 Logic circuits and F 22 Cascaded logic circuits. 20 The input terminals of the logic circuit serve as the input terminals of the F8 logic circuit; F 20 The output terminal F of the logic circuit 20 With F 22 The input terminals of the logic circuit are connected; F 22 The output terminal of the logic circuit is used as the output terminal F8 of the F8 logic circuit.

[0055] When input terminal A is connected to -V DD At that time, F 20 Logic circuit section output terminal F 20 The logic value is "1", which is equivalent to sending a signal to F. 22 The logic circuit section inputs logic "1", F 22 The logic circuit output is logic "-1", meaning the output terminal F8 of the F8 logic circuit is logic "-1"; when input terminal A is grounded, F... 20 The output of the logic circuit section is logic "-1", which is equivalent to sending a signal to F. 22 The logic circuit section inputs logic "-1", F 22 The logic circuit output is logic "1", meaning the output terminal F8 of the F8 logic circuit is logic "1"; when input terminal A is connected to V... DD At that time, F 20 The output of the logic circuit section is logic "0", which is equivalent to sending a signal to F. 22 The logic circuit section inputs logic "0", F 22 The logic circuit output is logic "0", that is, the output terminal F8 of the F8 logic circuit is logic "0".

[0056] For F 11 The logic circuit consists of the F7 logic circuit and the F... 16 Cascaded logic circuits constitute the circuit. The input terminal of the F7 logic circuit serves as the F... 11 The input terminals of the logic circuit; the output terminals of the F7 logic circuit. 16 The input terminals of the logic circuit are connected; F 16 The output of the logic circuit is used as F 11 The output terminal F of the logic circuit 11 .

[0057] When input terminal A is connected to -V DD or V DD At that time, the output terminal F7 of the F7 logic circuit is logic "-1", which is equivalent to sending a signal to F7. 16 The logic circuit section inputs logic "-1", F 16 The logic circuit output is logic "0", i.e., F 11 The output terminal F of the logic circuit 11 The input is logic "0"; when input terminal A is grounded, the output of the F7 logic circuit is logic "1", which is equivalent to sending a signal to F7. 16 The logic circuit section inputs logic "1", F 16 The logic circuit output is logic "-1", i.e., F. 11 The output terminal F of the logic circuit 11 It is a logical "-1".

[0058] For F 12 Logic circuits, which consist of F 16 Logic circuits and F 22 Cascaded logic circuits. 16 The input terminal of the logic circuit is used as F 12 The input terminal of a logic circuit; F 16 The output terminal F of the logic circuit 16 With F 22 The input terminals of the logic circuit are connected; F 22 The output of the logic circuit is used as F 12 The output terminal F of the logic circuit 12 .

[0059] When input terminal A is connected to -V DD At that time, F 16 Logic circuit section output terminal F 16 The logic value is "0", which is equivalent to sending a signal to F. 22 The logic circuit section inputs logic "0", F 22 The logic circuit output is logic "0", i.e., F 12 The output terminal F of the logic circuit 12 The value is logic "0"; when input terminal A is grounded, F16 The output of the logic circuit section is logic "1", which is equivalent to sending a signal to F. 22 The logic circuit section inputs logic "1", F 22 The logic circuit output is logic "-1", i.e., F. 12 The output terminal F of the logic circuit 12 The value is logic "-1"; when input A is connected to V. DD At that time, F 16 The output of the logic circuit section is logic "-1", which is equivalent to sending a signal to F. 22 The logic circuit section inputs logic "-1", F 22 The logic circuit output is logic "1", i.e., F. 12 The output terminal F of the logic circuit 12 It is logical "1".

[0060] For F 15 Logic circuits, which consist of F 25 Logic circuits and F 26 Cascaded logic circuits. 25 The input terminal of the logic circuit is used as F 15 The input terminal of a logic circuit; F 25 The output terminal F of the logic circuit 25 With F 26 The input terminals of the logic circuit are connected; F 26 The output of the logic circuit is used as F 15 The output terminal F of the logic circuit 15 .

[0061] When input terminal A is connected to -V DD Or when grounded, F 25 Logic circuit section output terminal F 25 The logic value is "1", which is equivalent to sending a signal to F. 26 The logic circuit section inputs logic "1", F 26 The logic circuit output is logic "0", i.e., F 15 The output terminal F of the logic circuit 15 The value is logic "0"; when input A is connected to V. DD At that time, F 25 The output of the logic circuit section is logic "-1", which is equivalent to sending a signal to F. 26 The logic circuit section inputs logic "-1", F 26 The logic circuit output is logic "1", i.e., F. 15 The output terminal F of the logic circuit 15 It is logical "1".

[0062] For F 17 The logic circuit consists of the F4 logic circuit and the F... 16Cascaded logic circuits constitute the F4 logic circuit. The input terminal of the F4 logic circuit serves as the F... 17 The input terminals of the logic circuit; the output terminals of the F4 logic circuit, F4 and F... 16 The input terminals of the logic circuit are connected; F 16 The output of the logic circuit is used as F 17 The output terminal F of the logic circuit 17 .

[0063] When input terminal A is connected to -V DD or V DD At that time, the output terminal F4 of the F4 logic circuit is logic "-1", which is equivalent to sending a signal to F4. 16 The logic circuit section inputs logic "-1", F 16 The logic circuit output is logic "0", i.e., F 17 The output terminal F of the logic circuit 17 The logic value is "0"; when input terminal A is grounded, the output terminal of the F4 logic circuit is logic "0", which is equivalent to sending F... 16 The logic circuit section inputs logic "0", F 16 The logic circuit output is logic "1", i.e., F. 17 The output terminal F of the logic circuit 17 It is logical "1".

[0064] For F 21 Logic circuits, which consist of F 16 Logic circuits and F 25 Cascaded logic circuits. 16 The input terminal of the logic circuit is used as F 21 The input terminal of a logic circuit; F 16 The output terminal F of the logic circuit 16 With F 25 The input terminals of the logic circuit are connected; F 25 The output of the logic circuit is used as F 21 The output terminal F of the logic circuit 21 .

[0065] When input terminal A is connected to -V DD At that time, F 16 Logic circuit section output terminal F 16 The logic value is "0", which is equivalent to sending a signal to F. 25 The logic circuit section inputs logic "0", F 25 The logic circuit output is logic "1", i.e., F. 21 The output terminal F of the logic circuit 21 It is logic "1"; when input terminal A is grounded, F 16 The output of the logic circuit section is logic "1", which is equivalent to sending a signal to F. 25 The logic circuit section inputs logic "1", F25 The logic circuit output is logic "-1", i.e., F. 21 The output terminal F of the logic circuit 21 The value is logic "-1"; when input A is connected to V. DD At that time, F 16 The output of the logic circuit section is logic "-1", which is equivalent to sending a signal to F. 25 The logic circuit section inputs logic "-1", F 25 The logic circuit output is logic "1", i.e., F. 21 The output terminal F of the logic circuit 21 It is logical "1".

[0066] For F 24 The logic circuit consists of the F4 logic circuit and the F... 22 Cascaded logic circuits constitute the F4 logic circuit. The input terminal of the F4 logic circuit serves as the F... 24 The input terminals of the logic circuit; the output terminals of the F4 logic circuit, F4 and F... 22 The input terminals of the logic circuit are connected; F 22 The output of the logic circuit is used as F 24 The output terminal F of the logic circuit 24 .

[0067] When input terminal A is connected to -V DD or V DD At that time, the output terminal F4 of the F4 logic circuit is logic "-1", which is equivalent to sending a signal to F4. 22 The logic circuit section inputs logic "-1", F 22 The logic circuit output is logic "1", i.e., F. 24 The output terminal F of the logic circuit 24 The input is logic "1"; when input terminal A is grounded, the output of the F4 logic circuit is logic "0", which is equivalent to sending a signal to F4. 22 The logic circuit section inputs logic "0", F 22 The logic circuit output is logic "0", i.e., F 24 The output terminal F of the logic circuit 24 It is logic "0".

[0068] Those skilled in the art should recognize that the above embodiments are only used to verify the present invention and are not intended to limit the present invention. Any changes or modifications to the above embodiments that are within the scope of the present invention will fall within the protection scope of the present invention.

Claims

1. A balanced three-valued single-variable logic circuit based on memristors, comprising eighteen types of single-variable logic circuits, characterized in that: The output circuits of logic circuits F4 and F9 each consist of only one memristor and one NMOS transistor; F5, F 10 F 13 F 18 F 23 F 26 The output circuits of F3 and F7 are each composed of two memristors and one NMOS transistor; the output circuits of F2 and F7 are each composed of two memristors and two NMOS transistors; 15 The output circuits are all composed of three memristors and two NMOS transistors; F 17 F 21 F 24 The circuits are all composed of three memristors and three NMOS transistors; F 11 F 12 The output circuits of all models consist of four memristors and four NMOS transistors; the F8 output circuit consists of five memristors and five NMOS transistors. The F4 logic circuit consists of a first memristor. M 1 and the first NMOS transistor T 1. Composition; the first memristor M The negative terminal of 1 is connected to the first NMOS transistor. T The gate of 1 is connected and serves as the input of the F4 logic circuit; the first memristor M The positive terminal of 1 is connected to the first NMOS transistor. T The drain of transistor 1 is connected and serves as the output terminal F4 of the F4 logic circuit; the first NMOS transistor T 1's source and power supply -V DD Connected; For the F4 logic circuit, the first NMOS transistor T The threshold for 1 is 1.5V, when the input terminal... A Connect -V DD When grounded, i.e., the input is logic "-1" or logic "0", the first NMOS transistor... T 1 is cut off, and the output terminal F4 passes through the first memristor. M 1. Directly connected to the input terminal A Connected, meaning the outputs correspond to logic "-1" and logic "0" respectively; when the input terminal... A Connect V DD When the input is logic "1", the first NMOS transistor... T 1 is on, output terminal F 4. Through the first NMOS transistor T 1 connected to -V DD The output is a logical "-1"; The F5 logic circuit consists of a second memristor. M 2. Third memristor M 3 and the second NMOS transistor T 2. Composition; the second memristor M The negative terminal of 2 and the second NMOS transistor T The gate of 2 is connected and serves as the input of the F5 logic circuit; the second memristor M The positive terminal of 2 and the third memristor M The negative terminal of 3 is connected and serves as the output terminal F5 of the F5 logic circuit; the third memristor M The positive terminal of 3 and the second NMOS transistor T The drains of transistor 2 are connected; the second NMOS transistor T 2's source and power supply -V DD Connected; For the F5 logic circuit, the second NMOS transistor T The threshold for 2 is 1.5V, when the input terminal... A Connect -V DD When grounded, i.e., when the input is logic "-1" or logic "0", the second NMOS transistor... T 2 is cut off, and the output terminal F5 passes through the second memristor. M 2. Directly connected to the input terminal A Connected, meaning the outputs correspond to logic "-1" and logic "0" respectively; when the input terminal... A Connect V DD When the input is logic "1", the second NMOS transistor... T When the second memristor is turned on, current will flow through the second memristor. M 2 and the third memristor M 3 From the input terminal A Flow to -V DD According to the resistance change pattern of the memristor, the second memristor at this time... M 2 and the third memristor M All 3 are switched to R OFF In this state, the output terminal F5 passes through the second memristor. M 2 and the third memristor M After a 3-voltage divider, the voltage is 0V, and the output is logic "0". The F9 logic circuit consists of a fourth memristor. M 4 and the third NMOS transistor T 3. Composition; the fourth memristor M 4's negative terminal and the third NMOS transistor T 3's gate and power supply V DD Connected; Fourth memristor M 4's positive terminal and the third NMOS transistor T The drain of transistor 3 is connected and serves as the output terminal F9 of the F9 logic circuit; the third NMOS transistor... T The source of 3 is used as the input terminal of the F9 logic circuit; For the F9 logic circuit, the third NMOS transistor T The threshold for 3 is 1.5V, when the input terminal... A Connect -V DD When the input is logic "-1", the third NMOS transistor... T When 3 is turned on, the output terminal F9 is connected to the third NMOS transistor. T 3. Directly connected to the input terminal A Connected, meaning the output corresponds to logic "-1"; when the input is connected... A Ground or V DD When the input is logic "0" or logic "1", the third NMOS transistor... T 3 is cut off, and the output terminal F9 passes through the fourth memristor. M 4 with power supply V DD Connected, the output is logic "1"; The F 10 Logic circuits and F 13 The logic circuit has the same structure, consisting of a fifth memristor. M 5. Sixth memory resistor M 6 and the fourth NMOS transistor T 4. Composition; Fifth memristor M 5's negative terminal is connected to the power supply V DD Connected; Fifth memristor M 5's positive terminal, the sixth memristor M The negative terminal of 6 and the fourth NMOS transistor T The drain of 4 is connected and serves as F. 10 The output terminal F of the logic circuit 10 or F 13 The output terminal F of the logic circuit 13 Fourth NMOS transistor T 4's gate as F 10 Logic circuits or F 13 Input terminal of logic circuit; sixth memristor M The positive terminal of 6 and the fourth NMOS transistor T 4's source and power supply -V DD Connected; For F 10 Logic circuit, fourth NMOS transistor T The threshold for 4 is 0.8V, when the input terminal A Connect -V DD When the input is logic "-1", the fourth NMOS transistor... T When the circuit 4 is cut off, the current will flow through the fifth memristor. M 5 and 6 memristors M 6 from power supply V DD Flow to power supply -V DD According to the resistance change pattern of the memristor, the fifth memristor at this time... M 5 and 6 memristors M All 6 are switched to R OFF Status, output terminal F 10 via the fifth memristor M 5 and 6 memristors M After a 6-voltage divider, the voltage is 0V, and the output is logic "0"; when the input terminal... A Ground or V DD When the input is logic "0" or logic "1", the fourth NMOS transistor... T 4 is on, output terminal F 10 Through the fourth NMOS transistor T 4 connected to -V DD The output is a logical "-1"; The F 18 The logic circuit consists of a seventh memristor. M 7. Eighth memristor M 8 and the fifth NMOS transistor T 5 components; Seventh memristor M The negative terminal of 7 and the gate of the fifth NMOS transistor T5 are connected to the power supply V. DD Connected; Seventh memristor M The positive terminal of 7 and the eighth memristor M The negative terminal of 8 is connected and used as F. 18 The output terminal F of the logic circuit 18 Eighth memristor M The positive terminal of 8 and the fifth NMOS transistor T The drain of 5 is connected; the fifth NMOS transistor T The source of 5 is F 18 The input terminal of a logic circuit; For F 18 Logic circuit, fifth NMOS transistor T The threshold for 5V is 1.5V, when the input terminal... A Connect -V DD When the input is logic "-1", the fifth NMOS transistor... T When circuit 5 is turned on, current will flow through the seventh memristor. M 7 and 8 memristors M 8 from power supply V DD Flow to input terminal A According to the resistance change pattern of the memristor, the seventh memristor at this time... M 7 and 8 memristors M All 8 are switched to R OFF Status, output terminal F 18 via the seventh memristor M 7 and 8 memristors M After being divided by 8, the voltage is 0V, and the output is logic "0"; when the input terminal... A Ground or V DD When the input is logic "0" or logic "1", the fifth NMOS transistor... T 5 is cut off, output terminal F 18 Through the seventh memristor M 7 and V DD Connected, the output is logic "1"; The F 23 Logic circuits and F 26 The logic circuit has the same structure, consisting of the ninth memristor. M 9. Tenth Memory Resistor M 10 and the sixth NMOS transistor T Composition 6; Ninth memristor M 9's negative terminal is connected to the power supply V DD Connected; Ninth memristor M The positive terminal of 9 and the tenth memristor M 10 The negative terminal is connected and serves as F. 23 The output terminal F of the logic circuit 23 or F 26 The output terminal F of the logic circuit 26 ; 10th memory resistor M 10 The positive electrode and the sixth NMOS transistor T The drains of transistor 6 are connected; the sixth NMOS transistor T The gate of 6 is used as F 23 Logic circuits or F 26 The input terminal of the logic circuit; the sixth NMOS transistor T 6's source and power supply -V DD Connected; For F 23 Logic circuit, sixth NMOS transistor T The threshold for 6 is 0.8V, when the input terminal A Connect -V DD When the input is logic "-1", the sixth NMOS transistor... T 6 is cut off, output terminal F 23 Through the ninth memristor M 9 and V DD When connected, the output is logic "1"; when the input is connected... A Ground or V DD When the input is logic "0" or logic "1", the sixth NMOS transistor... T When 6 is turned on, current will flow through the ninth memristor. M 9 and 10 memory resistors M 10 From power supply V DD Flow to power supply -V DD According to the resistance change pattern of the memristor, the ninth memristor at this time... M 9 and 10 memory resistors M 10 All switched to R OFF Status, output terminal F 23 via the ninth memristor M 9 and 10 memory resistors M 10 After voltage division, the voltage is 0V, and the output is logic "0".

2. The balanced three-valued single-variable logic circuit based on memristors according to claim 1, characterized in that: The F2 logic circuit consists of F 26 The logic circuit and the F4 logic circuit are cascaded together; F 26 The input terminal of the logic circuit serves as the input terminal of the F2 logic circuit; F 26 The output terminal F of the logic circuit 26 It is connected to the input terminal of the F4 logic circuit; the output terminal of the F4 logic circuit serves as the output terminal F2 of the F2 logic circuit. The F3 logic circuit is composed of F 25 Logic circuits and F 19 Cascaded logic circuits; F 25 The input terminal of the logic circuit serves as the input terminal of the F3 logic circuit; F 25 The output terminal F of the logic circuit 25 With F 19 The input terminals of the logic circuit are connected; F 19 The output terminal of the logic circuit is used as the output terminal F3 of the F3 logic circuit. The F7 logic circuit is composed of cascaded F4 and F9 logic circuits; the input terminal of the F4 logic circuit serves as the input terminal of the F7 logic circuit; the output terminal F4 of the F4 logic circuit is connected to the input terminal of the F9 logic circuit; and the output terminal of the F9 logic circuit serves as the output terminal F7 of the F7 logic circuit. The F8 logic circuit consists of F 20 Logic circuits and F 22 Cascaded logic circuits; F 20 The input terminals of the logic circuit serve as the input terminals of the F8 logic circuit; F 20 The output terminal F of the logic circuit 20 With F 22 The input terminals of the logic circuit are connected; F 22 The output terminal of the logic circuit is used as the output terminal F8 of the F8 logic circuit. The F 11 The logic circuit consists of the F7 logic circuit and F... 16 Cascaded logic circuits constitute the F7 logic circuit; the input terminal of the F7 logic circuit serves as the F7 logic circuit. 11 The input terminals of the logic circuit; the output terminals of the F7 logic circuit. 16 The input terminals of the logic circuit are connected; F 16 The output of the logic circuit is used as F 11 The output terminal F of the logic circuit 11 ; The F 12 The logic circuit consists of F 16 Logic circuits and F 22 Cascaded logic circuits; F 16 The input terminal of the logic circuit is used as F 12 The input terminal of a logic circuit; F 16 The output terminal F of the logic circuit 16 With F 22 The input terminals of the logic circuit are connected; F 22 The output of the logic circuit is used as F 12 The output terminal F of the logic circuit 12 ; The F 15 The logic circuit consists of F 25 Logic circuits and F 26 Cascaded logic circuits; F 25 The input terminal of the logic circuit is used as F 15 The input terminal of a logic circuit; F 25 The output terminal F of the logic circuit 25 With F 26 The input terminals of the logic circuit are connected; F 26 The output of the logic circuit is used as F 15 The output terminal F of the logic circuit 15 ; The F 17 The logic circuit consists of the F4 logic circuit and F... 16 Cascaded logic circuits constitute the F4 logic circuit; the input terminal of the F4 logic circuit serves as the F... 17 The input terminals of the logic circuit; the output terminals of the F4 logic circuit, F4 and F... 16 The input terminals of the logic circuit are connected; F 16 The output of the logic circuit is used as F 17 The output terminal F of the logic circuit 17 ; The F 21 The logic circuit consists of F 16 Logic circuits and F 25 Cascaded logic circuits; F 16 The input terminal of the logic circuit is used as F 21 The input terminal of a logic circuit; F 16 The output terminal F of the logic circuit 16 With F 25 The input terminals of the logic circuit are connected; F 25 The output of the logic circuit is used as F 21 The output terminal F of the logic circuit 21 ; The F 24 The logic circuit consists of the F4 logic circuit and F... 22 Cascaded logic circuits constitute the F4 logic circuit; the input terminal of the F4 logic circuit serves as the F... 24 The input terminals of the logic circuit; the output terminals of the F4 logic circuit, F4 and F... 22 The input terminals of the logic circuit are connected; F 22 The output of the logic circuit is used as F 24 The output terminal F of the logic circuit 24 .

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