Process integration method for selective metal via fill

Abstract

Methods and apparatus for forming an interconnect structure on a substrate and methods of forming the interconnect structure on the substrate. In embodiments, the methods include the steps of etching through a hard mask disposed on top of a low-k dielectric layer to form a via through the low-k dielectric layer and to expose a conductive surface; contacting the conductive surface with a dilute hydrofluoric acid to remove contaminants from the conductive surface; removing the hard mask disposed on top of the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

Description

Technical Field

[0001] Implementations of this disclosure generally relate to improved methods of forming interconnect structures. Background Technology

[0002] Reliably manufacturing features smaller than 100 nm is one of the key technological challenges for next-generation very large-scale integration (VLSI) and extremely large-scale integration (ULSI) in semiconductor devices. However, driven by the limits of circuit technology, the shrinking scale of VLSI and ULSI technologies has created additional demands on processing power. Reliably forming gate structures on substrates is crucial for the success of VLSI and ULSI and for ongoing efforts to increase the circuit density and quality of individual substrates and dies.

[0003] As the circuit density of next-generation devices increases, the width of interconnect structures (such as vias, trenches, contacts, gate structures, and other features) and the dielectric material between them decreases to scales of 45nm and 32nm or smaller, while the thickness of the dielectric layer remains substantially constant. This results in an increased aspect ratio for the features. To allow the fabrication of next-generation devices and structures, three-dimensional (3D) stacking of semiconductor chips is typically used to improve transistor performance. By arranging transistors in a three-dimensional manner instead of the conventional two-dimensional manner, multiple transistors can be placed very close to each other in an integrated circuit (IC). 3D stacking of semiconductor chips reduces wire length and maintains low wiring delay. During manufacturing, 3D stacking (stepped structures) of semiconductor chips is typically used to allow multiple interconnect structures to be placed on top, thereby forming high-density vertical transistor devices.

[0004] Furthermore, the conductive surfaces (e.g., copper or cobalt surfaces) formed at the bottom of the vias during the stacking process are typically contaminated by etching byproducts and residues formed during via opening and subsequent removal of the hard metal mask. While large particles can be removed by subsequent dry cleaning processes, dry cleaning processes cannot remove atomic-level contaminants from etching-related elements (e.g., oxygen, fluorine, and carbon) or from oxidation caused by air exposure on the conductive interconnect surfaces.

[0005] Generally, wet cleaning methods can remove fluorine, oxygen, and carbon contaminants. However, the inventors have observed that these techniques cannot be used in newer back-end of the line (BEOL) processes due to compatibility issues with low-k dielectrics and recent stringent requirements for low-k damage (e.g., carbon depletion). Therefore, post-via etching cleaning techniques remain necessary to improve electrical performance.

[0006] Furthermore, the inventors have observed that conventional via formation results in high resistance due to the materials used in the process integration. For example, filling vias and trenches connected to them with the same material results in high interconnect resistance, which can undesirably lead to resistive-capacitive delay (RC delay) and voltage drop (IR drop) in the semiconductor chip. Additionally, the positioning of barrier and pad layers can lead to high resistivity, resulting in high via resistance, for example, when deposited at the bottom of the via.

[0007] Therefore, there is a continuous need to improve the methods for forming interconnect structures in order to reduce the manufacturing cost, memory cell size, and power consumption of integrated circuits. Summary of the Invention

[0008] This document provides methods and apparatus for forming interconnect structures. In some embodiments, a method for forming an interconnect structure includes the steps of: etching through a hard mask disposed on top of a low-k dielectric layer to form vias through the low-k dielectric layer and exposing a conductive surface; contacting the conductive surface with diluted hydrofluoric acid to remove contaminants from the conductive surface; removing the hard mask disposed on top of the low-k dielectric layer; and applying remote hydrogen plasma to the conductive surface to form exposed portions of the conductive surface.

[0009] In some embodiments, a method of forming an interconnect structure includes the following steps: forming vias and trenches in a film stack including a hard mask and a dielectric layer disposed on a substrate to expose a conductive surface; contacting the conductive surface with diluted hydrofluoric acid; removing the hard mask; applying remote plasma to the conductive surface to form an exposed portion of the conductive surface; depositing a first metal of a first type in the vias; depositing a barrier layer on the exposed surface of the first metal and the trench; depositing a pad layer on the barrier layer; and filling the trench with a second metal different from the first metal.

[0010] In some embodiments, a non-transitory computer-readable medium is provided having instructions stored thereon that, when executed, cause a method for forming an interconnect structure to be performed. This method may be described as in any of the embodiments disclosed herein. In some embodiments, the method includes the steps of: etching through a hard mask disposed on top of a low-k dielectric layer to form vias through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with diluted hydrofluoric acid to remove contaminants from the conductive surface; removing the hard mask disposed on top of the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

[0011] Other and additional embodiments of this disclosure are described below. Attached Figure Description

[0012] Embodiments of this disclosure can be understood by referring to the illustrative embodiments depicted in the accompanying drawings, which have been briefly summarized above and are discussed in more detail below. However, the drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting the scope, as other equally effective embodiments are permissible with respect to this disclosure.

[0013] Figure 1 A method for forming an interconnect structure according to one embodiment of the present disclosure is illustrated.

[0014] Figures 2A-2K This illustration depicts one embodiment of the invention based on the present disclosure. Figure 1 Side cross-sectional views of interconnect structures formed on the substrate at different stages of the method.

[0015] Figure 3 A multi-chamber processing system according to one embodiment of the present disclosure is illustrated. Figure 1 The method can be implemented on this processing system.

[0016] Figure 4 A method for forming an interconnect structure according to one embodiment of the present disclosure is illustrated.

[0017] Figure 5 A method for forming an interconnect structure according to one embodiment of the present disclosure is illustrated.

[0018] To facilitate understanding, the same reference numerals have been used as much as possible to identify common components in the figures. The figures are not drawn to scale and may be simplified for clarity. Components and features of one embodiment may advantageously be incorporated into other embodiments without further detail. Detailed Implementation

[0019] This document provides methods for processing substrates. Embodiments of this disclosure advantageously facilitate cleaning and / or reducing (e.g., partial or complete removal of oxygen) conductive interconnect surfaces while maintaining low-k integrity, conductivity, and reliability of the IC interconnect structure. In embodiments, varying the materials used in vias and trenches connected to the vias reduces or eliminates RC delay and IR drop in the semiconductor chip. Furthermore, placing barrier layers and padding layers between the vias and the trenches connected to the vias reduces via resistance. The methods of this disclosure can be used to form metal interconnect structures in integrated circuits, or for gap-filling processes to form metal gates or metal contacts, and for other suitable applications where metal cleaning or reduction can be performed in via holes.

[0020] Figure 1A flowchart depicts a method 100 for processing a substrate according to some embodiments of this disclosure. The following describes such a method... Figures 2A-2K The method 100 for describing the stages of processing the substrate, as depicted in the document. Figures 2A-2K Drawn in Figure 1 Cross-sectional views of the substrate before and at different stages of method 100, and, for example, in a suitable reactor (e.g., hereinafter referred to as...). Figure 3 Method 100 is performed in the described reactor. Exemplary processing systems that can be used to perform the methods disclosed herein may include (but are not limited to) equipment available from Applied Materials Inc., Santa Clara, California. or Any of the processing system lines. Other processing chambers (including those available from other manufacturers) may also be used in conjunction with the teachings provided herein.

[0021] Figure 2A A cross-sectional view of the interconnect structure 200 is shown before the start of method 100. Generally, the interconnect structure 200 includes multiple film layers that can be used to form an interconnect structure, such as a dual damascene structure. A film stack 201 is formed on a substrate 202. The film stack 201 includes a second dielectric layer 204. Figure 2A The second dielectric layer 204 shown is disposed on the substrate 202, and has a conductive layer 206 formed in the second dielectric layer 204 and bounded by the second dielectric layer. In one example, the second dielectric layer 204 may be formed of one or more insulating materials (e.g., silicon oxide). In one example, the conductive layer 206 may be formed of a conductive layer such as copper or cobalt.

[0022] Back Figure 1 At block 102, a dielectric barrier layer 208 may optionally be deposited on substrate 202, such as... Figure 2B As illustrated, for example, a dielectric barrier layer 208 is deposited over the second dielectric layer 204 and the conductive layer 206. Therefore, the dielectric barrier layer 208 can form a uniform, uninterrupted layer over the second dielectric layer 204 and the conductive layer 206. The dielectric barrier layer can be formed of a low-k material. For example, the dielectric barrier layer 208 can be formed of a silicon carbide layer (SiC), a nitrogen-doped silicon carbide layer (SiCN), a silicon nitride layer, a metal nitride, or a metal oxide (e.g., AlN, AlOx, AlON), etc.

[0023] Referring to block 104, dielectric layer 210 is deposited on substrate 202, as follows. Figure 2CAs illustrated, for example, as illustrated, dielectric layer 210 is deposited over dielectric barrier layer 208. Dielectric layer 210 may be substantially similar to the second dielectric layer 204. In one embodiment, dielectric layer 210 may be formed of the same material as the second dielectric layer 204. In another embodiment, dielectric layer 210 may be formed of a different material than the second dielectric layer 204 while maintaining the same low-k properties. In another example, dielectric layer 210 may be formed of a low-k material (e.g., a material having a dielectric constant less than silicon oxide or less than about 3.9), etc. In embodiments, dielectric layer 210 is a dense material, such as Black available from Applied Materials Ltd. Brand 1 low-k material.

[0024] Referring now to block 105, the hard mask 211 is placed on top of the dielectric layer 210, which can be a low-k dielectric layer, as follows. Figure 2D As illustrated, for example, as shown, a hard mask 211 is deposited over the dielectric layer 210. In one embodiment, the hard mask 211 can be formed of any suitable hard mask material. Therefore, the hard mask 211 can form a uniform, uninterrupted layer directly on top of the dielectric layer 210 and over the conductive layer 206. In embodiments, the hard mask 211 is a dielectric material (e.g., SiO2, SiCO, SiON, or SiC), an intermetallic / metallic material (e.g., TiN or Ti), or a combination of a dielectric material and an intermetallic / metallic material. In some embodiments, the hard mask 211 is a layer formed of titanium nitride (TiN) or tantalum nitride (TaN). In embodiments, the hard mask 211 has a thickness of 15 to 25 nanometers.

[0025] At block 106, one or more vias 212 are formed in the interconnect structure 200 to expose the conductive layer 206, such as Figure 2E As illustrated in the diagram. For example, via 212 can be formed through a hard mask 211, a dielectric layer 210, and an optional dielectric barrier layer (e.g., dielectric barrier layer 208) to expose the underlying conductive layer 206. In embodiments, this disclosure includes the step of etching through a hard mask 211 disposed on top of a low-k dielectric layer (e.g., dielectric layer 210) to form a via 212 through the low-k dielectric layer and expose the conductive surface (e.g., conductive layer 206). Generally, via 212 has a width W1. In some embodiments, the width of each via 212 is uniform along the entire length of the via 212. In other embodiments, the width of each via 212 can gradually change from the top to the bottom of the via 212. In embodiments, via 212 has a high aspect ratio.

[0026] At block 108, one or more trenches 214 are formed in the interconnect structure 200, such as Figure 2F As illustrated in the figure. The one or more trenches 214 can be formed through the rigid mask 211 and into the dielectric layer 210. In some embodiments, the one or more trenches 214 are configured to widen at least a portion of the via 212. In some embodiments, block 108 can be performed before block 106, i.e., the trenches 214 can be formed before the via 212. In other embodiments, the one or more trenches 214 are formed after the via 212 or one or more vias are formed.

[0027] Embodiments of this disclosure include selective filling methods (e.g., copper or tungsten filling methods) that exhibit lower via resistance while meeting integration and reliability requirements. Interface processing (discussed below in conjunction with at least block 110) and filling processes (discussed below in conjunction with at least block 118) have been developed to selectively grow a metallic material (e.g., Cu or W) from the bottom of the via without damaging the underlying metal layer (e.g., Cu, W, Co, etc.) and the surrounding dielectric (e.g., low-k dielectric, oxide, etc.). As a result, the following discussion provides one or more techniques for reducing via resistance. In embodiments, after via filling, a mosaic fill is performed, which helps to form equal line resistance.

[0028] In one implementation, method 100 includes the following steps: at block 110, performing one or more preprocessing processes on interconnect structure 200 to prepare interconnect structure 200 to receive selective metal vias (e.g., via 212) filling. For example, block 110 may include sub-blocks 112-116.

[0029] At sub-block 112, the interconnect structure 200 undergoes a first processing step for the exposed portion 213 of the conductive surface of the conductive layer 206 in the via 212. For example, the first pretreatment process prepares the exposed portion 213 of the conductive layer 206 for bottom-up growth during bottom-up deposition of the via 212 with a first metal. In one embodiment, the exposed portion 213 of the conductive layer 206 in the via 212 is contacted with diluted hydrofluoric acid (DHF) under conditions suitable for contaminant removal. For example, the conductive surface (e.g., exposed portion 213) is contacted with diluted hydrofluoric acid to remove contaminants removed from the conductive surface. In one embodiment, the diluted hydrofluoric acid (DHF) treatment involves applying HF in the form of a diluted buffered oxide etchant (BOE) to the conductive surface. The diluted hydrofluoric acid (DHF) treatment can be performed by filling a container with diluted hydrofluoric acid (DHF) and then immersing the interconnect structure 200 in the container. To prevent streaking, the interconnect structure 200 should be quickly immersed in the HF bath. In one embodiment, diluted hydrofluoric acid (DHF) is used to strip oxides, thereby removing metals with a lower electronegativity than silicon. In another embodiment, the interconnect structure 200, including the membrane stack, is treated for a duration of approximately 30 to 60 seconds before the solution is rapidly poured into a discharge tank or recovery unit. In another embodiment, the diluted hydrofluoric acid has a pH value of 2-4, approximately 3, or 3. In another embodiment, the diluted hydrofluoric acid has a molar concentration of 0.01-0.5 M. In another embodiment, the diluted hydrofluoric acid is applied to the membrane stack at room temperature for a duration of 10 to 30 seconds, or 10 to 20 seconds.

[0030] Back Figure 1 and Figure 2GFollowing a first processing step for the exposed portion 213 of the conductive layer 206 in the via, a hard mask is removed at block 114. In one embodiment, the hard mask is removed by a wet etching removal process, whereby the hard mask is contacted with a wet etching solution under conditions suitable for removing the hard mask material. In another embodiment, the hard mask disposed on top of a low-k dielectric layer (e.g., dielectric layer 210) is removed. In some embodiments, the hard mask is removed by contacting it with a removal composition for removing the hard mask. In one embodiment, the removal composition is a wet etching solution that removes the metallic hard mask on the dielectric layer without corroding the exposed portion 213 of the conductive layer 206 in the via and without corroding the dielectric layer 210. In some embodiments, the hard mask is removed by contacting it with an alkaline chemical containing peroxide (e.g., H₂O₂) (high pH value, e.g., pH 9-11) under conditions suitable for stripping the hard mask. In one embodiment, the removal composition is a wet etch solution for removing a titanium nitride hard mask. In another embodiment, the removal composition is a wet etch solution for removing a TaN hard mask. In yet another embodiment, the removal composition includes a corrosion inhibitor to prevent oxidation activity toward the exposed portion 213 of the conductive layer 206. In some embodiments, a metal corrosion inhibitor is provided to prevent oxidation of copper, cobalt, and / or other metals suitable for use as the conductive layer 206. Non-limiting examples of metal corrosion inhibitors include 5-amino-1,3,4-thiadiazole-2-thiol (ATDT), benzotriazole (BTA), 1,2,4-triazole (TAZ), tolyltriazole, 5-methyl-benzotriazole (MBTA), and the like. In one embodiment, the hard mask 211 (e.g., TiN or TaN) is removed without leaving any hard mask material on the dielectric layer 210. In some embodiments, the non-limiting wet etch solution used herein includes those from BASF. S-series brand solutions.

[0031] Still refer to Figure 1After the hard mask is removed, a plasma cleaning process is applied to the exposed portion of the conductive layer in the via at block 116. In embodiments, a remote plasma cleaning process can be used to process the interconnect structure after the hard mask is removed. For example, a remote hydrogen plasma can be applied to the conductive surface to form an exposed portion of the conductive surface, where oxides are removed, for example, from the exposed portion or exposed surface. In embodiments, plasma cleaning includes, for example, low-density hydrogen plasma cleaning under conditions suitable for removing metal oxides (e.g., copper oxide) from the exposed portion 213 of the conductive layer 206. In some embodiments, the interconnect structure 200 can be conveyed to a processing chamber where it undergoes a plasma cleaning process. For example, the interconnect structure can undergo a cleaning process at a pressure of about 1-10 Torr, using H2 or hydrogen radicals, and at a temperature between about 150-250°C. In other embodiments, a small bias energy can be applied to promote oxide removal without metal sputtering. For example, 0-200 W of energy can be applied to a pretreatment chamber. In some embodiments, alcohols (e.g., methanol and / or ethanol) may also be applied under conditions suitable for removing metal oxides (e.g., copper oxide) from the exposed portion 213 of the conductive layer 206. For example, in conjunction with a remote plasma cleaning process used to process interconnect structures after hard mask removal, the interconnect structures may be contacted with ethanol and / or methanol in a hot immersion solution at a temperature of 150-250°C. In embodiments, the hot alcohol immersion solution is applied for 30 seconds to 1 hour.

[0032] In one embodiment, a suitable chamber for a plasma cleaning process according to this disclosure includes, for example, those available from Applied Materials Ltd. CuBS (Copper Barrier / Seedling System) Preclean (“APC”) chamber. In embodiments, the plasma cleaning process applicable herein provides a harmless and efficient cleaning process for metal low-k interconnect structures used in 28nm generation and below nodes to remove polymerization residues and / or metal oxides (e.g., copper oxide (“CuO”)). In embodiments, the APC is designed to effectively remove polymerization residues and reduce CuO deposits while preserving the integrity of porous low-k and ultra-low-k inter-level dielectric (“ILD”) films.

[0033] Back Figure 1 Following method 100 at block 110 (where one or more preprocessing steps are performed on interconnect structure 200 to prepare interconnect structure 200 for receiving selective metal vias (e.g., via 212) filling), a first metal layer is deposited in the one or more vias, as shown at block 118. At block 118, the first metal 220 selectively fills via 212, as shown... Figure 2H As illustrated in the diagram. For example, a first metal 220 material is deposited in the via 212 to point 222, where the via 212 meets the trench 214. The first metal 220 used can be any suitable metallic material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), etc. In some embodiments, the first metal 220 is a different material from the subsequent metal deposited in the trench 214. Selectively depositing the first metal 220 in the via helps reduce via resistance and meet reliability and line resistance requirements.

[0034] The first metal 220 can be deposited using a chemical vapor deposition (CVD) process. In embodiments, a suitable CVD process for use herein may include H2 pre-immersion at high temperatures (e.g., 350-500°C). In some embodiments, the CVD process can be performed at a temperature of approximately 200-500°C using a metal-containing precursor (e.g., WF6) at a low flow rate (e.g., 2-100 sccm) in a wide H2 environment. In embodiments, the metal-containing precursor is pre-selected to form at least one of ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), and copper (Cu) in the vias. The combination of flow rate, pressure, and temperature helps to reduce the morphology of the first metal 220 during deposition. A conventional nucleation layer may be applied for initial nucleation of 1-3 nm prior to the deposition of the first metal 220 material. The overall growth is controlled by process time, pressure, and precursor flow rate to uniformly fill the vias 212.

[0035] In some embodiments, method 100 may include an optional block (e.g., block 119) performed before depositing an additional layer or a second metal 224. At block 119, the interconnect structure 200 may undergo a pretreatment process before the second metal 224. In some embodiments, the process of this disclosure may include a process sequence at block 119, wherein the top surface of the metal-filled via undergoes an optional post-deposition cleaning. For example, optional cleaning may be used where there is oxidation or residue growth at the top surface of via 212 (e.g., at an exposed surface, such as at point 222 where via 212 meets trench 214). In embodiments, the optional pretreatment cleaning uses a peroxide (H2O2)-containing chemical with an alkaline pH adjustment to lightly strip away residue. In some embodiments, a plasma cleaning process may be performed before depositing an additional layer or a second metal 224. For example, plasma cleaning may optionally include the use of materials available from Applied Materials Ltd. The preclean (“APC”) chamber provides a harmless and efficient cleaning process for removing metal oxides or native oxides formed on top of the first metal 220 (or its exposed portion) filling the via 212. For example, if the via is filled with copper, a plasma cleaning step can be applied to remove copper oxide (“CuO”) at the point 222 where the via 212 meets the trench 214.

[0036] Refer to block 120 Figure 1 and Figure 2I One or more barrier layers 235 may be used to cover the trench 214. For example, barrier layers 235 may cover the sidewalls 251 of the trench, the bottom surface 252 of the trench (including the exposed metal surface 253 of the via 212). Barrier layer 216 may be used to prevent subsequently deposited metal from diffusing into the underlying layer (e.g., dielectric layer 210). Barrier layer 235 may include any material suitable for acting as a barrier. For example, in some embodiments, barrier layer 235 may include metals such as titanium (Ti), tantalum (Ta), cobalt (Co) (e.g., CVD-deposited cobalt), manganese (Mn), tungsten (W), hafnium (Hf), alloys of the above, etc., or in some embodiments may include metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc. Barrier layer 235 may have any thickness suitable for preventing subsequently deposited metal layer material from diffusing into the underlying layer. For example, in some embodiments, barrier layer 235 may have a thickness of about 10 to about 20 angstroms, or 10 to 15 angstroms. The barrier layer 235 can be formed by any process suitable for providing a barrier layer 235 with a suitable thickness. For example, in some embodiments, the barrier layer 235 can be formed via a deposition process, such as chemical vapor deposition, physical vapor deposition, or cyclic deposition processes, for example, atomic layer deposition, etc. In embodiments, the barrier layer 235 includes one of more TaN layers deposited by an atomic layer deposition (ALD) process. In embodiments, the ALD process can deposit TaN to form the barrier layer 235, or one or more layers of the barrier layer 235, to a thickness sufficient to serve as a barrier layer. In embodiments, the barrier layer 235 includes a layer of material conformally deposited on top of the inner trench surface.

[0037] Refer to block 170 Figure 1 and Figure 2JThe barrier layer 235 can be overlaid within one or more pad layers (e.g., pad layer 236). In some embodiments, the interconnect structure 200 may include a pad layer 236 comprising cobalt disposed on top of the barrier layer 235. In embodiments, the pad layer 236 can be formed by a CVD or PVD process performed in a processing chamber to provide a pad layer of predetermined thickness above the surface of the barrier layer within a trench. In embodiments, the pad layer 236 is a cobalt layer deposited on top of the sidewalls and bottom surface of the trench via a physical vapor deposition (PVD) process. In embodiments, the pad layer is deposited to a thickness of 20 to 40 angstroms (e.g., 30 angstroms). In embodiments, the pad layer is cobalt deposited to a thickness of 20 to 40 angstroms (e.g., 30 angstroms). In some embodiments, the pad layer 236, for example a cobalt layer, is conformally deposited to overlay the barrier layer 235.

[0038] Return to block 180 Figure 1 and Figure 2K A second metal 224 is deposited in each trench 214. For example, the second metal 224 is deposited on top of the pad layer 236, reaching the top of the trench 214. The second metal 224 used can be any suitable metallic material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), etc. In some embodiments, the second metal 224 is a different material from the first metal 220 deposited in the via 212. In some embodiments, the second metal 224 is the same material as the first metal 220 deposited in the via 212. In embodiments, a CVD process can be used to deposit the second metal 224. Dividing a conventional metal-filled single-metal material into a multi-step process helps reduce the resistance through the via 212, which involves the first metal 220 deposited in the via 212, the second metal 224 deposited in the trench 214, and a barrier layer / pad layer disposed between the first metal 220 and the second metal 224.

[0039] Still refer to Figure 2K The capping layer 271 can be deposited on top of the second metal, as shown in optional block 190. In an embodiment, the capping layer includes cobalt, ruthenium, or other suitable capping material.

[0040] Figure 3A multi-chamber processing system is illustrated as processing system 300. Processing system 300 may include loading and locking chambers 302 and 304, a robot 306, a transfer chamber 308, processing chambers 310, 312, 314, 316, 318, and 328, and a controller 320. Loading and locking chambers 302 and 304 allow substrates (not shown) to be transferred into and out of processing system 300. Loading and locking chambers 302 and 304 can evacuate substrates introduced into processing system 300 to maintain a vacuum seal. Robot 306 can transfer substrates between loading and locking chambers 302 and 304 and processing chambers 310, 312, 314, 316, 318, and 328. Robot 306 can also transfer substrates between loading and locking chambers 302 and 304 and transfer chamber 308.

[0041] Each processing chamber 310, 312, 314, 316, 318, and 328 can be configured to perform various substrate operations, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), PVD, etching, pre-cleaning, degassing, heating, orientation, or other substrate processes. Furthermore, each processing chamber 310, 312, 314, 316, 318, and 328 can also be configured to deposit a dielectric barrier layer, deposit a dielectric layer, form one or more vias and trenches in a stack, perform one or more pre-cleaning processes, deposit a first metal material layer, deposit a pad layer, deposit a barrier layer, deposit a second metal material layer, or deposit a capping layer.

[0042] The controller 320 can be configured to operate some or all aspects of the processing system 300, including Figure 1 The methods disclosed herein. For example, controller 320 may be configured to control the method of forming interconnect structures on a substrate. Controller 320 includes a programmable central processing unit (CPU) 322 operable with memory 324 and mass storage devices, an input control unit, and a display unit (not shown), as well as various components coupled to the processing system to facilitate control of substrate processing, such as power supplies, clocks, caches, input / output (I / O) circuitry, and pads. Controller 320 also includes hardware for monitoring substrate processing via sensors in processing system 300, including sensors for monitoring precursor, process gas, and purge gas flows. Other sensors measuring system parameters (e.g., substrate temperature, chamber atmospheric pressure, etc.) may also provide information to controller 320.

[0043] To facilitate control of the aforementioned processing system 300, the CPU 322 can be one of any form of general-purpose computer processing system (e.g., a programmable logic controller (PLC)) that can be used in an industrial environment to control various chambers and subprocessors. Memory 324 is coupled to the CPU 322 and is non-transitory, and can be one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disk drive, hard disk, or any other form of digital memory (local or remote). Support circuitry 326 is coupled to the CPU 322 to support the processor in a conventional manner. The generation of charged species, heating, and other processes are generally stored in memory 324 (generally as software routines). Software routines can also be stored and / or executed by a second CPU (not shown), which is located remotely relative to the hardware controlled by the CPU 322.

[0044] Memory 324 is in the form of a computer-readable storage medium containing instructions that, when executed by CPU 322, facilitate the operation of processing system 300. The instructions in memory 324 are in the form of a program product, such as a program implementing the methods of this disclosure. The program code may conform to any of a variety of different programming languages. In one example, this disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program of the program product defines the functionality of the implementation (including the methods described herein). Illustrative computer-readable storage media include (but are not limited to): (i) non-writable storage media (e.g., read-only storage devices within a computer, such as CD-ROM discs readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) where information can be permanently stored; and (ii) writable storage media (e.g., floppy disks within a disk drive, or hard disk drives, or any type of solid-state random access semiconductor memory) where changeable information is stored. Such computer-readable storage media are implementations of this disclosure when carrying computer-readable instructions that direct the functionality of the methods described herein.

[0045] The methods described above are not limited to processing system 300. For example, one or more blocks (e.g., block 120 or block 114) can be executed in a processing chamber outside processing system 300.

[0046] In some embodiments, this disclosure includes a non-transitory computer-readable medium having instructions stored thereon that, when executed, cause a method for forming an interconnect structure, the method comprising the steps of: etching through a hard mask disposed on top of a low-k dielectric layer to form vias through the low-k dielectric layer and exposing a conductive surface; contacting the conductive surface with diluted hydrofluoric acid to remove contaminants from the conductive surface; removing the hard mask disposed on top of the low-k dielectric layer; and applying remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

[0047] Now refer to Figure 4 In some embodiments, this disclosure includes a method 400 for forming an interconnect structure. Method 400 includes the steps of: at block 402, etching through a hard mask disposed on top of a low-k dielectric layer to form vias through the low-k dielectric layer and expose conductive surfaces. Next, at block 404, method 400 includes the step of contacting the conductive surfaces with diluted hydrofluoric acid to remove contaminants from the conductive surfaces. At block 406, method 400 includes the step of removing the hard mask disposed on top of the low-k dielectric layer. At block 406, method 400 includes applying a remote hydrogen plasma to the conductive surfaces to form exposed portions of the conductive surfaces. In some embodiments, the process sequence of blocks 402, 404, 406, and 408 is as follows: Figure 4 The steps are performed sequentially as shown. In some embodiments, the step of contacting the conductive surface with diluted hydrofluoric acid to aid in the removal of contaminants from the conductive surface is performed before removing the hard mask disposed on top of the low-k dielectric layer. In some embodiments, the step of removing the hard mask disposed on top of the low-k dielectric layer is performed before applying remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface. In some embodiments, the diluted hydrofluoric acid is a 100 to 1000:1 DHF solution. In some embodiments, the method includes the step of depositing a first metal of a first type in the via. In embodiments, the first metal of the first type is ruthenium, tungsten, cobalt, aluminum, or a combination of the foregoing. In embodiments, the method includes the step of forming a trench communicating with the via. In embodiments, the method includes the step of depositing a barrier layer within the trench and on top of the exposed portion of the conductive surface. In embodiments, the method includes the step of depositing a liner layer on top of the barrier layer. In embodiments, the method includes the step of filling the trench with a second metal different from the first metal of the first type. In one implementation, the method includes the following steps: adding a top cap layer on top of a second metal.

[0048] Now refer to Figure 5In some embodiments, this disclosure includes a method 500 for forming an interconnect structure, the method comprising the steps of: at block 502, forming vias and trenches in a film stack including a hard mask and a dielectric layer disposed on a substrate to expose conductive surfaces. Method 500 at block 504 includes the step of contacting the conductive surfaces with diluted hydrofluoric acid. Method 500 at block 506 includes the step of removing the hard mask. Method 500 at block 508 includes the step of applying remote plasma to the conductive surfaces to form exposed portions of the conductive surfaces. Method 500 at block 510 includes the step of depositing a first metal of a first type in the vias. Method 500 at block 512 includes the step of depositing a barrier layer on the exposed surfaces of the first metal and trenches. Method 500 at block 514 includes the step of depositing a pad layer on the barrier layer. Method 500 at block 516 includes the step of filling the trenches with a second metal different from the first metal. In one embodiment, the step of contacting the conductive surface with diluted hydrofluoric acid is performed before removing the hard mask. In another embodiment, the step of contacting the conductive surface with diluted hydrofluoric acid is performed before removing the hard mask, wherein the step of removing the hard mask is performed before applying remote plasma to the conductive surface to form an exposed portion of the conductive surface. In another embodiment, the first metal of the first type is one of ruthenium, tungsten, cobalt, aluminum, or a combination of the foregoing. In another embodiment, the barrier layer comprises TiN or TaN. In another embodiment, the liner layer comprises cobalt. In another embodiment, the second metal is copper. In another embodiment, the capping layer is disposed on top of the second metal.

[0049] In an embodiment, this disclosure includes a method for forming an interconnect structure, the method comprising the following steps in sequence: (1) etching through a hard mask disposed on top of a low-k dielectric layer to form vias through the low-k dielectric layer and expose conductive surfaces; (2) contacting the conductive surfaces with diluted hydrofluoric acid to remove contaminants from the conductive surfaces; (3) removing the hard mask disposed on top of the low-k dielectric layer, for example by wet etching; and (4) applying remote hydrogen plasma to the conductive surfaces to form exposed portions of the conductive surfaces.

[0050] Although the above describes an implementation method of this disclosure, other and additional implementation methods of this disclosure may be designed without departing from the basic scope of this disclosure.

Claims

1. A method for forming an interconnect structure, comprising the following steps: Etching is performed through a hard mask placed on top of a low-k dielectric layer to form vias through the low-k dielectric layer and expose conductive surfaces; The conductive surface is brought into contact with diluted hydrofluoric acid to remove contaminants from the conductive surface; Subsequently, the hard mask disposed on top of the low-k dielectric layer is removed; After removing the hard mask, a remote hydrogen plasma is applied to the exposed portion of the conductive surface to clean the exposed portion of the conductive surface; A first type of first metal is deposited in the through-hole; A groove is formed that communicates with the through hole; A barrier layer is deposited within the trench and on top of the exposed portion of the conductive surface; A liner layer is deposited on top of the barrier layer; and The trench is filled with a second metal that is different from the first metal of the first type.

2. The method of claim 1, wherein the step of contacting the conductive surface with diluted hydrofluoric acid to remove contaminants from the conductive surface is performed before removing the hard mask disposed on top of the low-k dielectric layer.

3. The method of claim 1 or 2, wherein the step of removing the hard mask disposed on top of the low-k dielectric layer is performed before applying remote hydrogen plasma to the exposed portion of the conductive surface to clean the exposed portion of the conductive surface.

4. The method of claim 1 or 2, wherein the diluted hydrofluoric acid is a DHF solution of 100 to 1000:

1.

5. The method of claim 1, wherein the first metal of the first type is one of ruthenium, tungsten, cobalt, aluminum, or a combination thereof.

6. The method of claim 1, further comprising the following steps: Add a top cap layer on top of the second metal.

7. A method for forming an interconnect structure, comprising the following steps: Through-holes and trenches are formed in a film stack including a rigid mask and a dielectric layer disposed on a substrate to expose conductive surfaces; The conductive surface is brought into contact with diluted hydrofluoric acid; Subsequently, the hard mask was removed; After removing the hard mask, remote plasma is applied to the exposed conductive surface to clean the exposed portion of the conductive surface; A first type of first metal is deposited in the through-hole; A barrier layer is deposited on the exposed surfaces of the first metal and the trench; A liner layer is deposited on the barrier layer; and The trench is filled with a second metal that is different from the first metal.

8. The method of claim 7, wherein the first metal of the first type is one of ruthenium, tungsten, cobalt, aluminum, or a combination thereof.

9. The method of claim 7, wherein the barrier layer comprises TiN or TaN.

10. The method of claim 7, wherein the liner layer comprises cobalt.

11. The method of claim 7, wherein the second metal is copper.

12. The method of claim 7, wherein the top cover is disposed on top of the second metal.

13. A non-transitory computer-readable medium having instructions stored thereon, said instructions, when executed, causing an execution of a method for forming an interconnect structure, said method as described in any of the preceding claims.

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