Method for forming a dielectric layer in a semiconductor device

Abstract

A method for forming a 3D memory device is provided. The method includes the following operations: forming a stacked structure in a stepped region and an array region; forming a dielectric material layer over the array region and the stepped region; coating an etch mask layer over the dielectric material layer; planarizing the etch mask layer on a first surface remote from the dielectric material layer; and etching the dielectric material layer and the remaining portion of the etch mask layer to form a dielectric layer over the stepped region and the array region.

Description

Technical Field

[0001] This disclosure relates to semiconductor manufacturing methods. Background Technology

[0002] In the fabrication of semiconductor devices, etching and polishing processes are commonly used to reduce material thickness. Etching refers to any process that removes material from a wafer. Chemical mechanical polishing (CMP, also known as chemical mechanical planarization) is a process that combines chemical etching and abrasive-free mechanical polishing to smooth the wafer surface. To planarize materials with uneven surfaces, etching and polishing processes can be combined to produce material of the desired thickness. Summary of the Invention

[0003] In one aspect, a method for forming a three-dimensional (3D) memory device is provided. The method includes: forming a stacked structure in a stepped region and an array region; forming a dielectric material layer over the array region and the stepped region; coating an etch mask layer over the dielectric material layer; polishing the etch mask layer on a first surface remote from the dielectric material layer; and etching the dielectric material layer and etching the remaining portion of the etch mask layer to form a dielectric layer over the stepped region and the array region.

[0004] In another aspect, a method for forming a 3D memory device is provided. The method includes: forming a stacked structure in a stepped region and an array region; forming a dielectric material layer over the array region and the stepped region; forming an etch mask portion over a portion of the dielectric material layer above the stepped region; and etching the dielectric material layer and the etch mask portion to form the dielectric layer over the stepped region and the array region. Attached Figure Description

[0005] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the present disclosure and enable those skilled in the art to make and use the invention.

[0006] Figure 1 A plan view of an exemplary wafer having multiple 3D memory device chips is shown, according to some aspects of this disclosure.

[0007] Figure 2A-2C The manufacturing process for forming a 3D memory device is shown.

[0008] Figure 2D and Figure 2E Each diagram shows a cross-sectional view of the 3D memory device at different stages of manufacturing.

[0009] Figures 3A-3C An exemplary manufacturing process for forming a 3D memory device is shown in accordance with some aspects of this disclosure.

[0010] Figure 3D A cross-sectional view of a 3D memory device during the manufacturing stage is shown, according to some aspects of this disclosure.

[0011] Figure 4 An exemplary 3D memory device is shown in accordance with some aspects of this disclosure.

[0012] Figure 5 This is a flowchart of an exemplary method for forming a 3D memory device according to some aspects of this disclosure. Detailed Implementation

[0013] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0014] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0015] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer, and “above” or “above” means not only “on” or “above” but also includes “on” or “above” without an intermediate feature or layer (i.e., directly on).

[0016] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0017] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between a top surface (e.g., a first surface) and a bottom surface (e.g., a second surface) of a continuous structure, or between any pair of horizontal planes at the top surface (e.g., the first surface) and the bottom surface (e.g., the second surface). A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0018] In the manufacture of 3D memory devices (e.g., 3D NAND memory devices), etching and polishing processes are typically combined to reduce layer thickness. Sometimes, the layer may be too thick before thickness reduction can be achieved. Layer thinning and planarization can be difficult to control and costly due to the thickness and the undesirable long time required to remove a portion of the layer. Specifically, as the number of layers in 3D NAND memory devices increases, the thinning and planarization of the dielectric material layer formed above the stepped structure of the 3D NAND memory device can present these problems.

[0019] Figure 1 A plan view of an exemplary wafer 100 having a plurality of dies 102 is shown, according to some aspects of this disclosure. The dies 102 may be separated by scribe lines 106. Figure 1As shown, die 102 may include a stacked structure 108, such as a memory stack having staggered conductive layers (e.g., gate lines / word lines) and dielectric layers (e.g., inter-gate dielectrics), the stacked structure 108 rising from a surrounding lower region. Each conductive / dielectric layer pair is at a different height and is referred to as a level / ladder. In some embodiments, the stacked structure 108 includes a stepped structure 110 on one or more sides of the stacked structure 108. The stepped structure 110 may have a sloping profile rising from a surrounding lower region outside the stacked structure 108 to an inner region within the stacked structure 108. Based on the different heights of the structures therein, die 102 may be divided into three regions: an array region (dot pattern fill) and a stepped region (diagonal pattern fill). In various embodiments, a peripheral region (unfilled) may be included in die 102 or may not be included in die 102. Figure 1 As shown, in some embodiments, the stack structure 108 exists in both the array region and the stepped region, and the stepped structure 110 of the stack structure 108 is located in the stepped region on one (or more) sides of the stack structure 108. The memory cell array formed by the intersection of conductive layers and channel structures can be formed in the array region, for example, as an array of NAND memory strings, each NAND memory string extending vertically through the stack structure 108. The memory cell array can be used to store data. For example, scribing 106 can be present between dies 102. Other protective, test, or measurement structures (e.g., sealing rings, test pads, alignment marks, etc.) can also be located in the peripheral region.

[0020] Figure 2A-2C An exemplary manufacturing process for forming a 3D memory device during manufacturing is shown. Specifically, an etching and polishing process for forming a dielectric layer over a stepped structure of a 3D memory device is shown. Figure 2D It shows Figure 2B The diagram shows a cross-sectional view of a portion of the 3D memory device along the A-A' direction (e.g., along the xz plane). Figure 2E yes Figure 2C The cross-sectional view of a portion of the 3D memory device shown is along the A-A' direction.

[0021] like Figure 2AAs shown, to form a 3D memory device, a stacked structure 206 is formed over a substrate 202. The stacked structure 206 includes multiple conductive layers and multiple dielectric layers staggered in a vertical direction (e.g., the z-direction). The stacked structure 206 is partially located in an array region and partially in a stepped region. A memory cell array may be formed in the array region, for example, as an array of NAND memory strings, each NAND memory string extending vertically through the stacked structure 206. As described above, a stepped structure with multiple steps of the stacked structure 206 is located in the stepped region. Contact vias may be formed to contact the steps in the stepped region, thereby connecting the conductive layers (e.g., word lines) to peripheral circuitry. (Back to Reference) Figure 1 And related descriptions. A protective material layer 208 is formed to at least cover the stepped structure. A dielectric material layer 210 is formed over the stacked structure 206 (e.g., and the protective material layer 208) in the array region and the stepped region. A photoresist layer is formed over the dielectric material layer 210 in the array region and the stepped region.

[0022] like Figure 2A As shown, the photoresist layer is first patterned. The patterned photoresist layer 204 covers a portion of the dielectric material layer 210 in the stepped region and exposes a portion of the dielectric material layer 210 in the array region. Figure 2B As shown, a patterned photoresist layer 204 is used as an etch mask to etch the dielectric material layer 210 to remove portions of the dielectric material layer 210 and the protective material layer 208 in the array region. A protective layer 218 (formed by patterning the protective material layer 208) and a patterned dielectric material layer 220 (formed by patterning the dielectric material layer 210) are formed above the stepped structure. The patterned photoresist layer 204 is then removed. An etch stop layer 212 is formed, covering the exposed portions of the stacked structure 206 and the patterned dielectric material layer 220. Figure 2C As shown, the patterned dielectric material layer 220 then undergoes a polishing process to remove any excess material above the stacked structure 206. The polishing of the patterned dielectric material layer 220 then stops at the etch stop layer 212 as a certain amount of dielectric material is removed from the top of the stacked structure 206. The patterned dielectric material layer 220 is then planarized, thereby forming a dielectric layer 222 above the stepped structure.

[0023] like Figure 2DAs shown, the patterned dielectric material layer 220 may have steps above the stacked structure 206 before the polishing process. The steps, with a thickness (or step height) H0, are formed by the difference in etching depth between the dielectric material layer 210 and the step region. For 3D memory devices with an increased number of layers (e.g., an increased number of conductive / dielectric layer pairs or steps), the height of the step structure increases accordingly. H0 may become undesirably large due to the increased deposition of dielectric material to cover the step structure. For example, for a step structure with approximately 200 steps, H0 can reach approximately 10 μm. Polishing the patterned dielectric material layer 220 in the z-direction may take an undesirably long time, resulting in high manufacturing costs. Simultaneously, the polishing process is stopped by the etch stop layer 212. Due to the long polishing process, the patterned dielectric material layer 220 may be susceptible to over-etching / polishing, causing voids, scratches, or other defects on the polished surface of the formed dielectric layer 222. Figure 2E As shown, the formed dielectric layer 222 may have an uneven polished surface. As a result, other structures formed above the dielectric layer 222 are also susceptible to the effects of the uneven surface, which can cause various potential problems in subsequent manufacturing processes, such as misalignment and over / under-etching.

[0024] To address one or more of the aforementioned problems, this disclosure introduces a solution for forming a dielectric layer with improved surface flatness. According to the method of this disclosure, the photoresist layer is polished rather than patterned in both the array region and the stepped region. Polishing of the photoresist layer can be stopped when the underlying dielectric material layer is exposed in the array region. The remaining photoresist portions in the stepped region and the exposed portions of the dielectric material layer in the array region undergo the same etching process, with a higher etching rate for the dielectric material layer than for the remaining photoresist portions. Due to the blocking effect of the remaining photoresist portions, the amount of dielectric material that can be removed by etching in the array region is greater than the amount removed in the stepped region. After etching the dielectric material layer to the desired thickness in the array region, the remaining photoresist portions are removed. The dielectric material layer is then polished to form a dielectric layer over the stepped structure.

[0025] By polishing rather than etching the photoresist layer, the remaining photoresist portions formed in the stepped structure during etching of the dielectric material in the array region can provide protection (e.g., a barrier effect) for the underlying dielectric material layer. When the dielectric material layer is etched, the remaining photoresist portions, having an etch rate lower than that of the dielectric material, can reduce the etch depth difference between the array region and the stepped region. The step height of the dielectric material can be reduced. The reduced step height can effectively reduce the time and cost of the polishing process, thus allowing for easier control of the polishing process. The resulting dielectric layer can have improved flatness on the polished surface, thereby providing an improved substrate surface for subsequent processes.

[0026] Although the methods of this disclosure are illustrated based on 3D memory devices, consistent with the scope of this disclosure, the methods disclosed herein can also be applied to the thinning and planarization of any suitable film having steps (e.g., steps with undesirably large step heights) between adjacent surfaces with different heights / slopes. The methods can be applied to form any suitable semiconductor device, including but not limited to logic devices (e.g., central processing units (CPUs), graphics processing units (GPUs), and application processors (APs)), volatile memory devices (e.g., dynamic random-access memory (DRAM) and static random-access memory (SRAM)), non-volatile memory devices (e.g., NAND flash, NOR flash), or any combination thereof (2D, 2.5D, or 3D architectures).

[0027] Figures 3A-3C An exemplary manufacturing process for forming part of a 3D memory device according to some aspects of this disclosure is shown. For the sake of simplicity, Figures 3A-3C and Figure 4 The formation of a stacked structure in a 3D memory device according to some embodiments is only shown. Figure 3D The 3D memory device shown in this disclosure is an example of some aspects thereof. Figure 3B The cross-sectional view of the manufacturing stage is shown. Figure 4 A cross-sectional view of a 3D memory device according to some aspects of this disclosure is shown. Figure 5 This is a flowchart of an exemplary method 500 for forming a 3D memory device according to some aspects of this disclosure. 3A-3D and... Figure 5It should be understood that the operations shown in method 500 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 5 The different execution orders shown.

[0028] refer to Figure 5 Method 500 begins with operation 502, wherein a stacked structure is formed in the stepped region and the array region, and a dielectric material layer is formed on top of the stacked structure. Figure 3A The corresponding structure is shown.

[0029] like Figure 3A As shown, a stacked structure 306 may be formed over a substrate 302. The stacked structure 306 may be over a stepped region and an array region. In some embodiments, a stepped structure of the stacked structure 306 is formed in the stepped region, and a plurality of memory cells are formed in the array region. A dielectric material layer 310 may be formed over the stacked structure 306 in the stepped region and the array region. In some embodiments, a protective material layer 308 is formed over the stacked structure 306, between the stacked structure 306 and the dielectric material layer 310.

[0030] Note that the x-axis, y-axis, and z-axis are included. Figures 3A-3D and Figure 4 This is used to help illustrate the spatial relationships of components in a 3D memory device. For example, Figures 3A-3D The diagram includes x-axis and y-axis to illustrate two perpendicular lateral directions in the wafer plane: the x-axis represents the word line direction of the 3D memory device, and the y-axis represents the bit line direction. (Reference) Figure 4 The word line direction (e.g., the x-direction) represents the lateral direction in which the conductive layer 404 extends, while the bit line direction (y-direction) represents the lateral direction in which the bit line (not shown) extends. The x-direction and y-direction are perpendicular to each other. The substrate 302 of the 3D memory device includes two lateral surfaces extending laterally in the xy plane: a first surface on the front side of the wafer, on which the 3D memory device can be formed; and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate 302 is located in the lowest plane of the 3D memory device in the z-direction (a direction perpendicular to the xy plane), the z-direction relative to the substrate 302 of the 3D memory device determines whether a component (e.g., a layer or device) of the 3D memory device is "on," "above," or "below" another component (e.g., a layer or device). The same concepts are applied in this disclosure to describe spatial relationships.

[0031] Substrate 302 may comprise silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, substrate 302 is a thinned substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, substrate 302 comprises silicon.

[0032] The stacked structure 306 may include a plurality of interleaved conductive and dielectric layers perpendicularly interleaved above the substrate 302. Figure 4 The conductive layer 404 and dielectric layer 406 are shown in the figure. The conductive layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The dielectric layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (high k) dielectric, or any combination thereof. The staggered conductive and dielectric layers may be formed by a plurality of staggered first and second material layers (not shown) perpendicularly staggered above the substrate 302. The first and second material layers may be alternately deposited above the substrate 302 to form a stacked structure 306 using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0033] The edges of the staggered first and second material layers can define a stepped structure on one side of the stacked structure in the stepped region. In some embodiments, the first material layer includes a first dielectric layer, and the second material layer (also known as a sacrificial layer) includes a second dielectric layer different from the first dielectric layer. For example, the first material layer may include silicon oxide, while the second material layer may include silicon nitride. A conductive layer can be formed by a so-called gate replacement process (e.g., in a gate-first process), in which the second material layer is replaced with a conductive layer. For example, the first material layer may include silicon oxide, while the conductive layer may include a metal (e.g., W). In some embodiments, the first material layer includes a dielectric layer, and the second material layer includes a conductive layer. For example, the first material layer may include silicon oxide, while the second material layer may include polysilicon. The second material layer may be a conductive layer (e.g., in a gate-first process).

[0034] A stepped structure with tiered, sloping forms (e.g., such as...) Figure 4 The stepped structure (shown in step 408) is formed on one side of the stacked structure 306 for purposes such as letter fan-out. That is, the edges of the staggered first and second material layers can define the stepped structure on the side of the stacked structure 306. It should be understood that, in some examples, additionally or alternatively, the stepped structure may be formed in the middle (e.g., the center) of the stacked structure 306. Each step (also called a level) of the stepped structure may include one or more pairs of first and second material layers. That is, the height of each step may be equal to the total thickness of one or more pairs of first and second material layers.

[0035] The stepped structure can be formed using a so-called trimming etch process, in which, in each cycle, trims (e.g., typically etches incrementally and inwards from all directions) the patterned photoresist layer, and then uses the trimmed photoresist layer as an etch mask to etch the exposed portions of the staggered first and second material layers of the stacked structure 306 to form one step of the stepped structure. This process can be repeated until all steps of the stepped structure are formed.

[0036] Multiple NAND memory strings can be formed in the array region of the stacked structure 306 (e.g., Figure 4 The NAND memory string 413 is shown in the figure. Multiple memory cell arrays can be formed within the NAND memory string. In some embodiments, the fabrication process for forming the NAND memory string includes: forming channel vias through the stacked structure 306 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), followed by filling the channel vias with multiple layers (e.g., a memory film and a semiconductor channel) using a thin-film deposition process. For example, the memory film can be a composite dielectric layer, such as a combination of multiple dielectric layers including, but not limited to, a barrier layer, a storage layer, and a tunneling layer. The memory film and semiconductor channel can be formed by sequentially depositing multiple layers using one or more thin-film deposition processes (including, but not limited to, ALD, CVD, PVD, or any combination thereof), such as a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a polysilicon layer. The remaining space in the channel vias can be filled with a capping layer by depositing silicon oxide into the channel vias. In some implementations, for example, a channel plug is formed in the top portion of the channel hole by using dry etching and / or wet etching to etch back the semiconductor channel to form a groove and filling the groove with polysilicon using one or more thin film deposition processes (including but not limited to ALD, CVD, PVD or any combination thereof).

[0037] like Figure 3A As shown, the 3D memory device may include an array region and a stepped region laterally adjacent to the array region. The array region and the stepped region may be respectively... Figure 1Examples of array regions and stepped regions are shown. In some implementations, other structures / regions may be located between the stepped region and the array region, for example... Figure 1 The peripheral region is shown. In some embodiments, a stacked structure 306 is formed in both the array region and the stepped region, with the stepped structure formed on the side of the stacked structure 306 in the stepped region. Figure 3A During the manufacturing stage, the stepped structure can have tiered ramps with gradually increasing height from the outer area to the array area.

[0038] The protective material layer 308 may include a suitable insulating material that can provide the desired isolation and protection for the stepped structure. In some embodiments, the protective material layer includes a high-quality dielectric material, such as high-quality silicon oxide and / or high-quality silicon oxynitride. The dielectric material layer 310 may include a suitable insulating material that can provide isolation for contacts subsequently formed in the dielectric layer. In some embodiments, the dielectric material layer 310 includes silicon oxide. In some embodiments, an etch stop layer (not shown) is deposited on the dielectric material layer 310. The etch stop layer may include a suitable material, such as silicon nitride, on which subsequent polishing processes are stopped. The protective material layer 308, the dielectric material layer 310, and the etch stop layer (e.g., if present) can each be formed by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof).

[0039] like Figure 5 As shown, method 500 proceeds to operation 504, in which an etch mask layer is coated onto a dielectric material layer. Figure 3A The corresponding structure is shown.

[0040] like Figure 3AAs shown, an etch mask layer 304 can be coated over the dielectric material layer 310 in the array region and the staircase region. The etch mask layer 304 can have a desired lateral (in the xy plane) flatness on its top surface (e.g., the first surface) (i.e., the lateral surface away from the stack structure 306). The etch mask layer 304 can be formed on the stack structure 306 by a spin coating process. Depending on the material, the etch mask layer 304 may or may not undergo a curing process to increase its hardness. The etch mask layer 304 can include any suitable etch mask material capable of withstanding a polishing process. When the etch mask material is coated onto the stack structure, it is fluid. After coating, the etch mask material is processed to become solid. In subsequent anisotropic etching processes, the etching rate of the dielectric material layer 310 can be higher than the etching rate of the etch mask layer 304. In some embodiments, the ratio of the etch rate of the dielectric material layer to the etch rate of the etch mask layer is in the range of about 20:1 to about 100:1. The etch mask layer 304 may include a photoresist, resin, polymer, and / or other suitable materials capable of forming a flat (e.g., planar) surface over the stacked structure 306. In some embodiments, the etch mask layer 304 includes a photoresist layer and is applied to the stacked structure 306 by a spin-coating process.

[0041] Method 500 proceeds to operation 506, wherein a polishing process is performed on the etched mask layer to completely remove a portion of the etched mask layer in the array region and partially remove a portion of the etched mask layer in the stepped region. Figure 3B The corresponding structure is shown.

[0042] like Figure 3B As shown, a polishing process can be performed on the etch mask layer 304 to completely remove the portion of the etch mask layer 304 in the array region. The polishing process can be stopped after the portion of the etch mask layer 304 in the array region has been completely removed and the dielectric material layer 310 has been exposed. In some embodiments, if an etch stop layer is formed between the dielectric material layer 310 and the etch mask layer 304, the polishing process stops at the etch stop layer in the array region. The polishing process can also partially remove the portion of the etch mask layer 304 in the stepped region. After the polishing process, the etch mask portion 314 (e.g., the remaining portion of the etch mask layer 304 in the stepped region) can remain in the stepped region, for example, above the stepped structure. The thickness of the etch mask portion 314 can gradually increase along the x-direction away from the array region. In some embodiments, the polishing process includes a CMP process.

[0043] Method 500 proceeds to operation 508, in which an anisotropic etching process is performed to etch the dielectric material layer in the array region and the etch mask portion in the step region. Figure 3B The corresponding structure is shown.

[0044] like Figure 3B As shown, an anisotropic etching process can be performed to etch the exposed portions of the dielectric material layer 310 and the etching mask portion 314. In some embodiments, an etch stop layer (if present) is etched away. The etching process can be controlled until the desired thickness of the dielectric material layer 310 in the array region is reached. In some embodiments, the anisotropic etching process includes dry etching. The anisotropic etching process can reduce the thickness of the etching mask portion 314 in the z-direction or completely remove the etching mask portion 314. In various embodiments, the exposed portions of the dielectric material layer 310 and the etching mask portion 314 can be etched in the same etching process or in different etching processes.

[0045] Because the etch rate of the dielectric material layer 310 is higher than that of the etch mask portion 314, the dielectric material layer 310 is consumed faster than the etch mask portion 314. Furthermore, portions of the dielectric material layer 310 covered with a thinner etch mask material can begin to be etched faster than portions covered with a thicker etch mask material, and therefore undergo more etch. Consequently, portions of the dielectric material layer 310 closer to the array region may undergo more etch than portions farther from the array region. This difference in etch rates can reduce or eliminate step formation in the dielectric material layer 310. In some embodiments, etch selectivity (e.g., etch rates for the dielectric material and the etch mask material) can be selected / changed to obtain a desired etch profile, thereby minimizing potential step height. Figure 3D It shows Figure 3B The diagram shows a cross-sectional view of the 3D memory device along the A-A' direction. For ease of illustration, Figure 3D The etching mask portion 314 is not shown. Assuming a dielectric material layer 310 of the same thickness is deposited over the corresponding stacked structure, the step height H1 of the dielectric material layer 310 can be less than the step height H0. In some embodiments, assuming a dielectric material layer 310 of the same thickness is deposited over the corresponding stacked structure, the step height H1 can be reduced by approximately 80% compared to the step height H0. The reduced step height can effectively reduce the time in subsequent polishing processes. In some embodiments, using the disclosed method, the total manufacturing time can be reduced by at least 80%.

[0046] Method 500 proceeds to operation 510, in which the etched mask portion is removed. Figure 3C The corresponding structure is shown.

[0047] like Figure 3CAs shown, after the etching process of operation 508 is completed, any etched mask portion 314 in the stepped region can be completely removed. In some embodiments, the etched mask portion 314 includes a photoresist portion, and removal includes an ashing process, such as an oxygen plasma cleaning process.

[0048] Method 500 proceeds to operation 512, in which another polishing process is performed to planarize the remaining dielectric material layer. Figure 3C The corresponding structure is shown.

[0049] like Figure 3C As shown, after the etching process of operation 508, another polishing process can be performed to planarize the remaining dielectric material layer. Following the polishing process, a dielectric layer 320 can be formed in the stepped structure and array regions. The polishing process can remove any excess dielectric material in the array regions and stepped regions until a dielectric layer 320 of the desired thickness is formed in the array regions and stepped regions. The step height of the dielectric layer 320 can be minimized or eliminated. This can effectively reduce the time of the polishing process and the overall manufacturing process. In some embodiments, the polishing process includes a CMP process. Figure 4 The diagram shows the structure along the A-A' direction after another polishing process (e.g., after removing a portion of the dielectric material layer 310 in the array region in operation 512).

[0050] Figure 4 A cross-sectional view of a 3D memory device 400 formed by a method according to some embodiments of the present disclosure is shown. The 3D memory device 400 may be formed after or during operation 512. The 3D memory device 400 may include an array region 401 and a stepped region 403 laterally adjacent to the array region 401. The stacked structure 306 may include a plurality of staggered conductive layers 404 and a plurality of dielectric layers 406 arranged in the z-direction. The 3D memory device 400 may include NAND memory strings 413 and source contact structures 416 in the array region 401. In the stepped region 403, the 3D memory device 400 may include a stepped structure 408 having multiple steps. A dielectric layer 320 may be formed over the stacked structure 306 in the stepped region 403 and the array region 401 (e.g., over the stepped structure 408). In various embodiments, the formation of the conductive layer 404, the NAND memory string 413, and the source contact structure 416 may occur before, simultaneously with, or after the formation of the dielectric layer 320, and should not be limited to the implementation of this disclosure.

[0051] NAND memory string 413 may extend vertically through stacked structure 306 into substrate 302. In some embodiments, NAND memory string 413 is formed to extend vertically within stacked structure 306. In some embodiments where the second material layer includes a dielectric layer (e.g., silicon nitride), a gate replacement process is performed to replace the second material layer with a conductive layer 404 comprising a conductive material (e.g., W). For example, wet etching and / or dry etching (e.g., DRIE) can be used to etch gaps through stacked structure 306, which can serve as channels for the gate replacement process. Replacing the second material layer with a conductive material can be performed by selectively wet etching the second material layer (e.g., silicon nitride) relative to the first material layer (e.g., silicon oxide) and filling the resulting lateral grooves with a conductive material (e.g., W). The conductive material can be deposited using one or more thin-film deposition processes, including but not limited to ALD, CVD, PVD, or any combination thereof.

[0052] The source contact structure 416 can be formed by sequentially depositing one or more dielectric layers (e.g., silicon oxide, as spacers) and one or more conductive layers (e.g., W and polysilicon, as contacts) into the gap using one or more thin film deposition processes (including but not limited to ALD, CVD, PVD or any combination thereof).

[0053] Embodiments of this disclosure provide a method for forming a 3D memory device. The method includes: forming a stacked structure over a stepped region and an array region; forming a dielectric material layer over the array region and the stepped region; coating an etch mask layer over the dielectric material layer; planarizing the etch mask layer on a first surface remote from the dielectric material layer; and etching the dielectric material layer and etching the remaining portion of the etch mask layer to form a dielectric layer over the stepped region and the array region.

[0054] In some implementations, the first surface of the etched mask layer is horizontal.

[0055] In some embodiments, the etch mask layer includes a photoresist.

[0056] In some implementations, planarizing the etch mask layer includes performing CMP on the etch mask layer until a portion of the dielectric material layer above the array region is exposed.

[0057] In some embodiments, the method further includes etching the remaining portion of the etch mask layer in the stepped region in the same etch process used to etch the dielectric material layer.

[0058] In some implementations, the etching rate of the dielectric material layer is higher than the etching rate of the etch mask layer.

[0059] In some embodiments, the ratio of the etching rate of the dielectric material layer to the etching rate of the etch mask layer is in the range of about 20:1 to about 100:1.

[0060] In some embodiments, etching the dielectric material layer and etching the remainder of the etch mask layer includes a dry etching process.

[0061] In some embodiments, the method further includes completely removing any remaining portion of the etch mask layer in the stepped region after etching the dielectric material layer.

[0062] In some implementations, removing the remaining portion of the etched mask layer includes an ashing process.

[0063] In some embodiments, the method further includes planarizing the dielectric layer above the array region and the stepped region.

[0064] In some implementations, forming the etch mask layer includes a spin coating process.

[0065] In some embodiments, forming the stacked structure includes forming a plurality of interleaved first and second material layers. The edges of the interleaved first and second material layers define a stepped structure on one side of the stacked structure in a stepped region. A dielectric material layer is positioned above the stepped structure.

[0066] Embodiments of this disclosure provide a method for forming a 3D memory device. The method includes: forming a stacked structure over a stepped region and an array region; forming a dielectric material layer over the array region and the stepped region; forming an etch mask portion over a portion of the dielectric material layer above the stepped region; and etching the dielectric material layer and the etch mask portion to form the dielectric layer over the stepped region and the array region.

[0067] In some embodiments, the etch mask portion includes a photoresist portion.

[0068] In some embodiments, forming the etch mask portion includes coating an etch mask layer on a dielectric material layer above the stepped region and the array region. In some embodiments, the etch mask layer is planarized to completely remove the portion of the etch mask layer above the array region.

[0069] In some implementations, planarizing the etch mask layer includes performing CMP on the etch mask layer until a portion of the dielectric material layer above the array region is exposed.

[0070] In some embodiments, the etch mask portion and the dielectric material layer are etched in the same etch process.

[0071] In some implementations, the etching rate of the dielectric material layer is higher than the etching rate of the etch mask portion.

[0072] In some embodiments, the ratio of the etching rate of the dielectric material layer to the etching rate of the etch mask portion is in the range of about 20:1 to about 100:1.

[0073] In some implementations, etching the dielectric material layer and the etching mask portion includes a dry etching process.

[0074] In some implementations, removing the etched mask portion includes an ashing process.

[0075] In some embodiments, the method further includes planarizing the dielectric layer above the array region and the stepped region.

[0076] In some implementations, forming the etch mask layer includes a spin coating process.

[0077] In some embodiments, forming the stacked structure includes forming a plurality of interleaved first and second material layers. The edges of the interleaved first and second material layers define a stepped structure on one side of the stacked structure in a stepped region. A dielectric material layer is positioned above the stepped structure.

[0078] The foregoing description of the specific embodiments can be readily modified and / or altered to suit various applications. Therefore, based on the teachings and guidance given herein, such changes and modifications are intended to fall within the meaning and scope of equivalent variations of the disclosed embodiments.

[0079] The scope and extent of this disclosure should not be limited by any of the above exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A method for forming a three-dimensional (3D) memory device, comprising: A stacked structure is formed above the stepped and array regions; A dielectric material layer is formed above the array region and the stepped region; An etching mask layer is coated over the dielectric material layer; The first surface of the etch mask layer away from the dielectric material layer is planarized to completely remove the portion of the etch mask layer above the array region and form the remaining portion of the etch mask layer above the stepped region. as well as The dielectric material layer is etched and the remaining portion of the etch mask layer above the stepped region is etched to form a dielectric layer above the stepped region and the array region.

2. The method of claim 1, wherein, The first surface of the etched mask layer is horizontal.

3. The method according to claim 1, wherein, The etch mask layer includes a photoresist.

4. The method according to claim 1, wherein, Planarizing the etch mask layer includes performing chemical mechanical polishing (CMP) on the etch mask layer until the portion of the dielectric material layer above the array region is exposed.

5. The method of claim 4, further comprising etching the remaining portion of the etch mask layer in the stepped region in the same etch process as etching the dielectric material layer.

6. The method according to any one of claims 1-5, wherein, The etching rate of the dielectric material layer is higher than the etching rate of the etching mask layer.

7. The method according to claim 6, wherein, The ratio of the etching rate of the dielectric material layer to the etching rate of the etching mask layer is in the range of about 20:1 to about 100:

1.

8. The method according to any one of claims 1-5 and 7, wherein, Etching the dielectric material layer and etching the remaining portion of the etching mask layer includes a dry etching process.

9. The method according to any one of claims 1-5 and 7, further comprising completely removing the remaining portion of the etch mask layer above the stepped region after etching the dielectric material layer.

10. The method according to claim 9, wherein, Removing the remaining portion of the etched mask layer includes an ashing process.

11. The method according to any one of claims 1-5, 7, and 10, further comprising planarizing the dielectric layer above the array region and the stepped region.

12. The method according to any one of claims 1-5, 7, and 10, wherein, The formation of the etched mask layer includes a spin coating process.

13. The method according to any one of claims 1-5, 7, and 10, wherein, Forming the stacked structure includes forming a plurality of interlaced first and second material layers, the edges of which define a stepped structure on one side of the stacked structure in the stepped region, the dielectric material layer above the stepped structure.

14. A method for forming a three-dimensional (3D) memory device, comprising: A stacked structure is formed above the stepped and array regions; A dielectric material layer is formed above the array region and the stepped region; An etching mask layer is formed over the dielectric material layer, the etching mask layer comprising a first portion over the array region and a second portion over the stepped region, wherein the second portion is thicker than the first portion; The first portion of the etch mask layer above the array region is completely removed, and an etch mask portion is formed above the stepped region, the etch mask portion being a portion of the second portion of the etch mask layer; as well as The dielectric material layer and the etching mask portion are etched to form a dielectric layer over the stepped region and the array region.

15. The method according to claim 14, wherein, The etching mask portion includes a photoresist portion.

16. The method of claim 14, wherein: Completely removing the first portion of the etched mask layer over the array region includes: planarizing the etched mask layer to completely remove the first portion of the etched mask layer over the array region.

17. The method according to claim 16, wherein, Planarizing the etch mask layer includes performing chemical mechanical polishing (CMP) on the etch mask layer until the portion of the dielectric material layer above the array region is exposed.

18. The method according to claim 14, wherein, The etching mask portion and the dielectric material layer are etched in the same etching process.

19. The method according to any one of claims 14-18, wherein, The etching rate of the dielectric material layer is higher than the etching rate of the etching mask portion.

20. The method according to claim 19, wherein, The ratio of the etching rate of the dielectric material layer to the etching rate of the etch mask portion is in the range of about 20:1 to about 100:

1.

21. The method according to any one of claims 14-18 and 20, wherein, Etching the dielectric material layer and the etching mask portion includes a dry etching process.

22. The method according to any one of claims 14-18 and 20, further comprising: After etching the dielectric material layer and the etch mask portion, the remaining portion of the etch mask portion is removed using an ashing process.

23. The method according to any one of claims 14-18 and 20, further comprising planarizing the dielectric layer above the array region and the stepped region.

24. The method according to any one of claims 14-18 and 20, wherein, The formation of the etched mask layer includes a spin coating process.

25. The method according to any one of claims 14-18 and 20, wherein, Forming the stacked structure includes forming a plurality of interlaced first and second material layers, the edges of which define a stepped structure on one side of the stacked structure in the stepped region, the dielectric material layer above the stepped structure.

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