Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a substrate, an interlayer insulating layer covering an upper surface of the substrate, a separate device in the interlayer insulating layer, a lower insulating layer covering a lower surface of the substrate, a through silicon via (TSV) structure extending through the substrate, the interlayer insulating layer, and the lower insulating layer, a conductive pad connected to an upper end of the TSV structure, a via insulating layer surrounding the TSV structure, and a cap insulating layer inside the via insulating layer surrounding the TSV structure. The via insulating layer and the cap insulating layer have an air gap therebetween. A portion of the air gap extends into the lower insulating layer.

Description

Technical Field

[0001] Some exemplary embodiments of the inventive concept relate to semiconductor devices including through-silicon vias (TSVs) and / or methods of manufacturing them. Background Technology

[0002] Alternative bonding wire technology / In addition to bonding wire technology, through-silicon via (TSV) technology, in which the TSV extends across the entire semiconductor substrate, has been used as a recent semiconductor technology. Compared to existing bonding wire technology, such TSV technology greatly reduces the physical distance, thus significantly contributing to increased communication speeds between semiconductor chips.

[0003] Such TSVs must be gradually reduced in size as semiconductor devices are scaled down and / or integrated. As a result, the insulating film surrounding the TSV also becomes thinner, which may damage and / or degrade the insulating film, leading to a deterioration in the insulation properties between the semiconductor substrate and the TSV. Summary of the Invention

[0004] Some exemplary embodiments of the inventive concept provide semiconductor devices including through-silicon vias (TSVs) with excellent insulation and electrical properties and / or methods for producing / manufacturing them.

[0005] A method of manufacturing a semiconductor device according to some exemplary embodiments of the inventive concept includes: forming a front-end process (FEOL) structure including separate devices and an interlayer insulating layer on an upper surface of a substrate; forming vias extending through the substrate and the interlayer insulating layer; forming a via insulating layer covering an inner sidewall of the substrate exposed through the vias and covering an inner bottom surface of the substrate exposed through the vias; forming a sacrificial insulating layer covering the via insulating layer in the vias; forming a cap insulating layer covering the sacrificial insulating layer in the vias; forming a barrier layer covering the cap insulating layer in the vias; forming a through-silicon via (TSV) filling the vias on the barrier layer; partially removing the substrate from a lower surface of the substrate such that a lower portion of the via insulating layer, a lower portion of the sacrificial insulating layer, a lower portion of the cap insulating layer, a lower portion of the barrier layer, and a lower portion of the TSV protrudes from the lower surface of the substrate; partially removing the via insulating layer to expose the sacrificial insulating layer; removing the sacrificial insulating layer to form a trench between the via insulating layer and the cap insulating layer; and forming a lower insulating layer with a sealing trench on the lower surface of the substrate to form an air gap.

[0006] A semiconductor device according to some exemplary embodiments of the inventive concept includes: an interlayer insulating layer covering an upper surface of a substrate; a separate device within the interlayer insulating layer; a lower insulating layer covering a lower surface of the substrate; a through-silicon via (TSV) structure extending through the substrate, through the interlayer insulating layer, and through the lower insulating layer; a conductive pad connected to an upper end of the TSV structure; a via insulating layer surrounding the TSV structure; and a cap insulating layer surrounding the TSV structure inside the via insulating layer, the via insulating layer and the cap insulating layer having an air gap therebetween. A portion of the air gap extends into the lower insulating layer.

[0007] A semiconductor device according to some exemplary embodiments of the inventive concept includes: an interlayer insulating layer covering an upper surface of a substrate; a separate device within the interlayer insulating layer; a lower insulating layer covering a lower surface of the substrate; a through-silicon via (TSV) structure extending through the substrate, through the interlayer insulating layer, and through the lower insulating layer; a conductive pad connected to an upper end of the TSV structure; a via insulating layer surrounding the TSV structure; a cap insulating layer surrounding the TSV structure, the cap insulating layer being inside the via insulating layer; and an intermediate insulating layer between the via insulating layer and the cap insulating layer. The via insulating layer and the intermediate insulating layer have a first air gap therebetween. The intermediate insulating layer and the cap insulating layer have a second air gap therebetween. The first air gap and the second air gap have different vertical lengths. Attached Figure Description

[0008] Figure 1A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept.

[0009] Figure 1B yes Figure 1A An enlarged view of region P1 in the image.

[0010] Figure 2 It is along Figure 1A The cross-sectional view taken by line I-I' in the diagram.

[0011] Figure 3A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept.

[0012] Figure 3B yes Figure 3A A magnified view of region P2 in the image.

[0013] Figure 4A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept.

[0014] Figure 4B yes Figure 4A A magnified view of region P3 in the image.

[0015] Figure 5 It is along Figure 4AThe cross-sectional view taken from line II-II' in the diagram.

[0016] Figure 6A , Figure 6B and Figure 6C It is based on Figure 4A An enlarged view of region P4 in the example implementation.

[0017] Figure 7A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept.

[0018] Figure 7B yes Figure 7A A magnified view of region P5 in the image.

[0019] Figures 8 to 25 This is a process flow diagram illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the inventive concept.

[0020] Figures 26 to 36 This is a process flow diagram illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the inventive concept.

[0021] Figure 37 This is a cross-sectional view of a semiconductor package according to some exemplary embodiments of the inventive concept. Detailed Implementation

[0022] Figure 1A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept. Figure 1B yes Figure 1A An enlarged view of region P1 in the image. Figure 2 It is along Figure 1A The cross-sectional view taken by line I-I' in the diagram.

[0023] Reference Figure 1A , Figure 1B and Figure 2 The semiconductor device 100A may include a substrate 10, a front-end process (FEOL) structure 11, a lower insulating layer 60, a through-silicon via (TSV) structure 30, a via insulating layer 21, a cap insulating layer 25, an air gap AG, a wiring layer 40, a connection terminal 50, and a conductive layer 70.

[0024] Substrate 10 may be or include a semiconductor substrate, such as, but not limited to, a silicon substrate, a silicon-germanium wafer, a III-V substrate, a silicon-on-insulator substrate, etc. Substrate 10 may be or correspond to a wafer, and may be undoped or lightly doped, for example, lightly doped with P-type impurities. Furthermore, substrate 10 may include an upper surface 10A as an active surface and a lower surface 10B as an inactive surface. FEOL structure 11, including interlayer insulating layer 12 and individual devices 13, may be disposed at the upper surface 10A of substrate 10. Multiple individual devices (IDs) 13 of various types may be disposed in interlayer insulating layer 12. Individual devices 13 may include various microelectronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), system-on-large-scale integrated circuits (LSIs), image sensors such as CMOS imaging sensors (CIS), microelectromechanical systems (MEMS), active devices such as diodes (such as light-emitting diodes), passive devices such as resistors and / or capacitors, etc. Individual devices 13 may be electrically connected to conductive regions of substrate 10. Alternatively or additionally, adjacent devices in individual devices 13 may be electrically isolated from each other by interlayer insulation layer 12.

[0025] The TSV structure 30 may extend through the substrate 10 and the interlayer insulating layer 12. The lower portion of the TSV structure 30 may partially protrude from the lower surface 10B of the substrate 10. The TSV structure 30 may include a TSV 33 and a barrier layer 31. The TSV 33 may be cylindrical. The TSV 33 may include Cu and / or W. For example, the TSV 33 may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuW, W, or a W alloy, or may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuW, W, or a W alloy, but is not limited thereto. The diameter of the TSV 33 may be about 3 to 10 μm, such as 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, but is not limited thereto. The barrier layer 31 may surround the sidewalls of the TSV 33. The barrier layer 31 may be a conductive layer with relatively low wiring resistance / resistivity. For example, the barrier layer 31 may be a single-layer film or a multilayer film comprising at least one of W, WN, Ti, TiN, Ta, TaN, and Ru. For example, the barrier layer 31 may be composed of / correspond to a multilayer film made of at least one of TaN / W, TiN / W, and WN / W.

[0026] A lower insulating layer 60 may be disposed on the lower surface 10B of the substrate 10. The lower insulating layer 60 may surround the portion of the TSV structure 30 that protrudes from the lower surface 10B of the substrate 10. The lower insulating layer 60 may cover a portion of the barrier layer 31. The lower insulating layer 60 may include a first lower insulating layer (also called a capping layer) 61, a second lower insulating layer (also called a support layer) 63, and a third lower insulating layer (also called a passivation layer) 65. The first lower insulating layer 61 may cover the lower surface 10B of the substrate 10. The second lower insulating layer 63 may be disposed between the first lower insulating layer 61 and the third lower insulating layer 65. The first lower insulating layer 61 and the third lower insulating layer 65 may include the same material or multiple materials, for example, they may be composed of the same material or multiple materials. For example, the first lower insulating layer 61 and the third lower insulating layer 65 may both include silicon oxide. The second lower insulating layer 63 may include silicon nitride.

[0027] A via insulating layer 21 may be disposed between the substrate 10 and the TSV structure 30, and between the interlayer insulating layer 12 and the TSV structure 30. The via insulating layer 21 may contact the inner sidewall of the substrate 10 while simultaneously contacting the inner sidewall of the interlayer insulating layer 12. The via insulating layer 21 may be spaced apart from the TSV structure 30. The via insulating layer 21 may have a cylindrical shape, such as a hollow cylindrical shape. The via insulating layer 21 may be spaced apart from the cap insulating layer 25 such that the via insulating layer 21 may surround the cap insulating layer 25 and the TSV structure 30. A portion of the via insulating layer 21 may protrude from the lower surface 10B of the substrate 10. The lower portion of the via insulating layer 21 may partially extend into the lower insulating layer 60. The horizontal LV21 of the lower end of the via insulating layer 21 may be lower than the horizontal LV1 of the lower surface 10B of the substrate 10, but higher than the horizontal LV2 of the lower end of the TSV structure 30.

[0028] The pathway insulating layer 21 may include oxides. For example, the oxides included in the pathway insulating layer 21 may include at least one of tetraethyl orthosilicate (TEOS), high-density plasma (HDP) oxides, borosilicate glass (BPSG), and flowable chemical vapor deposition (FCVD) oxides, and may be formed using chemical vapor deposition (CVD) processes, such as plasma-enhanced CVD (PECVD) and / or low-pressure CVD (LPCVD) processes, but are not limited thereto.

[0029] In some exemplary embodiments, the via insulating layer 21 may include a nitride and / or a low-k dielectric. For example, the nitride included in the via insulating layer 21 may be composed of / correspond to at least one of SiN and SiON. For example, the low-k dielectric included in the via insulating layer 21 may be composed of / correspond to an ultra-low k (ULK) film having an ultra-low dielectric constant K of 2.2 to 2.4. For example, the ULK film may be made of SiOC or SiCOH. However, the exemplary embodiments are not limited to the examples described above.

[0030] A cap insulating layer 25 may be disposed between the channel insulating layer 21 and the TSV structure 30. The cap insulating layer 25 may have a cylindrical shape, such as a hollow cylindrical shape. The cap insulating layer 25 may cover the outer side surface of the barrier layer 31 while surrounding the TSV structure 30. The lower portion of the cap insulating layer 25 may partially extend into the lower insulating layer 60. The horizontal LV25 of the lower end of the cap insulating layer 25 may be lower than the horizontal LV1 of the lower surface 10B of the substrate 10, but higher than the horizontal LV2 of the lower end of the TSV structure 30. Thus, the cap insulating layer 25 may not cover a portion of the lower part of the TSV structure 30. The horizontal LV25 of the lower end of the cap insulating layer 25 may be equal to or different from the horizontal LV21 of the lower end of the channel insulating layer 21. In some example embodiments, the horizontal LV25 of the lower end of the cap insulating layer 25 may be lower than the horizontal LV21 of the lower end of the channel insulating layer 21. The cover insulation layer 25 may include one or more of the same materials as the passage insulation layer 21, for example, it may be composed of one or more of the same materials as the passage insulation layer 21.

[0031] An air gap AG can be formed between the through insulating layer 21 and the cover insulating layer 25. The through insulating layer 21 and the cover insulating layer 25 can be spaced apart from each other by the air gap AG. The air gap AG can be defined by the through insulating layer 21, the cover insulating layer 25, the wiring layer 40, and the lower insulating layer 60. The upper end of the air gap AG can be defined by the conductive pad 45 of the wiring layer 40, and the lower end of the air gap AG can be defined by the lower insulating layer 60.

[0032] In some example embodiments, the air gap AG may extend into the lower insulating layer 60. A portion of the lower insulating layer 60 may extend between the via insulating layer 21 and the cap insulating layer 25, such that a seal can be formed between the via insulating layer 21 and the cap insulating layer 25, thereby defining the lower end of the air gap AG. The horizontal LVAG of the lower end of the air gap AG may be lower than the horizontal LV1 of the lower surface 10B of the substrate 10. The horizontal LVAG of the lower end of the air gap AG may be located between the horizontal LV1 of the lower surface 10B of the substrate 10 and the horizontal LV2 of the lower end of the TSV structure 30. The horizontal LVAG of the lower end of the air gap AG may be higher than the horizontal LV21 of the lower end of the via insulating layer 21 and the horizontal LV25 of the lower end of the cap insulating layer 25.

[0033] Wiring layer 40 may be disposed on the upper surface of interlayer insulation layer 12. Wiring layer 40 may also correspond to / be referred to as a "back-to-office (BEOL) structure". Wiring layer 40 may include conductive pad 45, short path 48, wiring pattern 49, and upper insulation layer 47. Conductive pad 45 may overlap perpendicularly with TSV structure 30. Conductive pad 45 may be directly connected to TSV structure 30. For example, the lower surface of conductive pad 45 may contact the upper ends of TSV 33 and barrier layer 31. The lower surface of conductive pad 45 may contact the upper ends of path insulation layer 21 and cover insulation layer 25. The lower surface of conductive pad 45 may define the upper end of air gap AG.

[0034] Short paths 48 and wiring patterns 49 can be stacked on conductive pads 45. Short paths 48 can electrically connect conductive pads 45 and wiring patterns 49 to each other between wiring patterns 49 and conductive pads 45. Furthermore, short paths 48 can electrically connect wiring patterns 49 that are perpendicularly spaced from each other. Conductive pads 45 and connection terminals 50 can be electrically connected to each other through wiring patterns 49 and short paths 48. Additionally, wiring patterns 49 and short paths 48 can be used to electrically connect individual devices 13 to external devices. Short paths 48 and wiring patterns 49 can include metals, such as at least one of Cu, Al, and W, and may or may not include the same material.

[0035] The upper insulating layer 47 may cover the surfaces of the conductive pad 45, short path 48, and wiring pattern 49 on the interlayer insulating layer 12. The upper insulating layer 47 may cause / act as a means of separating two or more wiring patterns 49 from each other. Although the upper insulating layer 47 is shown in the figures as having a single-layer structure, the upper insulating layer 47 may be formed as having a multilayer structure. For example, the upper insulating layer 47 may include at least one of silicon oxide and silicon nitride.

[0036] Figure 3A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept. Figure 3B yes Figure 3A A magnified view of region P2 in the image.

[0037] Reference Figure 3A and Figure 3B In some example embodiments, a portion of the lower insulating layer 60 included in the semiconductor device 100B may extend between the via insulating layer 21 and the cap insulating layer 25, such that the upper end of the extended portion at the level LVAG may be higher than the level LV1 of the lower surface 10B of the substrate 10. In some example embodiments, within the lower insulating layer 60, the lower ends of the via insulating layer 21 and the cap insulating layer 25 at the levels LV21 and LV25 may be equal.

[0038] Figure 4A This is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 4B yes Figure 4A A magnified view of region P3 in the image. Figure 5 It is along Figure 4A The cross-sectional view taken from line II-II' in the diagram. Figure 6A , Figure 6B and Figure 6C It is based on Figure 4A An enlarged view of region P4 in the implementation method.

[0039] Reference Figure 4A , Figure 4B and Figure 5 The semiconductor device 100C may further include an intermediate insulating layer 23 between the via insulating layer 21 and the cap insulating layer 25. The air gap AG may include an outer air gap (also referred to as a first air gap) AG1 formed between the via insulating layer 21 and the intermediate insulating layer 23, and an inner air gap (also referred to as a second air gap) AG2 formed between the intermediate insulating layer 23 and the cap insulating layer 25. Either or both of the outer air gap AG1 and the inner air gap AG2 may be formed by air such as clean dry air (CDA) or may include air such as clean dry air (CDA), and / or may be in a vacuum; however, the inventive concept is not limited thereto. The dielectric constant of the outer air gap AG1 and / or the inner air gap AG2 may be about 1.0, and may be the same or different from each other; however, the exemplary embodiments are not limited thereto.

[0040] An intermediate insulating layer 23 may be disposed inside the channel insulating layer 21. The intermediate insulating layer 23 may have a cylindrical shape, such as a hollow cylindrical shape. The intermediate insulating layer 23 may surround the cover insulating layer 25 outside the cover insulating layer 25. The intermediate insulating layer 23 may be spaced apart from the channel insulating layer 21 and the cover insulating layer 25. The lower portion of the intermediate insulating layer 23 may partially extend into the lower insulating layer 60. The horizontal LV23 at the lower end of the intermediate insulating layer 23 may be located between the horizontal LV1 of the lower surface 10B of the substrate 10 and the horizontal LV2 of the lower end of the TSV structure 30. The thickness of the intermediate insulating layer 23 may be equal to or different from the thickness of the channel insulating layer 21, and / or may be equal to or different from the thickness of the cover insulating layer 25. The intermediate insulating layer 23 may comprise one or more of the same materials as the channel insulating layer 21 and the cover insulating layer 25, for example, it may be composed of one or more of the same materials as the channel insulating layer 21 and the cover insulating layer 25.

[0041] In some example embodiments, the lower ends of the channel insulating layer 21, the intermediate insulating layer 23, and the cover insulating layer 25 may have different levels, such as being at different levels. For example, the lower end of the channel insulating layer 21 may have the lowest level LV21, the lower end of the cover insulating layer 25 may have the highest level LV25, and the lower end of the intermediate insulating layer 23 may be located between the lower end of the channel insulating layer 21 and the lower end of the cover insulating layer 25.

[0042] The outer air gap AG1 may be defined by the intermediate insulating layer 23, the via insulating layer 21, the lower insulating layer 60, and the wiring layer 40. A portion of the lower insulating layer 60 may extend between the via insulating layer 21 and the intermediate insulating layer 23 to seal the outer air gap AG1, thereby defining the lower end of the outer air gap AG1. The horizontal LVAG1 of the lower end of the outer air gap AG1 may be located between the horizontal LV1 of the lower surface 10B of the substrate 10 and the horizontal LV2 of the lower end of the TSV structure 30. The horizontal LVAG1 of the lower end of the outer air gap AG1 may be higher than either or both of the horizontal LV21 and LV23 of the lower ends of the via insulating layer 21 and the intermediate insulating layer 23. The horizontal LVAG1 of the lower end of the outer air gap AG1 may be lower than the horizontal LV25 of the lower end of the cover insulating layer 25; however, the exemplary embodiment is not limited thereto.

[0043] The inner air gap AG2 can be defined by an intermediate insulating layer 23, a cover insulating layer 25, a lower insulating layer 60, and a wiring layer 40. A portion of the lower insulating layer 60 can extend between the intermediate insulating layer 23 and the cover insulating layer 25 to seal the inner air gap AG2, thus defining the lower end of the inner air gap AG2. The horizontal LVAG2 of the upper end of the portion of the lower insulating layer 60 extending between the intermediate insulating layer 23 and the cover insulating layer 25 can be different from the horizontal LVAG1 of the upper end of the portion of the lower insulating layer 60 extending between the intermediate insulating layer 23 and the passage insulating layer 21. Thus, the horizontal LVAG1 of the lower end of the outer air gap AG1 can be different from the horizontal LVAG2 of the lower end of the inner air gap AG2, and the vertical length of the outer air gap AG1 can be different from the vertical length of the inner air gap AG2. For example, the horizontal LVAG1 of the lower end of the outer air gap AG1 can be lower than the horizontal LVAG2 of the lower end of the inner air gap AG2. For example, the vertical length of the outer air gap AG1 can be greater than the vertical length of the inner air gap AG2.

[0044] Although not shown, in some example embodiments, the lower ends of each or at least two of the via insulating layer 21, intermediate insulating layer 23, and cover insulating layer 25 may be at the same level. The upper end of the portion of the lower insulating layer 60 extending between the intermediate insulating layer 23 and the cover insulating layer 25 may be at the same level as the upper end of the portion of the lower insulating layer 60 extending between the intermediate insulating layer 23 and the via insulating layer 21. Thus, the lower end of the inner air gap AG2 may be at the same level as the lower end of the outer air gap AG1. For example, the vertical length of the outer air gap AG1 may be equal to the vertical length of the inner air gap AG2.

[0045] Reference Figure 6A In some example implementations, the horizontal widths W1 and W2 of the outer air gap AG1 and the inner air gap AG2 can be substantially equal. (Refer to...) Figure 6B and Figure 6C In some example implementations, the horizontal width W1 of the outer air gap AG1 may differ from the horizontal width W2 of the inner air gap AG2. (Refer to...) Figure 6B For example, the horizontal width W2 of the inner air gap AG2 can be greater than the horizontal width W1 of the outer air gap AG1. (Refer to...) Figure 6C For example, the horizontal width W2 of the inner air gap AG2 can be smaller than the horizontal width W1 of the outer air gap AG1.

[0046] Figure 7A These are cross-sectional views of semiconductor devices according to some exemplary embodiments of the inventive concept. Figure 7B yes Figure 7A A magnified view of region P5 in the image.

[0047] Reference Figure 7A and Figure 7B The vertical lengths of the via insulating layer 21, intermediate insulating layer 23, and cap insulating layer 25 included in the semiconductor device 100D can be different. For example, the horizontal LV21, LV23, and LV25 at the lower ends of the via insulating layer 21, intermediate insulating layer 23, and cap insulating layer 25 can be different from each other. In some example embodiments, the horizontal LV21 at the lower end of the via insulating layer 21 can be the highest, the horizontal LV25 at the lower end of the cap insulating layer 25 can be the lowest, and the lower end of the intermediate insulating layer 23 can be disposed between the lower end of the via insulating layer 21 and the lower end of the cap insulating layer 25.

[0048] The vertical lengths of the inner air gap AG2 and the outer air gap AG1 can be different. The horizontal LVAG1 at the upper end of the portion of the lower insulating layer 60 extending between the through insulating layer 21 and the intermediate insulating layer 23 can be higher than the horizontal LVAG2 at the upper end of the portion of the lower insulating layer 60 extending between the intermediate insulating layer 23 and the cover insulating layer 25. Thus, the vertical length of the inner air gap AG2 can be greater than the vertical length of the outer air gap AG1.

[0049] Figures 8 to 25 This is a cross-sectional process flow diagram illustrating a method for producing / manufacturing a semiconductor device according to some exemplary embodiments of the inventive concept.

[0050] Reference Figure 8 The method may include forming a front-end process (FEOL) structure 11 on a substrate 10, including an interlayer insulating layer 12 and multiple individual devices 13 of various types; forming an etch stop layer 14 on the FEOL structure 11; and forming a mask pattern 16 on the etch stop layer 14. A hole 16H exposing a portion of the upper surface of the etch stop layer 14 may be formed at the mask pattern 16. For example, the etch stop layer 14 may comprise silicon nitride or silicon oxide nitride. The etch stop layer 14 may be formed having approximately 200 to... The thickness is, but not limited to, that of the etch stop layer 14. The etch stop layer 14 can be formed by chemical vapor deposition (CVD) processes such as plasma-enhanced CVD (PECVD) and / or low-pressure CVD (LPCVD). The mask pattern 16 can be composed of / correspond to a photoresist film.

[0051] Reference Figure 9 The method may include forming a via H. Forming the via H may include using a mask pattern 16 as an etching mask to etch the etch stop layer 14, the interlayer insulating layer 12, and the substrate 10. The via H may be formed using Bosch processes and / or laser drilling techniques. For example, the via H may be formed with a width of about 10 μm or less. The via H may be formed with a depth of about 50 to 100 μm from the upper surface of the interlayer insulating layer 12, while the thickness of the substrate 10 may be 775 μm; however, the example embodiments are not limited thereto. The width and / or depth of the via H are not limited to the conditions described above, and the via H may be formed with various sizes if necessary. After forming the via H, the mask pattern 16 may be removed, thereby exposing the upper surface of the etch stop layer 14.

[0052] Now refer to Figure 10 The method may include forming a via insulating layer 21 in the via H and on the etch stop layer 14. The via insulating layer 21 may be formed using CVD and / or thermal growth processes to conformally cover the inner sidewalls and inner bottom surface of the substrate 10 exposed through the via H, the inner sidewalls of the interlayer insulating layer 12, and the inner sidewalls of the etch stop layer 14, and conformally cover the upper surface of the etch stop layer 14. For example, the via insulating layer 21 may include any one or both of oxides and nitrides.

[0053] Reference Figure 11The method may include forming a sacrificial insulating layer 22 on the via insulating layer 21 using, for example, a CVD process, and forming a cap insulating layer 25 on the sacrificial insulating layer 22 using, for example, a CVD process performed separately from and / or in situ with respect to the formation of the sacrificial insulating layer 22.

[0054] The sacrificial insulating layer 22 may be formed to cover the surface of the via insulating layer 21. The material included in the sacrificial insulating layer 22 may include a material that has etch selectivity relative to the via insulating layer 21, for example, it may be etched slower or faster than the via insulating layer 21, and may include any of oxides, nitrides, and low-k dielectrics. For example, when the via insulating layer 21 includes an oxide, the sacrificial insulating layer 22 may include a nitride, and when the via insulating layer 21 includes a nitride, the sacrificial insulating layer 22 may include a nitride or a low-k dielectric.

[0055] The cover insulation layer 25 may be formed to cover the surface of the sacrificial insulation layer 22. In some example embodiments, the cover insulation layer 25 may comprise the same material as the pass insulation layer 21. For example, the cover insulation layer 25 may comprise oxides and / or nitrides.

[0056] The thicknesses of the path insulation layer 21, the sacrificial insulation layer 22, and the cap insulation layer 25 may be equal or different. If necessary, the thickness ratios between the path insulation layer 21, the sacrificial insulation layer 22, and the cap insulation layer 25 may be determined to be different. Each or some of the path insulation layer 21, the sacrificial insulation layer 22, and the cap insulation layer 25 may be formed by chemical vapor deposition (CVD) processes such as plasma-enhanced chemical vapor deposition (PECVD) and / or low-pressure CVD (LPCVD).

[0057] Reference Figure 12 The method may include forming a barrier layer 31 on the cover insulating layer 25 and forming a metal layer 33p on the barrier layer 31.

[0058] The barrier layer 31 can be formed to cover the surface of the insulating layer 25. The barrier layer 31 can be formed using at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) processes. The barrier layer 31 can be constituted / included in a multilayer film comprising two materials or a monolayer film made of one material. For example, the barrier layer 31 can include at least one material selected from W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB.

[0059] The metal layer 33p can be formed to cover the surface of the barrier layer 31. The metal layer 33p can be formed to not only completely fill the internal space of the via H, but also to have a specific (e.g., variablely determined or predetermined) thickness outside the via H. The metal layer 33p can be formed by an electroplating process. The formation of the metal layer 33p can be achieved by forming a seed layer on the surface of the barrier layer 31 and growing a metal film from the seed layer via an electroplating process. The seed layer can be made of at least one of Cu, Cu alloys, Co, Ni, Ru, Co / Cu, and Ru / Cu. The seed layer can be formed by a physical vapor deposition (PVD) process; however, the example embodiments are not limited thereto. The metal layer 33p can include Cu or W. The metal layer 33p can be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuW, W, or W alloys, but is not limited thereto. The electroplating process can be performed at a temperature of about 10 to 65°C. For example, the electroplating process can be performed at room temperature. After the metal layer 33p is formed, it may be annealed at a temperature of about 150 to 450°C if necessary.

[0060] Reference Figure 13 The method may include forming a TSV 33. Forming the TSV 33 may include removing the upper portions of the metal layer 33p, barrier layer 31, cap insulating layer 25, sacrificial insulating layer 22, and via insulating layer 21 by a process such as chemical mechanical polishing (CMP), thereby exposing the etch stop layer 14. The portions of the metal layer 33p, barrier layer 31, cap insulating layer 25, sacrificial insulating layer 22, and via insulating layer 21 disposed outside the via H may be removed, thus forming the TSV 33 within the via H.

[0061] Reference Figure 14 The method may include heat-treating the TSV 33. The heat treatment may be performed at a temperature of approximately 400 to 500°C. Metal particles constituting / included in the TSV 33 may grow / form according to the heat treatment, thereby reducing the roughness of the exposed surface of the TSV 33. For this purpose, a portion of the TSV 33 may be removed, for example by an etch-back process and / or a chemical mechanical polishing (CMP) process, thereby planarizing the exposed surface of the TSV 33. The etch stop layer 14 may also be removed by a chemical mechanical polishing (CMP) process, thereby exposing the upper surface of the interlayer insulating layer 12.

[0062] Reference Figure 15 , Figure 16 and Figure 17 The method may include forming a wiring layer 40 on the interlayer insulating layer 12. The wiring layer 40 may include conductive pads 45, short paths 48, wiring patterns 49, and an upper insulating layer 47.

[0063] The formation of wiring layer 40 may include forming a plurality of insulating layers 41, 42, and 43 on interlayer insulating layer 12 and patterning the plurality of insulating layers 41, 42, and 43 to form wiring vias PH. The plurality of insulating layers 41, 42, and 43 may include a first insulating layer 41 to a third insulating layer 43 sequentially stacked on interlayer insulating layer 12. The first insulating layer 41 and the third insulating layer 43 may include silicon nitride or silicon oxide nitride. The second insulating layer 42 may include silicon oxide.

[0064] Subsequently, the formation of wiring layer 40 may include forming conductive pads 45 in wiring holes PH. The formation of conductive pads 45 can be achieved by forming conductive material in wiring holes PH and on the third insulating layer 43 using, for example, a damascene or dual damascene process, and performing a planarization process, such as chemical mechanical polishing (CMP), on the conductive material while the third insulating layer 43 serves as a polishing stop layer. The third insulating layer 43 can be removed by the chemical mechanical polishing (CMP) process, thereby exposing the second insulating layer 42.

[0065] Subsequently, the formation of wiring layer 40 may include forming short paths 48, wiring patterns 49, and insulating layers on the second insulating layer 42 and conductive pad 45. The formation of short paths 48, wiring patterns 49, and insulating layers may be similar to bonding. Figure 15 and Figure 16 The process for forming the conductive pad 45 is described. For example, the formation of the short passage 48 and / or wiring pattern 49 can be achieved by forming an insulating layer with holes and filling the holes with a conductive material. The short passage 48 and wiring pattern 49 can be alternately stacked on the conductive pad 45 as they are formed alternately. An upper insulating layer 47 can be formed when the insulating layers formed during the formation of the conductive pad 45, the short passage 48, and the wiring pattern 49 are stacked. For example, each of the short passage 48 and wiring pattern 49 may include at least one of W, Al, and Cu, and may or may not include the same material.

[0066] Now refer to Figure 18 The method may include forming a connection terminal 50 on the wiring layer 40. The connection terminal 50 may be, or may include, solder balls, but is not limited thereto.

[0067] Reference Figure 19The method may include partially removing the substrate 10, thereby causing the TSV 33 to protrude from the substrate 10. With the substrate 10 in an inverted state, the substrate 10 may be partially removed from its lower surface 10B. The substrate 10 may be partially removed using an etching process such as a wet etching process and / or a dry etching process. When the substrate 10 is partially removed, the surface of the via insulating layer 21 is partially exposed, and portions of the TSV 33, the barrier layer 31, the via insulating layer 21, the sacrificial insulating layer 22, and the cap insulating layer 25 may protrude from the lower surface 10B of the substrate 10. In some example embodiments, when the substrate 10 is partially removed, the exposed via insulating layer 21 may also be partially removed.

[0068] Reference Figure 20 The method may include partially removing the via insulating layer 21 to expose the sacrificial layer 22. The via insulating layer 21 may be removed until the lower surface of the sacrificial insulating layer 22 is exposed. In some example embodiments, when the substrate 10 is partially removed, the via insulating layer 21 may be partially removed together with the substrate 10 to expose the sacrificial insulating layer 22. In this case, the process of partially removing the via insulating layer 21 may be omitted, and it is a separate process from the process of partially removing the substrate 10.

[0069] Reference Figure 21 The method may include removing the sacrificial insulating layer 22 to form a trench TR. By removing the sacrificial insulating layer 22, the trench TR can be formed between the passage insulating layer 21 and the cover insulating layer 25. For example, when the sacrificial insulating layer 22 is an oxide, it can be removed using a Limulus amoebocyte lysate (LAL) stripping process or a chemical oxide removal (COR) process. For example, when the sacrificial insulating layer 22 is a nitride, it can be removed using a phosphoric acid stripping process. In some example embodiments, the sacrificial insulating layer 22 may be incompletely removed, such that at least some portion of it remains around the conductive pad 45.

[0070] Reference Figure 22The method may include partially removing the cap insulating layer 25, thereby exposing the barrier layer 31. When the cap insulating layer 25 is removed, at least a portion of the via insulating layer 21 may also be removed, thereby reducing the height of the lower end of the via insulating layer 21 protruding from the lower surface 10B of the substrate 10. The via insulating layer 21 and the cap insulating layer 25 may be removed, for example by a wet etching process, until the level of their lower ends becomes lower than the level of the lower end of the TSV 33 (in the inverted state of the substrate 10). This reduces the height of the trench TR. The lower ends of the via insulating layer 21 and the cap insulating layer 25 may be positioned at a level higher than the lower surface 10B of the substrate 10 (in the inverted state of the substrate 10). For example, the lower portions of the via insulating layer 21 and the cap insulating layer 25 may protrude from the lower surface 10B of the substrate 10.

[0071] Reference Figure 23 The method may include forming a lower insulating layer 60 comprising a capping layer 61, a support layer 63, and a passivation layer 65 on the lower surface 10B of the substrate 10. The formation of the lower insulating layer 60 may include sequentially forming the capping layer 61, the support layer 63, and the passivation layer 65 on the lower surface 10B of the substrate 10. After the lower insulating layer 60 is formed, an air gap AG may be formed. The air gap AG may be formed under pressure; however, the exemplary embodiment is not limited thereto. Furthermore, the air gap AG may comprise air, such as clean, dry air; however, the exemplary embodiment is not limited thereto.

[0072] Cap layer 61 can be formed to cover the exposed surface of substrate 10 and the surface of barrier layer 31 protruding from substrate 10. Cap layer 61 can seal trench TR while covering exposed via insulating layer 21 and exposed cap insulating layer 25. A portion of cap layer 61 can extend between via insulating layer 21 and cap insulating layer 25, thus having a shape that protrudes from cap layer 61. For example, cap layer 61 can comprise silicon oxide.

[0073] A support layer 63 may be formed to cover the surface of the capping layer 61. The support layer 63 may function to support the TSV 33 protruding from the substrate 10 to prevent or reduce the likelihood of the TSV 33 bending during a chemical mechanical polishing (CMP) process. For example, the support layer 63 may comprise a silicon nitride. A passivation layer 65 may be formed to cover the surface of the support layer 63. For example, the passivation layer 65 may comprise a silicon oxide. The capping layer 61, the support layer 63, and the passivation layer 65 may be formed using chemical vapor deposition (CVD) processes (such as PECVD and / or LPCVD processes) and / or ALD processes.

[0074] Reference Figure 24The method may include polishing and / or etching back the underlying insulating layer 60 to planarize the exposed surface of the underlying insulating layer 60. The barrier layer 31 and TSV 33 may be exposed through a polishing process. Furthermore, the support layer 63 and capping layer 61 may be exposed through a polishing process.

[0075] Reference Figure 25 The method may include forming a conductive layer 70 connected to the TSV 33 on the lower insulating layer 60. The conductive layer 70 may be formed by electroplating under the condition that a seed layer is provided on the TSV 33. The conductive layer 70 may be made of Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CrCu or combinations thereof. For example, the conductive layer 70 may be composed of / included in the following: a Cr / Cu / Au stacked structure, a Cr / CrCu / Cu stacked structure, a TiWCu compound, a TiWCu / Cu stacked structure, a Ni / Cu stacked structure, a NiV / Cu stacked structure, a Ti / Ni stacked structure, a Ti / NiP stacked structure, a TiWNiV compound, an Al / Ni / Au stacked structure, an Al / NiP / Au stacked structure, a Ti / TiNi / CuNi stacked structure, a Ti / Ni / Pd stacked structure, a Ni / Pd / Au stacked structure, or a NiP / Pd / Au stacked structure. In some example implementations, the conductive layer 70 may be a stacked structure of Ti / Cu / Ni / Au.

[0076] Figures 26 to 36 This is a process flow diagram illustrating a method for manufacturing / producing a semiconductor device according to some exemplary embodiments of the inventive concept.

[0077] Reference Figure 26 The method may include combining Figure 8 and Figure 9 The described process forms a via H extending through the substrate 10 and the interlayer insulating layer 12, and then forms the via insulating layer 21, the first sacrificial insulating layer 22, the intermediate insulating layer 23, the second sacrificial insulating layer 24 and the cap insulating layer 25 on the substrate 10 by sequentially stacking the via insulating layer 21, the first sacrificial insulating layer 22, the intermediate insulating layer 23, the second sacrificial insulating layer 24 and the cap insulating layer 25.

[0078] In some example embodiments, the via insulating layer 21, the intermediate insulating layer 23, and the cap insulating layer 25 may be made of the same material or multiple materials, for example, they may comprise the same material or multiple materials, or be composed of the same material or multiple materials. The first sacrificial insulating layer 22 and the second sacrificial insulating layer 24 may be made of the same material or multiple materials, for example, they may comprise the same material or multiple materials, or be composed of the same material or multiple materials. Each of the via insulating layer 21, the intermediate insulating layer 23, and the cap insulating layer 25 may comprise a material different from the material of the first sacrificial insulating layer 22 and the second sacrificial insulating layer 24. Each of the via insulating layer 21, the intermediate insulating layer 23, and the cap insulating layer 25 may be made of a material that has etch selectivity relative to each of the first sacrificial insulating layer 22 and the second sacrificial insulating layer 24. For example, each of the via insulating layer 21, the intermediate insulating layer 23, and the cap insulating layer 25 may be silicon oxide and / or silicon nitride, may comprise silicon oxide and / or silicon nitride, or may be composed of silicon oxide and / or silicon nitride. Each of the first sacrificial insulating layer 22 and the second sacrificial insulating layer 24 may be a silicon oxide, a silicon nitride, or a low-k dielectric, and may be composed of silicon oxide, silicon nitride, or a low-k dielectric.

[0079] Reference Figure 27 The method may include forming a barrier layer 31 on the cover insulating layer 25 and forming a metal layer 33p on the barrier layer 31.

[0080] Reference Figure 28 The method may include by combining with Figures 13 to 18 The processes described are the same or similar to form TSV 33, wiring layer 40 and connection terminal 50.

[0081] Reference Figure 29 The method may include partially removing the substrate 10, thereby causing the TSV 33 to protrude from the lower surface of the substrate 10. By partially removing the substrate 10 from the lower surface of the substrate 10 in an inverted state, a portion of the surface of the via insulating layer 21 can be exposed, and the lower portions of the TSV 33, the barrier layer 31, the cap insulating layer 25, the second sacrificial insulating layer 24, the intermediate insulating layer 23, the first sacrificial insulating layer 22, and the via insulating layer 21 can protrude from the lower surface of the substrate 10.

[0082] Reference Figure 30 The method may include partially removing the via insulating layer 21 to expose the first sacrificial insulating layer 22. The via insulating layer 21 may be removed until the lower surface of the first sacrificial insulating layer 22 is exposed. In some example embodiments, when the substrate 10 is as Figure 29When the partially removed / etched layer 21 is shown, the via insulating layer 21 is also removed / etched, thus exposing the first sacrificial insulating layer 22. In this case, the process of partially removing the via insulating layer 21 can be omitted, as it is a separate process from the process of partially removing the substrate 10.

[0083] Reference Figure 31 The method may include removing the first sacrificial insulating layer 22 to form the first trench TR1. For example, when the first sacrificial insulating layer 22 is an oxide, it may be removed using a horseshoe crab cell lysate (LAL) stripping process or a chemical oxide removal (COR) process. For example, when the first sacrificial insulating layer 22 is a nitride, it may be removed using a wet etching process such as a phosphoric acid stripping process.

[0084] Reference Figure 32 The method may include partially removing the intermediate insulating layer 23 to expose the second sacrificial insulating layer 24. The intermediate insulating layer 23 may be removed until the lower surface of the second sacrificial insulating layer 24 is exposed. When the intermediate insulating layer 23 is removed, a portion of the via insulating layer 21, which comprises the same material as the intermediate insulating layer 23, may also be etched, for example, by wet etching.

[0085] Reference Figure 33 The method may include removing the second sacrificial insulating layer 24 to form a second trench TR2. By removing the second sacrificial insulating layer 24, the second trench TR2 can be formed between the intermediate insulating layer 23 and the cap insulating layer 25. The second sacrificial insulating layer 24 can be removed using the same process as that used to remove the first sacrificial insulating layer 22.

[0086] Reference Figure 34 The method may include partially removing the cover insulation layer 25 to expose the barrier layer 31. When the cover insulation layer 25 is removed, the passage insulation layer 21 and the intermediate insulation layer 23 may also be removed, thereby reducing the height of the lower ends of the passage insulation layer 21 and the intermediate insulation layer 23.

[0087] Reference Figure 35 The method may include forming a lower insulating layer 60. The formation of the lower insulating layer 60 may include sequentially forming a capping layer 61, a support layer 63, and a passivation layer 65 on the lower surface of the substrate 10.

[0088] The capping layer 61 can be formed to cover the exposed surface of the substrate 10 and the surface of the barrier layer 31 protruding from the substrate 10. The capping layer 61 can seal the first trench TR1 and the second trench TR2 while covering the exposed via insulating layer 21, the exposed intermediate insulating layer 23, and the exposed cap insulating layer 25, thereby forming a first air gap AG1 and a second air gap AG2. A portion of the capping layer 61 can extend between the via insulating layer 21 and the intermediate insulating layer 23, thus sealing the first trench TR1 and forming the first air gap AG1. Another portion of the capping layer 61 can extend between the intermediate insulating layer 23 and the cap insulating layer 25, thus sealing the second trench TR2 and forming the second air gap AG2. The first air gap AG1 and / or the second air gap AG2 can be formed as a vacuum; however, the exemplary embodiment is not limited thereto. The pressure in the first air gap AG1 and / or the second air gap AG2 can be less than atmospheric pressure; however, the exemplary embodiment is not limited thereto.

[0089] Reference Figure 36 The method may include etching and / or polishing the lower insulating layer 60 to planarize the exposed surface of the lower insulating layer 60. The barrier layer 31 and TSV 33 may be exposed through a polishing process. Furthermore, the support layer 63 and capping layer 61 may be exposed through a polishing process.

[0090] Subsequently, referring to Figure 4A The method may include forming a conductive layer 70 connected to the TSV 33 on the lower insulating layer 60.

[0091] Figure 37 This is a cross-sectional view of a semiconductor package according to some exemplary embodiments of the inventive concept.

[0092] Reference Figure 37 The semiconductor package 200 may include a package substrate 210, at least one semiconductor chip 100 mounted on the package substrate 210, and a molding layer 220 covering the at least one semiconductor chip 100 on the package substrate 210. Although two semiconductor chips 100 are shown as stacked in the figure, various numbers of stacked semiconductor chips 100, such as 4, 8, 16, etc., may be used.

[0093] The package substrate 210 may be a printed circuit board in which the wiring structure 213 is included. External connection terminals 215 electrically connected to the wiring structure 213 may be disposed on the package substrate 210. The external connection terminals 215 can electrically connect the wiring structure 213 to external devices. For example, the external connection terminals may be solder balls, but are not limited thereto.

[0094] The packaging substrate 210 and the semiconductor chip 100 can be electrically connected to each other via the TSV structure 30 and the connection terminal 50. Alternatively or additionally, adjacent semiconductor chips in the semiconductor chip 100 can be electrically connected to each other via the TSV structure 30, the connection terminal 50 and the conductive layer 70.

[0095] Figure 37 The semiconductor chip 100 may include a combination of Figure 1A The constituent elements are described. Although the semiconductor package 200 is in Figure 37 The middle is shown as including the combination Figure 1A The constituent elements described, however, the semiconductor package 200 may include combinations of Figure 3A , Figure 4A or Figure 7A The constituent elements described.

[0096] The molding layer 220 may surround a side surface of the semiconductor chip 100. The molding layer 220 may cover at least a portion of the upper surface of the semiconductor chip 100. The molding layer 220 may cover the top surface of the packaging substrate. The molding layer 220 may contact the connection terminal 50. For example, the molding layer 220 may include EMC (epoxy molding compound).

[0097] According to some example embodiments, the insulating film includes an air gap with a capacitance close to 1 between the TSV and the substrate. Due to this air gap, the TSV can have improved / superior insulation properties relative to the substrate. Alternatively or additionally, the insulating film and / or air gap surrounding the TSV can be provided in multiple forms, thus avoiding or reducing the likelihood of damage or degradation to the insulating film. Alternatively or additionally, the breakdown voltage (BV) of the TSV can be maintained, and / or its parasitic capacitance can be reduced. Therefore, a semiconductor device with improved reliability can be provided.

[0098] While some exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of this disclosure and without altering its essential characteristics. Therefore, the above embodiments should be considered in a descriptive sense only and not for limiting purposes.

[0099] This application claims priority to Korean Patent Application No. 10-2020-0119642, filed on September 17, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor device, comprising: A front-end process (FEOL) structure, comprising individual devices and an interlayer insulating layer, is formed on the upper surface of the substrate; Forming vias extending through the substrate and the interlayer insulating layer; A via insulating layer is formed, which covers the inner sidewalls of the substrate exposed through the via and the inner bottom surface of the substrate exposed through the via; A sacrificial insulating layer covering the passage insulating layer is formed in the through hole; A cover insulation layer is formed in the through hole to cover the sacrificial insulation layer; A barrier layer covering the cover insulation layer is formed in the through hole; A through-silicon via (TSV) is formed on the barrier layer to fill the via. The substrate is partially removed from its lower surface so that the lower portion of the via insulating layer, the lower portion of the sacrificial insulating layer, the lower portion of the cap insulating layer, the lower portion of the barrier layer, and the lower portion of the through silicon via protrude from the lower surface of the substrate. Partially remove the pathway insulation layer to expose the sacrificial insulation layer; Remove the sacrificial insulation layer to form a trench between the passage insulation layer and the cover insulation layer; as well as A lower insulating layer is formed on the lower surface of the substrate to seal the trenches and form an air gap. The lower end of the passage insulation layer and the lower end of the cover insulation layer are located in the lower insulation layer, and their levels are different from each other.

2. The method of claim 1, wherein forming the trench includes removing the sacrificial insulation layer to expose the cover insulation layer.

3. The method according to claim 1, further comprising: After the trench is formed, the cover insulation layer is partially removed to expose the barrier layer.

4. The method of claim 3, wherein the partial removal of the cover insulation layer simultaneously partially removes the passage insulation layer and exposes the barrier layer.

5. The method of claim 4, wherein the level of the lower end of the via insulating layer and the cover insulating layer is between the level of the lower surface of the substrate and the level of the lower end of the through silicon via.

6. The method of claim 1, wherein a portion of the lower insulating layer extends between the passage insulating layer and the cover insulating layer to define a lower end of the air gap.

7. The method of claim 6, wherein the portion of the lower insulating layer extending between the passage insulating layer and the cover insulating layer is on the lower surface of the substrate.

8. The method of claim 1, wherein the passage insulation layer and the cover insulation layer are spaced apart from each other.

9. A semiconductor device, comprising: An interlayer insulating layer covering the upper surface of the substrate; Individual devices within the interlayer insulation layer; A lower insulating layer covering the lower surface of the substrate; A through-silicon via (TSV) structure extending through the substrate, through the interlayer insulating layer, and through the lower insulating layer; A conductive pad connected to the upper end of the through-silicon via structure; A via insulating layer surrounding the through-silicon via structure; as well as A cover insulating layer surrounds the through silicon via structure inside the via insulating layer, with an air gap between the via insulating layer and the cover insulating layer. A portion of the air gap extends into the lower insulating layer. The lower end of the passage insulation layer and the lower end of the cover insulation layer are located in the lower insulation layer, and their levels are different from each other.

10. The semiconductor device of claim 9, wherein the via insulating layer and the cover insulating layer are spaced apart from each other.

11. The semiconductor device of claim 9, wherein the via insulating layer extends into the lower insulating layer.

12. The semiconductor device of claim 9, wherein the cover insulating layer extends into the lower insulating layer.

13. The semiconductor device of claim 9, wherein the lower ends of the via insulating layer and the cap insulating layer are between the lower surface of the substrate and the lower end of the through silicon via structure.

14. The semiconductor device of claim 9, wherein each of the via insulating layer and the cap insulating layer comprises silicon nitride.

15. The semiconductor device according to claim 9, wherein The through-silicon pathway structure includes: Open up silicon pathways; as well as The barrier layer surrounding the through silicon pathway, and The lower insulating layer surrounds the outer side surface of the barrier layer.

16. The semiconductor device according to claim 9, further comprising: An intermediate insulating layer between the passage insulating layer and the cover insulating layer.

17. The semiconductor device of claim 16, wherein the air gap includes a first air gap between the through insulating layer and the intermediate insulating layer.

18. The semiconductor device of claim 17, wherein the air gap includes a second air gap between the intermediate insulating layer and the cap insulating layer.

19. A semiconductor device, comprising: An interlayer insulating layer covering the upper surface of the substrate; Individual devices within the interlayer insulation layer; A lower insulating layer covering the lower surface of the substrate; A through-silicon via (TSV) structure extending through the substrate, through the interlayer insulating layer, and through the lower insulating layer; A conductive pad connected to the upper end of the through-silicon via structure; A via insulating layer surrounding the through-silicon via structure; A cover insulating layer surrounds the through silicon pathway structure, the cover insulating layer being inside the pathway insulating layer; An intermediate insulating layer between the passage insulating layer and the cover insulating layer, wherein The through-hole insulating layer and the intermediate insulating layer have a first air gap between them. The intermediate insulating layer and the cover insulating layer have a second air gap therebetween, and The vertical lengths of the first air gap and the second air gap are different.

20. The semiconductor device of claim 19, wherein the first air gap and the second air gap have different horizontal widths.

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