Semiconductor package structure

Abstract

The application relates to a semiconductor packaging structure. The semiconductor packaging structure comprises a substrate, a first chip and a second chip which are laterally spaced apart on the substrate, and a bridge circuit layer between the first chip and the second chip, the first chip and the second chip being electrically connected to the bridge circuit layer through leads.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] For existing semiconductor packaging structures such as Fan-Out Chip on Substrate (FOCoS), when connecting fan-out chips, using a bridge die connected to the fan-out chips may encounter the following problems: Figure 1a As shown, functional chips, namely chip 20 and chip 30, are attached to substrate 10. The upper surface of chip 20 is higher than the upper surface of chip 30. When there is a large height difference between the upper surfaces of chip 20 and chip 30, when bridging chip 40 is connected to chip 20 and chip 30, as shown in region S1, bridging chip 40 and chip 20 will not be connected.

[0003] like Figure 1b As shown, the common plane interface between chips 20 and 30 can be completed through processes such as molding molding compound 50 and grinding, and the bridging chip 40 can be bonded on this common plane interface. Although this method can solve the above-mentioned problems, it requires more process steps and is correspondingly more expensive.

[0004] If two functional chips are directly connected using bonding wires, the large pitch between the chips will result in a high bonding height for the wires, which will increase the thickness of the entire semiconductor package structure. Summary of the Invention

[0005] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure and its formation method, which can reduce the wire bonding height.

[0006] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: a substrate; a first chip and a second chip, the first chip and the second chip being disposed laterally spaced on the substrate; and a bridging circuit layer located between the first chip and the second chip, wherein both the first chip and the second chip are electrically connected to the bridging circuit layer via leads.

[0007] In some embodiments, a bridging layer spans the gap between the first chip and the second chip and is disposed on the first chip and the second chip.

[0008] In some embodiments, the bridging line layer has a tilt angle.

[0009] In some embodiments, a first rewiring layer is provided between the first chip and the bridging layer, and a second rewiring layer is provided between the second chip and the bridging layer. The first rewiring layer has a first I / O interface, and the second rewiring layer has a second I / O interface. The first I / O interface and the second I / O interface are not coplanar.

[0010] In some embodiments, the second I / O interface is higher than the first I / O interface, wherein the opposing sidewalls of the first and second rewiring layers have a stepped structure, and the bridging line layer is disposed on the stepped structure.

[0011] In some embodiments, both the first chip and the second chip are electrically connected to the substrate via leads.

[0012] In some embodiments, the semiconductor package structure further includes a bridging chip located between the bridging circuit layer and the first chip and the second chip.

[0013] In some embodiments, the semiconductor package structure further includes a third chip, with the second and third chips located on opposite sides of the first chip; and an additional bridging layer located between the first and third chips, with both the first and third chips electrically connected to the additional bridging layer via leads.

[0014] In some embodiments, the I / O interfaces corresponding to the second and third chips are higher than the I / O interface corresponding to the first chip.

[0015] In some embodiments, the upper surfaces of the first chip and the second chip are not flush, the bridging circuit layer has a tilt angle, and a lead is provided below the bridging circuit layer to electrically connect one of the first chip and the second chip to the substrate. Attached Figure Description

[0016] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0017] Figure 1a and Figure 1b These are side and top views of the current semiconductor packaging structure, respectively.

[0018] Figure 2 This is a side view schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0019] Figure 3a This is a side view schematic diagram of a portion of a semiconductor packaging structure according to an embodiment of the present invention.

[0020] Figure 3b yes Figure 3aThe diagram shows a top view of the semiconductor package structure at section A-A'.

[0021] Figures 4a to 7 This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention.

[0022] Figures 8a to 8j This is a schematic diagram of the various stages of a method for forming a first chip and a second chip in a semiconductor package structure according to an embodiment of the present invention.

[0023] Figures 9a to 9h This is a schematic diagram of the various stages of a method for forming a bridging chip in a semiconductor package structure according to an embodiment of the present invention.

[0024] Figures 10a to 10i This is a schematic diagram of various stages of a method for forming a semiconductor package structure using a pre-formed first chip, a second chip, and a bridging chip according to an embodiment of the present invention. Specific Implementation

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0026] An embodiment of the present invention provides a semiconductor packaging structure. Figure 2 This is a side view schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Figure 2 The semiconductor package structure shown includes a substrate 200, with a first chip 210 and a second chip 220 laterally spaced above the substrate 200. Solder balls 208 may be disposed below the substrate 200. In some embodiments, the spacing between the first chip 210 and the second chip 220 is in the range of 30 μm to 300 μm. In some embodiments, the first chip 210 and the second chip 220 may be attached to the substrate 200 respectively by an adhesive layer 204. The thicknesses of the first chip 210 and the second chip 220 may be different, and after being disposed on the substrate 200, the upper surfaces of the first chip 210 and the second chip 220 are not flush. Figure 2 In the embodiment shown, the upper surface of the second chip 220 is higher than the upper surface of the first chip 210.

[0027] A bridging layer 240 is located between the first chip 210 and the second chip 220, bridging both chips. The bridging layer 240 may include a dielectric layer 241 and conductive lines 242, such as vias and traces, located within the dielectric layer 241. Because the upper surface of the second chip 220 is higher than the upper surface of the first chip 210, the bridging layer 240 bridging the first and second chips 220 has a tilt angle. The first chip 210 and the second chip 220 are electrically connected to the bridging layer 240 via bonding wires 205.

[0028] In the above-described technical solution of the invention, a bridging layer 240 is provided between the first chip 210 and the second chip 220, and leads 205 are used to electrically connect the bridging layer 240 to the first chip 210 and the second chip 220, respectively, thereby achieving electrical connection between the first chip 210 and the second chip 220. Therefore, by providing the bridging layer 240, the connection path of the leads can be shortened, avoiding the problem of excessive wire bonding height caused by the large pitch between the first chip 210 and the second chip 220, and further avoiding the increase in semiconductor package thickness caused by excessive wire bonding height. In addition, compared to the tolerance of approximately 5μm allowed by conventional solder bump bonding, wire bonding allows for a larger bonding tolerance, for example, approximately 9μm to 20μm.

[0029] Continue to refer to Figure 2 A first redistribution layer 250 is disposed between the first chip 210 and the bridging layer 240. The first redistribution layer 250 may cover the upper surface of the first chip 210 and be electrically connected to the first chip 210. In the illustrated embodiment, the first redistribution layer 250 includes dielectric layers 251 and 252 and conductive lines, such as vias and traces, located in the dielectric layers 251 and 252. A second redistribution layer 260 is disposed between the second chip 220 and the bridging layer 240. The second redistribution layer 260 may cover the upper surface of the second chip 220 and be electrically connected to the second chip 220. In the illustrated embodiment, the second redistribution layer 260 includes dielectric layers 261, 262, and 263 and conductive lines, such as vias and traces, located in the dielectric layers 261, 262, and 263.

[0030] The first routing layer 250 can be connected to the lead 205 via pads 2505 on its upper surface. The upper surface of the pads 2505 forms a first I / O (input / output) interface 2510 corresponding to the first routing layer 250. Similarly, the second routing layer 260 can be connected to the lead 205 via pads 2605 on its upper surface. The upper surface of the pads 2605 forms a second I / O interface 2610 corresponding to the second routing layer 260. The first I / O interface 2510 of the first routing layer 250 and the second I / O interface 2610 of the second routing layer 260 are not coplanar, such as... Figure 2 As shown, the second I / O interface 2610 of the second rerouting layer 260 is higher than the first I / O interface 2510 of the first rerouting layer 250.

[0031] The first I / O interface 2510 of the first wiring layer 250 is also connected to the pad 202 on the surface of the substrate 200 via a lead 205. The second I / O interface 2610 of the second wiring layer 260 can also be connected to the pad 202 on the surface of the substrate 200 via a lead 205. The first chip 210 and the second chip 220 can be electrically connected to the substrate 200 via leads 205 respectively.

[0032] By providing a bridging layer 240 between the first chip 210 and the second chip 220, the first chip 210 and the second chip 220 are connected by leads 205, and the first chip 210 and the second chip 220 are also connected to the substrate 200 by leads 205. By utilizing leads 205 to achieve electrical connection between the first chip 210 and the second chip 220 and the substrate 200, the wire bonding method can provide more I / O terminals between the first chip 210 and the second chip 220 and the substrate 200. By using wire bonding to connect the bridging line (bridging layer 240) and the functional chips (first chip 210, second chip 220), as well as the functional chips and the substrate 200, instead of existing through-holes for electrical connection, the complex processes of using through-holes (such as drilling, seed layer fabrication, photomask covering, exposure, development, electroplating, and etching) can be avoided, thus reducing manufacturing costs.

[0033] A bridging chip 245 is disposed between the bridging layer 240 and the first chip 210 and the second chip 220. One end of the bridging chip 245 is disposed above the first chip 210, and the other end is disposed above the second chip 220. The bridging chip 245 can be fixed between the first chip 210 and the second chip 220 by an adhesive layer 206. In some embodiments, the thickness of the bridging chip 245 can be in the range of 20 μm to 100 μm. A bridging line 244 is disposed on the upper surface of the bridging chip 245. The bridging layer 240 can cover the bridging line 244 and the upper surface of the bridging chip 245. The bridging line 244 can be electrically connected to the first rewiring layer 250 and the second rewiring layer 260 through conductive lines 242 and leads 205 in the bridging layer 240, respectively.

[0034] In some embodiments, the bridging line layer 240 and the bridging chip 245 are tilted relative to the substrate 200. The tilt angle of the bridging line layer 240 and the bridging chip 245 can be represented by the angle θ between the bottom surface of the adhesive layer 206 and the horizontal plane, and θ can be in the range of 0° to 75°.

[0035] The opposing sidewalls of the first and second wiring layers 250 are configured with a stepped structure. For example... Figure 2 As shown, the first redistribution layer 250 includes a dielectric layer 251 on the first chip 210 and a dielectric layer 252 on the dielectric layer 251. The size of the dielectric layer 251 can be larger than the size of the dielectric layer 252, such that the sidewall of the dielectric layer 251 adjacent to the second chip 220 is closer to the second chip 220 than the sidewall of the dielectric layer 252, and a portion of the surface of the dielectric layer 251 is exposed by the dielectric layer 262. Thus, a stepped structure can be formed by the sidewall of the dielectric layer 252, the exposed upper surface of the dielectric layer 251, and the sidewall of the dielectric layer 251. The second redistribution layer 260 includes a dielectric layer 261 on the second chip 220, a dielectric layer 262 on the dielectric layer 261, and a dielectric layer 263 on the dielectric layer 262. The size of dielectric layer 261 can be larger than the size of dielectric layer 262, such that the sidewall of dielectric layer 261 adjacent to the first chip 210 is closer to the first chip 210 than the sidewall of dielectric layer 262, and a portion of the upper surface of dielectric layer 261 is exposed by dielectric layer 262. The size of dielectric layer 262 can be larger than the size of dielectric layer 263, such that the sidewall of dielectric layer 262 adjacent to the first chip 210 is closer to the first chip 210 than the sidewall of dielectric layer 263, and a portion of the upper surface of dielectric layer 262 is exposed by dielectric layer 263. Thus, a stepped structure can be formed by the sidewall of dielectric layer 263, the exposed upper surface of dielectric layer 262, the sidewall of dielectric layer 262, the exposed upper surface of dielectric layer 261, and the sidewall of dielectric layer 261. A bridging layer 240 is disposed on the aforementioned stepped structure. Figure 2As shown, one end of the bridging layer 240 and the bridging chip 245 adjacent to the first chip 210 is disposed on the exposed surface of the dielectric layer 251 of the first redistribution layer 250. One end of the bridging layer 240 and the bridging chip 245 adjacent to the second chip 220 is disposed on the exposed surface of the dielectric layer 262 of the second redistribution layer 260.

[0036] In some embodiments, the thickness of substrate 200 can be in the range of 10 μm to 30 μm. In some embodiments, the thickness of first chip 210 is in the range of 20 μm to 100 μm, and the thickness of second chip 220 is in the range of 20 μm to 100 μm. In some embodiments, the thickness of each dielectric layer 251, 252 of first redistribution layer 250 can be in the range of 3 μm to 10 μm. In some embodiments, the thickness of each dielectric layer 261, 262, 263 of second redistribution layer 260 can be in the range of 3 μm to 10 μm. In some embodiments, the linewidth / spacing L / S of the lines in first redistribution layer 250 or second redistribution layer 260 can be in the range of 2 μm / 2 μm to 20 μm / 20 μm. In some embodiments, the linewidth / spacing L / S of bridging line 244 is less than 2 μm / 2 μm. In some embodiments, the diameter of lead 250 is in the range of 10 μm to 50 μm. The above size configuration is only an example; other applicable size configurations can be used in other embodiments.

[0037] A protective layer 275 is formed on the substrate 200 and covers the first chip 210, the second chip 220, the first redistribution layer 250, the second redistribution layer 260, the bridging layer 240, and a plurality of leads 205. The protective layer 275 is also formed below the bridging layer 240 within the gap between the first chip 210 and the second chip 220. The protective layer 275 can fix and protect the leads 205 to ensure good bonding between the bridging layer 240 and the first chip 210 and the second chip 220, and to ensure good bonding between the first chip 210 and the second chip 220 and the substrate 200. It can also fix the first chip 210, the second chip 220, the bridging layer 240, and the bridging chip 245. In some embodiments, the protective layer 275 can be formed of an organic material, such as polyimide (PI), epoxy resin, acrylic, or laminated film (ABF). In some embodiments, the protective layer 275 can be formed of an inorganic material, such as an oxide (e.g., SiO2). x SiN x TaO x Materials include glass, silicon, and ceramics. In some embodiments, the protective layer 275 may also be formed of a non-photosensitive liquid material or a non-photosensitive dry film material.

[0038] exist Figure 2In one embodiment, molding compound 277 is formed on substrate 200 and encapsulates protective layer 275. In other embodiments, only protective layer 275 may be formed without molding compound 277.

[0039] Figure 3a This is a side view schematic diagram of a portion of a semiconductor packaging structure according to an embodiment of the present invention. Figure 3a The diagram shows a substrate 200, a first chip 210 and a first redistribution layer 250 thereon, a second chip 220 and a second redistribution layer 260 thereon, and a bridging layer 240. Figure 3b yes Figure 3a The diagram shows a top view of the semiconductor package structure at section A-A'. (Combined with...) Figure 3a and Figure 3b As shown, the number of chips connected to the substrate 200 can be more than two. Figure 3b The diagram shows a substrate 200 on which a first chip 210, a second chip 220, and a third chip 230 are disposed. The second chip 220 and the third chip 230 may be disposed on the same side of the same sidewall of the first chip 210, and are arranged side-by-side with a gap along the longitudinal direction of that sidewall. A bridging layer 240 is located above the gap between the first chip 210 and the second and third chips 220. A third wiring layer 280 is disposed on the third chip 230. The third wiring layer 280 may have a similar configuration to the second wiring layer 260.

[0040] Since the bridging layer 240 and the bridging chip 245 are disposed on the exposed surfaces of the dielectric layer 251 of the first redistribution layer 250 and the exposed surfaces of the dielectric layer 262 of the second redistribution layer 260, therefore... Figure 3b In the top view shown, dielectric layers 251 and 262 can be seen at the edge of the bridging layer 240.

[0041] Figure 4a and Figure 4b This is a schematic diagram of a semiconductor package structure according to other embodiments of the present invention. Figure 2 The difference is that the number of horizontally arranged chips connected to the substrate 200 can be more than two, and multiple bridging circuit layers are formed accordingly. Figure 4aThe substrate 200 shows three chips: a first chip 210, a second chip 220, and a third chip 230. The second chip 220 and the third chip 230 are located on opposite sides of the first chip 210. A third redistribution layer 280 is formed on the surface of the third chip 230. A third I / O interface 2810 is formed on the upper surface of the third redistribution layer 280. The first I / O interface 2510 of the first redistribution layer 250 is lower than the second I / O interface 2610 of the second redistribution layer 260 and the third I / O interface 2810 of the third redistribution layer 280. Another bridging layer 290 is located above the gap between the first chip 210 and the third chip 230. The bridging layer 290 is inclined. The bridging layer 240 is electrically connected to the first redistribution layer 250, the first chip 210, the second redistribution layer 260, and the second chip 220 via leads 205. The second bridging line 290 is electrically connected to the first rewiring layer 250, the first chip 210, the third rewiring layer 280, and the third chip 230 via lead 205. The second chip 220 and the third chip 230 are also electrically connected to the substrate 200 via lead 205.

[0042] The protective layer 275 covers the first chip 210, the first rewiring layer 250, the bridging line layer 240, and the bridging line layer 290, and the protective layer 275 partially covers the second chip 220, the third chip 230, the second rewiring layer 260, the third rewiring layer 280, and part of the lead 205.

[0043] Figure 4b An embodiment is shown in which four chips are disposed on a substrate 200: a first chip 210, a second chip 220, a third chip 230, and a fourth chip 270. The fourth chip 270 is disposed adjacent to the first chip 210 between the second chip 220 and the third chip 230, and is also adjacent to the first chip 210. A fourth redistribution layer 271 is disposed on the fourth chip 270. Figure 4b In this configuration, an additional bridging layer 290 is disposed above the gap between the third chip 230 and the fourth chip 270. Bridging layer 240 is electrically connected via leads 205 to the first rewiring layer 250 on the first chip 210 and the second rewiring layer 260 on the second chip 220. The additional bridging layer 290 is electrically connected via leads 205 to the fourth rewiring layer 271 on the fourth chip 270 and the third rewiring layer 280 on the third chip 230. The second chips 220 and the third chip 230 on both sides are also connected to the substrate 200 via leads 205, and the fourth chip 270 in the middle is electrically connected to the first chip 210 via leads 205.

[0044] The protective layer 275 covers the first chip 210, the fourth chip 270, the bridging layer 240 and the additional bridging layer 290 in the middle area, and partially covers the second chip 220 and the third chip 230 on both sides.

[0045] Figures 5a to 5b This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention. For example... Figure 5a As shown, the molding compound 277 has patterned metal parts 278 on its surface. The patterned metal parts 278 can be connected to the first rewiring layer 250 and the second rewiring layer 260 through through holes 288. The metal parts 278 can be used for electrical connection to external structures, for example, they can be connected to other package structures to form a PoP (Package on Package).

[0046] like Figure 5b As shown, a heat dissipation layer 279 may be disposed on the surface of the molding compound 277. An adhesive layer 276 is disposed between the molding compound 277 and the heat dissipation layer 279. The heat dissipation layer 279 is attached to the molding compound 277 through the adhesive layer 276. In some embodiments, the adhesive layer 276 may be made of any suitable adhesive material. In some embodiments, the heat dissipation layer 279 may be any suitable structure with heat dissipation properties.

[0047] Figure 6 This is a schematic diagram of a semiconductor package structure according to other embodiments of the present invention. Figure 2 The difference in the embodiments is that an interposer 296 can be used instead of the first chip 210 or the second chip 220. Figure 6 In the illustrated embodiment, an interposer 296 and a second chip 220 are formed on the substrate 200. The interposer 296 includes a silicon dielectric layer 207 and a through-silicon via (TSV) 209 penetrating the silicon dielectric layer 207. A first redistribution layer 250 can be connected to the substrate 200 through the TSV 209.

[0048] Figure 7 This is a schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention. The bridging layer 240 has a tilted angle. One end of the bridging layer 240 and the bridging chip 245 is disposed on the uppermost dielectric layer 263 of the second redistribution layer 260. Conductive lines 266 can be disposed on the surface of the dielectric layer 261 exposed by the dielectric layer 262. The conductive lines 266 can be connected to the pads 202 of the substrate 200 via leads 205.

[0049] Figures 8a to 8j This is a schematic diagram of the various stages of a method for forming a first chip and a second chip in a semiconductor package structure according to an embodiment of the present invention.

[0050] like Figure 8a As shown, a wafer 802 is provided. The surface of wafer 802 has pads 804. As... Figure 8b A dielectric layer 261 can be formed over the wafer 802 and pads 804 using, for example, a lamination process. The dielectric layer 261 can then be patterned. Patterning can be performed using acceptable processes, such as photolithography.

[0051] like Figure 8c As shown, an opening 821 is formed in the patterned dielectric layer 261. A seed layer 831 is formed on the dielectric layer 261 and within the opening 821. In some embodiments, the seed layer 831 can be formed using a deposition process such as physical vapor deposition (PVD). In some embodiments, the material of the seed layer 831 can be, for example, Ti, W, Ni, etc.

[0052] like Figure 8d As shown, a mask layer 841 is formed on the seed layer 831. In some embodiments, the mask layer 841 may be a photomask layer. Figure 8e As shown, a patterned mask layer 841 is formed in which an exposed seed layer 831 is formed and an opening 822 is located above the opening 821. In some embodiments, the mask layer 841 may be a photomask and patterned using a photolithography process. Furthermore, a conductive material 850 is formed on the seed layer 831 in the opening 821 of the first dielectric layer 261 and at the bottom of the opening 822 of the mask layer 841. The conductive material 850 may be formed by processes such as electroplating. In some embodiments, the material of the conductive material 850 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt) and / or a non-metal (e.g., graphene).

[0053] like Figure 8f As shown, the patterned mask layer 841 and the seed layer 831 covered by the patterned mask layer 841 are removed. The remaining seed layer 831 and the conductive material 850 thereon form a conductive line 861, which may include traces located on the dielectric layer 261 as well as interconnect traces and vias of the pads 804.

[0054] Then, it can be repeated like this. Figures 8b to 8f The steps involve forming more dielectric layers and traces and vias within those dielectric layers to form a first redistribution layer 250 or a second redistribution layer 260 on the wafer 802. For example, in... Figure 8g In this process, a plurality of spaced dielectric layers 262, dielectric layers 263 on dielectric layers 262, and conductive lines 861 located therein are formed on dielectric layer 261. The size of each dielectric layer 262 may be larger than the size of the corresponding dielectric layer 263, so as to form a stepped structure on one sidewall of the second redistribution layer 260.

[0055] Subsequently, as Figure 8h As shown, Figure 8g The resulting structure is inverted, and an adhesive layer 204 is applied to the surface of wafer 802 opposite to the second redistribution layer 260. Then... Figure 8h The resulting structure is inverted, such as Figure 8i As shown, the substrate 802 is cut along the position of the dashed line L1. After the cutting process, as... Figure 8j Therefore, wafer 802 is diced into multiple individual second chips 220, and a second super-wiring layer 260 is attached to the second chip 220. The second chip 220 and the second super-wiring layer 260 thereon can be picked up using a connector 892 for subsequent processes. It should be understood that it can also be done through a similar method... Figures 8a to 8j A similar process is used to form the first chip 210 and the first redistribution layer 250 attached to the first chip 210.

[0056] Figures 9a to 9h This is a schematic diagram of the various stages of a method for forming a bridging chip in a semiconductor package structure according to an embodiment of the present invention.

[0057] like Figure 9a As shown, wafer 902 is provided. Bridging lines 244 are present on the surface of wafer 902. As... Figure 9b As shown, a dielectric layer 241 covering the bridging line 244 is formed above the wafer 802.

[0058] like Figure 9c As shown, dielectric layer 241 is patterned, and openings 921 are formed in dielectric layer 241. Openings 921 expose bridging lines 244 on wafer 902. A seed layer 931 is formed on the patterned dielectric layer 241 and within openings 921. In some embodiments, the material of seed layer 931 may be, for example, Ti, W, Ni, etc. In some embodiments, seed layer 931 may be formed using a deposition process such as physical vapor deposition (PVD).

[0059] like Figure 9d As shown, a mask layer 941 is formed on the seed layer 931. (As indicated...) Figure 9e As shown, a patterned mask layer 941 is formed, and an opening 922 is formed within the mask layer 941, exposing a seed layer 931 and located above the opening 921. A conductive material 950 is formed on the seed layer 931 in the openings 921 and 922 and at the bottom of the opening 922 in the mask layer 941. The conductive material 950 can be formed by processes such as electroplating. In some embodiments, the material of the conductive material 950 can be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt) and / or a non-metal (e.g., graphene).

[0060] like Figure 9fAs shown, the patterned mask layer 941 and the seed layer 931 covered by the patterned mask layer 941 are removed. The remaining seed layer 931 and the conductive material 950 thereon form conductive lines 242, such as vias and traces. The dielectric layer 241 and the conductive lines 242 together form a bridging line layer 240.

[0061] Subsequently, as Figure 9g As shown, Figure 9f The resulting structure is inverted and cut along the dotted line L2. For example... Figure 9h As shown, after the dicing process, wafer 902 is diced into multiple individual bridge chips 245. Bridge lines 244 are attached to the surface of the bridge chip 245. Subsequently, the bridge chip 245 and its attached bridge line layer 240 can be picked up using a connector 892 for subsequent processes.

[0062] Figures 10a to 10i This is a schematic diagram of various stages of a method for forming a semiconductor package structure using a pre-formed first chip, a second chip, and a bridging chip according to an embodiment of the present invention.

[0063] like Figure 10a As shown, a substrate 200 is provided, and the upper surface of the substrate 200 has a plurality of pads 202. The pads 202 can be used for subsequent connection with leads.

[0064] Then as Figure 10b As shown, a pre-fabricated first chip 210 and its first redistribution layer 250, and a second chip 220 and its second redistribution layer 260 are respectively placed on a substrate 200 at intervals using a bonding head 892. In some embodiments, the first chip 210 and the second chip 220 are respectively attached to the substrate 200 via a bottom adhesive layer 204. The thickness of the second chip 220 may be greater than the thickness of the first chip 210. The thickness of the second redistribution layer 260 is greater than that of the first redistribution layer 250; therefore, the second I / O interface located on the second redistribution layer 260 is higher than the first I / O interface located on the first redistribution layer 250. A portion of the pads 202 of the substrate 200 are exposed by the first chip 210 and the second chip 220.

[0065] Then as Figure 10c As shown, the adhesive layer 204 is cured using, for example, a reflow operation to strengthen the bonding strength between the first chip 210 and the second chip 220 and the substrate 200. Then as... Figure 10d As shown, the bridging chip 245 and the bridging line layer 240 are disposed between the first chip 210 and the second chip 220 using the connector 892.

[0066] like Figure 10eAs shown, one end of the bridging chip 245 and the bridging layer 240 is disposed on the dielectric layer 251 of the first rewiring layer 250, and the other end is disposed on the dielectric layer 262 of the second rewiring layer 260, such that the bridging layer 240 is obliquely disposed between the first chip 210 and the second chip 220, which have different heights. In some embodiments, the bridging layer 240 is attached to the first rewiring layer 250 and the second rewiring layer 260 via an adhesive layer 206 at the bottom of the bridging chip 245. The adhesive layer 206 is then cured using, for example, a reflow operation.

[0067] like Figure 10f As shown, leads 205 are formed connecting the bridging line layer 240 and the first rewiring layer 250, as well as leads 205 connecting the bridging line layer 240 and the second rewiring layer 260. Leads 205 are also formed connecting the first rewiring layer 250 and the substrate 200, and leads 205 connecting the second rewiring layer 260 and the substrate 200.

[0068] like Figure 10g As shown, a protective layer 275 is formed on the substrate 200, covering the first chip 210, the second chip 220, the bridging circuit layer 240, and the leads 205. The protective layer 275 is also formed below the bridging circuit layer 240, within the spacing between the first chip 210 and the second chip 220. A molding compound 277 is formed to encapsulate the first chip 210, the second chip 220, and the protective layer 275. In some embodiments, the molding compound 277 may be formed using a molding process or a dispensing process.

[0069] Then as Figure 10h As shown, Figure 10g The structure shown is inverted, and solder balls 208 are formed on the substrate 200. After forming the solder balls 208, Figure 10h The structure shown is inverted, as... Figure 10i As shown, a cutting process is performed along the dashed line L3 to form the final package structure.

[0070] In the method for forming the package structure described above, firstly, a first chip 210 and a second chip 220 are placed at intervals on a substrate 200. A first redistribution layer 250 is pre-formed on the first chip 210, and a second redistribution layer 260 is pre-formed on the second chip 220. A stepped structure is formed at the outermost wall of the second redistribution layer 260 adjacent to the first chip 210. Then, a bridging layer 240 is disposed between the first chip 210 and the second chip 220, wherein one end of the bridging layer 240 is disposed on the stepped structure of the second redistribution layer 260 to give the bridging layer 240 an inclined angle. Then, the bridging layer 240 is connected to the first I / O interface of the first redistribution layer 250 and the second I / O interface of the second redistribution layer 260 using leads 205. Finally, a protective layer 275 and a molding compound 277 covering the first chip 210, the second chip 220, the bridging layer 240, and the leads 205 are formed on the substrate 200. The final package structure is formed after the solder ball placement and cutting process is completed.

[0071] By setting up a bridging layer, the connection path of the leads can be shortened, avoiding the problem of excessive wire bonding height caused by the large pitch between the first and second chips, and further avoiding the increase in semiconductor package thickness due to excessive wire bonding height. By using leads to bond the bridging layer to the first chip, the second chip, and the substrate, instead of existing through-holes for electrical connection, the complex processes of using through-holes (such as drilling, seed layer fabrication, photomask covering, exposure, development, electroplating, and etching) can be avoided, thus reducing manufacturing costs.

[0072] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; A first chip and a second chip are disposed laterally spaced on the substrate, and the upper surface of the first chip is not flush with the upper surface of the second chip. A bridging chip is disposed on the first chip and the second chip, spanning the gap between the first chip and the second chip; A bridging circuit layer is disposed on the upper surface of the bridging chip facing away from the substrate; A first and a second wiring layer are respectively disposed on the upper surfaces of the first and second chips, which are not flush with each other. The opposing sidewalls of the first and second wiring layers have a stepped structure, and the bridging chip is disposed on the bottom surface of the stepped structure of the opposing sidewalls. The upper surface of the first redistribution layer above the first chip forms a first I / O interface electrically connected to the first chip, and the upper surface of the second redistribution layer above the second chip forms a second I / O interface electrically connected to the second chip. The first I / O interface and the second I / O interface are not coplanar. Both the bridging layer and the bridging chip have a tilt angle. The first I / O interface of the first redistribution layer and the second I / O interface of the second redistribution layer are electrically connected to the bridging layer on the upper surface of the bridging chip through leads.

2. The semiconductor packaging structure according to claim 1, characterized in that, The lower surfaces of the first chip and the second chip are respectively attached to the substrate via adhesive layers.

3. The semiconductor packaging structure according to claim 1, characterized in that, The second I / O interface is higher than the first I / O interface.

4. The semiconductor packaging structure according to claim 1, characterized in that, Both the first chip and the second chip are electrically connected to the substrate via leads.

5. The semiconductor packaging structure according to claim 1, characterized in that, The lower surface of the bridging chip is attached to the first and second rewiring layers via an adhesive layer.

6. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: The third chip, the second chip and the third chip are located on opposite sides of the first chip; An additional bridging layer is located between the first chip and the third chip, and both the first chip and the third chip are electrically connected to the additional bridging layer via leads.

7. The semiconductor packaging structure according to claim 6, characterized in that, The I / O interfaces corresponding to the second chip and the third chip are higher than the I / O interface corresponding to the first chip.

8. The semiconductor packaging structure according to claim 1, characterized in that, Below the bridging circuit layer, there are leads that electrically connect one of the first chip and the second chip to the substrate.

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