Semiconductor package structure

Abstract

The present application relates to a kind of semiconductor package structure.The semiconductor package structure includes: substrate;First chip and second chip, on substrate and with substrate electric connection;Bridge circuit layer, in substrate, first chip and second chip are communicated by bridge circuit layer, bridge circuit layer is electrically connected with substrate by lead wire.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] like Figure 1 As shown, in the FOCOS (Fan Out Chip on Substrate) concept applied to the FOSUB (Fan-Out Substrate) structure, the redistribution layer (RDL) 20 is attached to the substrate 10 via the adhesive layer 30. The RDL layer 20 is electrically connected to the substrate 10 via through-holes 25. The RDL layer 20 includes a region 44 with low line density and a region 42 with high line density. Above region 44 is a location 50 for bonding chips, and bridging lines can be provided in region 42. However, the following problems exist in this structure:

[0003] Because the RDL layer needs to contain both high-density and low-density circuits, the number of RDL layers is required to be high, which will lead to a lower yield.

[0004] In the FOSUB process, the formation of through-vias must take into account the location of the traces to avoid them, which greatly limits the demand for high IO (input / output) counts.

[0005] Although in one existing technology, the bridging circuit is first placed inside the substrate, and then the RDL layer is fabricated on the substrate, this method also needs to meet the RDL layer number requirement, resulting in low yield and high cost. Summary of the Invention

[0006] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure and a method for forming the same.

[0007] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: a substrate; a first chip and a second chip located on the substrate and electrically connected to the substrate; and a bridging circuit layer located within the substrate, wherein the first chip and the second chip communicate through the bridging circuit layer, and the bridging circuit layer is electrically connected to the substrate through leads.

[0008] In some embodiments, the semiconductor package structure further includes: a first circuit layer, including a first dielectric layer on a substrate and a via in the first dielectric layer, the via extending from the upper surface of the first dielectric layer to the substrate, and the first circuit layer being electrically connected to the substrate through the via.

[0009] In some embodiments, the first dielectric layer is a single-layer structure.

[0010] In some embodiments, the first dielectric layer further extends into the gap between the bridging layer and the substrate.

[0011] In some embodiments, the bridging line layer is exposed by the first line layer, and an adhesive layer is disposed on the first line layer and the bridging line layer, wherein the adhesive layer covers the leads.

[0012] In some embodiments, the semiconductor package structure further includes a second circuit layer located above the first circuit layer.

[0013] In some embodiments, the second circuit layer includes a second dielectric layer, wherein the second dielectric layer is a single-layer structure.

[0014] In some embodiments, the semiconductor package structure further includes: an adhesive layer located between the first circuit layer and the second circuit layer; and a through-hole connected to the first chip and the second chip, the through-hole passing through the second circuit layer and the adhesive layer to be electrically connected to the substrate.

[0015] In some embodiments, leads are provided on the surface of the first dielectric layer to interconnect the lines of the first circuit layer.

[0016] In some embodiments, the semiconductor package structure further includes: an additional bridging layer located within the substrate, the additional bridging layer being spaced apart from the bridging layer by the substrate, and the additional bridging layer being electrically connected to the substrate by additional leads.

[0017] According to another aspect of the present invention, a method for forming a semiconductor package structure is provided, comprising: providing a substrate having a cavity; placing a bridging circuit layer in the cavity; electrically connecting the bridging circuit layer to the substrate using leads; and disposing a first chip and a second chip electrically connected to the substrate on the substrate.

[0018] In some embodiments, before electrically connecting the bridging line layer to the substrate using leads, the method further includes: forming a first dielectric layer over the substrate and the bridging line layer; and forming a via through the first dielectric layer and electrically connected to the substrate.

[0019] In some embodiments, a first dielectric layer is formed as a single-layer structure.

[0020] In some embodiments, there is a gap between the sidewall of the bridging layer and the sidewall of the cavity, and the first dielectric layer is also filled within the gap.

[0021] In some embodiments, after forming the first dielectric layer over the substrate and the bridging layer, the method further includes: removing the first dielectric layer covering the bridging layer to expose the surface of the bridging layer.

[0022] In some embodiments, after electrically connecting the bridging line layer to the substrate using leads, the method further includes forming an adhesive layer on the first dielectric layer and the bridging line layer, wherein the adhesive layer covers the leads.

[0023] In some embodiments, after forming the adhesive layer, the method further includes: forming a second circuit layer above the adhesive layer; and forming a through-hole that passes through the second circuit layer and the adhesive layer and is electrically connected to the substrate.

[0024] In some embodiments, setting the first chip and the second chip includes: setting the first chip and the second chip connected to the through-hole on the second circuit layer.

[0025] In some embodiments, the dielectric layer in the second circuit layer is a single-layer structure.

[0026] In some embodiments, setting the second circuit layer includes: forming the second circuit layer on a carrier; placing the second circuit layer over the adhesive layer via the carrier; and removing the carrier. Attached Figure Description

[0027] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0028] Figure 1 This is a schematic diagram of an existing semiconductor packaging structure.

[0029] Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0030] Figure 3 yes Figure 2 A partially enlarged schematic diagram of the bridging circuit layer and bridging chip section.

[0031] Figure 4 yes Figure 2 A partially enlarged schematic diagram of the lead wire portion.

[0032] Figure 5 yes Figure 2 A top view of section AA in the diagram.

[0033] Figure 6 and Figure 7 This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention.

[0034] Figures 8a to 8m This is a schematic diagram of the various stages of a method for forming a bridging layer in a semiconductor package structure according to an embodiment of the present invention.

[0035] Figures 9a to 9e This is a schematic diagram of the various stages of a method for forming a first circuit layer in a semiconductor package structure according to an embodiment of the present invention.

[0036] Figures 10a to 10m This is a schematic diagram of the various stages of a method for forming a semiconductor package structure according to an embodiment of the present invention. Specific Implementation

[0037] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] Embodiments of the present invention provide a semiconductor packaging structure. In some embodiments, the semiconductor packaging structure provided by the present invention may be FOSUB. Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Figure 2 As shown, the semiconductor package structure includes a substrate 218, a first chip 252, and a second chip 254 located on and electrically connected to the substrate 218. In some embodiments, the substrate 218 may have a filler 219. The filler 219 may be, for example, glass fiber. The filler 219 can provide overall substrate strength to overcome stress. In other embodiments, the substrate 218 may not have a filler. In some embodiments, the thickness of the substrate 218 may be in the range of 50 μm to 200 μm.

[0039] A bridging circuit layer 240 is embedded in the substrate 218. A first chip 252 and a second chip 254 can be disposed on opposite sides of the bridging circuit layer 240. The first chip 252 and the second chip 254 communicate with each other through the bridging circuit layer 240. The bridging circuit layer 240 and the substrate 218 are electrically connected to each other via multiple leads 205. The bridging circuit layer 240 also includes a bridging line 244. The bridging line 244 can be located on the upper surface of the bridging circuit layer 240.

[0040] Continue to refer to Figure 2As shown, a bridging chip 215 is disposed below the bridging circuit layer 240. In some embodiments, the bridging chip 215 is attached to the substrate 218 by an adhesive layer 208. The upper surface of the bridging circuit layer 240 may be lower than the upper surface of the substrate 218, thereby protecting the bridging circuit layer 240 and the bridging chip 215 under stress loading.

[0041] A first circuit layer 230 is disposed on the substrate 218. The first circuit layer 230 includes a first dielectric layer 232 located on the substrate 218 and circuits located in the first dielectric layer 232, such as vias and pads. A bridging circuit layer 240 and a bridging chip 215 may be disposed in a cavity 217 of the substrate 218. Figure 2 The reference numeral 217 points to the sidewall of the cavity. The sidewall of cavity 217 may be spaced from the sidewalls of bridging layer 240 and bridging chip 215. The first dielectric layer 232 extends into the space between bridging layer 240 and bridging chip 215 and substrate 218.

[0042] The first dielectric layer 232 is a single-layer structure, formed from a single layer of the same material. In some embodiments, the material of the first dielectric layer 232 may include, for example, PI, epoxy, and ABF. In some embodiments, the thickness of the first dielectric layer 232 of the first circuit layer 230 is in the range of 1 μm to 10 μm. The size of the bridging chip 215 can be in the range of 100 μm to 1000 μm. The size of the cavity 217 can be in the range of 100 μm to 1000 μm. The spacing between the sidewalls of the cavity 217 and the sidewalls of the bridging chip 215 can be in the range of 10 μm to 100 μm. The ratio between the size of the bridging chip 215 and the size W1 of the cavity 217 can be in the range of 0.5 to 0.8. By forming a first dielectric layer 232 within the cavity 217 of the substrate 218, which fills the space between the bridging circuit layer 240 and the bridging chip 215 and the sidewall of the cavity 217, the first dielectric layer 232 can be regarded as a buffer structure to avoid large coefficient of thermal expansion (CTE) mismatch and can provide stress relief when thermal stress is applied along the surface of the substrate 218.

[0043] The bridging layer 240 is exposed by a first dielectric layer 232 of the first wiring layer 230. The first dielectric layer 232 may cover the edge of the bridging layer 240. In some embodiments, the dimension DCR of the first dielectric layer 232 covering the bridging layer 240 may be in the range of 5 μm to 50 μm. An adhesive layer 235 is provided on the first wiring layer 230 and the bridging layer 240, wherein the adhesive layer 235 covers a plurality of leads 205 connected to the first wiring layer 230 and the bridging layer 240. In some embodiments, the diameter of the leads 205 may be in the range of 10 μm to 100 μm. The thickness of the adhesive layer 235 may be in the range of 20 μm to 60 μm.

[0044] The second circuit layer 220 is located above the adhesive layer 235. The second circuit layer 220 includes a second dielectric layer 911 and circuits therein. The second dielectric layer 911 is also a single-layer structure. In some embodiments, the thickness of the second dielectric layer 911 is in the range of 1 μm to 10 μm. A through-hole 222 connects the first chip 252 and the second chip 254, and the through-hole 222 passes through the second circuit layer 220 and the adhesive layer 235 to reach the first circuit layer 230, so as to electrically connect to the substrate 218 and the bridging circuit layer 240.

[0045] The line density in bridging layer 240 is greater than the line density in the first line layer 230 and the second line layer 220. The linewidth / spacing L / S of bridging line 244 in bridging layer 240 is < 2 μm / 2 μm. The linewidth / spacing L / S of other lines in bridging layer 240 is < 5 μm / 5 μm. The linewidth / spacing L / S of lines in the first line layer 230 and the second line layer 220 is < 10 μm / 10 μm and > 5 μm / 5 μm.

[0046] In the above-described FOSUB structure of the present invention, the bridging line layer 240 is embedded in the substrate 218, and the bridging line layer 240 is directly electrically connected to the substrate 218 through the lead 205. Therefore, the uppermost second line layer 220 does not need to have a line design, and only a dielectric layer is needed to directly connect the upper and lower layers. In this way, the existing RDL layer process of forming a multi-layer structure on the substrate 218 is replaced, avoiding the limitation on the number of line layers, effectively reducing the number of layers, improving yield and reducing cost.

[0047] Figure 3 It shows Figure 2 A partially enlarged schematic diagram of the bridging circuit layer and bridging chip section. (See attached image.) Figure 3As shown, the bridging layer 240 may include multiple stacked dielectric layers 811, 812, and 813 and an RDL located within the multiple dielectric layers 811, 812, and 813. The bridging layer 240 may also be referred to as a bridging RDL layer. In some embodiments, the thickness of each dielectric layer 811, 812, and 813 may be in the range of 1 μm to 10 μm. A bridging line 244 that can be coupled to a lead is also provided on the upper surface of the bridging layer 240.

[0048] Figure 4 It shows Figure 2 A partially enlarged schematic diagram of the lead wire portion. Figure 5 It shows Figure 2 A top view of section AA in the diagram. Figure 4 As shown, via 239 extends from the upper surface of the first dielectric layer 232 to the surface of the substrate 218, and the first circuit layer 230 is electrically connected to the substrate 218 through via 239. A plurality of pads 238 are provided on the surface of the first dielectric layer 232. The via 239 can connect to the pads 238. Figure 4 and Figure 5 As shown, one end of lead 2051 is connected to bridging line 244 in bridging layer 240, and the other end of lead 2051 is connected to pad 238 on the surface of first circuit layer 230. Pad 238 is also connected to via 222, which is connected to first chip 252 or second chip 254, thereby interconnecting the first chip 252 and the second chip 254 through bridging line 244. One end of lead 2052 is connected to other lines 247 in bridging layer 240 besides bridging line 244, and the other end of lead 2052 is connected to pad 238 on the surface of first circuit layer 230. Pad 238 is also connected to via 239 passing through first dielectric layer 232, which is connected to the underlying substrate 218, thereby electrically connecting the lines 247 in bridging layer 240 to substrate 218.

[0049] Figure 6 This is a schematic diagram of a semiconductor packaging structure according to other embodiments of the present invention. For example... Figure 6 As shown, additional leads 205' may be provided on the surface of the first dielectric layer 232 to interconnect the lines in the first circuit layer 230. Figure 6 Other aspects of the illustrated embodiments may be related to Figure 2 The embodiments shown are the same.

[0050] Figure 7 This is a schematic diagram of a semiconductor package structure according to other embodiments of the present invention. Figure 7In the illustrated embodiment, an additional bridging layer 240' is also provided within the substrate 218. The additional bridging layer 240' is spaced apart from the bridging layer 240 by the substrate 218. The additional bridging layer 240' is also electrically connected to the substrate 218 via a lead 205'. Figure 7 Other aspects of the illustrated embodiments may be related to Figure 2 The embodiments shown are the same.

[0051] Figures 8a to 8m This is a schematic diagram of the various stages of a method for forming a bridging layer in a semiconductor package structure according to an embodiment of the present invention.

[0052] like Figure 8a As shown, a carrier board 802 is provided. The carrier board 802 can be a bridge chip with pads 806. For example... Figure 8b As shown, a dielectric layer 811 is formed above the pads 806 of the carrier board 802. The dielectric layer 811 is then patterned. Patterning can be performed using acceptable processes, such as exposing the dielectric layer 811 to light. After exposure, the dielectric layer 811 is developed, and openings 821 are formed in the dielectric layer 811, as shown. Figure 8c As shown.

[0053] like Figure 8c As shown, a seed layer 831 is formed on the patterned dielectric layer 811 and within the opening 821. In some embodiments, the seed layer 831 may be formed using a deposition process such as physical vapor deposition (PVD).

[0054] like Figure 8d As shown, a mask layer 841 is formed on the seed layer 831. In some embodiments, the mask layer 841 may be a photomask layer. Figure 8e As shown, a patterned mask layer 841 is formed to create openings 822 in the mask layer 841 that expose the seed layer 831. Some openings 822 may be located above the openings 821. In some embodiments, the mask layer 841 may be a photomask and patterned using a photolithography process. Furthermore, a conductive material 850 is formed on the seed layer 831 in the openings 821 of the dielectric layer 811 and at the bottom of the openings 822 of the mask layer 841. The conductive material 850 may be formed by processes such as electroplating.

[0055] like Figure 8f As shown, the patterned mask layer 841 and the seed layer 831 covered by the patterned mask layer 841 are removed. The remaining seed layer 831 and the conductive material 850 thereon form the circuit 242.

[0056] Then, it can be repeated like this. Figures 8b to 8f The steps are to form more layers of dielectric layers and the circuitry located within those dielectric layers. For example... Figure 8gAs shown, a dielectric layer 812, a trace 241 located on the dielectric layer 812, and a line 242 located within the dielectric layer 812 are formed on the dielectric layer 811.

[0057] like Figure 8h A dielectric layer 813 is formed on the dielectric layer 812, and the dielectric layer 813 is patterned to form an opening 823 located in the dielectric layer 813. A seed layer 832 is deposited on the dielectric layer 813 and within the opening 823. Then, as... Figure 8i As shown, a mask layer 842 is formed on the seed layer 832.

[0058] like Figure 8j As shown, a patterned mask layer 842 is formed to create openings 824 in the mask layer 842 that expose the seed layer 832. Some openings 824 in the mask layer 842 may be formed above openings 823 in the dielectric layer 813. A conductive material 850 is formed on the seed layer 832 in the openings 823 of the dielectric layer 813 and at the bottom of the openings 824 in the mask layer 842. In some embodiments, the conductive material 850 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt, solder) and / or a non-metal (e.g., graphene). In some embodiments, the seed layers 831, 832 may be made of, for example, Ti, W, Ni, etc.

[0059] like Figure 8k The mask layer 842 and the seed layer 832 covered by the mask layer 842 are removed. The remaining seed layer 832 and the conductive material 850 thereon form a higher layer of circuitry 242. At this time, the seed layer 832 and the conductive material 850 thereon, which are retained on the dielectric layer 813, also form a bridging circuit 244. Thus, a bridging circuit layer 240 with fine lines is formed on the carrier board 802.

[0060] Subsequently, as Figure 8l As shown, Figure 8k The resulting structure is inverted, and an adhesive layer 208 is applied to the surface of the carrier plate 802. Then... Figure 8l The resulting structure is inverted and then cut. For example... Figure 8m As shown, after the dicing process, the carrier board 802 is diced into multiple individual bridge chips 215, and a bridging layer 240 is formed above each individual bridge chip 215. Subsequently, the bridge chip 215 and the bridging layer 240 thereon can be picked up using the connector 892 for subsequent processes.

[0061] Figures 9a to 9e This is a schematic diagram of the various stages of a method for forming a first circuit layer in a semiconductor package structure according to an embodiment of the present invention.

[0062] like Figure 9aAs shown, a dielectric layer 911 for the second circuit layer is formed on the carrier 902, for example, by a lamination process. The dielectric layer 911 is then patterned.

[0063] like Figure 9b The patterned dielectric layer 911 has an opening 921 that exposes the carrier 902. A seed layer 931 is formed over the dielectric layer 911 and in the opening 921. In some embodiments, the seed layer 931 can be formed using, for example, physical vapor deposition (PVD).

[0064] like Figure 9c A mask layer 941 is formed on the seed layer 931. The mask layer 941 is then patterned to form openings 922 within the mask layer 941 that expose the seed layer 931, such as... Figure 9d As shown. The opening 922 of the mask layer 941 may be located above the opening 921 of the dielectric layer 911. A conductive material 950 is formed on the seed layer 931 within the opening 921 of the dielectric layer 911 and at the bottom of the opening 922 of the mask layer 941.

[0065] like Figure 9e As shown, the mask layer 941 and the seed layer 931 below the mask layer 941 are removed. The remaining seed layer 931 and the conductive material 950 thereon form a circuit 221. Thus, a second circuit layer 220 is formed on the carrier 902, the second circuit layer 220 including a dielectric layer 911 and the circuit 221 therein.

[0066] Figures 10a to 10m This is a schematic diagram of various stages of a method for forming a semiconductor package structure using a pre-formed bridging layer, a first line layer, and a second line layer according to an embodiment of the present invention.

[0067] like Figure 10a As shown, a substrate 218 is provided, wherein the substrate 218 has a recessed cavity 217. Then as... Figure 10b As shown, using the connector 892 to, for example Figure 8m A bridging layer 240, formed above the bridging chip 215, is placed within a cavity 217 of the substrate 218. The bridging chip 215 and the bridging layer 240 can be attached to the cavity 217 via an adhesive layer 208 below the bridging chip 215. The size of the bridging layer 240 is smaller than the size of the cavity 217, so after the bridging layer 240 is placed within the cavity 217, there will be a gap between the bridging layer 240 and the sidewalls of the cavity 217.

[0068] like Figure 10cAs shown, a first dielectric layer 232 is formed. The first dielectric layer 232 covers the upper surface of the substrate 218 outside the cavity 217, and the first dielectric layer 232 also extends into the cavity 217 to fill the gap between the bridging chip 215 and the bridging line layer 240 and the sidewall of the cavity 217.

[0069] like Figure 10d As shown, the first dielectric layer 232 is patterned, and an opening 1021 is formed in the first dielectric layer 232. The opening 1021 can expose the pads on the surface of the substrate 218. A seed layer 1031 is covered on the first dielectric layer 232 and inside the opening 1021. The seed layer 1031 can cover the bridging circuit layer 240.

[0070] like Figure 10e As shown, a mask layer 1041 is formed on the seed layer 1031. The mask layer 1041 is patterned, and openings 1022 are formed in the mask layer 1041, as shown. Figure 10f As shown. The opening 1022 of the mask layer 1041 can be located above the opening 1021 of the dielectric layer 232. A conductive material 1050 is formed on the seed layer 1031 in the opening 1021 of the first dielectric layer 232 and at the bottom of the opening 1022 of the mask layer 1041.

[0071] like Figure 10g As shown, the mask layer 1041 and the seed layer 1031 below the mask layer 1041 are removed to form pads 238 on the first dielectric layer 232 and vias 239 connected to the pads 238. The bridging circuit layer 240 is also exposed at this time. Thus, the first circuit layer 230 is formed on the substrate 218 outside the cavity 217.

[0072] like Figure 10h As shown, a lead 205 is formed to connect the bridging line layer 240 and the first line layer 230. (As shown...) Figure 10i As shown, an adhesive layer 235 is applied to the first circuit layer 230 and the bridging circuit layer 240. The second circuit layer 220 is then attached to the first circuit layer 230 and the bridging circuit layer 240 via the adhesive layer 235. The carrier 902 is then removed.

[0073] like Figure 10j As shown, an opening 1052 is formed from the upper surface of the second circuit layer 220, which can be formed, for example, by a laser drilling process. The opening 1052 extends to the surface of the first circuit layer 230. Then, a seed layer 1032 is deposited on the second circuit layer 220, within the opening 1052.

[0074] like Figure 10kAs shown, a mask layer 1042 is formed on the seed layer 1032. The mask layer 1042 fills each opening 1052. The mask layer 1042 is then patterned, and openings 1023 are formed in the mask layer 1042, as shown. Figure 10l As shown. Patterning of the mask layer 1042 removes the mask layer 1042 from the opening 1052, thereby forming an opening 1023 in the mask layer 1042 that exposes the opening 1052. Then, a conductive material 1050 is formed on the seed layer 1032 in the opening 1052 and at the bottom of the opening 1023. In some embodiments, the conductive material 1050 may be a metal (e.g., Cu, Ag, Au, Al, Ni, Ti, Pd, Pt, solder) and / or a non-metal (e.g., graphene). In some embodiments, the seed layers 1031, 1032 may be made of, for example, Ti, W, Ni, etc.

[0075] Then as Figure 10m As shown, the mask layer 1042 and the seed layer 1032 below the mask layer 1042 are removed. The seed layer 1032 and conductive material 1050 within the opening 1052 form a through-hole 222, and the seed layer 1032 and conductive material 1050 above the opening 1052 form a pad 229 connected to the through-hole 222. Subsequently, a first chip and a second chip can be placed on the second circuit layer 220 to form, for example,... Figure 2 The semiconductor packaging structure shown.

[0076] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; The first chip and the second chip are located on the substrate and electrically connected to the substrate; A bridging layer, located within the substrate, is used by the first chip and the second chip to communicate. The first circuit layer includes a first dielectric layer located on the substrate and a via located in the first dielectric layer, the via extending from the upper surface of the first dielectric layer to the substrate, the first circuit layer being electrically connected to the substrate through the via, wherein the bridging circuit layer is exposed from the first circuit layer; A second circuit layer is located above the first circuit layer. An adhesive layer is provided between the first circuit layer and the second circuit layer. The second circuit layer extends across the bridging circuit layer and is perpendicularly spaced from the bridging circuit layer through the adhesive layer. The bridging circuit layer is disposed in a cavity of the substrate, and the upper surface of the bridging circuit layer is lower than the upper surface of the substrate. The circuit density in the bridging circuit layer is greater than the circuit density in the first circuit layer and the second circuit layer. Through-holes, laterally spaced from the bridging circuit layer, connect the first chip and the second chip, pass through the second circuit layer and the adhesive layer, and reach the first circuit layer to electrically connect to the substrate. No through-holes are provided in the adhesive layer and the second circuit layer above the bridging circuit layer. The lead wire has one end directly connected to the first circuit layer and the other end directly connected to the bridging circuit layer. The bridging circuit layer is electrically connected to the substrate through the lead wire.

2. The semiconductor packaging structure according to claim 1, characterized in that, The first dielectric layer is a single-layer structure.

3. The semiconductor packaging structure according to claim 1, characterized in that, The first dielectric layer also extends into the gap between the bridging layer and the substrate.

4. The semiconductor packaging structure according to claim 1, characterized in that, The bridging circuit layer is exposed by the first circuit layer, and an adhesive layer is provided on the first circuit layer and the bridging circuit layer, wherein the adhesive layer covers the lead wire.

5. The semiconductor packaging structure according to claim 1, characterized in that, The second circuit layer includes a second dielectric layer, wherein the second dielectric layer is a single-layer structure.

6. The semiconductor packaging structure according to claim 1, characterized in that, Leads are provided on the surface of the first dielectric layer to interconnect the lines of the first circuit layer.

7. The semiconductor packaging structure according to claim 1, characterized in that, It also includes an additional bridging circuit layer located within the substrate, the additional bridging circuit layer being spaced apart from the original bridging circuit layer by the substrate, and the additional bridging circuit layer being electrically connected to the substrate by additional leads.

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