Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor package device and a manufacturing method thereof. The semiconductor package device comprises a molding material, a bridge chip covered in the molding material, the bridge chip being provided with a conductive pad and a first conductive hole, the conductive pad being located on a first surface of the bridge chip, the first conductive hole being located in the bridge chip and electrically connected with the conductive pad, and a buffer layer provided on the first surface of the bridge chip, the buffer layer being provided with a second conductive hole, a first end of the second conductive hole being electrically connected with the conductive pad, and a second end of the second conductive hole being exposed outside the buffer layer. The semiconductor package device can avoid the problem of excessive wear or difficult exposure of through silicon vias due to warping of the semiconductor package device in the grinding process, and is conducive to ensuring the electrical connection performance of the semiconductor package device with the outside.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] FOCoS (Fan Out Chip on Substrate) packaging technology achieves this by using a fan-out composite chip on a typical ball grid array substrate. It offers a lower-cost solution and, in practice, provides better electrical and thermal performance than silicon interposer structures.

[0003] Figure 1A This is a schematic diagram of a FOCoS semiconductor packaging device. Figure 1A As shown, a bridging chip 11 and an electronic component 12 are encapsulated within the molding material 13. The bridging chip 11 is electrically connected to the electronic component 12. A through-silicon via (TSV) 14 is provided within the bridging chip 11. The TSV 14 is used for external connections. Typically, it starts from one side of the bottom of the bridging chip 11 (corresponding to...). Figure 1A The upper side of the bridge chip 11 is ground to expose the end of the through silicon via 14, thereby forming an electrical connection.

[0004] However, due to factors such as the thermal processing, FOCoS semiconductor packaging devices are prone to warping. For example... Figure 1B As shown above, the packaging device 15 has an upward convex warp, and when the polishing device 16 polishes from top to bottom, it can easily cause excessive wear on the through-silicon vias. Figure 1B As shown below, the packaging device 15 has a concave warp, making it difficult for the through-silicon vias (TSVs) to be exposed when the polishing device 16 polishes from top to bottom. Both excessive wear and difficulty in exposing the TSVs can affect their electrical connectivity.

[0005] Therefore, it is necessary to propose a new technical solution to solve at least one of the above-mentioned technical problems. Summary of the Invention

[0006] This disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0007] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0008] Molding materials;

[0009] A bridging chip is encapsulated within the molding material. The bridging chip is provided with a conductive pad and a first conductive hole. The conductive pad is located on the first surface of the bridging chip, and the first conductive hole is located inside the bridging chip and is electrically connected to the conductive pad.

[0010] A buffer layer is disposed on the first surface of the bridging chip. A second conductive hole is disposed on the buffer layer. The first end of the second conductive hole is electrically connected to the conductive pad, and the second end of the second conductive hole is exposed outside the buffer layer.

[0011] In some alternative embodiments, the second end of the conductive hole is electrically connected to the first electronic component via solder.

[0012] In some alternative embodiments, the diameter of the second conductive hole gradually increases from the first end to the second end.

[0013] In some alternative embodiments, the diameter of the second conductive hole remains uniform from the first end to the second end.

[0014] In some alternative implementations, the stiffness of the buffer layer is less than the stiffness of the second conductive via or the bridging chip.

[0015] In some alternative embodiments, the buffer layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed on a first surface of the bridging chip, the second dielectric layer being disposed on the surface of the first dielectric layer, and the second conductive via penetrating the first dielectric layer and the second dielectric layer.

[0016] In some alternative embodiments, the buffer layer further includes a third dielectric layer disposed on the surface of the second dielectric layer and covering the second conductive hole, wherein the third dielectric layer has an opening through which the second conductive hole is exposed.

[0017] In some alternative embodiments, the length of the second conductive hole is greater than the thickness of the conductive pad.

[0018] In some alternative embodiments, the minimum diameter of the second conductive hole is greater than the diameter of the first conductive hole.

[0019] In some alternative implementations, the semiconductor packaging device further includes at least two second electronic components electrically connected via the bridging chip.

[0020] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0021] A bridging chip is connected to a buffer layer, wherein the bridging chip is provided with a conductive pad and a first conductive hole, the conductive pad is located on a first surface of the bridging chip, and the first conductive hole is located inside the bridging chip and is electrically connected to the conductive pad;

[0022] A molding material covering the bridging chip is formed by molding.

[0023] A second conductive hole is formed on the buffer layer by drilling and electroplating to obtain a semiconductor package device, wherein a first end of the conductive hole is electrically connected to the conductive pad, and a second end of the second conductive hole is exposed outside the buffer layer.

[0024] In the semiconductor packaging device and manufacturing method disclosed herein, the external connection of the semiconductor packaging device is achieved through a second conductive hole on the buffer layer. Since the second conductive hole can be formed by drilling, no grinding process is required. This avoids the problem of excessive wear or difficulty in exposing the through-silicon vias caused by warping of the semiconductor packaging device during the grinding process, which is beneficial to ensuring the electrical connection performance between the semiconductor packaging device and the outside. Attached Figure Description

[0025] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1A and Figure 1B This is a schematic diagram of a semiconductor packaging device in the prior art;

[0027] Figures 2-5 These are first to fourth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention;

[0028] Figures 6-13 This is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0029] Symbol explanation:

[0030] 11. Bridging chip; 12. Electronic component; 13. Molding material; 14. Through-silicon via (TSV); 15. Packaging device; 16. Polishing device; 100. First electronic component; 200. Bridging chip; 210. First conductive via; 220. Conductive pad; 230. First conductive post; 300. Buffer layer; 310. First dielectric layer; 320. Second dielectric layer; 330. Third dielectric layer; 340. Second conductive via; 400. Solder; 500. Second electronic component; 600. Molding material; 610. Second conductive post; 700. Circuit layer; 910. Carrier; 920. Metal layer; 930. Opening. Detailed Implementation

[0031] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0032] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0033] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0034] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0035] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0036] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] This disclosure provides a semiconductor packaging apparatus. Figures 2-5 These are first to fourth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention.

[0038] Figure 2 A longitudinal cross-section of the semiconductor packaging device is shown. (See figure) Figure 2As shown, the semiconductor packaging device includes a molding compound 600, a bridging chip 200, and a buffer layer 300. The bridging chip 200 is encapsulated within the molding compound 600. A conductive pad 220 and a first conductive via 210 are disposed on the bridging chip 200. The conductive pad 220 is located on the first surface of the bridging chip 200 (i.e.,...). Figure 2 The lower surface of the bridging chip 200). The first conductive hole 210 is located inside the bridging chip 200 and is electrically connected to the conductive pad 220. The buffer layer 300 is disposed on the first surface of the bridging chip 200, and a second conductive hole 340 is disposed on the buffer layer 300. The first end of the second conductive hole 340 (i.e., the lower surface of the bridging chip 200). Figure 2 The upper end of the second conductive hole 340 is electrically connected to the conductive pad 220, and the second end of the second conductive hole 340 (i.e., the upper end of the second conductive hole 340) is electrically connected to the conductive pad 220. Figure 2 The lower end of the middle section is exposed outside the buffer layer 300.

[0039] like Figure 2 As shown, the semiconductor packaging device also includes a first electronic component 100. The first electronic component 100 is located below the molding material 600. The second end of the second conductive hole 340 is electrically connected to the first electronic component 100 via solder 400. The first electronic component 100 is, for example, a substrate.

[0040] like Figure 2 As shown, the semiconductor packaging device also includes a second electronic component 500. The second electronic component 500 is also encapsulated within the molding material 600. A wiring layer 700 is disposed between the bridging chip 200 and the second electronic component 500. Specifically, the two second electronic components 500 on the left are electrically connected to the bridging chip 200 on the left through the wiring layer 700, thereby achieving electrical connection between the two second electronic components 500.

[0041] Figure 3 yes Figure 2 A partially enlarged view of a semiconductor packaging device shows components such as a bridge chip 200, a molding compound 600, and a buffer layer 300 (relative to...). Figure 2 (It was flipped).

[0042] like Figure 3 As shown, the diameter of the second conductive hole 340 gradually increases from the top to the bottom because it is formed by laser drilling, and energy attenuation occurs as the drilling depth increases.

[0043] like Figure 3As shown, the buffer layer 300 includes a first dielectric layer 310, a second dielectric layer 320, and a third dielectric layer 330. The first dielectric layer 310 is disposed on a first surface of the bridging chip 200. The second dielectric layer 320 is disposed on the surface of the first dielectric layer 310. A second conductive via 340 penetrates the first dielectric layer 310 and the second dielectric layer 320. The third dielectric layer 330 is disposed on the surface of the second dielectric layer 320 and covers the second conductive via 340. An opening is provided on the third dielectric layer 330, through which the second conductive via 340 is exposed. The first dielectric layer 310 is, for example, a die-attach film (DAF), and the second and third dielectric layers 320 are, for example, polyimide (PI) materials.

[0044] In this embodiment, the stiffness of the buffer layer 300 is less than that of the second conductive hole 340 or the bridging chip 200. The bridging chip 200, the second conductive hole 340, and the first electronic component 100 are typically rigid components that cannot effectively absorb stress, making the structure prone to fracture. By providing the buffer layer 300, the stress in the structure can be effectively absorbed, thus significantly reducing the risk of structural fracture.

[0045] In this embodiment, the first conductive hole 210 can be used to transmit power. Because the aperture of the first conductive hole 210 is small (optionally less than 10 micrometers, for example, 8 micrometers), its impedance is relatively high. Heat is easily generated at the junction of the first conductive hole 210 and the conductive pad 220, forming a heat accumulation area, such as... Figure 4 As shown by the dashed line.

[0046] In this embodiment, the second conductive hole 340 is directly connected to the conductive pad 220. This can disperse the heat accumulation area and allow heat to be transferred to the outside along the second conductive hole 340 (e.g., Figure 4 (As shown by the dashed line with arrows in the middle), which effectively improves the heat dissipation performance of the structure.

[0047] In some embodiments, the length of the second conductive hole 340 may be greater than the thickness of the conductive pad 220, or the minimum diameter of the second conductive hole 340 may be greater than the diameter of the first conductive hole 210, so as to further improve the heat dissipation performance of the structure.

[0048] Figure 5 yes Figure 3 A variation of the structure shown. Figure 3 In this process, the second conductive hole 340 is formed by laser drilling, thus exhibiting a change in hole diameter along the drilling direction. Figure 5 In the process, the second conductive hole 340 is formed by plasma drilling, so the hole diameter remains approximately uniform in the drilling direction (from the bottom to the top).

[0049] In the semiconductor packaging device of this disclosure embodiment, the external connection of the semiconductor packaging device is achieved through the second conductive hole 340 on the buffer layer 300. Since the second conductive hole 340 can be formed by drilling, no grinding process is required. This avoids the problem of excessive wear or difficulty in exposing the through-silicon via due to warping of the semiconductor packaging device during the grinding process, which is beneficial to ensuring the electrical connection performance between the semiconductor packaging device and the outside.

[0050] This disclosure also provides a method for manufacturing a semiconductor packaging device. Figures 6-13 This is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0051] Figure 6 and Figure 7 The fabrication process of the bridge chip 200 is illustrated. First, a first conductive via 210 is formed on the silicon material, and a first conductive post 230 is formed above the first conductive via 210, resulting in... Figure 6 The bridge chip 200 is shown. Next, [the following will be used]. Figure 6 The bridging chip 200 is flipped and a conductive pad 220 is formed on its upper surface, resulting in the following: Figure 7 The bridge chip 200 is shown.

[0052] Figures 8-13 The packaging process of the bridge chip 200 is illustrated. First, a metal layer 920 and a second conductive pillar 610 are formed on the carrier 910, and the bridge chip 200 is bonded to the metal layer 920 through the first dielectric layer 310, resulting in the following... Figure 8 The structure shown is as follows. Next, molding is performed on top of the carrier 910, and the upper surface of the molding material 600 is ground to obtain the structure shown. Figure 9 The structure shown. Next, a circuit layer 700 is formed above the molding material 600, resulting in the structure shown. Figure 10 The structure is shown. Next, a second electronic component 500 is placed on the circuit layer 700, and molding is performed from above the circuit layer 700 to obtain the structure shown. Figure 11 The structure shown. Next, will Figure 11 The structure is flipped, the carrier 910 and metal layer 920 are removed, and an opening 930 is formed on the first dielectric layer 310. Finally, a second dielectric layer 320 and a third dielectric layer 330 are formed on the first dielectric layer 310 to form a buffer layer 300, and a second conductive hole 340 and solder 400 are formed on the buffer layer 300 to obtain a semiconductor packaging device as shown in Figure 13.

[0053] The manufacturing method of the semiconductor packaging device provided in this disclosure can achieve similar technical effects to the semiconductor packaging device described above, and will not be repeated here.

[0054] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: Molding materials; A bridging chip is encapsulated within the molding material. The bridging chip is provided with a conductive pad and a first conductive hole. The conductive pad is located on the first surface of the bridging chip, and the first conductive hole is located inside the bridging chip and is electrically connected to the conductive pad. A buffer layer is disposed on the first surface of the bridging chip. A second conductive hole is disposed on the buffer layer. The first end of the second conductive hole is electrically connected to the conductive pad, and the second end of the second conductive hole is exposed outside the buffer layer. The stiffness of the buffer layer is less than that of the second conductive hole or the bridge chip.

2. The semiconductor packaging apparatus according to claim 1, wherein, The second end of the conductive hole is electrically connected to the first electronic component via solder.

3. The semiconductor packaging apparatus according to claim 1, wherein, The diameter of the second conductive hole gradually increases from the first end to the second end.

4. The semiconductor packaging apparatus according to claim 1, wherein, The diameter of the second conductive hole remains uniform from the first end to the second end.

5. The semiconductor packaging apparatus according to claim 1, wherein, The buffer layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on a first surface of the bridging chip, and the second dielectric layer is disposed on the surface of the first dielectric layer. The second conductive via penetrates the first dielectric layer and the second dielectric layer.

6. The semiconductor packaging apparatus according to claim 5, wherein, The buffer layer further includes a third dielectric layer, which is disposed on the surface of the second dielectric layer and covers the second conductive hole. An opening is provided on the third dielectric layer, through which the second conductive hole is exposed.

7. The semiconductor packaging apparatus according to claim 1, wherein, The length of the second conductive hole is greater than the thickness of the conductive pad.

8. The semiconductor packaging apparatus according to claim 1, wherein, The minimum diameter of the second conductive hole is greater than the diameter of the first conductive hole.

9. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging device further includes at least two second electronic components, which are electrically connected via the bridging chip.

10. A method for manufacturing a semiconductor packaging device, comprising: A bridging chip is connected to a buffer layer, wherein the bridging chip is provided with a conductive pad and a first conductive hole, the conductive pad is located on a first surface of the bridging chip, and the first conductive hole is located inside the bridging chip and is electrically connected to the conductive pad; A molding material covering the bridging chip is formed by molding. A second conductive hole is formed on the buffer layer by drilling and electroplating to obtain a semiconductor packaging device, wherein the first end of the conductive hole is electrically connected to the conductive pad, and the second end of the second conductive hole is exposed outside the buffer layer; The stiffness of the buffer layer is less than that of the second conductive hole or the bridge chip.

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