A "bridge-type" structure for on-chip diode testing and its fabrication method

Abstract

This invention relates to a "bridge-type" structure for on-chip diode testing and its fabrication method. The structure includes a "bridge-type" structure disposed on a silicon pad, comprising two pillars or platforms for supporting the circuit under test (DUT) and withstanding probe pressure during testing. The method involves defining a photolithographic pattern on the silicon wafer according to the structure of the DUT, protecting the "bridge-type" structure location with photoresist, and then performing deep silicon etching according to the photolithographic pattern to etch through the entire thickness of the silicon wafer, forming the "bridge-type" structure. A complete silicon wafer is selected as the silicon pad, and a layer of photoresist is spin-coated onto the silicon pad to stably connect the silicon pad to the "bridge-type" structure. After drying, the DUT is assembled onto the etched silicon wafer surface using a cross-alignment structure, forming the "bridge-type" structure for on-chip diode testing. This invention improves the impact of the substrate thickness on the extraction of diode parasitic parameters.

Description

Technical Field

[0001] This invention relates to the field of on-chip testing substrate structures for Schottky diodes, and particularly to a "bridge-type" structure for on-chip testing of diodes and its fabrication method. Background Technology

[0002] Terahertz waves are electromagnetic waves that lie between microwaves, millimeter waves, and infrared light, with frequencies typically ranging from 0.1 to 10 THz, corresponding to wavelengths of 0.03 to 3 mm. Since the 1990s, with the development of laser technology and compound semiconductor technology, significant progress has been made in terahertz science research. The terahertz frequency domain lies in the transition zone between macroscopic classical theory and microscopic quantum theory. Due to its unique spectral position, terahertz waves exhibit many excellent properties, including: the ability to penetrate most non-metallic materials without causing molecular ionization, making them particularly suitable for live detection of biological tissues and next-generation security imaging applications; and quantum properties, allowing them to be reflected and focused by designated quasi-optical devices and transmitted in designated waveguides, while also penetrating many opaque objects such as ceramics, plastics, wood, and organic materials, making them suitable for detecting sealed items and security checks. Furthermore, this property of terahertz waves can be used to detect specific components in the atmosphere, such as water vapor, ice clouds, ozone, and for monitoring atmospheric environmental quality. With such excellent characteristics, terahertz technology has been widely used in the fields of space science, matter detection, communications, and biological science.

[0003] As the frequency rises to the terahertz band, the impact of diode parasitic effects becomes increasingly pronounced, thus necessitating research into these effects. The inconsistency between the substrate thickness of on-chip Schottky diodes and the substrate thickness of monolithic terahertz circuits is a factor affecting the accurate extraction of parasitic parameters. Accurate modeling of Schottky diodes can improve the performance of terahertz mixers.

[0004] On-chip testing of Schottky diodes requires a substrate of a certain thickness to withstand probe pressure. Currently, the substrate thickness for on-chip testing is typically not reduced, resulting in a substrate thickness at the Schottky diode location that is much greater than the thickness under actual monolithic circuit operation. Consequently, the extracted parasitic parameters of the Schottky diode include the influence of the thick substrate, which cannot be eliminated in subsequent data processing, affecting the accuracy of the extracted parameters.

[0005] To improve the accuracy of on-chip parameter extraction for Schottky diodes, an improved monolithic process structure for on-chip testing was proposed, using a "bridge-like" structure design that reduces the substrate thickness at the Schottky diode location to match the actual operating circuit. When force is applied by probes on both sides, the "bridge-like" structure can withstand greater forces, preventing deformation and damage to the monolith. A complete silicon wafer serves as a base support, while the etched silicon wafer acts as the bridge piers, supporting the two ends where the probes apply force. This monolithic diode structure corresponds to a substrate thickness at the micrometer level. Summary of the Invention

[0006] The purpose of this invention is to overcome the influence of a thicker substrate on the extraction of parasitic parameters during on-chip testing of Schottky diodes, thereby providing a "bridge-type" structure for on-chip testing of diodes and its fabrication method.

[0007] To solve the above-mentioned technical problems, the present invention provides a "bridge-type" structure for on-chip testing of diodes, the structure comprising:

[0008] A "pier-type" structure (1) is set on the silicon pad (2), the "pier-type" structure (1) comprising two pillars or platforms for supporting the single-chip circuit under test and bearing the pressure of the probe during testing.

[0009] As an improvement to the above technical solution, the column can be any shape column known in the art and applicable to the present invention, such as, but not limited to, a cube, cuboid, cylinder, regular triangular prism, regular hexagonal prism, etc.

[0010] As an improvement to the above technical solution, the frustum can be any shape frustum known in the art and applicable to the present invention, such as, but not limited to, frustum of a cylinder, frustum of a triangular prism, frustum of a square prism, frustum of a hexagonal prism, etc.

[0011] As another improvement to the above technical solution, the distance between the two pillars or platforms is preferably, but not limited to, 50 to 400 μm, depending on the requirements of different terahertz frequency bands;

[0012] As another improvement to the above technical solution, the height range of the column or platform is preferably, but not limited to, not exceeding 1 mm.

[0013] As another improvement to the above technical solution, the surface of the "pier-type" structure (1) has a layer of photoresist (3). When assembling the single-chip circuit under test, the alignment structure is set on its front side to achieve alignment between the single-chip circuit under test and the "pier-type" structure (1), thereby assembling the single-chip circuit under test on the photoresist (3) on the surface of the "pier-type" structure (1).

[0014] As an improvement to the above technical solution, the silicon pad (2) has a layer of photoresist (3) on its surface, which is used to stably connect the silicon pad (2) to the bottom of the "pier-type" structure (1).

[0015] The present invention provides a method for fabricating a "bridge-type" structure for on-chip diode testing, the method comprising the following steps:

[0016] 1) Photolithography pattern definition: Define the photolithography pattern of a silicon wafer according to the structure of the single-chip circuit under test, and spin-coat a layer of photoresist on the "bridge-like" structure surface on both sides of the silicon wafer for protection;

[0017] 2) Deep silicon etching: After the photolithography pattern is defined, the uncoated portion of the silicon wafer of full thickness is etched through according to the photolithography pattern to obtain a "bridge-like" structure.

[0018] 3) Fixing the silicon pad: Select a complete silicon wafer as the silicon pad, spin-coat a layer of photoresist on the surface of the silicon pad, fix the bottom of the "bridge-type" structure obtained after deep silicon etching in step 2) on the photoresist surface, and dry it after stable connection to obtain the "bridge-type" structure for on-wafer testing of diodes.

[0019] As an improvement to the aforementioned technical solution, silicon wafer etching is divided into two structures: one where each diode is etched as a unit on the bottom, and the other where a row of diodes is etched as a unit on the bottom. Both structures have their advantages and can fulfill design requirements. The "bridge-like" structure obtained by etching a silicon wafer with a row of diodes as a unit offers greater alignment tolerance during installation, reducing the impact of installation errors on testing. The "bridge-like" structure, where each diode is etched as a unit, can support stronger on-wafer test probe pressure, making the GaAs substrate less prone to breakage.

[0020] When using the "pier-type" structure described in this invention for on-chip testing, the circuit under test (DUT) needs to be assembled onto the "pier-type" structure as a "bridge". During the assembly process, the DUT is aligned with the "pier-type" structure by an alignment structure. After ensuring that the alignment is correct, the DUT is assembled onto the photoresist on the surface of the "pier-type" structure. After assembly, the DUT is suspended and then the whole assembly is placed on a probe station for testing.

[0021] This invention proposes a "bridge-type" structure for on-chip testing of Schottky diodes. The advantage of this structure is that the thickness of the "bridge-type" structure can withstand the probe testing pressure, reducing the thickness of the substrate during on-chip testing of Schottky diodes. This makes the substrate thickness consistent with that of the terahertz operating monolithic circuit, effectively improving the influence of substrate thickness on the extraction of parasitic parameters of Schottky diodes.

[0022] This invention proposes a "bridge-type" structure for on-chip testing of diodes and its fabrication method. The advantages of this structure are: it effectively improves the problem of large differences between the substrate thickness and the actual working circuit in traditional terahertz Schottky diode on-chip testing structures, improves the accuracy of parasitic parameter extraction of terahertz Schottky diodes, and thus improves diode modeling in the terahertz band. Attached Figure Description

[0023] Figure 1 This is a cross-sectional schematic diagram of the "bridge-type" structure for on-chip diode testing as described in this invention;

[0024] Figure 2 This is a schematic diagram of step 1) in the fabrication method of the "bridge-type" structure for on-chip testing of diodes according to the present invention;

[0025] Figure 3 This is a schematic diagram of step 2) in the fabrication method of the "bridge-type" structure for on-chip testing of diodes according to the present invention;

[0026] Figure 4 This is a schematic diagram of step 3) in the fabrication method of the "bridge-type" structure for on-chip testing of diodes according to the present invention;

[0027] Figure 5 This is a schematic diagram of the "bridge-type" structure for on-chip diode testing of the present invention, used to assemble the single-chip circuit under test.

[0028] Figure 6 This is a schematic diagram illustrating an implementation of the "bridge-type" structure for on-chip diode testing as described in this invention.

[0029] Figure 7 This is a schematic diagram of the parasitic inductance extracted during on-chip testing in the 25-40GHz frequency band;

[0030] Figure 8 This is a schematic diagram of the parasitic inductance extracted during on-chip testing in the 75-110GHz frequency band.

[0031] Attached Figure Labels

[0032] 1. "Pier-type" structure; 2. Silicon pad; 3. Photoresist.

[0033] 4. The circuit under test; 5. Probes; 6. Probe station. Detailed Implementation

[0034] The technical solutions provided by the present invention will be further illustrated below with reference to the embodiments.

[0035] like Figure 1 The diagram shows a cross-sectional view of the "bridge-type" structure for on-chip diode testing according to the present invention. The structure includes: a "bridge-type" structure 1 disposed on a silicon pad 2, the "bridge-type" structure 1 comprising two pillars or platforms, such as cuboids, for supporting the single-chip circuit under test (DUT) and bearing the pressure of the probe during testing. The surface of the "bridge-type" structure 1 has a layer of photoresist 3. During assembly of the DUT, alignment is achieved between the DUT and the "bridge-type" structure 1 by setting an alignment structure on its front side, thereby assembling the DUT onto the photoresist 3 on the surface of the "bridge-type" structure 1; the surface of the silicon pad 2 also has a layer of photoresist 3, which is used to stably connect the silicon pad 2 to the bottom of the "bridge-type" structure 1.

[0036] like Figure 2 The diagram shown is a schematic diagram of step 1) photolithography pattern definition in the fabrication method of the "bridge-type" structure for on-chip diode testing described in this invention: A 2-inch silicon wafer with a thickness of 150μm is defined with photolithography pattern according to the structure of a GaAs monolithic circuit. The surface of the "bridge-type" structure is protected with photoresist, and the silicon substrate directly below the Schottky diode will be etched.

[0037] like Figure 3 The diagram shown is a schematic of step 2) deep silicon etching in the method for fabricating the "bridge-type" structure for on-wafer testing of diodes according to the present invention: After the photolithography pattern is defined, deep silicon etching is performed according to the photolithography pattern to etch through the entire thickness of the silicon wafer to form a "bridge-type" structure. The distance between the two cuboid "bridge piers" is 300μm.

[0038] like Figure 4 The diagram shows step 3) of fixing the silicon pad in the fabrication method of the "bridge-type" structure for on-chip diode testing described in this invention: A complete silicon wafer is selected as the silicon pad, and a certain thickness of photoresist is spin-coated on the silicon pad to make the silicon pad stably connected to the bottom of the "bridge-type" structure, thereby fixing the silicon wafer of the "bridge-type" structure on the complete silicon pad; after the silicon pad is stably connected to the "bridge-type" structure, it is dried for the next process operation.

[0039] like Figure 5The diagram shows the "bridge-type" structure for on-chip diode testing described in this invention, used in assembling the monolithic circuit under test. After the GaAs monolithic circuit structure and silicon wafer structure are fabricated, the monolithic circuit is assembled onto the etched silicon wafer surface using a cross alignment structure, forming the "bridge-type" structure for on-chip testing of the Schottky diode under test. At this time, the substrate thickness is 20 μm, achieving consistency with the terahertz operating monolithic circuit.

[0040] Both types of silicon wafers have an alignment structure on the etched front side to align the Schottky diode with the supporting silicon wafer during assembly. To facilitate assembly, the alignment structure is located on the front side of the silicon wafer, with "cross-shaped" alignments at the four corners, allowing for position determination in both the X and Y directions. Since different frequency bands require different probe sizes for on-chip testing, Schottky diode structures suitable for probe testing of different frequency bands need to be arranged on the same substrate. The overall planar dimensions of the diode under test are 3.5mm × 5mm. Each frequency band includes an on-chip calibration component and the diode under test structure.

[0041] like Figure 6 The diagram shows an implementation of the "bridge-type" structure for on-chip diode testing according to the present invention: In this embodiment, the silicon pad 2 is a 3-inch silicon wafer with a thickness of 510μm; the "bridge-type" structure 1 is a 2-inch silicon wafer with a thickness of 150μm, etched according to the structure of the single-chip circuit 4 under test; the distance between the two cuboid "bridge piers" is set between 120 and 400μm; the single-chip circuit 4 under test with a thickness of 20μm is aligned and assembled on the "bridge-type" structure 1; the "bridge-type" structure 1 with the assembled single-chip circuit 4 under test is placed on the probe station 6 for on-chip Schottky diode testing; during testing, two probes 5 are respectively placed above the single chip of the "bridge-type" structure 1, and the two cuboid "bridge piers" are used to bear the pressure of the probes 5 to prevent deformation of the single-chip circuit 4 under test, while the probes 5 will be subjected to... Figure 6 The pressure in the direction indicated by the middle arrow causes probe 5 to deform to the position indicated by the dashed line. At this point, the substrate thickness corresponding to the Schottky diode is 20 μm, which reduces the substrate thickness and thus avoids the substrate thickness affecting the extraction of test parameters.

[0042] Setting up an on-chip diode testing platform is quite complex, with high requirements for both the testing platform and the probes. The flatness of the testing platform has a significant impact on on-chip testing; the instruments must be placed at an absolutely horizontal level to ensure optimal testing conditions.

[0043] Due to the different frequency bands and sizes of the probes, on-chip testing mainly includes testing in two frequency bands: 0.1-40 GHz, with a probe GSG spacing of 150 μm; and 75-110 GHz, with a probe GSG spacing of 100 μm. Before each test, probe tip-to-tip calibration is performed using an external calibration device. After calibration, the S-parameters of each circuit structure are tested individually.

[0044] Multiple sets of parasitic parameters obtained under on-chip testing conditions with different substrate thicknesses and frequency bands were compared and analyzed. The parasitic parameter results show that the extraction of parasitic capacitance is not significantly related to substrate thickness and frequency, while the extraction of parasitic inductance parameters is related to several factors. For test results below 40 GHz, parasitic inductance parameter extraction for 20 μm and 300 μm substrate thicknesses was compiled. The parasitic inductance parameters obtained under different substrate thicknesses are shown below. Figure 7 As shown in the figure, the results indicate that the extracted parasitic inductance parameters differ somewhat from those extracted when the monolithic chip is suspended compared to when it is placed on a silicon substrate. Therefore, measurements taken in the suspended state are a crucial part of the process design for extracting parasitic parameters.

[0045] Based on on-chip test results from 75-110GHz, parasitic inductance parameters for monolithic suspended and monolithic placement on a silicon substrate were extracted. The parasitic inductance parameters obtained under different test conditions are as follows: Figure 8 As shown in the figure, the results reveal certain differences in inductance parameters extracted from on-chip testing at different frequency bands. Therefore, increasing the on-chip testing frequency will provide an important theoretical basis for high-frequency diode modeling.

[0046] As can be seen from the above detailed description of the present invention, the "bridge-type" structure for on-chip testing of diodes described in the present invention reduces the thickness of the single substrate during on-chip testing of Schottky diodes, making the thickness of the single substrate consistent with that of the terahertz operating single-chip circuit, and effectively improving the influence of the single substrate thickness on the extraction of parasitic parameters of Schottky diodes.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A "bridge-type" structure for on-chip diode testing, characterized in that, The structure includes: A "pier-type" structure (1) is set on a silicon pad (2), the "pier-type" structure (1) comprising two pillars or platforms for supporting the single-chip circuit under test and bearing the pressure of the probe during testing; The silicon pad (2) has a layer of photoresist (3) on its surface, which is used to stably connect the silicon pad (2) to the bottom of the "pier-type" structure (1); The surface of the "pier-type" structure (1) has a layer of photoresist (3), which is used to align the single-chip circuit under test with the "pier-type" structure (1) by setting an alignment structure on its front side when assembling the single-chip circuit under test, thereby assembling the single-chip circuit under test on the photoresist (3) on the surface of the "pier-type" structure (1). The diode in question is a terahertz Schottky diode; The substrate thickness of the circuit under test is reduced to match the thickness of the actual terahertz Schottky diode circuit.

2. The "bridge-type" structure for on-chip diode testing according to claim 1, characterized in that, The prism can be a cube, cuboid, cylinder, regular triangular prism, or regular hexagonal prism.

3. The "bridge-type" structure for on-chip diode testing according to claim 1, characterized in that, The frustum is a truncated cone, a triangular frustum, a quadrangular frustum, or a hexagonal frustum.

4. The "bridge-type" structure for on-chip diode testing according to claim 1, characterized in that, The distance between the two columns or platforms is 50–400 μm.

5. The "bridge-type" structure for on-chip diode testing according to claim 1, characterized in that, The height of the column or platform is less than or equal to 1 mm.

6. A method for fabricating a "bridge-type" structure for on-chip testing of diodes as described in claim 1, characterized in that, The method includes the following steps: 1) Photolithography pattern definition: Define the photolithography pattern of a silicon wafer according to the structure of the single-chip circuit under test, and spin-coat a layer of photoresist on the "bridge-like" structure surface on both sides of the silicon wafer for protection; 2) Deep silicon etching: After the photolithography pattern is defined, the uncoated portion of the silicon wafer of full thickness is etched through according to the photolithography pattern to obtain a "bridge-like" structure. 3) Fixing the silicon pad: Select a complete silicon wafer as the silicon pad, spin-coat a layer of photoresist on the surface of the silicon pad, fix the bottom of the "bridge-type" structure obtained after deep silicon etching in step 2) on the photoresist surface, and dry it after stable connection to obtain the "bridge-type" structure for on-wafer testing of terahertz Schottky diodes.

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