Three-dimensional memory and methods of making the same

Abstract

The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The method can include forming an etching stop layer and a sacrificial layer adjacent to each other in a direction parallel to a substrate on the substrate; forming a stack structure on the etching stop layer and the sacrificial layer; forming a channel structure through the stack structure to the sacrificial layer; removing the substrate and the sacrificial layer to expose an end portion of the channel structure; removing a portion of a functional layer of the channel structure to expose a channel layer of the channel structure; and forming a lead-out structure in contact with the channel layer. The method for manufacturing the three-dimensional memory according to the present disclosure can avoid the leakage problem caused by the virtual channel being etched in the manufacturing process, and improve the electrical performance and product yield of the three-dimensional memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of three-dimensional memory and its fabrication method. Background Technology

[0002] The core region of a three-dimensional memory can be composed of a stacked structure including multiple gate layers and multiple dielectric layers, as well as a channel structure passing through the stacked structure. The portions of the channel structure corresponding to the gate layers, and the corresponding gate layers, can form memory cells. Some gate layers of the stacked structure can serve as control gates to control the memory cells and realize the storage function.

[0003] As the demand for storage density continues to increase, the number of layers in the stacked structure is also increasing, and the structure of 3D memory is becoming increasingly complex. This presents corresponding challenges in processes such as the formation of stepped structures in 3D memory, and the etching of vias and gate line gaps. Summary of the Invention

[0004] This disclosure provides a three-dimensional memory and a method for its fabrication.

[0005] One aspect of this disclosure provides a method for fabricating a three-dimensional memory. The method may include: forming an etch stop layer and a sacrificial layer adjacent to each other in a direction parallel to the substrate on a substrate; forming a stacked structure on the etch stop layer and the sacrificial layer; forming a channel structure penetrating the stacked structure to the sacrificial layer, wherein the channel structure includes a functional layer and a channel layer; removing the substrate and the sacrificial layer to expose the ends of the channel structure; removing portions of the functional layer of the channel structure to expose the channel layer of the channel structure; and forming an lead-out structure in contact with the channel layer.

[0006] In some embodiments, forming an etch stop layer and a sacrificial layer may include: forming a first sacrificial layer on a substrate; removing a portion of the first sacrificial layer to form a gap at a predetermined location, the remaining portion of the first sacrificial layer being the sacrificial layer; and forming an etch stop layer in the gap.

[0007] In some implementations, the preset position may correspond to a non-core array region that does not have a channel structure.

[0008] In some implementations, the etch stop layer and the sacrificial layer may have an etch selectivity ratio.

[0009] In some implementations, the material of the sacrificial layer may include oxides.

[0010] In some implementations, the material of the etch stop layer may include polysilicon.

[0011] In some implementations, the removal of the sacrificial layer and the removal of the functional layer can be performed simultaneously.

[0012] In some embodiments, after exposing the channel layer, the method may further include: heavily doping the channel layer.

[0013] In some implementations, the material of the lead-out structure may include heavily doped polycrystalline silicon.

[0014] In some embodiments, after forming the channel structure, the method may further include forming a virtual channel and gate line slot through the stacked structure at a location corresponding to the etch stop layer.

[0015] In some embodiments, the stacked structure may include a plurality of alternately stacked second sacrificial layers and a plurality of dielectric layers, and the method may further include: replacing the plurality of second sacrificial layers with gate layers via gate line gaps; and forming a gate line gap structure in the gate line gaps.

[0016] In some embodiments, the method may further include bonding a peripheral circuit wafer on the side away from the substrate before removing the substrate and sacrificial layer.

[0017] Another aspect of this disclosure provides a three-dimensional memory. The three-dimensional memory may include: a stacked structure including a plurality of alternating gate layers and a plurality of dielectric layers; a semiconductor layer and a lead-out structure located on the stacked structure and adjacent to each other in a direction parallel to the stacked structure; and a channel structure extending through the stacked structure to the lead-out structure and including a channel layer in contact with the lead-out structure.

[0018] In some embodiments, the three-dimensional memory may further include a virtual channel and a gate gap structure, the virtual channel and the gate gap structure passing through the stacked structure at locations corresponding to the semiconductor layer.

[0019] In some implementations, the material of the lead-out structure may include heavily doped polycrystalline silicon.

[0020] In some implementations, the material of the semiconductor layer may include polycrystalline silicon.

[0021] In some implementations, the lead-out structure can cover the surface of the semiconductor layer away from the stacked structure.

[0022] In some implementations, the material of the channel layer adjacent to the end of the lead-out structure may include heavily doped polysilicon.

[0023] Another aspect of this disclosure provides a chip structure. The chip structure may include: the three-dimensional memory; and a peripheral circuit wafer, bonded to the three-dimensional memory on the side of the three-dimensional memory away from the semiconductor layer and lead-out structures.

[0024] The three-dimensional memory and its fabrication method according to the exemplary embodiments of this disclosure first form an etch stop layer and a sacrificial layer on a substrate, and then form a channel structure corresponding to the sacrificial layer and a virtual channel and gate line gap structure corresponding to the etch stop layer. This can protect the virtual channel and gate line gap structure in the process of removing a portion of the functional layer of the channel structure from the back side of the substrate, and avoid leakage problems and increased wafer warpage caused by corrosion of structures such as virtual channels. Attached Figure Description

[0025] Other features, objects, and beneficial effects of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0026] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of the present disclosure;

[0027] Figures 2 to 13 This is a schematic cross-sectional view illustrating the fabrication process of a three-dimensional memory according to an exemplary embodiment of the present disclosure; and

[0028] Figure 14 This is a schematic plan view illustrating a three-dimensional memory according to a disclosed exemplary embodiment. Detailed Implementation

[0029] The present disclosure will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Throughout the specification, the same reference numerals denote the same elements.

[0030] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation rather than degree and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0031] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "containing," and / or "comprise" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. When describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to indicate an example or illustration.

[0032] In addition, when terms such as “connection,” “covering,” and / or “formed on” are used in this disclosure, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly stated herein, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as idealized or overly formalized.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0035] In some embodiments, a 3D memory may include a core region in which a core memory array is disposed and a stepped region surrounding the core region. A channel structure may be located in the core region and, together with the gate layer, implement the memory function. In current 3D memory manufacturing processes, a common method for forming gate layers (word lines) is to first form gate line gaps in the core region, and then replace multiple gate sacrificial layers in the stacked structure that forms the main framework of the 3D memory with conductive material through the gate line gaps. After forming the gate layer, a gate line gap structure can be formed in the gate line gaps. The gate line gap structure can be formed as, but is not limited to, the common source of the memory array.

[0036] The channel structure can generally have a cylindrical shape and can consist of a functional layer and a channel layer from the outside in. The functional layer may include a charge trapping layer. The charge trapping layer can trap charge from the channel layer or release the trapped charge to the channel layer to achieve a storage function.

[0037] In the stepped area, the layered structure is patterned into a stepped shape to guide the letter lines. Virtual channels may also be incorporated into the stepped area, passing through the layered structure. These virtual channels may have a similar shape to the channel structure and may include insulating material to provide additional mechanical support during manufacturing.

[0038] In some related technologies, to achieve connectivity between the channel layer and external circuitry, a common approach is to first form a channel structure on / in a substrate, then remove a portion of the functional layer from the back side of the substrate and form an exit structure in contact with the channel layer. However, since virtual channels and / or gate gap structures are also present on / in the substrate, these structures may be damaged during substrate and functional layer removal. For example, when a virtual channel has defects or cracks due to its formation process, the etchant used to remove part of the functional layer will etch the virtual channel along these defects or cracks. Since the virtual channel passes through the stacked structure and contacts the gate layer, etching of the virtual channel can cause a short circuit between the gate layer and the subsequently formed exit structure, thus affecting the reliability of the 3D memory. Furthermore, etching of the virtual channel can exacerbate stress imbalance in the 3D memory, leading to more severe wafer warpage.

[0039] This disclosure provides aspects of a three-dimensional memory and a method for fabricating the same, which can at least partially solve the aforementioned problems existing in related technologies. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] An exemplary embodiment of this disclosure provides a method for fabricating a three-dimensional memory. Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an exemplary embodiment of the present disclosure. For example... Figure 1 As shown, the method 1000 for fabricating a three-dimensional memory may include the following steps:

[0041] S1, an etch stop layer and a sacrificial layer are formed on the substrate in a direction parallel to the substrate and adjacent to each other;

[0042] S2, a stacked structure is formed on the etch stop layer and the sacrificial layer;

[0043] S3 forms a channel structure that extends through the laminated structure to the sacrificial layer;

[0044] S4, Remove the substrate and sacrificial layer to expose the ends of the channel structure;

[0045] S5, partially removing the functional layer of the trench structure to expose the trench layer of the trench structure; and

[0046] S6 forms the lead-out structure that contacts the channel layer.

[0047] Figures 2 to 13 This is a schematic plan view illustrating the fabrication process of a three-dimensional memory according to an exemplary embodiment of the present disclosure. Reference will be made below. Figures 2 to 13 Detailed description of the preparation method 1000.

[0048] S1, an etch stop layer and a sacrificial layer are formed on the substrate, adjacent to each other in a direction parallel to the substrate.

[0049] In step S1, the substrate 110 may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, and any other suitable materials. The substrate 110 may serve as a support structure for structures formed thereon, such as channel structures, virtual channels, and gate gap structures.

[0050] refer to Figure 2 A first sacrificial layer 120 may be formed on the substrate 110. The first sacrificial layer 120 may include, but is not limited to, oxides. Methods for forming the first sacrificial layer 120 include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof.

[0051] refer to Figure 3 After forming the first sacrificial layer 120, a portion of the first sacrificial layer 120 can be removed to form gaps 130 and sacrificial layer 140. For example, photolithography and etching processes (dry etching or wet etching) or chemical mechanical polishing processes can be used to remove portions of the first sacrificial layer 120 to form gaps 130. In some embodiments, the step of forming gaps 130 includes, after forming the first sacrificial layer 120, using an existing photomask and photolithography and dry etching processes to remove a certain thickness of the first sacrificial layer 120 at a predetermined location. The existing photomask includes, but is not limited to, a photomask that can define the core array region. In this case, using an existing photomask can avoid increasing manufacturing costs. In some embodiments, gaps 130 can extend through the first sacrificial layer 120, segmenting the sacrificial layer 140, but the embodiments are not limited to this. In some embodiments, gaps 130 can correspond to non-core array regions of the three-dimensional memory.

[0052] refer to Figure 4An etch stop layer 150 may be formed in the gap 130. The material of the etch stop layer 150 may include, but is not limited to, polysilicon. In some embodiments, the etch stop layer 150 may include any suitable material having an etch selectivity ratio with the sacrificial layer 140. In some embodiments, after forming the etch stop layer 150, the side of the sacrificial layer 140 and the etch stop layer 150 away from the substrate 110 is further subjected to chemical mechanical polishing to planarize them. In some embodiments, an isolation layer 170 may also be formed on the sacrificial layer 140 and the etch stop layer 150 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. In some embodiments, the isolation layer 170 may be omitted.

[0053] S2 forms a stacked structure on the etch stop layer and the sacrificial layer.

[0054] like Figure 5 As shown, the stacked structure 180 includes a plurality of alternately stacked gate sacrificial layers 181 and a plurality of dielectric layers 182, wherein the gate sacrificial layers 181 include, but are not limited to, silicon nitride (SiN). X The dielectric layer 182 includes, but is not limited to, silicon oxide (SiO2). X The number of layers in the 180-layer stacked structure is not limited to... Figure 5 The number of layers shown can be adjusted as needed, such as 32 layers, 64 layers, 128 layers, etc. In some embodiments, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to form a stacked structure 180 on the side of the sacrificial layer 140 and the etch stop layer 150, or the isolation layer 170, away from the substrate 110. The gate sacrificial layer 181 and the dielectric layer 182 may have an etch selectivity. The gate sacrificial layer 181 can be removed in a subsequent process to form the gate layer (word line).

[0055] It should be understood that the method of forming the gate layer is not limited to this. For example, the gate layer can be formed by depositing the gate material directly on the dielectric layer 182.

[0056] S3 forms a channel structure that extends from the stacked structure to the sacrificial layer.

[0057] like Figure 6As shown, the channel structure 190 penetrates the stacked structure 180 and extends into the sacrificial layer 140 in a direction perpendicular to the substrate 110. The channel structure 190 may have a generally cylindrical or prismatic shape and may include a functional layer 191 and a channel layer 192 arranged sequentially from the outside to the inside. In some embodiments, the functional layer 191 may include a barrier layer, a charge trapping layer, and a tunneling layer arranged sequentially from the outside to the inside. The materials of the barrier layer, charge trapping layer, and tunneling layer may be, but are not limited to, silicon oxide, silicon nitride, and silicon oxide, respectively. The channel layer 192 may include, but is not limited to, amorphous silicon, polycrystalline silicon, monocrystalline silicon, etc. Multiple channel structures 190 may be arranged in a two-dimensional array in a direction parallel to the substrate 110.

[0058] In some embodiments, the channel structure 190 can be formed using photolithography and etching processes, as well as thin-film deposition processes. For example, photolithography and etching processes can be used to form a channel hole that penetrates the stacked structure 180 and extends to the sacrificial layer 140. Then, a thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to sequentially form a functional layer 191, including a barrier layer, a charge trapping layer, and a tunneling layer, and a channel layer 192, on the inner wall of the channel hole. In some embodiments, a thin-film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to fill the channel hole with a dielectric material such as silicon oxide. Optionally, one or more air gaps can be formed during the channel filling process by controlling the channel filling process to reduce structural stress.

[0059] In some embodiments, the channel structure 190 may further include a drain 193 located at its end away from the substrate 110. The drain 193 may be made of the same material as the channel layer 192 and may be in contact with the channel layer 192.

[0060] The functional layer 191 and channel layer 192 of the channel structure 190, together with the corresponding portions of the gate layer in the stacked structure 180 and the corresponding gate layer, form a memory cell. A subsequently formed gate layer may correspond to the control terminal of the memory cell. Multiple memory cells in the channel structure 190 are connected in series in a direction perpendicular to the substrate 110 and share the channel layer 192. Under the voltage control of the gate layer, charge carriers in the channel layer 192 enter the charge trapping layer of the functional layer 191, or charge carriers in the charge trapping layer of the functional layer 191 return to the channel layer 192, thereby realizing the programmed state or erased state (unprogrammed state) of the memory cell. Furthermore, the memory cells located at both ends of the multiple memory cells connected in series in a direction perpendicular to the substrate 110 can serve as selection transistors to control the on or off of the multiple memory cells. Exemplarily, the selection transistors can be referred to as top selection transistors or bottom selection transistors depending on their location. Optionally, the top selection transistor may be located near the drain 193.

[0061] In some embodiments, the edges of the stacked structure 180 may be formed as a stepped structure 210. The stepped structure 210 can be formed by performing multiple trim-etch cycles on alternatingly stacked dielectric layers 182 and gate sacrificial layers 181. In a direction parallel to the substrate 110, a pair of dielectric layers 182 and gate sacrificial layers 181 away from the substrate 110 may partially cover an adjacent pair of dielectric layers 182 and gate sacrificial layers 181 close to the substrate 110, thereby exposing the gate sacrificial layer 181 in the pair of dielectric layers 182 and gate sacrificial layers 181 close to the substrate 110 to the adjacent pair of dielectric layers 182 and gate sacrificial layers 181 away from the substrate 110. The exposed area of ​​the gate sacrificial layer 181 can serve as an electrical connection region for forming conductive channels in a direction perpendicular to the substrate 110 during subsequent processes. Optionally, the top side of the stepped structure 210 may be filled with at least one insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0062] like Figure 7 As shown, the virtual channel 220 may penetrate at least a portion of the stacked structure 180 and may extend to the etch stop layer 150 in a direction perpendicular to the substrate 110. The virtual channel 220 may have a similar shape to the channel structure 190. Exemplarily, the process for forming the virtual channel 220 may be similar to the process for forming the channel structure 190. In some embodiments, after forming the virtual channel via, at least one insulating material may be directly filled within the virtual channel via using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, thereby eliminating the functional layer and channel layer of the virtual channel 220. In this case, the virtual channel 220 may be used to provide mechanical support. Optionally, one or more air gaps may be formed during the filling process by controlling the channel filling process to alleviate structural stress.

[0063] The gate line gap structure 230 can penetrate the stacked structure 180 and can extend to the etch stop layer 150 in a direction perpendicular to the substrate 110. The gate line gap structure 230 can extend in a direction parallel to the substrate 110 and divide the multiple channel structures 190 into multiple memory blocks. Figure 14 This is a schematic plan view illustrating a three-dimensional memory according to a disclosed exemplary embodiment. Figure 14As shown, multiple channel structures 190 are arranged in staggered rows, and gate gap structures 230 extend in a direction parallel to the rows of channel structures. Multiple rows of channel structures divided by adjacent gate gap structures 230 can constitute a memory block. Optionally, multiple sub-gate gap structures 231 (e.g., two) parallel to adjacent gate gap structures 230 can be included. The sub-gate gap structures 231 further divide the multiple rows of channel structures into memory regions. It should be noted that since the sub-gate gap structures 231 and gate gap structures 230 have similar structures, they are collectively referred to as gate gap structures 230 in this document.

[0064] In some embodiments, a gate line gap extending through the stacked structure 180 and to the etch stop layer 150 can first be formed using, for example, photolithography and etching processes (dry etching or wet etching). Further, if the etch stop layer 150 is made of polysilicon, a portion of the etch stop layer 150 exposed by the gate line gap can be converted to silicon oxide using, for example, thermal oxidation. Further, the gate sacrificial layer 181 in the stacked structure 180 can be replaced with a gate layer 183 using the gate line gap. The gate layer 183 can include a composite layer structure. Specifically, the gate layer 183 can include a conductive core and an adhesive layer and a high-dielectric-constant layer that sequentially at least partially surround the conductive core. The material of the conductive core can include conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof. The material of the adhesive layer can include titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof, used to bond the conductive core to the high-dielectric-constant layer and effectively prevent the diffusion of conductive material from the conductive core. The high dielectric constant layer can be made of materials such as alumina, hafnium oxide, or any combination thereof. Optionally, the high dielectric constant layer can cover the inner wall of the gate gap. Further, a spacer layer 232 and a core 233 can be sequentially formed on the inner wall of the gate gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form the gate gap structure 230. The spacer layer 232 can be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The core 233 can be made of conductive materials such as tungsten, cobalt, copper, aluminum, or doped semiconductors, or an insulating material, depending on its specific function. In some embodiments, the core 233 (including conductive material) used as a common source portion can be in contact with the etch stop layer 150.

[0065] According to some embodiments of the present disclosure, the method 1000 for fabricating a three-dimensional memory may further include forming a first wafer 100 on which a three-dimensional memory according to an exemplary embodiment of the present disclosure is formed. Figure 8 ) and a second wafer 200 having peripheral circuits formed thereon Figure 9 The steps for connecting.

[0066] like Figure 8As shown, the stepped structure 210 (see Figure 6 The top side may be filled with an insulating material. The through-contact structure 240 can penetrate the insulating material and extend to the etch stop layer 150. The through-contact structure 240 can be used to transmit electrical signals between the two wafers and to realize the interaction between the electrical signals of the two wafers and external control signals after the first wafer 100 and the second wafer 200 are connected. The material of the through-contact structure 240 can be a conductive material such as tungsten, cobalt, copper, aluminum, or doped semiconductor materials.

[0067] In some embodiments, multiple conductive channels 250 may extend in a direction perpendicular to the substrate 110 to the electrical connection regions of multiple gate layers 183, such that one end of the conductive channel 250 contacts the gate layer 183. The conductive channels 250 may be formed by photolithography and etching processes as well as thin film deposition processes, and the material of the conductive channels 250 may include conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof. Optionally, the through-contact structure 240 and the conductive channels 250 may include an adhesive layer or a metal barrier layer as an outer wall structure.

[0068] In some embodiments, a first interconnect layer 260 may be formed on the side of the stacked structure 180 away from the substrate 110 for transmitting electrical signals to and from the second wafer 200. The first interconnect layer 260 may include a plurality of interconnect lines (not shown) extending in a direction parallel to the substrate 110 and a plurality of interconnect channels 261 extending in a direction perpendicular to the substrate 110. The first interconnect layer 260 may also include a plurality of interlayer dielectric layers. The interconnect lines and interconnect channels 261 may be formed in the interlayer dielectric layers; that is, the first interconnect layer 260 may include interconnect lines and interconnect channels 261 located in a plurality of interlayer dielectric layers. The materials of the interconnect lines and interconnect channels 261 may include conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof. The materials of the interlayer dielectric layers may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials, or any combination thereof. In some implementations, interconnect lines and / or interconnect channels 261 in the first interconnect layer 260 may contact the other end of the conductive channel 250 and the other end of the through contact structure 240 to enable signal interaction.

[0069] like Figure 9As shown, the first wafer 100 and the second wafer 200, after the above-described process, can be connected by, for example, bonding. The second wafer 200 can be formed simultaneously with the process of forming the first wafer 100, thereby enabling the first wafer 100 and the second wafer 200 to be processed in parallel to improve production efficiency. The second wafer 200 may include multiple peripheral devices formed therein. The peripheral devices may include any suitable semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, inductors, and capacitors. The multiple peripheral devices can constitute digital, analog, and / or mixed-signal circuit modules that support multiple channel structures 190 to realize various functions.

[0070] In some embodiments, the second wafer 200 may include a second interconnect layer for transmitting electrical signals to and from the first wafer 100. The second interconnect layer may have a similar structure and formation method to the first interconnect layer 260, and therefore will not be described further herein.

[0071] When the first wafer 100 and the second wafer 200 are bonded together, the first wafer 100 may have a first bonding surface 101 away from the substrate 110. Interconnect lines and / or interconnect channels 261 in the first interconnect layer 260 may be exposed to the first bonding surface 101 and may serve as first bonding contacts of the first wafer 100. Similarly, the second wafer 200 may have a second bonding surface 201. Interconnect lines and / or interconnect channels in the second interconnect layer may be exposed to the second bonding surface 201 and may serve as second bonding contacts of the second wafer 200. Further, the first wafer 100 can be positioned on the second wafer 200 by aligning the first and second bonding contacts, thereby electrically connecting the first and second bonding contacts at the aligned positions, and thus electrically coupling structures such as the channel structure 190 and the through-contact structure 240 in the first wafer 100 to peripheral devices in the second wafer 200. The back side of the first wafer 100 or the second wafer 200 (i.e., the side where the memory array or peripheral circuitry is not formed) can be used to form the back-end process structure.

[0072] S4, Remove the substrate and sacrificial layer to expose the ends of the channel structure.

[0073] like Figure 10 and Figure 11 As shown, substrate 110 can be removed using processes such as etching (see...). Figure 9The etch stop layer 150 and the sacrificial layer 140 expose the ends of the channel structure 190. According to an exemplary embodiment of this disclosure, since the sacrificial layer 140 and the etch stop layer 150 can be configured to have a high etch selectivity ratio, the etch stop layer 150 can remain undamaged during the etching process of the sacrificial layer 140, thereby protecting structures such as the virtual channel 220 and the gate line gap structure 230. In this case, corrosive substances such as etchants will not corrode the structure along defects or cracks in the structure such as the virtual channel 220 and the gate line gap structure 230, thereby reducing leakage current between the structure and subsequently formed lead-out structures. Since the etch stop layer 150 can avoid or reduce unnecessary etching or damage to the structure, wafer warpage problems due to stress imbalance can also be mitigated.

[0074] In some embodiments, the method for removing the sacrificial layer 140 may include, but is not limited to, photolithography and etching processes using a mask or chemical mechanical polishing processes. In some embodiments, the location of the sacrificial layer 140 may correspond to the core array region where the channel structure 190 is formed.

[0075] S5, Remove part of the functional layer of the trench structure to expose the trench layer of the trench structure.

[0076] reference Figure 11 The functional layer 191 extending into the sacrificial layer 140 can be removed using processes such as photolithography and etching to expose the channel layer 192. If an isolation layer 170 is included between the etch stop layer 150 and the stack structure 180, this step may further include removing portions of the isolation layer 170 exposed due to the removal of the sacrificial layer 140. In some embodiments, the removal of portions of the functional layer 191 may be performed simultaneously with the removal of the sacrificial layer 140.

[0077] In some embodiments, a doped region 194 may be formed in a portion of the channel layer 192 near the etch stop layer 150 using processes such as ion implantation and annealing. The height of the doped region 194 in the direction perpendicular to the etch stop layer 150 may be greater than the height of at least one gate layer 183. The doped region 194 of the channel layer 192 and corresponding portions of the functional layer 191 may be used to form bottom-select transistors, and the bottom-select transistors may have different threshold voltage values ​​by adjusting the doping concentration of the doped region 194.

[0078] S6 forms the lead-out structure that contacts the channel layer.

[0079] like Figure 12As shown, the lead-out structure 270 in contact with the channel layer 192 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The lead-out structure 270 can cover the etch stop layer 150 and the channel layer 192. The lead-out structure 270 can be, but is not limited to, heavily doped polysilicon. Optionally, the surface of the lead-out structure 270 can be planarized using, for example, a chemical mechanical polishing process. The lead-out structure 270 achieves electrical connection through contact with the channel layer 192 and can serve as a common source electrical coupling region of the channel structure 190.

[0080] In some embodiments, photolithography and etching processes may be used to remove the portion of the etch stop layer 150 corresponding to the through contact structure 240, so that insulating material can surround the through contact structure 240 in subsequent processes, thereby electrically isolating the through contact structures 240 from each other.

[0081] like Figure 13 As shown, the insulating layer 280 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The insulating layer 280 can cover the lead-out structure 270 and surround the through-contact structure 240. Further, a first contact 241 that contacts the through-contact structure 240 and a second contact 271 that contacts the lead-out structure 270 can be formed using processes such as photolithography and etching, as well as thin film deposition processes. The first contact 241 and the second contact 271 can serve as electrical connection structures for the through-contact structure 240 and the lead-out structure 270, respectively. The materials of the first contact 241 and the second contact 271 can include conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0082] According to the exemplary embodiments of the present disclosure, the method for fabricating a three-dimensional memory can protect structures such as virtual channels and gate gap structures from corrosive substances in processes such as removing some functional layers of the channel structure by forming an etch stop layer and a sacrificial layer corresponding to the channel structure (core array region). This avoids or mitigates leakage and wafer warping problems caused by unnecessary etching or damage, thereby improving the reliability of the three-dimensional memory.

[0083] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, comprising: An etch stop layer and a sacrificial layer are formed on a substrate, the etch stop layer and the sacrificial layer being adjacent to each other in a direction parallel to the substrate, and the etch stop layer being made of a semiconductor material; A stacked structure is formed on the etch stop layer and the sacrificial layer; A channel structure is formed that extends through the stacked structure to the sacrificial layer, wherein the channel structure includes a functional layer and a channel layer; At the location corresponding to the etch stop layer, virtual channels and gate line gaps are formed through the stacked structure, and the etch stop layers on the same side of multiple virtual channels are connected together; A grid line gap structure is formed in the grid line gap; Remove the substrate and the sacrificial layer to expose the ends of the channel structure; Removing a portion of the functional layer of the channel structure to expose the channel layer of the channel structure; and An outgoing structure is formed that contacts the channel layer.

2. The method according to claim 1, wherein, The formation of the etch stop layer and the sacrificial layer includes: A first sacrificial layer is formed on the substrate; A portion of the first sacrificial layer is removed to form a gap at a predetermined location, the remaining portion of the first sacrificial layer constituting the sacrificial layer; and The etching stop layer is formed in the gap.

3. The method according to claim 2, wherein, The preset position corresponds to the non-core array region where the channel structure has not been formed.

4. The method according to claim 1, wherein, The etch stop layer and the sacrificial layer have an etch selectivity ratio.

5. The method according to claim 1, wherein, The material of the sacrificial layer includes oxides.

6. The method according to claim 1, wherein, The material of the etch stop layer includes polycrystalline silicon.

7. The method according to claim 1, wherein, The removal of the sacrificial layer and the removal of the functional layer are performed simultaneously.

8. The method according to claim 1, wherein, After exposing the channel layer, the method further includes: heavily doping the channel layer.

9. The method according to claim 1, wherein, The material of the lead-out structure includes heavily doped polycrystalline silicon.

10. The method according to claim 1, wherein, The stacked structure includes multiple alternately stacked second sacrificial layers and multiple dielectric layers, and the method further includes: The plurality of second sacrificial layers are replaced with gate layers via the gate line gaps.

11. The method according to any one of claims 1 to 10, wherein, Before removing the substrate and the sacrificial layer, the method further includes: On the side away from the substrate, the peripheral circuit wafer is bonded and connected.

12. A three-dimensional memory, comprising: The stacked structure includes multiple gate layers and multiple dielectric layers stacked alternately; A semiconductor layer and a lead-out structure are located on the stacked structure and are adjacent to each other in a direction parallel to the stacked structure; as well as A channel structure extends through the stacked structure to the lead-out structure and includes a channel layer in contact with the lead-out structure; The virtual channel and gate gap structure penetrates the stacked structure and extends to the semiconductor layer; the semiconductor layers on the same side of the multiple virtual channels are connected together; The semiconductor layer is configured as an etch stop layer in the formation process of the virtual channel and the gate gap structure, and the semiconductor layer is also configured to protect the virtual channel and the gate gap structure in the process of removing a portion of the functional layer of the channel structure from the back side of the substrate.

13. The three-dimensional memory according to claim 12, wherein, The material of the lead-out structure includes heavily doped polycrystalline silicon.

14. The three-dimensional memory according to claim 12, wherein, The semiconductor layer is made of polycrystalline silicon.

15. The three-dimensional memory according to claim 12, wherein, The lead-out structure covers the surface of the semiconductor layer away from the stacked structure.

16. The three-dimensional memory according to claim 12, wherein, The material of the channel layer adjacent to the end of the lead-out structure includes heavily doped polycrystalline silicon.

17. A chip structure, comprising: The three-dimensional memory as described in any one of claims 12 to 16; as well as The peripheral circuit wafer is bonded to the three-dimensional memory on the side of the three-dimensional memory away from the semiconductor layer and the lead-out structure.

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