Nonvolatile memory device and nonvolatile memory system

Abstract

A nonvolatile memory device and a nonvolatile memory system are provided, the nonvolatile memory device including: a substrate extending in a first direction; a ground select line extending on the substrate in the first direction; a plurality of word lines sequentially stacked on the ground select line and extending in the first direction; a positioning pad spaced apart from the ground select line and the plurality of word lines in the first direction; a back contact plug connected to a lower surface of the positioning pad and extending in a second direction intersecting the first direction; a front contact plug connected to an upper surface of the positioning pad opposite the lower surface and extending in the second direction; an input / output pad electrically connected to the back contact plug; and an upper bonding pad electrically connected to the front contact plug and connected to at least a portion of a plurality of circuit elements of the nonvolatile memory device.

Description

Technical Field

[0001] This disclosure relates to a non-volatile memory device, a system including the non-volatile memory device, and a method of manufacturing the non-volatile memory device. Background Technology

[0002] Semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices. The integration density of non-volatile memory devices has been improved, enabling performance enhancement and cost reduction to meet consumer needs. Incidentally, in the case of two-dimensional or planar memory devices, the integration density is determined by the area occupied by each memory cell. Therefore, recently, three-dimensional memory devices in which each memory cell is vertically positioned have been developed. Summary of the Invention

[0003] Embodiments of the present invention provide a non-volatile storage device with improved alignment margin between contact plugs connected to the outside and contact plugs for connecting circuit elements to peripheral circuit regions.

[0004] Embodiments of the present invention also provide a non-volatile storage system with improved alignment margin between contact plugs connected to the outside and contact plugs for connecting circuit elements in peripheral circuit regions.

[0005] Embodiments of the present invention also provide a method for manufacturing a non-volatile memory device having an improved alignment margin between a contact plug connected to the outside and a contact plug for connecting circuit elements to a peripheral circuit region.

[0006] An embodiment of the present invention provides a non-volatile memory device comprising: a substrate extending along a first direction; a ground select line extending along the first direction on the substrate; a plurality of word lines sequentially stacked on the ground select line and extending along the first direction; a positioning pad spaced apart from the ground select line and the plurality of word lines in the first direction; a rear contact plug connected to a lower surface of the positioning pad and extending along a second direction intersecting the first direction and perpendicular to an upper surface of the substrate; a front contact plug connected to an upper surface of the positioning pad opposite the lower surface and extending along the second direction; an input / output pad electrically connected to the rear contact plug; and an upper bonding pad electrically connected to the front contact plug and connected to at least a portion of a plurality of circuit elements of the non-volatile memory device.

[0007] An embodiment of the present invention also provides a non-volatile storage device comprising: a peripheral region including a plurality of circuit elements; and a cell region electrically connected to the plurality of circuit elements and storing data. The unit region includes: a substrate extending along a first direction; a ground select line extending along the first direction on the substrate; multiple word lines sequentially stacked on the ground select line and extending along the first direction; a channel structure passing through the ground select line and the multiple word lines, and extending along a second direction intersecting the first direction and perpendicular to the upper surface of the substrate; a positioning pad spaced apart from the ground select line and the multiple word lines in the first direction; a rear contact plug connected to the lower surface of the positioning pad and extending along the second direction; a front contact plug connected to the upper surface of the positioning pad opposite the lower surface, extending along the second direction; an input / output pad electrically connected to the rear contact plug; and an upper bonding pad electrically connected to the front contact plug and connected to at least a portion of the multiple circuit elements.

[0008] An embodiment of the present invention also provides a non-volatile memory system, comprising: a motherboard; a non-volatile memory device located on the motherboard; and a controller electrically connected to the non-volatile memory device on the motherboard. The non-volatile memory device includes: a substrate extending along a first direction; a ground select line extending along the first direction on the substrate; a plurality of word lines sequentially stacked on the ground select line and extending along the first direction; a channel structure passing through the ground select line and the plurality of word lines and extending along a second direction intersecting the first direction and perpendicular to the upper surface of the substrate, the channel structure storing data; and positioning pads extending along the first direction from the ground select line and the plurality of word lines. Word lines are spaced apart; a rear contact plug is connected to the lower surface of the positioning pad and extends along a second direction intersecting the first direction; a front contact plug is connected to the upper surface of the positioning pad opposite the lower surface and extends along the second direction; an input / output pad is electrically connected to the rear contact plug; and an upper bonding pad is electrically connected to the front contact plug and connected to at least a portion of the circuit elements of the non-volatile memory device. Attached Figure Description

[0009] Figure 1An exemplary view of a non-volatile storage device according to an embodiment of the present invention is shown.

[0010] Figure 2 An embodiment of the invention is shown. Figure 1 An exemplary enlarged view of the CSLR region.

[0011] Figure 3 Other embodiments based on the concept of the present invention are shown. Figure 1 An exemplary enlarged view of the CSLR region.

[0012] Figure 4 An embodiment of the invention is shown. Figure 1 A schematic enlarged view of region R1.

[0013] Figure 5 It shows along Figure 4 An exemplary cross-sectional view taken from line A-A'.

[0014] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 An exemplary view is shown of intermediate steps in a method for illustrating an embodiment of the invention of a non-volatile storage device.

[0015] Figure 11 Other embodiments based on the concept of the present invention are shown. Figure 1 An exemplary enlarged view of region R1.

[0016] Figure 12 It shows along Figure 11 An exemplary cross-sectional view taken from line A-A' in the diagram.

[0017] Figure 13 An exemplary view of a non-volatile storage device according to an embodiment of the present invention is shown.

[0018] Figure 14 An embodiment of the invention is shown. Figure 13 A magnified schematic diagram of region R2.

[0019] Figure 15 It shows along Figure 14 An exemplary cross-sectional view taken from line A-A'.

[0020] Figure 16 Other embodiments based on the concept of the present invention are shown. Figure 14 An exemplary enlarged view of region R2.

[0021] Figure 17 It shows along Figure 16 An exemplary cross-sectional view taken from line B-B'.

[0022] Figure 18 It shows along Figure 16 An exemplary cross-sectional view taken from line C-C'.

[0023] Figure 19 An exemplary view of a non-volatile storage device according to an embodiment of the present invention is shown.

[0024] Figure 20 It shows Figure 19 A magnified schematic cross-sectional view of region R3.

[0025] Figure 21 An exemplary view of a non-volatile storage device according to an embodiment of the present invention is shown.

[0026] Figure 22 An exemplary block diagram of a non-volatile memory system including non-volatile memory devices, according to an embodiment of the present invention, is shown.

[0027] Figure 23 An exemplary perspective view of a non-volatile memory system including non-volatile memory devices, according to an embodiment of the present invention, is shown.

[0028] Figure 24 The illustration shows a section along line I-I' containing a non-volatile memory device, according to an embodiment of the present invention. Figure 23 An exemplary cross-sectional view of a non-volatile memory package.

[0029] Figure 25 This illustrates another embodiment of the invention, showing a section along line I-I' including a non-volatile memory device. Figure 23 An exemplary cross-sectional view of a non-volatile memory package. Detailed Implementation

[0030] As is customary in the field of this invention, embodiments are described and illustrated in blocks of one or more functions as described in the implementation. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and can be optically driven by firmware and / or software. The circuitry may, for example, be embedded in one or more semiconductor chips, or embedded on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of this invention, each block of an embodiment may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of this invention, the blocks of an embodiment may be physically combined into more complex blocks.

[0031] Figure 1 An exemplary view of a non-volatile storage device according to an embodiment of the present invention is shown. Figure 2 and Figure 3 It shows Figure 1 An exemplary enlarged view of the CSLR region.

[0032] Reference Figure 1 According to some embodiments, the non-volatile memory device 400a may have a C2C (chip-to-chip) structure. A C2C structure can refer to a structure in which an upper chip including cell regions (CELL) is fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERI) is fabricated on a second wafer different from the first wafer. The upper and lower chips are then bonded to each other at contact surfaces C_F using a bonding method or technique. As an example, the bonding method can refer to the way in which bonding metals formed on the uppermost metal layer of the upper chip and bonding metals formed on the uppermost metal layer of the lower chip are electrically connected. For example, when the upper bonding metal is formed of copper (Cu), the bonding method can be a Cu-Cu bonding method, and the bonding metal can be formed of aluminum or tungsten.

[0033] According to some embodiments, the peripheral circuit region PERI and cell region CELL of the non-volatile memory device 400a may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0034] The Peripheral Circuit Region (PERI) may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, 230c, and 230d connected to each of the plurality of circuit elements 220a, 220b, and 220c, and second metal layers 240a, 240b, 240c, and 240d formed on the first metal layers 230a, 230b, 230c, and 230d. In an embodiment, for example, the first metal layers 230a, 230b, 230c, and 230d may be formed of tungsten, which has relatively high resistance, and the second metal layers 240a, 240b, 240c, and 240d may be formed of copper, which has relatively low resistance.

[0035] Although only the first metal layers 230a, 230b, 230c, and 230d and the second metal layers 240a, 240b, 240c, and 240d are shown and described, the embodiments are not limited thereto, and at least one or more metal layers may be further formed on the second metal layers 240a, 240b, 240c, and 240d. At least a portion of one or more metal layers formed above the second metal layers 240a, 240b, 240c, and 240d may be formed of aluminum or the like, which has a lower resistance than copper, which forms the second metal layers 240a, 240b, 240c, and 240d. A third metal layer 250a may be connected to the second metal layer 240a.

[0036] An interlayer insulating layer 215 is disposed on the first substrate 210 to cover a plurality of circuit elements 220a, 220b and 220c, first metal layers 230a, 230b, 230c and 230d and second metal layers 240a, 240b, 240c and 240d, and may include insulating materials such as silicon oxide and silicon nitride. A lower insulating film 201 covers the lower surface of the first substrate 210.

[0037] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL in a bonding manner. The lower bonding metals 271b and 272b, as well as the upper bonding metals 371b and 372b, can be formed of aluminum, copper, tungsten, or the like.

[0038] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 310 and a common source line 319. Multiple word lines (331 to 338; 330) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). Serial select lines and ground select lines may be located above and below the word lines 330, and the multiple word lines 330 may be located between the serial select lines and the ground select lines.

[0039] In the bit line bonding region BLBA, the channel structure CH extends in a direction perpendicular to the upper surface of the second substrate 310 and can pass through the word line 330, the serial select line and the ground select line.

[0040] The channel structure CH extends along the vertical direction Z, such as... Figure 2 and Figure 3 As shown, it may include a data storage layer 397, a channel layer 390, a buried insulating layer 391, etc. The channel layer 390 may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In an embodiment, the bit line 360c may extend along a second direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0041] The second substrate 310, ground select line 320, and channel structure CH of the non-volatile memory device 400a according to some embodiments can be configured in various forms. (See below) Figure 2 and Figure 3 Various structures of the second substrate 310, ground select line 320, and channel structure CH of the non-volatile memory device 300a according to some embodiments will be illustrated by expanding the CSLR region.

[0042] Figure 2 and Figure 3 The illustration is shown Figure 1 Various exemplary magnified views of the CSLR region.

[0043] Reference Figures 1 to 3 The channel layer 390 may extend in the third direction Z. Although the channel layer 390 is shown as having a stacked cup shape, this is only an example, and the channel layer 390 may also have various shapes such as cylindrical, square tube, solid filler, and single cup shapes. The channel layer 390 may include, but is not limited to, semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0044] Interlayer insulation layer 330I can correspond to Figure 1 Interlayer insulation layer 315. Data storage layer 397 may be located between channel layer 390 and including ground select line 320 (in Figure 2 and Figure 3 (Not shown in the image) Between word lines 330. For example, data storage layer 397 may extend along the side surface of channel layer 390.

[0045] In some embodiments, the data storage layer 397 may be formed of multiple films. For example, the data storage layer 397 may include a tunnel insulating film 397a, a charge storage film 397b, and a barrier insulating film 397c sequentially stacked on the channel layer 390. The tunnel insulating film 397a may include, for example, silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3) and hafnium oxide (HfO2)). The charge storage film 397b may include, for example, silicon nitride. The barrier insulating film 397c may include, for example, silicon oxide or a high dielectric constant material (e.g., silicon oxide). In some embodiments, the data storage layer 397 may also include a gate insulating film 397d extending along the surface of each word line 330.

[0046] In some embodiments, the channel structure CH may further include a buried insulating layer 391. The buried insulating layer 391 may be formed to fill the interior of a semiconductor pattern 390 having a cup shape. The buried insulating layer 391 may include, but is not limited to, an insulating material such as silicon oxide.

[0047] The common source line 319 can be formed as a channel layer 390 connected to the channel structure CH.

[0048] like Figure 2 As shown, in some embodiments, the channel structure CH may pass through the common source line 319 and be buried in the second substrate 310. The common source line 319 may pass through a portion of the data storage layer 397 and connect to the side surface of the channel layer 390.

[0049] like Figure 3 As shown, in some embodiments, at least a portion of the common source line 319 may be buried within the second substrate 310. The common source line 319 may be formed from the second substrate 310, for example, by a selective epitaxial growth (SEG) process. The channel structure CH may pass through a portion of the data storage layer 397 and may be connected to the upper surface of the common source line 319.

[0050] Refer again Figure 1The region containing the channel structure CH and bit line 360c can be defined as the bit line bonding region BLBA. Within the bit line bonding region BLBA, bit line 360c can be electrically connected to circuit element 220c, which provides page buffer 393 in the peripheral circuit region PERI. As an example, bit line 360c is connected to upper bonding metals 371c and 372c, and upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c in the peripheral circuit region PERI that are connected to circuit element 220c of page buffer 393.

[0051] In the word line bonding area (WLBA), word lines 330 can extend along a first direction (X-axis direction) parallel to the upper surface of the second substrate 310 and can be connected to a plurality of cell contact plugs (341 to 347; 340). Word lines 330 and cell contact plugs 340 can be connected at pads provided by extending at least a portion of the word lines 330 along the first direction by different lengths. A first metal layer 350b and a second metal layer 360b can be sequentially connected to the upper portion of the cell contact plugs 340 connected to the word lines 330. In the word line bonding area (WLBA), cell contact plugs 340 can be connected to the peripheral circuit region PERI via upper bonding metals 371b and 372b of the cell region CELL and lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0052] The cell contact plug 340 can be electrically connected to circuit element 220b that provides a row decoder 394 in the peripheral circuitry region PERI. In an embodiment, the operating voltage of circuit element 220b providing the row decoder 394 may be different from the operating voltage of circuit element 220c providing the page buffer 393. As an example, the operating voltage of circuit element 220c providing the page buffer 393 may be higher than the operating voltage of circuit element 220b providing the row decoder 394.

[0053] A common source line contact plug 380 may be located within an external pad bonding region PA. The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to a common source line 319. A first metal layer 350a and a second metal layer 360a may be sequentially stacked on top of the common source line contact plug 380. As an example, the area containing the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a may be defined as the external pad bonding region PA.

[0054] On the other hand, the second input / output pad 305 can be located in the external pad bonding area PA.

[0055] Reference Figure 1An upper insulating film 301 covering the upper surface of the second substrate 310 may be formed above the second substrate 310, and a second input / output pad 305 may be formed on the upper insulating film 301. The second input / output pad 305 is connected to at least one of a plurality of circuit elements 220a, 220b, and 220c located in the peripheral circuit region PERI via a rear input / output contact plug 303a, a landing pad 302a, a front contact plug 303b, and an upper bonding pad 373. The landing pad 302a may be formed to be spaced apart from the ground select line 320 in a first direction (X direction). Furthermore, the landing pad 302a may be formed at the same height as the ground select line 320 in a third direction (Z direction).

[0056] The rear input / output contact plug 303a extends in the third direction Z and can be electrically connected to the positioning pad 302a. Furthermore, the rear input / output contact plug 303a can pass through the side insulation layer 313 and be electrically connected to the second input / output pad 305.

[0057] According to this configuration, by using the positioning pad 302a, the alignment margin for connecting at least one of the plurality of circuit elements 220a, 220b, and 220c to the rear input / output contact plug 303a of the second input / output pad 305 can be improved. That is, by using the positioning pad 302a, the yield of non-volatile memory devices according to some embodiments can be improved. Reference will be made below. Figures 4 to 12 The positioning pad 302a of the improved input / output contact plug 303a is described in detail.

[0058] Figure 4 It shows Figure 1 A schematic enlarged view of region R1. For reference only. Figure 4 It is observed in the third direction (Z direction). Figure 1 A top view of region R1.

[0059] Reference Figure 1 and Figure 4 When an exemplary region R1a of a region R1 of a non-volatile storage device according to some embodiments is viewed in a third direction (Z direction), the positioning pad 302a may be formed to have a second length D2 in a first direction (X direction).

[0060] The lower surface of the positioning pad 302a can be connected to a rear input / output contact plug 303a extending in the third direction (Z direction). The portion of the lower surface of the positioning pad 302a that intersects with the rear input / output contact plug 303a can be defined as the rear contact surface BCF. The upper surface of the positioning pad 302a, opposite to the lower surface, can be connected to a front input / output contact plug 303b extending in the third direction (Z direction). The portion of the upper surface of the positioning pad 302a that intersects with the front input / output contact plug 303b can be defined as the front contact surface FCF. The positioning pad notch B_C used to form the positioning pad 302a can be located on the side surface of the positioning pad 302a.

[0061] In non-volatile storage devices according to some embodiments, the rear contact surface BCF and the front contact surface FCF do not intersect each other. Hereinafter, reference will be made to the area along... Figure 4 The cross section intercepted by line A-A' in the middle Figure 5 Region R1a will be described in more detail. However, the non-volatile storage device according to some embodiments is not limited thereto; for example, a portion of the rear contact surface BCF and a portion of the front contact surface FCF may overlap each other.

[0062] Figure 5 It shows along Figure 4 An exemplary cross-sectional view taken from line A-A'.

[0063] Reference Figure 1 and Figure 5 In region R1a according to some embodiments, the second input / output pad 305 can be electrically connected to circuit element 220a via rear input / output contact plug 303a, positioning pad 302a, front input / output contact plug 303b and upper bonding pad 373.

[0064] More specifically, circuit element 220a can be electrically connected to upper bonding pad 373 by a first metal layer 230d, a second metal layer 240d, and lower bonding metals 271a and 272a that are sequentially stacked from circuit element 220a in the third direction (Z direction).

[0065] In addition, the upper bonding pad 373 can be electrically connected to the front input / output contact plug 303b through the first metal layer 350d and the second metal layer 360d.

[0066] The alignment margin of the rear input / output contact plug 303a, which is positioned such that the second input / output pad 305 is electrically connected to the circuit element 220a, can have a second length D2 in the first direction (X direction). The second length D2 is longer than the first length D1 of the upper bonding pad 373 in the first direction (X direction). Therefore, without the positioning pad 302a, when the alignment margin of the second input / output pad 305 to be electrically connected to the circuit element 220a is the first length D1, the yield of the non-volatile memory device may be reduced because the alignment margin is very small. That is, by forming a positioning pad 302a having a second length D2 longer than the first length D1 of the upper bonding pad 373 and including conductive material, the alignment margin of the rear input / output contact plug 303a connecting the circuit element 220a of the non-volatile memory device to the second input / output pad 305 can be improved according to embodiments of the present invention. Therefore, the yield of the non-volatile memory device according to some embodiments can also be improved. The second length D2 of the positioning pad 302a is not limited to the first direction (X direction). For example, the length of the positioning pad 302a in the second direction (Y direction) may be longer than the length of the upper bonding pad 373 in the second direction (Y direction). Alternatively, for example, the area of ​​the positioning pad 302a viewed in the third direction (Z direction) may be larger than the area of ​​the upper bonding pad 373 viewed in the third direction (Z direction).

[0067] The positioning pad 302a of the non-volatile memory device according to some embodiments can be formed by using a sacrificial film replacement process. The positioning pad notch B_C can also be formed by a replacement process. In the following, reference will be made to... Figures 6 to 10 The method of manufacturing a non-volatile storage device according to some embodiments will be described using region R1a as an example.

[0068] Figures 6 to 10 Exemplary views are shown illustrating intermediate steps of a method for manufacturing a non-volatile memory device according to some embodiments. For reference, in order to illustrate a method for manufacturing a non-volatile memory device according to some embodiments, Figure 5 The accompanying diagram will be interpreted in reverse. That is, in Figure 5 In the figure, the upper insulating film 301 is shown at the top, while... Figures 6 to 10 In the figure, the middle structure is flipped so that the upper insulating film 310 is shown at the bottom of the figure.

[0069] First, refer to Figure 6 A substrate 310, an interlayer insulating layer 315, a sacrificial film S_L, and an interlayer insulating layer 315 are sequentially stacked on the upper insulating film 301.

[0070] The sacrificial film S_L may include at least one of, for example, silicon nitride, silicon oxynitride, silicon-rich nitride, and nanocrystalline silicon (Si). For ease of illustration, the sacrificial film S_L will be described below as containing silicon nitride.

[0071] Interlayer insulating layer 315 may include insulating material. Interlayer insulating layer 315 may include, for example, silicon oxide, such as BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), USG (undoped silicate glass), TEOS (tetraethyl orthosilicate glass), or HDP-CVD (high-density plasma-CVD), but is not limited thereto.

[0072] In the following text, refer to Figure 7 A portion of the substrate 310, interlayer insulating layer 315, and sacrificial film S_L can be etched to form the positioning pad notch trench B_C_T.

[0073] Subsequently, referring to Figure 8 The sacrificial film S_L can be removed using a full back process within the space of the positioning pad notch groove B_C_T. That is, a recess can be formed at the location where the sacrificial film S_L has been removed.

[0074] Subsequently, referring to Figure 9 The recess formed by the full back process can be filled with a conductive material to form the positioning pad 302a. The conductive material may include metals such as tungsten (W), cobalt (Co), and nickel (Ni), or semiconductor materials such as silicon. Alternatively, the conductive material used to form the positioning pad 302a may be, but is not limited to, the same material used to form the ground select line 320.

[0075] Then, refer to Figure 10 The positioning pad notch groove B_C_T can be filled with an insulating material to form the positioning pad notch B_C. The insulating material forming the positioning pad notch B_C can include, for example, silicon oxide, such as BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), USG (undoped silicate glass), TEOS (tetraethyl orthosilicate glass), or HDP-CVD (high-density plasma-CVD), but is not limited to these.

[0076] Subsequently, a front input / output contact plug 303b and an upper bonding pad 373 extending along a third direction (Z direction) can be sequentially formed, and the front input / output contact plug 303b and the upper bonding pad 373 can be bonded to the lower bonding metal 272a of the peripheral circuit region PERI. Then, an upper insulating film 301 and an interlayer insulating layer 315 can be etched to form a rear input / output contact plug 303a that will contact the positioning pad 302a, and a second input / output pad 305 can be formed on the rear input / output contact plug 303a and the upper insulating film 301, thereby forming as shown... Figure 5 The structure shown.

[0077] In the following text, it will be through Figure 11 and Figure 12 Description according to some embodiments Figure 1 Another example of a region R1 for a non-volatile storage device. For reference, the content described above will not be repeated, and the differences will be the main focus.

[0078] Figure 11 It shows Figure 1 Another exemplary enlarged view of region R1. For reference, Figure 11 It is observed in the third direction (Z direction). Figure 1 A top view of region R1.

[0079] Reference Figure 1 and Figure 11 When viewed in a third direction (Z direction), the positioning pad 302a may be formed to have a second length D2 in the first direction (X direction) when viewing an exemplary region R1b of a region R1 of a non-volatile storage device according to some embodiments.

[0080] The lower surface of the positioning pad 302a can be connected to a rear input / output contact plug 303a extending in the third direction (Z direction). The portion of the lower surface of the positioning pad 302a that intersects with the rear input / output contact plug 303a can be defined as the rear contact surface BCF. The upper surface of the positioning pad 302a, opposite to the lower surface, can be connected to a front input / output contact plug 303b extending in the third direction (Z direction). The portion of the upper surface of the positioning pad 302a that intersects with the front input / output contact plug 303b can be defined as the front contact surface FCF. The positioning pad notch B_C used to form the positioning pad 302a can be located on the side surface of the positioning pad 302a.

[0081] In non-volatile storage devices according to some embodiments, the rear contact surface BCF and the front contact surface FCF do not overlap each other. More specifically, the front contact surface FCF and the rear contact surface BCF may not overlap each other. Hereinafter, reference will be made to the following: along... Figure 11 The cross section intercepted by line A-A' Figure 12 The region R1b is described. However, the non-volatile storage device according to some embodiments is not limited thereto; for example, the rear contact surface BCF and the front contact surface FCF can be located anywhere they do not overlap.

[0082] Figure 12 It shows along Figure 11 An exemplary cross-sectional view taken from line A-A' in the diagram.

[0083] Reference Figure 1 and Figure 12 In region R1b according to some embodiments, the second input / output pad 305 can be electrically connected to circuit element 220a via rear input / output contact plug 303a, positioning pad 302a, front input / output contact plug 303b and upper bonding pad 373.

[0084] More specifically, circuit element 220a can be electrically connected to upper bonding pad 373 by a first metal layer 230d, a second metal layer 240d, and lower bonding metals 271a and 272a that are sequentially stacked from circuit element 220a in the third direction (Z direction).

[0085] In addition, the upper bonding pad 373 can be electrically connected to the front contact plug 303b through the first metal layer 350d and the second metal layer 360d.

[0086] The alignment margin of the rear input / output contact plug 303a, positioned such that the second input / output pad 305 is electrically connected to the circuit element 220a, can have a second length D2 in the first direction (X direction). The second length D2 is longer than the first length D1 of the upper bonding pad 373 in the first direction (X direction). Therefore, without the positioning pad 302a, when the alignment margin of the second input / output pad 305 to be electrically connected to the circuit element 220a is the first length D1, the yield of the non-volatile memory device may be reduced because the alignment margin is very small. That is, by forming a positioning pad 302a having a second length D2 longer than the first length D1 of the upper bonding pad 373 and including conductive material, the alignment margin of the rear input / output contact plug 303a connecting the circuit element 220a of the non-volatile memory device to the second input / output pad 305 can be improved according to embodiments of the present invention. Therefore, the yield of the non-volatile memory device according to some embodiments can also be improved. The second length D2 of the positioning pad 302a is not limited to the first direction (X direction). For example, the length of the positioning pad 302a in the second direction (Y direction) may be longer than the length of the upper bonding pad 373 in the second direction (Y direction). Alternatively, for example, the area of ​​the positioning pad 302a viewed in the third direction (Z direction) may be larger than the area of ​​the upper bonding pad 373 viewed in the third direction (Z direction).

[0087] The positioning pad 302a of the non-volatile memory device according to some embodiments can be formed using a sacrificial film replacement process. The positioning pad notch B_C can be formed using a replacement process. This is because the method of manufacturing the non-volatile memory device according to some embodiments is similar to that described above. Figures 6 to 10 The explanation is for reference only, so a detailed description will not be provided.

[0088] Refer again Figure 1 According to an embodiment, the second input / output pad 305 does not overlap with the word line 380 in the third direction (Z-axis direction). See reference... Figure 1 The input / output contact plug 303a is separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and can pass through the interlayer insulating layer 315 of the cell region and connect to the second input / output pad 305.

[0089] According to some embodiments, the second input / output pads 305 may be selectively formed. As an example, the non-volatile memory device 400a according to some embodiments may include only the second input / output pads 305 located above the second substrate 310.

[0090] The metal pattern of the top metal layer exists as a dummy pattern in each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, or the top metal layer can be cleared.

[0091] In a non-volatile memory device 400a according to some embodiments, a lower metal pattern 273a having the same shape as the upper metal pattern 372a of the cell region CELL can be formed in the uppermost metal layer of the peripheral circuit region PERI, corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to another contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI can be formed in the upper metal layer of the cell region CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0092] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b of the peripheral circuit region PERI can be electrically connected in a bonding manner to the upper bonding metals 371b and 372b of the cell region CELL.

[0093] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 392 having the same shape as the lower metal pattern 252 of the peripheral circuit region PERI can be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 252 formed on the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 251 can be connected to the upper metal pattern 252. No contact is formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.

[0094] Figure 13 Exemplary views illustrating some embodiments of a non-volatile storage device according to the present invention are shown. In the following description, the content described above will not be repeated, and the main description will be related to… Figure 1 The 400a is a different aspect of non-volatile storage devices.

[0095] Reference Figure 13 ,and Figure 1Unlike the non-volatile memory device 400a according to some embodiments, in the external pad bonding area PA, the non-volatile memory device 400b according to some embodiments may include a plurality of second input / output pads 305a and 305b, a plurality of rear input / output contact plugs 303a and 303c, a plurality of positioning pads 302a and 302b, a plurality of front input / output contact plugs 303b and 303d, a plurality of upper bonding pads 373 and 373b, a plurality of lower bonding metals 272a, 271a, 272d and 271d, a plurality of second metal layers 240d and 240e, a plurality of first metal layers 230d and 230e, and a plurality of circuit elements 220a and 220d.

[0096] More specifically, the second input / output pad 305a can be electrically connected to circuit element 220a via the rear input / output contact plug 303a, positioning pad 302a, front input / output contact plug 303b, and upper bonding pad 373. Additionally, the second input / output pad 305b can be electrically connected to circuit element 220d via the rear input / output contact plug 303c, positioning pad 302b, front input / output contact plug 303d, and upper bonding pad 373b.

[0097] Multiple positioning pads 302a and 302b can be formed via positioning pad notches B_C, and the non-volatile memory device 400b according to some embodiments can improve the alignment margin of each of the multiple rear input / output contact plugs 303a and 303c through each of the multiple positioning pads 302a and 302b. Therefore, the yield of the non-volatile memory device 400b according to some embodiments can also be improved.

[0098] Figure 14 It shows Figure 13 A magnified view of region R2. For reference only. Figure 14 It is observed in the third direction (Z direction). Figure 13 A top view of region R2.

[0099] Reference Figure 13 and Figure 14 When an exemplary region R2a of a region R2 of a non-volatile storage device according to some embodiments is observed in a third direction (Z direction), positioning pads 302a and 302b may be formed to have a third length D2a and a fourth length D2b respectively in a first direction (X direction).

[0100] The lower surfaces of multiple locating pads 302a and 302b can be connected to multiple rear input / output contact plugs 303a and 303c extending along a third direction (Z direction). The portions where the lower surfaces of locating pads 302a and 302b intersect with the multiple rear input / output contact plugs 303a and 303c can be defined as rear contact surfaces BCFa and BCFb, respectively. The upper surfaces of locating pads 302a and 302b, respectively opposite to the lower surfaces of the multiple locating pads 302a and 302b, can be connected to multiple front input / output contact plugs 303b and 303d extending along a third direction (Z direction), respectively. The portions where the upper surfaces of locating pads 302a and 302b intersect with the multiple front input / output contact plugs 303b and 303d can be defined as front contact surfaces FCFa and FCFb, respectively. The locating pad cutout B_C used to form multiple locating pads 302a and 302b can be located between the multiple locating pads 302a and 302b.

[0101] In a non-volatile storage device according to some embodiments, the rear contact surface BCFa and the front contact surface FCFa, as well as the rear contact surface BCFb and the front contact surface FCFb, may overlap each other. More specifically, the front contact surfaces FCFa and FCFb may each be included within the respective rear contact surfaces BCFa and BCFb along a third direction (Z direction). Hereinafter, reference will be made to the direction along... Figure 14 The cross section intercepted by line A-A' Figure 15 Region R2a is described in detail. However, it should be understood that in other embodiments, at least a portion of the rear contact surfaces BCFa and BCFb may overlap with a portion of the corresponding front contact surfaces FCFa and FCFb.

[0102] Figure 15 It shows along Figure 14 An exemplary cross-sectional view taken from line A-A'.

[0103] Reference Figure 13 and Figure 15 In region R2a according to some embodiments, a plurality of second input / output pads 305a and 305b may be electrically connected to corresponding circuit elements 220a and 220d via a plurality of rear input / output contact plugs 303a and 303c, a plurality of positioning pads 302a and 302b, a plurality of front input / output contact plugs 303b and 303d, and a plurality of upper bonding pads 373 and 373b.

[0104] More specifically, circuit elements 220a and 220d can be electrically connected to a plurality of upper bonding pads 373 and 373b by first metal layers 230d and 230e, second metal layers 240d and 240e, and lower bonding metals 271a, 272a, 271d and 272d sequentially stacked from each of the circuit elements 220a and 220d in the third direction (Z direction).

[0105] According to some embodiments, multiple positioning pads 302a and 302b of a non-volatile memory device can be formed by using a sacrificial film replacement process. Positioning pad notches B_C can also be formed by the replacement process. In the following, because the method of manufacturing a non-volatile memory device according to some embodiments is similar to that described above... Figures 6 to 10 The description is similar to that of the previous one, so no further description will be provided.

[0106] Figure 16 It shows Figure 14 Another exemplary enlarged view of region R2. For reference, Figure 16 It is observed in the third direction (Z direction). Figure 13 A top view of region R2. That is, Figure 16 Region R2b can be replaced Figure 13 Region R2.

[0107] Reference Figure 13 and Figure 16 When observing an exemplary region R2b of a non-volatile storage device according to some embodiments in a third-party direction (Z direction), due to the replacement process of the positioning pad notch B_C, positioning pads 302a and 302b (see Figure 13 ) can have connected shapes (see Figure 16 Therefore, positioning pads 302a and 302b can form a single positioning pad 302, as shown. Figure 16 As shown. According to some embodiments, the positioning pads 302a and 302b of the non-volatile memory device can be formed to have a third length D2a and a fourth length D2b respectively in a first direction (X direction). The shape of the positioning pad 302 is not limited to this and can be elliptical.

[0108] The lower surface of the positioning pad 302 can be connected to a rear input / output contact plug 303a extending in the third direction (Z direction). The portion of the lower surface of the positioning pad 302 that intersects with the rear input / output contact plug 303a can be defined as the rear contact surface BCFa. The upper surface of the positioning pad 302, opposite to the lower surface, can be connected to a front input / output contact plug 303d extending in the third direction (Z direction). The portion of the upper surface of the positioning pad 302 that intersects with the front input / output contact plug 303d can be defined as the front contact surface FCFb. The positioning pad notch B_C used to form the positioning pad 302 can be located at the center of the positioning pad 302.

[0109] In some embodiments of the non-volatile storage device, the rear contact surface BCFa and the front contact surface FCFb do not overlap each other. More specifically, the front contact surface FCFb may not overlap with the rear contact surface BCFa. In the following, reference will be made to the diagram showing the path along... Figure 16 The cross section intercepted by line B-B' Figure 17 A detailed description of region R2b is provided. References are shown along... Figure 16 The cross section intercepted by line C-C' Figure 18 The region R2b will be described in further detail. The non-volatile storage device according to some embodiments is not limited thereto; for example, the rear contact surface BCFa and the front contact surface FCFb may be located at any position where they do not overlap.

[0110] Figure 17 It shows along Figure 16 An exemplary cross-sectional view taken from line B-B'. Figure 18 It shows along Figure 16 An exemplary cross-sectional view taken from line C-C'.

[0111] Reference Figure 17 The circuit element 220d, the front input / output contact plug 303d, and the positioning pad 302b can be electrically connected to each other.

[0112] Reference Figure 18 The second input / output pad 305a, the rear input / output contact plug 303a, and the positioning pad 302a can be electrically connected to each other.

[0113] That is, the second input / output pad 305a can be electrically connected to the circuit element 220d through the positioning pad 302.

[0114] Figure 19 An exemplary view showing another non-volatile storage device according to some embodiments is shown. Figure 20 It shows Figure 19 A magnified schematic cross-sectional view of region R3.

[0115] Reference Figure 19 and Figure 20 According to some embodiments Figure 1 Unlike the non-volatile memory device 400a, in addition to the positioning pad 302a formed at the same height as the ground select line 320, the non-volatile memory device 400c according to some embodiments may also include the positioning pad 302c formed at the same height as the word line 331.

[0116] The non-volatile memory device according to some embodiments is not limited thereto, and may also include positioning pads formed at the same height as other word lines 332 to 338. For example, four (or more) positioning pads may be configured to be spaced apart from each other along a third direction (Z direction). In yet another example, the non-volatile memory device according to some embodiments is not limited thereto, and may also include serial select lines and / or positioning pads formed at the same height as ground select lines located above and below word line 330. In yet another embodiment, four (or more) positioning pads may be configured to be spaced apart from each other along a first direction (X direction).

[0117] Figure 21 An exemplary view showing another non-volatile storage device according to some embodiments is shown.

[0118] Reference Figure 21 ,and Figure 1 Unlike the non-volatile memory device 400a, the non-volatile memory device 400d according to some embodiments may have a positioning pad 302c formed at the same height as the word line 331.

[0119] The non-volatile memory device according to some embodiments is not limited thereto, and the positioning pads may be formed at the same height as other word lines 332 to 338. In yet another example, the non-volatile memory device according to some embodiments is not limited thereto, and the positioning pads may also be formed at the same height as the string select line and / or ground select line located above and below word line 330.

[0120] Figure 22 An exemplary block diagram is shown illustrating a non-volatile memory system including non-volatile memory devices according to some embodiments.

[0121] Reference Figure 22According to some embodiments, a non-volatile memory system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The non-volatile memory system 1000 may be a storage device including one or more semiconductor devices 1100, or an electronic device including a storage device. For example, the non-volatile memory system 1000 may be an SSD (Solid State Drive), USB (Universal Serial Bus), computing system, medical device, or communication device including one or more semiconductor devices 1100.

[0122] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, a reference to... Figures 1 to 21 The NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be located close to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR located between the bit line BL and the common source line CSL.

[0123] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT located between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0124] In an exemplary embodiment, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0125] In an exemplary embodiment, the lower transistors LT1 and LT2 may each include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may each include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 can be used in an erase operation that utilizes the gate-induced drain leakage (GIDL) phenomenon to delete data stored in the memory cell transistor MCT.

[0126] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the interior of the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the interior of the first structure 1100F to the second structure 1100S.

[0127] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via one or more input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the interior of the first structure 1100F to the second structure 1100S.

[0128] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to an embodiment, the non-volatile memory system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0129] Processor 1210 can control the operation of the entire non-volatile memory system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface (I / F) 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data recorded in memory cell transistors (MCTs) of semiconductor device 1100, and data read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted through NAND interface 1221. Host interface 1230 can provide communication functionality between non-volatile memory system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0130] Figure 23 An exemplary perspective view is shown, illustrating a non-volatile memory system including non-volatile memory devices according to some embodiments.

[0131] Reference Figure 23 According to some embodiments, a non-volatile memory system 2000 may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more non-volatile memory packages 2003 and DRAMs 2004. The non-volatile memory packages 2003 and DRAMs 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the motherboard 2001.

[0132] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary depending on the communication interface between the non-volatile storage system 2000 and the external host. In an exemplary embodiment, the non-volatile storage system 2000 may communicate with the external host via any of the following interfaces: M-Phy for USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Fast), SATA (Serial Advanced Technology Attachment), and UFS (Universal Flash Memory). In an exemplary embodiment, the non-volatile storage system 2000 may operate using power supplied from the external host via the connector 2006. The non-volatile storage system may also include a PMIC (Power Management Integrated Circuit) that distributes power supplied from the external host to the controller 2002 and the non-volatile storage package 2003.

[0133] The controller 2002 can record data in or read data from the non-volatile memory package 2003, and can improve the operating speed of the non-volatile memory system 2000.

[0134] DRAM 2004 can be a buffer memory used to reduce the speed difference between the non-volatile memory package 2003, which serves as data storage space, and an external host. DRAM 2004 included in the non-volatile memory system 2000 can also function as a cache memory and can provide space for temporarily storing data during the control operations of the non-volatile memory package 2003. When DRAM 2004 is included in the non-volatile memory system 2000, in addition to the NAND controller for controlling the non-volatile memory package 2003, controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0135] The non-volatile memory package 2003 may include a first non-volatile memory package 2003a and a second non-volatile memory package 2003b spaced apart from each other. Both the first non-volatile memory package 2003a and the second non-volatile memory package 2003b may be non-volatile memory packages that each include a plurality of semiconductor chips 2200. Both the first non-volatile memory package 2003a and the second non-volatile memory package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 located on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0136] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 22 Input / output pads 1101. Each semiconductor chip 2200 may include word lines 3210 and channel structures 3220. Each semiconductor chip 2200 may include references. Figures 1 to 21 The semiconductor device described.

[0137] In an exemplary embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 to the on-package pads 2130. Therefore, in each of the first non-volatile memory package 2003a and the second non-volatile memory package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to an embodiment, in each of the first non-volatile memory package 2003a and the second non-volatile memory package 2003b, instead of the bonding wire type connection structure 2400, the semiconductor chips 2200 may also be electrically connected to each other via a connection structure including through-silicon vias (TSVs).

[0138] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may also be included in a single package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate, different from the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may also be connected to each other via wiring formed on the interposer substrate.

[0139] Figure 24 and Figure 25 The diagram illustrates a section taken along line I-I' according to some embodiments, and includes a non-volatile memory device. Figure 23 An exemplary cross-sectional view of a non-volatile memory package.

[0140] Reference Figure 24 In semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 located on the semiconductor substrate 4010, and a second structure 4200 located on the first structure 4100 and connected to the first structure 4100 by wafer bonding. The semiconductor chip 2200 is disposed on a package substrate 2100, which, in addition to including an upper pad 2130 on an upper (first) surface, also includes a lower pad 2125 on a second (lower) surface and a metal layer 2135 therein for interconnection. External terminals 2800 may be disposed on the lower pad 2125 for connection to, for example, a motherboard.

[0141] The first structure 4100 may include a peripheral circuit region, which includes peripheral wiring 4110 and a first connection structure 4150. The second structure 4200 may include a common source line 4205, a word line 4210 located between the common source line 4205 and the first structure 4100, a channel structure 4220 and an isolation structure 4230 passing through the word line 4210, and a word line electrically connected to the channel structure 4220 and the word line 4210. Figure 22The second connection structure 4250 of the WL). For example, the second connection structure 4250 can be electrically connected to the bit line 4240 of the channel structure 4220 and electrically connected to the word line (WL). Figure 22 Gate connection wiring of WL) Figure 22 1115) is electrically connected to the channel structure 4220 and the word line ( Figure 22 (WL). The first connecting structure 4150 of the first structure 4100 and the second connecting structure 4250 of the second structure 4200 can be connected while in contact with each other. The connecting portion between the first connecting structure 4150 and the second connecting structure 4250 can be formed of, for example, copper (Cu).

[0142] The semiconductor chip 2200a, including a non-volatile memory device according to some embodiments, may further include a positioning pad 4302 located in the second structure 4200. Additionally, a positioning pad notch B_C may be further included on the side surface of the positioning pad 4302. Input / output connection wiring 4265 may be electrically connected to the input / output pads ( Figure 23 (2210). Furthermore, the input / output connection wiring 4265 can be electrically connected to a portion of the first connection structure 4150. The input / output connection wiring 4265 can be referenced. Figures 1 to 21 The terms used to describe the front input / output contact plug and the rear input / output contact plug are generic. Each semiconductor chip 2200a may also include input / output pads electrically connected to the peripheral wiring 4110 of the first structure 4100. Figure 23 (of 2210).

[0143] Figure 24 Semiconductor chips 2200a can be electrically connected to each other via a lead-type connection structure 2400. However, in an exemplary embodiment, semiconductor chips (such as...) in a semiconductor package... Figure 24 The semiconductor chips 2200a can also be electrically connected to each other through a connection structure including a through-silicon via (TSV).

[0144] Reference Figure 25 In the semiconductor package 2003B, semiconductor chips 2200b can be arranged perpendicularly to each other. Each semiconductor chip 2200b may include a semiconductor substrate 5010, a first structure 5100 formed below the semiconductor substrate 5010, and a second structure 5200 located below the first structure 5100 and connected to the first structure 5100 by wafer bonding.

[0145] The first structure 5100 may include a peripheral circuit region, which includes peripheral wiring 5110 and a first connection structure 5150. The second structure 5200 may include a common source line 5205, a word line 5210 located between the common source line 5205 and the first structure 5100, a channel structure 5220 and an isolation structure 5230 passing through the word line 5210, and a word line electrically connected to the channel structure 5220 and the word line 5210. Figure 22 The second connection structure 5250 of the WL). For example, the second connection structure 5250 can be electrically connected to the bit line 5240 of the channel structure 5220 and electrically connected to the word line (WL). Figure 22 Gate connection wiring of WL) Figure 22 1115) is electrically connected to the channel structure 5220 and the word line ( Figure 22 (WL). The first connecting structure 5150 of the first structure 5100 and the second connecting structure 5250 of the second structure 5200 can be connected while in contact with each other. The connecting portion between the first connecting structure 5150 and the second connecting structure 5250 can be formed of, for example, copper (Cu).

[0146] In semiconductor chip 2200b, the remaining semiconductor chips, excluding the topmost semiconductor chip, may include a back insulating layer 5300 on semiconductor substrate 5010, back input / output pads 5320 on back insulating layer 5300, and through-silicon via structures 5310 that pass through semiconductor substrate 5010 and back insulating layer 5300 and electrically connect peripheral wiring 5110 of first structure 5100 and back input / output pads 5320. Each through-silicon via structure 5310 may include through-silicon via 5310a and insulating spacers 5310b surrounding the side surface of through-silicon via 5310a. Semiconductor device 2003B may also include connection structures 5400, such as conductive bumps, located below each semiconductor chip 2200b. Connection structures 5400 may electrically connect semiconductor chip 2200b and may electrically connect semiconductor chip 2200b and package substrate 2100. Underfill material layer 5510 may surround the side surface of conductive bump 5400.

[0147] According to some embodiments, the semiconductor chip 2200b may also include a positioning pad 5302 and a positioning pad notch B_C formed on the side surface of the positioning pad 5302 in the second structure 5200. The input / output contact plug 5265 may be a reference... Figures 1 to 21 The terminology used to describe the front and rear input / output contact plugs is general. The input / output contact plug 5265 can be electrically connected to the input / output pads (...). Figure 23 (2210). In addition, the input / output contact plug 5265 can be electrically connected to a portion of the first connection structure 5150.

[0148] In concluding this detailed description, those skilled in the art should understand that many variations and modifications can be made to the disclosed embodiments without substantially departing from the inventive concept. Therefore, the disclosed embodiments should be considered in a general and descriptive sense only, and not for limiting purposes.

Claims

1. A non-volatile storage device, the non-volatile storage device comprising: A substrate extending along a first direction; A ground selection line, the ground selection line extending on the substrate along the first direction; Multiple word lines, which are sequentially stacked on the ground selection line and extend along the first direction; Positioning pads, which are spaced apart from the ground select line and the plurality of word lines in the first direction; A rear contact plug is connected to the lower surface of the positioning pad and extends along a second direction that intersects the first direction and is perpendicular to the upper surface of the substrate; A front contact plug, the front contact plug being connected to the upper surface of the positioning pad opposite the lower surface, the front contact plug extending along the second direction; Input / output pads, which are connected to the rear contact plug; as well as An upper bonding pad, which is electrically connected to the front contact plug and to at least a portion of the circuit elements of the non-volatile memory device, The positioning pad is positioned at the same height as the ground selection line or at least one of the multiple word lines.

2. The non-volatile storage device according to claim 1, wherein, When viewed in the second direction, at least a portion of the rear contact surface where the positioning pad and the rear contact plug meet overlaps with at least a portion of the front contact surface where the positioning pad and the front contact plug meet.

3. The non-volatile storage device according to claim 2, wherein, When viewed in the second direction, the front contact surface overlaps with the rear contact surface.

4. The non-volatile storage device according to claim 1, wherein, When viewed in the second direction, the rear contact surface where the positioning pad and the rear contact plug meet does not overlap with the front contact surface where the positioning pad and the front contact plug meet.

5. The non-volatile storage device according to claim 1, wherein, The first length of the upper bonding pad in the first direction is less than the second length of the positioning pad in the first direction.

6. The non-volatile storage device according to claim 1, wherein, The positioning pads include at least four positioning pads formed sequentially in the second direction.

7. The non-volatile storage device according to claim 1, wherein, The positioning pads include at least four positioning pads spaced apart from each other in the first direction.

8. A non-volatile storage device, the non-volatile storage device comprising: The peripheral region includes multiple circuit elements; as well as A unit region, which is electrically connected to the plurality of circuit elements and stores data, The unit region includes: Substrate, the substrate extending along a first direction, A ground selection line, which extends on the substrate along the first direction. Multiple word lines, which are sequentially stacked on the ground select line and extend along the first direction. A channel structure passing through the ground select line and the plurality of word lines, and extending along a second direction intersecting the first direction and perpendicular to the upper surface of the substrate. Positioning pads, which are spaced apart from the ground select line and the plurality of word lines in the first direction. A rear contact plug, the rear contact plug being connected to the lower surface of the positioning pad and extending along the second direction. A front contact plug, the front contact plug being connected to the upper surface of the positioning pad opposite the lower surface, the front contact plug extending along the second direction. Input / output pads, the input / output pads being electrically connected to the rear contact plug; and An upper bonding pad, which is electrically connected to the front contact plug and to at least a portion of the plurality of circuit elements. The positioning pad is positioned at the same height as the ground selection line or at least one of the multiple word lines.

9. The non-volatile storage device according to claim 8, wherein, When viewed in the second direction, at least a portion of the rear contact surface where the positioning pad and the rear contact plug meet overlaps with at least a portion of the front contact surface where the positioning pad and the front contact plug meet.

10. The non-volatile storage device according to claim 9, wherein, When viewed in the second direction, the front contact surface overlaps with the rear contact surface.

11. The non-volatile storage device according to claim 8, wherein, When viewed in the second direction, the rear contact surface where the positioning pad and the rear contact plug meet does not overlap with the front contact surface where the positioning pad and the front contact plug meet.

12. The non-volatile storage device according to claim 8, wherein, The first length of the upper bonding pad in the first direction is less than the second length of the positioning pad in the first direction.

13. The non-volatile storage device according to claim 8, wherein, The positioning pads include at least four positioning pads formed sequentially in the second direction.

14. The non-volatile storage device according to claim 8, wherein, The positioning pads include at least four positioning pads spaced apart from each other in the first direction.

15. A non-volatile memory system, the non-volatile memory system comprising: Motherboard; A non-volatile storage device, wherein the non-volatile storage device is located on the motherboard; as well as A controller, electrically connected on the motherboard to the non-volatile storage device, The non-volatile storage device includes: Substrate, the substrate extending along a first direction, A ground selection line, which extends on the substrate along the first direction. Multiple word lines, which are sequentially stacked on the ground select line and extend along the first direction. A channel structure, which passes through the ground select line and the plurality of word lines and extends along a second direction intersecting the first direction and perpendicular to the upper surface of the substrate, the channel structure storing data. Positioning pads, which are spaced apart from the ground select line and the plurality of word lines in the first direction. A rear contact plug, the rear contact plug being connected to the lower surface of the positioning pad and extending along the second direction. A front contact plug, the front contact plug being connected to the upper surface of the positioning pad opposite the lower surface, the front contact plug extending along the second direction. Input / output pads, the input / output pads being electrically connected to the rear contact plug; and An upper bonding pad, which is electrically connected to the front contact plug and to at least a portion of the circuit elements of the non-volatile memory device, The positioning pad is positioned at the same height as the ground selection line or at least one of the multiple word lines.

16. The non-volatile storage system according to claim 15, wherein, When viewed in the second direction, at least a portion of the rear contact surface where the positioning pad and the rear contact plug meet overlaps with at least a portion of the front contact surface where the positioning pad and the front contact plug meet.

Images