Shielded gate skew trench field-effect transistor and its fabrication method

Abstract

This application relates to a shielded gate skewed trench field-effect transistor and its fabrication method, comprising: a substrate region, a drift region, a base region, a source region, a trench region, a drain, and a source; the source region consists of a P-type source region and an N-type source region, the P-type source region, the N-type source region, and the trench region being sequentially disposed along the top surface of the base region; in the direction from the substrate region to the drift region, the projected area of ​​the bottom surface of the base region onto the P-type source region is less than or equal to the area of ​​the bottom surface of the P-type source region; the N-type source region is connected to the trench region. When avalanche breakdown occurs, hole current can be directly injected into the P-type source region from the bottom surface of the base region along the shortest straight-line distance, shortening the hole movement path, delaying the turn-on of the parasitic transistor, and improving the avalanche tolerance of the shielded gate skewed trench field-effect transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to shielded gate skew trench field-effect transistors and their fabrication methods. Background Technology

[0002] Split-gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. SGTs feature high channel density and good charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the control gate and drain, thus significantly reducing transfer capacitance.

[0003] Therefore, SGT has lower specific on-resistance, lower conduction and switching losses, and higher operating frequency.

[0004] However, when a traditional SGT is blocked or turned on by a forward high voltage, it is prone to generating hole current due to the avalanche effect. This hole current flowing through the substrate channel will cause the parasitic transistor to turn on. The turning on of the parasitic transistor will lead to avalanche failure of the transistor.

[0005] Therefore, in order to suppress the turn-on of parasitic transistors in SGT before avalanche failure occurs, it is urgent to design a new type of shielded gate skew trench field-effect transistor. Summary of the Invention

[0006] To address the problems in the prior art, the first aspect of this application provides a shielded gate skew trench field-effect transistor, comprising:

[0007] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0008] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 as the top, and the substrate region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0009] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively; the source region 4 is composed of a P-type source region 41 and an N-type source region 42, and the P-type source region 41, the N-type source region 42 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3; the N-type source region 42 is connected to the trench region 5;

[0010] In the direction from the substrate region 1 to the drift region 2, the projected area of ​​the bottom surface of the substrate region 3 onto the P-type source region 41 is less than or equal to the area of ​​the bottom surface of the P-type source region 41.

[0011] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate 8;

[0012] The control grid 52 and the shielding grid 51 are arranged sequentially from top to bottom in the trench area 5 and are separated by the insulating layer 53;

[0013] The shielding grid 51 is connected to the drift region 2 through the insulating layer 53;

[0014] The source electrode 7 is disposed above the source region 4; the drain electrode 6 is disposed below the substrate region 1; and the metal gate electrode 8 is disposed above the control gate 52.

[0015] In one embodiment, the side of the substrate region 3 connected to the control grid is a body region drainage slope 9, and the lower end of the body region drainage slope 9 is inclined away from the groove region 5.

[0016] In one embodiment, the side of the drift zone 2 connected to the shielding grid 51 is a drift zone drainage slope 10, the top edge of the drift zone drainage slope 10 is attached to the bottom edge of the body zone drainage slope 9, and the drift zone drainage slope 10 is inclined toward the groove zone 5.

[0017] In one embodiment, the doping concentrations of both the P-type source region 41 and the N-type source region 42 are heavily doped.

[0018] In one embodiment, the substrate region 1 is doped with N-type doping and the doping concentration of the substrate region 1 is a heavily doped concentration; the drift region 2 is doped with N-type doping and the doping concentration of the drift region 2 is a lightly doped concentration.

[0019] The substrate region 3 is p-type doped, and the doping concentration of the substrate region 3 is medium.

[0020] The doping concentration of the source region 4 is a heavily doped concentration; the doping concentration of the control gate 52 is a heavily doped concentration and the doping type of the control gate 52 is P-type doping.

[0021] The second aspect of this application provides a method for fabricating a shielded gate skewed trench field-effect transistor, used to fabricate a shielded gate skewed trench field-effect transistor as described in any one of the first aspects of this application, comprising:

[0022] A substrate region is prepared using a semiconductor material; a drift region is epitaxially formed on the substrate region; a base region is formed on the drift region by ion implantation or diffusion; trenches for the control gate are etched on the side of the base region; trenches for the shielding gate are etched on the side of the drift region; P-type doped semiconductor material, polysilicon, oxide, and polysilicon are sequentially deposited in the trenches to form a shielding gate, an insulating layer, and a control gate; a P-type source region and an N-type source region are formed on the base region using P-type doped semiconductor material and N-type doped semiconductor material, respectively; a source electrode is formed above the source region; a metal gate electrode is formed above the trench; and a drain electrode is fabricated below the substrate region.

[0023] In one embodiment, etching the trench of the control gate on the side of the substrate region includes:

[0024] The control gate is etched into the side of the substrate region; the etching depth of the control gate gradually increases from top to bottom; the direction of the etching depth is the direction of the groove pointing towards the substrate region.

[0025] In one embodiment, etching grooves into the side of the shielding grid in the drift region further includes:

[0026] The trenches of the shielding gate are etched on the side of the drift region; the etching depth of the trenches of the shielding gate gradually decreases from top to bottom, and the maximum etching depth of the trenches of the shielding gate and the trenches of the control gate are equal.

[0027] In one embodiment, the doping formation of the source region on the substrate region includes:

[0028] On the substrate region, a P-type source region and an N-type source region are formed using P-type doped semiconductor material and N-type doped semiconductor material, respectively, such that the P-type source region and the N-type source region are connected.

[0029] The technical solution provided in this application may include the following beneficial effects:

[0030] Since the P-type source region, N-type source region, and trench region are sequentially arranged along the top surface of the substrate region; the N-type source region is connected to the trench region; in the direction from the substrate region to the drift region, the projected area of ​​the bottom surface of the substrate region on the P-type source region is less than or equal to the area of ​​the bottom surface of the P-type source region, that is, the distance between any point on the bottom surface of the substrate region and the P-type source region is the straight-line distance from the substrate region to the drift region.

[0031] When an avalanche breakdown occurs, the hole current can be injected directly into the P-type source region from the bottom surface of the substrate region along the shortest straight distance, which shortens the movement path of the holes, delays the turn-on of the parasitic transistor, and improves the avalanche tolerance of the shielded gate skew trench field-effect transistor.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0033] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0034] Figure 1 This is a schematic diagram of the structure of a shielded gate oblique trench field-effect transistor shown in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of the hole current path in a shielded gate trench transistor of the prior art;

[0036] Figure 3 yes Figure 1 The diagram shows the hole current path of a shielded gate skew trench field-effect transistor.

[0037] Figure 4 This is a schematic flowchart illustrating the fabrication method of a shielded gate oblique trench field-effect transistor according to an embodiment of this application;

[0038] Figure 5 This is a schematic flowchart of a trench etching method for a shielded gate oblique trench field-effect transistor as shown in an embodiment of this application. Detailed Implementation

[0039] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0040] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0041] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] Example 1

[0043] When a traditional SGT is blocked or turned on by a forward high voltage, it is prone to generating hole current due to the avalanche effect. This hole current flowing through the substrate channel will cause the parasitic transistor to turn on. The turn-on of the parasitic transistor will lead to avalanche failure of the transistor.

[0044] To address the aforementioned issues, this application provides a shielded gate skew trench field-effect transistor that can suppress the activation of parasitic transistors in the SGT before avalanche failure occurs.

[0045] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of the structure of a shielded gate oblique trench field-effect transistor shown in an embodiment of this application;

[0047] The system comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a trench region 5, a drain 6, and a source 7. The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 considered upward. The base region 3 and the source region 4 are sequentially disposed above the drift region 2. The trench region 5 is disposed to the side of the base region 3 and is connected to the drift region 2, the base region 3, and the source region 4, respectively.

[0048] The source region 4 is composed of a P-type source region 41 and an N-type source region 42. The P-type source region 41, the N-type source region 42, and the trench region 5 are sequentially arranged along the top surface of the substrate region 3. The N-type source region 42 is connected to the trench region 5. In the direction from the substrate region 1 to the drift region 2, the projected area of ​​the bottom surface of the substrate region 3 on the P-type source region 41 is less than or equal to the area of ​​the bottom surface of the P-type source region 41.

[0049] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate 8;

[0050] The control grid 52 and the shielding grid 51 are arranged sequentially from top to bottom in the trench area 5 and are separated by the insulating layer 53;

[0051] The shielding grid 51 is connected to the drift region 2 through the insulating layer 53;

[0052] The source electrode 7 is disposed above the source region 4; the drain electrode 6 is disposed below the substrate region 1; and the metal gate electrode 8 is disposed above the control gate 52.

[0053] In this embodiment of the application, the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavily doped concentration;

[0054] The drift region 2 is N-type doped, and the doping concentration of the drift region 2 is light doping concentration;

[0055] The substrate region 3 is p-type doped, and the doping concentration of the substrate region 3 is medium.

[0056] The doping concentration of the source region 4 is a heavily doped concentration; the doping concentration of the control gate 52 is a heavily doped concentration and the doping type of the control gate 52 is P-type doping.

[0057] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0058] In this embodiment, the doping type of the shielding gate is P-type doping, the doping type of the P-type source region is P-type doping, and the doping concentration of the P-type source region is medium doping concentration or heavy doping concentration.

[0059] Furthermore, the doping concentration of the shielding gate can be either heavily doped or moderately doped.

[0060] Preferably, both the P-type source region 41 and the N-type source region 42 are heavily doped. For example, both are medium doped or both are heavily doped, thereby enabling the P-type source region to more easily receive hole current and achieve better shunting effect.

[0061] Furthermore, the side of the substrate region 3 connected to the control grid is a body region drainage slope 9, and the lower end of the body region drainage slope 9 is inclined away from the groove region 5.

[0062] In the embodiments of this application, when a positive voltage is applied to the control gate of the transistor, majority carriers in the substrate region gather at the position of the current-guiding slope in the substrate region to form a conductive channel. The majority carriers are injected into the drift region from the source region through the substrate region along the conductive channel, thereby realizing the energization.

[0063] When in an avalanche state, the drift region is in a positive blocking state and acts as a reverse bias withstand voltage region. The hole current generated by collision ionization in the reverse bias withstand voltage region can be diverted to the P-type source region. Since the hole current is generated at the interface between the trench region and the drift region, the hole current flows along the interface through the matrix region and then into the P-type source region.

[0064] Figure 2 This is a schematic diagram of a shielded gate trench field-effect transistor in the prior art; such as Figure 2 As shown, when a hole current is generated by an avalanche effect, the hole current needs to bypass the N-type source region to reach the P-type source region, so the movement path of the hole current is longer.

[0065] like Figure 3 As shown, in the shielded gate skew trench field-effect transistor of this application embodiment, when hole current occurs, the hole current is directly injected into the P-type source region, so the movement path of the hole current is shorter.

[0066] In the direction pointing from the substrate region to the drift region, the projected area of ​​the bottom surface of the substrate region onto the P-type source region is less than or equal to the area of ​​the bottom surface of the P-type source region, that is, the distance between any point on the bottom surface of the substrate region and the P-type source region is a straight-line distance along this direction.

[0067] When an avalanche breakdown occurs, the hole current can be injected directly into the P-type source region from the bottom surface of the substrate region along the shortest straight distance, which shortens the movement path of the holes, delays the turn-on of the parasitic transistor, and improves the avalanche tolerance of the shielded gate skew trench field-effect transistor.

[0068] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application.

[0069] Example 2

[0070] Based on the above embodiment one, since the projected area of ​​the bottom surface of the substrate region on the P-type source region is smaller than the area of ​​the bottom surface of the P-type source region in the direction from the substrate region to the drift region, the control gate and shielding gate of the transistor also need to be structurally adjusted according to the channel formed by the substrate region.

[0071] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0072] See Figure 1 The shielded gate skew trench field-effect transistor includes:

[0073] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0074] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 defined as upward.

[0075] The matrix region 3 and the source region 4 are sequentially disposed above the drift region 2;

[0076] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0077] The source region 4 is composed of a P-type source region 41 and an N-type source region 42. The P-type source region 41, the N-type source region 42 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3. The N-type source region 42 is connected to the trench region 5.

[0078] In the direction from the substrate region 1 to the drift region 2, the projected area of ​​the bottom surface of the substrate region 3 onto the P-type source region 41 is less than or equal to the area of ​​the bottom surface of the P-type source region 41.

[0079] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate 8;

[0080] The control grid 52 and the shielding grid 51 are arranged sequentially from top to bottom in the trench area 5 and are separated by the insulating layer 53;

[0081] The shielding grid 51 is connected to the drift region 2 through the insulating layer 53;

[0082] The source electrode 7 is disposed above the source region 4; the drain electrode 6 is disposed below the substrate region 1; and the metal gate electrode 8 is disposed above the control gate 52.

[0083] Furthermore, the side of the drift zone 2 connected to the shielding grid 51 is a drift zone drainage slope 10. The top edge of the drift zone drainage slope 10 is attached to the bottom edge of the body zone drainage slope 9, and the drift zone drainage slope 10 is inclined toward the groove zone 5.

[0084] In existing transistors, when the source and drain of the transistor are forward-biased or reverse-biased, the electric field peak is located at both ends of the transistor; however, in the shielded gate skew trench transistor provided in this application embodiment, the positive charge generated by the drift region tends to cross the insulating layer between the shielded gate and the drift region, and finally terminates in the shielded gate.

[0085] Therefore, in the shielded gate sloping trench transistor provided in this application embodiment, the electric field peak is located on the drift region's current-guiding slope. During transistor breakdown voltage testing, this shielded gate and drift region structure can improve the electric field distribution in the drift region and increase the breakdown voltage.

[0086] In this embodiment, the P-type source region, N-type source region, and trench region are sequentially arranged along the top surface of the substrate region; the N-type source region is connected to the trench region; at the same time, the side of the substrate region connected to the control grid is the body region drainage slope. Since the side of the body region drainage slope connected to the drift region is inclined away from the trench region, the length of the bottom edge of the substrate region connected to the drift region is less than the length of the top edge of the substrate region; at the same time, this bottom edge is projected onto the P-type source region in the vertical direction.

[0087] When an avalanche breakdown occurs, the hole current can reach the bottom edge connecting the substrate region and the drift region along the drift region's drainage slope, and then be directly injected into the P-type source region. This shortens the hole's movement path, delays the turn-on of the parasitic transistor, and improves the avalanche tolerance of the shielded gate skew trench field-effect transistor.

[0088] Example 3

[0089] Corresponding to the aforementioned shielded gate skew trench field-effect transistor and its embodiments, this application also provides a method for fabricating a shielded gate skew trench field-effect transistor and corresponding embodiments.

[0090] Figure 4 This is a schematic flowchart illustrating the fabrication method of a shielded gate oblique trench field-effect transistor according to an embodiment of this application.

[0091] See Figure 4 The method for fabricating the shielded gate oblique trench field-effect transistor includes:

[0092] 401. Fabrication of a substrate region using semiconductor materials;

[0093] In the embodiments of this application, the substrate region is prepared using N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is the heavy doping concentration.

[0094] In the embodiments of this application, the semiconductor material is silicon or silicon carbide.

[0095] 402. A drift region is epitaxially formed on the substrate region;

[0096] In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0097] 403. A matrix region is formed on the drift region by ion implantation or diffusion;

[0098] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0099] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0100] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0101] 404. Etch grooves for the control gate on the side of the substrate region;

[0102] 405. Etch grooves in the shielding grid on the side of the drift region;

[0103] In this embodiment, a trench is etched on one side of the drift region using photolithography, and the residual photoresist is removed by wet etching or dry etching.

[0104] The direction in which the trench points to the substrate region is the direction of the etching depth.

[0105] Furthermore, grooves of the control gate are etched on the side of the substrate region; the etching depth of the control gate grooves gradually increases from top to bottom.

[0106] 406. P-type doped semiconductor material, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shielding gate, an insulating layer and a control gate;

[0107] Specifically, the interface between the control gate and the substrate region forms the body region drainage slope. The anti-groove below the body region drainage slope is inclined.

[0108] In the embodiments of this application, when a positive voltage is applied to the control gate of the transistor, majority carriers in the substrate region gather at the position of the current-guiding slope in the substrate region to form a conductive channel. The majority carriers are injected into the drift region from the source region through the substrate region along the conductive channel, thereby realizing the energization.

[0109] 407. On the substrate region, the P-type source region and the N-type source region are formed respectively using P-type doped semiconductor material and N-type doped semiconductor material;

[0110] Furthermore, the P-type source region and the N-type source region are connected.

[0111] In the embodiments of this application, P-type doped semiconductor materials and N-type doped semiconductor materials are used to dope the substrate region to form P-type source regions and N-type source regions. The substrate region and the N-type source region connecting the trench region are short-circuited through the P-type source region, which suppresses the substrate floating effect of the power semiconductor device and ensures the stability of the device performance.

[0112] In the embodiments of this application, preferably, the doping concentrations of the above-mentioned P-type doped semiconductor material and N-type doped semiconductor material are both heavily doped to form an ohmic contact, thereby ensuring that no significant additional impedance is generated in the device.

[0113] 408. A source electrode is formed above the source region;

[0114] 409. A metal gate is formed above the trench of the control gate;

[0115] 410. Fabricate the drain below the substrate region.

[0116] In this embodiment, the P-type source region, the N-type source region, and the trench region are sequentially disposed along the top surface of the substrate region; the N-type source region is connected to the trench region;

[0117] Since the P-type source region, N-type source region, and trench region are sequentially arranged along the top surface of the substrate region; the N-type source region is connected to the trench region; in the direction from the substrate region to the drift region, the projected area of ​​the bottom surface of the substrate region on the P-type source region is less than or equal to the area of ​​the bottom surface of the P-type source region, that is, the distance between any point on the bottom surface of the substrate region and the P-type source region is a straight-line distance along the direction from the substrate region to the drift region.

[0118] When an avalanche breakdown occurs, the hole current can be injected directly into the P-type source region from the bottom surface of the substrate region along the shortest straight distance, which shortens the movement path of the holes, delays the turn-on of the parasitic transistor, and improves the avalanche tolerance of the shielded gate skew trench field-effect transistor.

[0119] Example 4

[0120] Based on the method for fabricating a shielded gate skewed trench field-effect transistor as shown in Embodiment 3 above, this application also provides a trench etching method for a shielded gate skewed trench field-effect transistor.

[0121] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0122] Figure 5 This is a schematic flowchart of a trench etching method for a shielded gate trench field-effect transistor as shown in an embodiment of this application.

[0123] See Figure 5 The trench etching method for the shielded gate trench field-effect transistor includes:

[0124] 501. The control gate is etched with grooves along the flow-guiding slope of the body region on the side of the substrate region;

[0125] 502. Etch grooves in the shielding grid along the flow-guiding slope of the drift zone on the side of the drift zone;

[0126] Specifically, the grooves of the shielding gate are etched on the side of the drift region; the etching depth of the grooves of the shielding gate gradually decreases from top to bottom, and the maximum etching depth of the grooves of the shielding gate and the grooves of the control gate are equal.

[0127] In this embodiment, the side of the substrate region connected to the control gate is a body region drainage slope, and the lower end of the body region drainage slope is inclined away from the trench region.

[0128] In this embodiment, the side of the drift area connected to the shielding grid is a drift area drainage slope, the top edge of the drift area drainage slope is attached to the bottom edge of the body area drainage slope, and the drift area drainage slope is inclined toward the groove area.

[0129] In existing transistors, when the source and drain of the transistor are subjected to forward or reverse bias, the electric field peak is located at both ends of the transistor; however, in the shielded gate skew trench transistor provided in this application embodiment, the positive charge generated by the drift region tends to cross the insulating layer between the shielded gate and the drift region, and finally terminates in the shielded gate.

[0130] Therefore, in the inclined trench transistor provided in this application embodiment, the electric field peak is located on the drift region's current-guiding slope. During transistor breakdown, this structure of the shielding gate and drift region can improve the electric field distribution in the drift region and increase the breakdown voltage.

[0131] 503. P-type doped semiconductor material, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shielding gate, an insulating layer and a control gate.

[0132] In this embodiment, the P-type source region, the N-type source region, and the trench region are sequentially disposed along the top surface of the substrate region; the N-type source region is connected to the trench region;

[0133] Meanwhile, the side connecting the substrate region and the control grid is a body region drainage slope. Because the side connecting the body region drainage slope and the drift region is inclined away from the trench region, the length of the bottom edge connecting the substrate region and the drift region is less than the length of the top edge of the substrate region; simultaneously, this bottom edge is projected vertically onto the P-type source region. The side connecting the drift region and the shielding grid is a drift region drainage slope, and the top edge of the drift region drainage slope is the same as the bottom edge of the body region drainage slope.

[0134] When an avalanche breakdown occurs, the hole current can reach the bottom edge connecting the substrate region and the drift region along the drift region's drainage slope, and then be directly injected into the P-type source region. This shortens the hole's movement path, delays the turn-on of the parasitic transistor, and improves the avalanche tolerance of the shielded gate skew trench field-effect transistor.

[0135] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0136] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0137] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0138] Alternatively, this application may be implemented as a non-transitory machine-readable storage medium (or computer-readable storage medium, or machine-readable storage medium) storing executable code (or computer program, or computer instruction code) that, when executed by a processor of an electronic device (or electronic device, server, etc.), causes the processor to perform some or all of the steps of the methods described above according to this application.

[0139] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the present application can be implemented as electronic hardware, computer software, or a combination of both.

[0140] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0141] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate skew trench type field-effect transistor, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), trench region (5), drain (6), and source (7); The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) as the top, and the substrate region (3) and the source region (4) are sequentially disposed above the drift region (2); The trench area (5) is located on the side of the substrate area (3) and is connected to the drift area (2), the substrate area (3) and the source area (4) respectively; The source region (4) is composed of a P-type source region (41) and an N-type source region (42). The P-type source region (41), the N-type source region (42) and the trench region (5) are arranged sequentially along the top surface of the substrate region (3). The N-type source region (42) is connected to the trench region (5). In the direction from the substrate region (1) to the drift region (2), the projected area of ​​the bottom surface of the substrate region (3) onto the P-type source region (41) is less than or equal to the area of ​​the bottom surface of the P-type source region (41). The trench region (5) includes a shielding gate (51), a control gate (52), an insulating layer (53), and a metal gate (8); The control grid (52) and the shielding grid (51) are arranged sequentially from top to bottom in the trench area (5) and separated by the insulating layer (53); The shielding grid (51) is connected to the drift region (2) through the insulating layer (53); The source electrode (7) is disposed above the source region (4); the drain electrode (6) is disposed below the substrate region (1); and the metal gate electrode (8) is disposed above the control gate (52). The side of the base region (3) connected to the control gate is the body region drainage slope (9), and the lower end of the body region drainage slope (9) is inclined away from the groove region (5); When an avalanche breakdown occurs, the hole current can be injected directly into the P-type source region (41) from the bottom surface of the substrate region (3) along the shortest straight distance.

2. The shielded gate oblique trench field-effect transistor according to claim 1, characterized in that, The side of the drift area (2) connected to the shielding grid (51) is the drift area drainage slope (10). The top edge of the drift area drainage slope (10) is attached to the bottom edge of the body area drainage slope (9), and the drift area drainage slope (10) is inclined toward the groove area (5).

3. The shielded gate oblique trench field-effect transistor according to claim 1, characterized in that, The doping concentrations of both the P-type source region (41) and the N-type source region (42) are heavy doping concentrations.

4. A shielded gate oblique trench field-effect transistor according to claim 1, characterized in that, The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavily doped concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is light doping concentration; The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping concentration of the source region (4) is a heavy doping concentration; the doping concentration of the control gate (52) is a heavy doping concentration and the doping type of the control gate (52) is P-type doping.

5. A method for fabricating a shielded gate oblique trench field-effect transistor, characterized in that, For fabricating a shielded gate skew trench field-effect transistor as described in any one of claims 1-4, comprising: The substrate region is prepared using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. The control gate is etched into the side of the substrate region; Grooves are etched into the side of the shielding grid in the drift region; P-type doped semiconductor material, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a shielding gate, an insulating layer and a control gate; On the substrate region, the P-type source region and the N-type source region are formed using P-type doped semiconductor material and N-type doped semiconductor material, respectively. A source electrode is formed above the source region; A metal gate is formed above the trench; The drain is fabricated below the substrate region.

6. The method for fabricating a shielded gate oblique trench field-effect transistor according to claim 5, characterized in that, The etching of the control gate trench on the side of the substrate region includes: The control gate is etched into the side of the substrate region; the etching depth of the control gate gradually increases from top to bottom; the direction of the etching depth is the direction of the groove pointing towards the substrate region.

7. The method for fabricating a shielded gate oblique trench field-effect transistor according to claim 5, characterized in that, The method of etching grooves on the side of the shielding grid in the drift region further includes: The trenches of the shielding gate are etched on the side of the drift region; the etching depth of the trenches of the shielding gate gradually decreases from top to bottom, and the maximum etching depth of the trenches of the shielding gate and the trenches of the control gate are equal.

8. The method for fabricating a shielded gate oblique trench field-effect transistor according to claim 5, characterized in that, The process of forming a source region by doping on the substrate region includes: forming a P-type source region and an N-type source region on the substrate region using a P-type doped semiconductor material and an N-type doped semiconductor material, respectively, such that the P-type source region and the N-type source region are connected.

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