Temperature-based memory management

Abstract

This application relates to temperature-based memory management. A memory device may include memory cells of a first type, each storing a single bit of information, and memory cells of a second type, each storing multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than those of the second type, but may have one or more drawbacks (e.g., lower density). The memory device can identify data to be written and, in response, can identify the temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, then the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, then the memory device may write the data to the memory cells of the first type.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT application No. PCT / CN2019 / 102337, filed by Wu on August 23, 2019, entitled "Temperature-Based Memory Management", which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves temperature-based memory management. Background Technology

[0004] The system may include various memory devices and controllers coupled via one or more buses to manage information in a variety of electronic devices, such as computers, wireless communication devices, Internet of Things (IoT) devices, cameras, digital displays, etc. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of memory cells. For example, a binary memory cell can store one of two states, typically indicated by a logic "1" or logic "0". Some memory cells can store more than one of more than two states. To access the stored information, the memory device can read or sense the stored states in the memory cell. To store information, the memory device can write or program states into the memory cell.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D Xpoint memory, and flash memory (such as floating gate flash devices and charge trap flash devices, which can be used in NOR and NAND memory devices). Memory devices can be volatile or non-volatile. For example, a non-volatile flash memory cell can maintain its stored logic state for a long time even without an external power supply. A volatile DRAM cell, for example, may lose its stored state over time unless it is periodically refreshed by an external power supply. Flash-based memory devices can offer improved performance compared to some non-volatile and volatile memory devices. Summary of the Invention

[0006] A method is described. The method may include identifying data to be written to a memory device comprising memory cells of a first type and memory cells of a second type. The method may include identifying the temperature of the memory device. The method may include selecting a type of memory cell from a set of memory cell types, including the first type and the second type, based on the temperature of the memory device. The method may include writing data to one or more memory cells of the selected type based on the selected memory cell type from the set of memory cell types.

[0007] An apparatus is described. The apparatus may include: a memory cell of a first type; a memory cell of a second type; a temperature sensor; and a controller coupled to the first type memory cell, the second type memory cell, and the temperature sensor, wherein the controller is operable to cause the apparatus to: identify data to be written to the memory device; determine that the temperature indicated by the temperature sensor is outside a temperature range; and write the data to one or more memory cells of the first type based on the temperature being outside the temperature range.

[0008] A method is described. The method may include receiving a write command for data at a memory device comprising memory cells of a first type and memory cells of a second type. The method may include determining, based on receiving the write command, that a first value of an operating condition of the memory device is outside a range associated with the operating condition. The method may include writing data to one or more memory cells of the first type based on determining that the first value of the operating condition is outside the range. The method may include, after writing data to the one or more memory cells of the first type, determining that a second value of the operating condition of the memory device is within the range. The method may include writing data to one or more memory cells of the second type based on determining that the second value of the operating condition is within the range. Attached Figure Description

[0009] Figure 1 This describes an example of a memory device that supports temperature-based memory management, based on examples disclosed herein.

[0010] Figure 2 This document describes an example of a NAND memory circuit that supports temperature-based memory management, based on examples disclosed herein.

[0011] Figure 3 This document describes an example of a system that supports temperature-based memory management, based on examples disclosed herein.

[0012] Figure 4 An example of a flowchart illustrating a process supporting temperature-based memory management, as disclosed in this document.

[0013] Figure 5 This document describes an example of a system that supports temperature-based memory management, based on examples disclosed herein.

[0014] Figure 6 This describes an example of a block diagram supporting temperature-based memory management, based on examples disclosed herein.

[0015] Figure 7 and 8 The flowchart illustrates one or more methods for supporting temperature-based memory management, based on examples disclosed herein. Detailed Implementation

[0016] In some cases, memory devices may be subjected to a wide range of operating temperatures, which may include relatively extreme (high or low) temperatures. Operating a memory device under such conditions may increase the likelihood of errors in the memory device, which can be particularly problematic for systems where accuracy and reliability are critical (e.g., safety-related systems), such as automotive applications or other systems.

[0017] Some types of memory cells can store a single bit of information in each memory cell. Such memory cells are called single-level cells (SLCs). Some types of memory cells can store two or more bits of information in each memory cell. Such memory cells are referred to herein as multi-level cells and may include, for example, memory cells capable of storing two bits, three bits, four bits, etc. A memory cell storing two bits is sometimes called a multi-level cell (MLC), but this term is sometimes used to refer to any memory cell storing more than one bit. A memory cell storing three bits is called a triple-level cell (TLC), and a memory cell storing four bits is called a quad-level cell (QLC), etc. Compared to SLCs, multi-level cells, such as MLCs, TLCs, and QLCs, offer cost and / or density advantages, while SLCs can be faster and more reliable than multi-level cells. In some cases, NAND memory cells can be (e.g., can be configured or operated as) SLCs or multi-level cells. Generally, the more bits stored in a memory cell, the more sensitive the memory cell can be to noise or other disturbances that can occur under relatively extreme operating conditions. Therefore, for example, SLC can be more robust to extreme temperatures than multilevel cell, but at a higher cost and with lower density. Similarly, MLC cells can be more robust than TLC cells, and TLC cells can be more robust than QLC cells.

[0018] Some safety-critical systems, such as those used in automotive applications, rely on SLC-based memory to improve system reliability. However, this approach can increase system cost and may not fully utilize the density advantages of multi-level memory cells. Therefore, as described herein, memory devices (e.g., NAND memory devices) can incorporate both SLC memory (or another type of highly reliable memory) and multi-level cell memory (or another type of high-density or low-cost memory), and the type of memory to be used can be determined based on factors such as the temperature of the memory device. For example, a memory device can be configured to write data to SLC memory blocks when operating at relatively extreme temperatures and to write data to multi-level cell memory when operating within a less extreme temperature range. In this way, compared to an SLC-only design, the memory device can provide excellent reliability across a range of operating conditions, while offering lower cost and higher density.

[0019] Initially, as referenced Figure 1 and 2 Features of this disclosure are described in the context of the memory devices and memory circuits described herein. Further details are provided by reference to [reference needed]. Figures 3-8 The system diagrams, device diagrams, and flowcharts describing temperature-based memory management illustrate and describe these and other features of this disclosure.

[0020] Figure 1 This description illustrates an example of a memory device 100 as disclosed herein. In some cases, the memory device 100 may be referred to as a memory chip, memory die, or electronic memory device. The memory device 100 may include one or more memory cells, such as memory cell 105-a and memory cell 105-b (other memory cells not labeled). Memory cell 105 may be, for example, a flash memory cell (e.g., in...). Figure 1 (as shown in the enlarged view of memory cell 105-a), DRAM memory cell, FeRAM memory cell, PCM memory cell, or another type of memory cell.

[0021] Each memory cell 105 can be programmed to store logical states representing one or more information bits. In some cases, memory cell 105 may store one information bit at a time (e.g., logical state 0 or logical state 1), for example, in a memory cell of an SLC memory block that may be referred to as an SLC memory cell. In some cases, a single memory cell 105 may store more than one information bit at a time, for example, in a memory cell of an MLC, TLC, or QLC memory block. For example, a single memory cell 105 in an MLC memory block (e.g., an MLC memory cell) may store two information bits at a time by storing one of the following four logical states: logical state 00, logical state 01, logical state 10, or logical state 11. For example, a single memory cell 105 in a TLC memory block (e.g., a TLC memory cell) may store three information bits at a time by storing one of the following eight logical states: 000, 001, 010, 011, 100, 101, 110, 111.

[0022] In some cases, the multilevel memory cell 105 (e.g., MLC memory cell, TLC memory cell, or QLC memory cell) may be physically different from the SLC cell. For example, the multilevel memory cell 105 may use different cell geometries or be manufactured using different materials. In some cases, the multilevel memory cell 105 may be physically identical or similar to the SLC cell, and other circuitry in the memory block (e.g., controller circuitry, sense amplifiers, drivers, etc.) may be configured to operate (e.g., read and write) the memory cell as an SLC cell, MLC cell, TLC cell, etc.

[0023] Different memory cell architectures can store logical states in different ways. In a FeRAM architecture, for example, each memory cell 105 may include a capacitor containing ferroelectric material for storing charges and / or polarizations representing programmable states. In a DRAM architecture, each memory cell 105 may include a capacitor containing a dielectric material (e.g., an insulator) for storing charges representing programmable states.

[0024] In a flash memory architecture, each memory cell 105 may include a transistor having a floating gate and / or dielectric material for storing charges representing logic states. For example, Figure 1An enlarged view of memory cell 105-a shows a flash memory cell containing a transistor 110 (e.g., a metal-oxide-semiconductor (MOS) transistor) for storing logic states. Transistor 110 has a control gate 115 and may include a floating gate 120 sandwiched between dielectric materials 125. Transistor 110 includes a first node 130 (e.g., a source or drain) and a second node 135 (e.g., a drain or source). Logic states can be stored in transistor 110 by placing (e.g., writing, storing) a certain number of electrons (e.g., charge) on the floating gate 120. The amount of charge to be stored on the floating gate 120 may depend on the logic state to be stored. The charge stored on the floating gate 120 can affect the threshold voltage of transistor 110, thereby affecting the amount of current that can flow through transistor 110 when transistor 110 is activated. The logic state stored in the transistor 110 can be read by applying a voltage to the control gate 115 (e.g., at the control node 140) to activate the transistor 110 and measuring (e.g., detecting, sensing) the resulting amount of current flowing between the first node 130 and the second node 135.

[0025] For example, sensing component 170 can determine whether an SLC memory cell stores logic state 0 or logic state 1 in binary form; for example, based on the presence or absence of current from the memory cell, or based on whether the current is above or below a threshold current. However, for multi-level cells, sensing component 170 can determine the logic state stored in the memory cell based on various intermediate current levels. For example, sensing component 170 can determine the logic state of a TLC cell based on eight different current levels (or current ranges) that define eight possible logic states that can be stored by a TLC cell. The spacing between such current levels can be quite small (in terms of magnitude), thus providing a lower error tolerance compared to the SLC case.

[0026] Similarly, flash SLC memory cells can be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell to store (or not store) charge representing one of two possible logic states on the floating gate. In contrast, writing to flash multilevel cells requires applying voltages at a finer granular level to more precisely control the amount of charge stored on the floating gate, thereby enabling the representation of a larger set of logic states. Therefore, multilevel cells can be more sensitive to voltage or current variations that may occur in the memory device due to temperature changes or other operating conditions.

[0027] A charge-trapping flash memory cell can operate similarly to a floating-gate flash memory cell, but instead of storing charge on the floating gate 120, the charge-trapping flash memory cell can store state-indicating charge in a dielectric material below the control gate 115. Therefore, a charge-trapping flash memory cell may or may not include the floating gate 120.

[0028] In some instances, each row of memory cells 105 may be connected to word lines 160, and each column of memory cells 105 may be connected to digital lines 165. Therefore, a memory cell 105 may be located at the intersection of word lines 160 and digital lines 165. This intersection may be referred to as the address of the memory cell. Digital lines are sometimes called bit lines. In some cases, word lines 160 and digital lines 165 may be substantially perpendicular to each other and may create an array of memory cells 105. In some cases, word lines 160 and digital lines 165 may generally be referred to as access lines or select lines.

[0029] In some cases, memory device 100 may include a three-dimensional (3D) memory array, in which multiple two-dimensional (2D) memory arrays are formed one above the other. Compared to 2D arrays, this can increase the number of memory cells that can be placed or generated on a single die or substrate, which in turn can reduce manufacturing costs, or increase the performance of the memory array, or both. Figure 1 In some instances, memory device 100 comprises a multi-level memory array. In some instances, the levels may be separated by an electrically insulating material. Each level may be aligned or positioned such that memory cells 105 are aligned (precisely, overlapping, or substantially) with each other on each level, thereby forming a memory cell stack 175. In some cases, the memory cell stack 175 may be referred to as a memory cell string, see reference... Figure 2 A more detailed discussion follows.

[0030] Access to memory cell 105 can be controlled via row decoder 145 and column decoder 150. For example, row decoder 145 receives a row address from memory controller 155 and activates the appropriate word line 160 based on the received row address. Similarly, column decoder 150 receives a column address from memory controller 155 and activates the appropriate digital line 165. Thus, a memory cell 105 can be accessed by activating one word line 160 and one digital line 165.

[0031] After access, memory cell 105 can be read or sensed by sensing component 170. For example, sensing component 170 can be configured to determine the stored logic state of memory cell 105 based on a signal generated by accessing memory cell 105. The signal may include voltage or current or both, and sensing component 170 may include a voltage-sensing amplifier, a current-sensing amplifier, or both. For example, current or voltage may be applied to memory cell 105 (using corresponding word line 160 and / or digital line 165), and the magnitude of the resulting current or voltage on digital line 165 may depend on the logic state stored by memory cell 105. For example, for flash memory cells, the amount of charge stored on the floating gate or in the insulating layer of the transistors in memory cell 105 may affect the threshold voltage of the transistors, thereby affecting the amount of current flowing through the transistors in memory cell 105 when accessing memory cell 105. Such differences in current can be used to determine the logic state stored in memory cell 105.

[0032] Sensing component 170 may include various transistors or amplifiers to detect and amplify signals (e.g., current or voltage) on digital line 165. The detected logic state of memory cell 105 may then be output via input / output block 180. In some cases, sensing component 170 may be part of column decoder 150 or row decoder 145, or sensing component 170 may be otherwise connected to or in electronic communication with column decoder 150 or row decoder 145.

[0033] Memory cell 105 can be set or written by similarly activating the associated word line 160 and digital line 165, enabling the storage of logical states (e.g., representing one or more information bits) in memory cell 105. Column decoder 150 or row decoder 145 can, for example, accept data to be written to memory cell 105 from input / output block 180. As previously discussed, in the case of flash memory (e.g., flash memory used in NAND and 3D NAND memory devices), memory cell 105 is written by storing electrons in a floating gate or insulating layer.

[0034] The memory controller 155 can control the operation (e.g., read, write, rewrite, refresh, etc.) of the memory cell 105 through various components such as the row decoder 145, column decoder 150, and sensing component 170. In some cases, one or more of the row decoder 145, column decoder 150, and sensing component 170 may co-address with the memory controller 155. The memory controller 155 can generate row and column address signals to activate the desired word line 160 and digital line 165. The memory controller 155 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0035] In some cases, the memory controller 155 can identify data to be written to a memory device 100 that includes first-type memory cells and second-type memory cells. For example, the first-type memory cells may be SLC memory cells, and the second-type memory cells may be multi-level memory cells. For example, the first-type memory cells and the second-type memory cells may be two different types of NAND memory cells.

[0036] The memory controller 155 can identify the temperature of the memory device based, for example, a signal received from a temperature sensor. The memory controller 155 can select the type of memory cell from a set of memory cell types, at least in part, based on the temperature of the memory device, wherein the set of memory cell types includes a first type and a second type. For example, the set of memory cell types may include SLC memory cells, MLC memory cells, TLC memory cells, QLC memory cells, etc. The memory controller 155 can write data to one or more memory cells of the selected type, at least in part, based on the selection of the memory cell type from the set of memory cell types. In this way, the memory controller 155 can write data to high-density, low-cost memory cells under normal operating conditions, while the memory controller 155 can write data to high-reliability memory cells under extreme operating conditions.

[0037] Figure 2 This description illustrates an example of a NAND memory circuit 200 supporting temperature-based memory management according to an embodiment of this disclosure. The NAND memory circuit 200 may be an example of a portion of a memory device (e.g., memory device 100). Although included... Figure 2 Some elements are labeled with reference numerals, while other corresponding elements are not labeled, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features.

[0038] NAND memory circuitry 200 includes a plurality of flash memory cells 205 connected in a NAND configuration (which may be, for example, referenced to...). Figure 1 The described flash memory cell). In a NAND memory configuration (referred to as NAND memory), multiple flash memory cells 205 are connected in series to form a string 210 of memory cells 205, wherein the drain of each flash memory cell 205 in the string 210 is coupled to the source of another flash memory cell 205 in the string. In some cases, flash memory cells connected in a NAND configuration to form NAND memory may be referred to as NAND memory cells.

[0039] Each string 210 of memory cells 205 may be associated with a corresponding digital line 215 shared by the memory cells 205 in the string 210. Each memory cell 205 in the string 210 may be associated with a separate word line 230 (e.g., word lines 230-a, 230-i, 230-n) such that the number of word lines 230 may be equal to the number of memory cells 205 in the string 210.

[0040] Generally, NAND flash memory can be hierarchically organized into strings 210 containing multiple memory cells 205, pages containing multiple strings 210, and blocks containing multiple pages. In some cases, NAND flash memory can be written to and read at the page-level granularity, but cannot be erased at the page-level granularity. For example, NAND flash memory can actually be erased at a higher granularity level, such as the block-level granularity. In some cases, NAND flash memory cells may need to be erased before they can be rewritten. Different memory devices may have different read / write / erase characteristics.

[0041] Each string 210 of memory cells 205 in the NAND memory circuit 200 is coupled at one end to a drain-side selected gate (SGD) transistor 220 and at the other end to a source-side selected gate (SGS) transistor 225. The SGD transistor 220 and the SGS transistor 225 can be used to couple the string 210 of memory cells 205 to bit lines 215 (e.g., bit line 215-a, bit line 215-b, or both) and / or source nodes 250 (e.g., source node 250-a, source node 250-b, or both) by applying voltages at the gate 245 of the SGD transistor 220 and / or the gate 240 of the SGS transistor 225, respectively.

[0042] During NAND memory operation, various voltage levels may be applied to the source node 250, the gate 240 of the SGS transistor 225 associated with the source node 250, the word line 230, the drain node 235 (e.g., drain node 235-a, drain node 235-b, or both), the gate 245 of the SGD transistor 220 associated with the drain node 235, and the bit line 215 to perform one or more operations (e.g., programming, erasing, or reading) on ​​at least some of the NAND memory cells in the string 210.

[0043] In some cases, during a first operation (e.g., a read operation), a positive voltage may be applied to bit line 215 connected to drain node 235, while source node 250 may be connected to ground or dummy ground (e.g., approximately 0V). For example, the voltage applied to drain node 235 may be 1V. Simultaneously, the voltage applied to gates 245 and 240 may be increased to a level higher than the threshold voltage of one or more SGS 225 associated with source node 250 and one or more SGD transistors 220 associated with drain node 235, such that the channel associated with memory string 210 is electrically connected to drain node 235 and source node 250. The channel may be an electrical path through memory cells 205 in string 210 (e.g., through transistors in memory cells 205), which may conduct current under certain operating conditions.

[0044] Simultaneously, multiple word lines 230 (e.g., in some cases all word lines 230) other than the selected word line (i.e., the word line associated with the unselected cell in string 210) can be connected to a voltage (e.g., VREAD) higher than the highest threshold voltage (VT) of the memory cell in string 210. VREAD can "turn on" all unselected memory cells in string 210, allowing each unselected memory cell to maintain high conductivity in its associated channel. In some instances, the word line 230 associated with the selected cell can be connected to a voltage target V. The target V can be selected as a value between the VT of the erased memory cell and the VT of the programmed memory cell in string 210. When the selected memory cell exhibits an erased VT (e.g., Vtarget > VT of the selected memory cell), the selected memory cell 205 can be "turned on" in response to the application of the target V, and thus allow current to flow from bit line 215 to source 250 in the channel of string 210. When the selected memory cell exhibits a programmed VT (e.g., therefore V<target < VT of the selected memory cell), the selected memory cell can be "disconnected" in response to V<target, and thus current is prevented from flowing from bit line 215 to source 250 in the channel of memory string 210. The amount of current (or its lack thereof) can be determined by reference to... Figure 1 The described sensing component 170 senses to read the information stored in the selected memory cell 205 within the string 210.

[0045] Figure 3 This describes an example of a system 300 that supports temperature-based memory management, based on examples disclosed herein. System 300 includes a memory device 305 that includes a temperature sensor 310, a controller 320, a first-type memory block 325, and a second-type memory block 330.

[0046] Sensor 310 may be a temperature sensor, voltage sensor, power sensor, or other type of sensor configured to sense temperature, voltage, power, or other operating conditions associated with memory device 305. For example, sensor 310 may be a temperature sensor configured to measure (e.g., detect, determine, identify, sample) the temperature of memory device 305. Sensor 310 may be configured to output a signal representing a temperature value (or another operating condition value) to controller 320 via communication path 315.

[0047] Memory device 305 includes a first type of memory block 325 and a second type of memory block 330. The first type of memory block 325 may contain multiple memory cells, such as referenced... Figure 1 and 2 The memory cells 105 and 205 are described. The first type of memory block 325 may be, for example, a type of memory block that is relatively robust to temperature variations and noise and provides a high level of reliability. In some cases, the memory cells of the first type of memory block 325 may each be used to store a single bit, for example, in an SLC memory cell. In some cases, the memory cells of the first type of memory block 325 may each be used to store multiple bits, for example, in a multi-level memory cell (e.g., MLC, TLC, QLC). In some cases, the memory cells of the first type of memory block 325 may be as described in the reference... Figure 2 The described NAND configuration is connected and can be referred to as a NAND memory cell.

[0048] The second type of memory block 330 may be a type of memory block that offers cost and / or density advantages relative to the first type of memory block 325, but may be less robust to temperature variations and noise. In some cases, the memory cells of the second type of memory block 330 may each store multiple bits, for example, in MLC, TLC, or QLC memory cells. In some cases, each memory cell in the second type of memory block 330 may store more bits than each memory cell in the first type of memory block 325. For example, if the first type of memory block 325 contains an SLC memory cell storing one bit, then the second type of memory block 330 may contain an MLC memory cell storing two bits, a TLC memory cell storing three bits, or a QLC memory cell storing four bits. For example, if the first type of memory block 325 contains an MLC memory cell storing two bits, then the second type of memory block 330 may contain TLC memory cells each storing three bits or QLC memory cells each storing four bits. In some cases, the memory cells of the second type of memory block 330 can be connected in a NAND configuration and can be referred to as NAND memory cells. In some cases, the first type of memory block 325 can provide less storage capacity compared to the second type of memory block 330. In some cases, there may be fewer first type of memory blocks 325 than the second type of memory block 330, or the area occupied by the first type of memory block 325 may be smaller than the area occupied by the second type of memory block 330.

[0049] In some cases, the memory cells in the first type of memory block 325 may be physically different from the memory cells in the second type of memory block 330. For example, the memory cells in the first type of memory block 325 may have different geometries or be manufactured from a different material than the memory cells in the second type of memory block 330. In some cases, the memory cells in the second type of memory block 330 may be physically the same as or similar to the memory cells in the first type of memory block 325, but may be able to store more bits due to differences in other circuitry, such as differences in control circuitry systems, sense amplifiers, etc., that may be coupled to or coupled to the memory cells in the second type of memory block 330.

[0050] In some cases, memory device 305 may be configured to use sensor 310 to sense the temperature (or other operating conditions) associated with memory device 305 and provide an indication of the sensed temperature value to controller 320 via communication path 315. Controller 320 may include control circuitry associated with accessing memory cells in memory device 305 and may be located on or within the same chip, package, or die as the first type memory block 325 and the second type memory block 330. Controller 320 may use the indication of the sensed temperature to select either the first type memory block 325 or the second type memory block 330 for write operations and cause memory device 305 to write data to the selected type of memory block. For example, if the sensed temperature is within the nominal temperature range, controller 320 may select the second type memory block 330 and write data to the second type memory block 330 to take advantage of the increased density and reduced cost associated with the second type memory block 330. If the sensed temperature is outside the nominal temperature range, indicating a higher probability of error, then the controller 320 may select a first type of memory block 325 and write data to the first type of memory block 325 to take advantage of the high reliability associated with the first type of memory block 325.

[0051] In some cases, after data is written to the first type of memory block 325, the controller 320 may subsequently move the data to the second type of memory block 330 when the sensor 310 detects that the temperature of the memory device 305 has returned to the nominal temperature range. In this way, the first type of memory block 325 can act as a data cache or buffer during periods of extreme operating temperature to ensure data integrity, and can be cleared (e.g., erased) after the data has been moved to a higher-density memory block. (See reference...) Figure 4 Additional details regarding the operation of system 300 are discussed. While the discussion herein primarily concerns the case of a memory device containing two types of memory blocks, in some cases, the memory device may contain a set of three or more types of memory blocks (e.g., SLC, MLC, TLC, QLC), and the type of memory block may be selected from the set of memory block types based on temperature.

[0052] Figure 4 A conceptual flowchart 400 illustrating temperature-based memory management is provided, based on examples disclosed herein. Operations of flowchart 400 may be performed by a memory device (e.g., memory device 100) or by a system containing memory devices (e.g., system 300). In some cases, some operations shown in flowchart 400 may be omitted or rearranged. While flowchart 400 primarily discusses temperature-based memory management, similar methods can be used to manage memory based on another operating condition.

[0053] At 405, the memory device can identify or determine that data exists in a memory cell to be written to the memory device. For example, the memory device can receive a write command (e.g., from a host device coupled to the memory device) to write data to the memory cell.

[0054] At 410, the memory device can identify its temperature based on the signal received from the temperature sensor, and can determine whether the temperature of the memory device is within the lower threshold (T). 低 ) and upper limit threshold (T) 高 Between, such as the temperature range T 低 Temperature <T 高 Expression. In some cases, T 低 With T 高 The temperature range between these ranges can be considered a relatively low-risk operating range, or nominal operating range, where the likelihood of temperature-induced errors is relatively small. Temperatures outside this range can be associated with a higher risk of temperature-induced errors, specifically for memory cells that are more sensitive to harsh operating conditions, such as some multi-level cells (MLC, TLC, QLC, etc.). In some cases, the memory device may identify (e.g., sample, detect, monitor) the temperature of the memory device in response to receiving a write command, enabling the memory device to select the type of memory block to which data will be written. In other cases, the memory device may identify its temperature in response to other stimuli or criteria, such as at periodic intervals or through substantially continuous temperature monitoring.

[0055] In some cases, if the memory device determines at 410 that the temperature is within the nominal operating range, then at 415, the memory device may select a second type of memory block, such as a reference. Figure 3 The second type of memory block 330 is described, and data is written to the second type of memory block. The second type of memory block may be, for example, a multi-level memory block, such as an MLC, TLC, or QLC memory block. In some cases, the second memory type contains multi-level memory cells organized in a NAND configuration, such as NAND memory.

[0056] If the memory device determines at 410 that the temperature is outside the nominal operating range (e.g., extremely hot or extremely cold), then at 420, the memory device can select a first type of memory block, such as referenced... Figure 3The first type of memory block 325 is described, and it is determined whether the first type of memory block meets a threshold data amount. For example, the memory device may determine whether a certain percentage or number of memory blocks of the first type are in use (e.g., contain data) and therefore can be used to store data. The first type of memory block may be a type of memory that is less prone to errors under harsh operating conditions compared to the second type of memory block, such as SLC memory blocks. In some cases, the first memory type contains memory cells organized in a NAND configuration, such as NAND memory.

[0057] If the memory device determines at 420 that a first-type memory block meets (e.g., meets or exceeds) a threshold data amount, then at 425, the memory device may transmit a message (e.g., to the host device) indicating that the first-type memory block meets the threshold data amount. For example, the message may indicate that the first-type memory block is full or nearly full (e.g., the available capacity of the first-type memory block is below the threshold capacity, or memory cells in the first-type memory block are not available for storing additional data, or the number of first-type memory cells available for storing additional data is below the threshold). In some cases, the host device may respond to the message by, for example, reducing the amount of data written to memory, instructing the memory device to store data elsewhere, reducing the clock speed of the memory device, or entering a read-only mode until the temperature drops back to the nominal temperature range. In some cases, the host device may configure the memory device to have one or more threshold data amounts, such that the memory device can send error messages indicating when the use of the first-type memory block has met each configured threshold data amount, thereby providing a progressive indication of the remaining capacity in the first-type memory block.

[0058] In some cases, the memory device may send at 425 one of at least two types of messages: a first type message indicating that a first type of memory block is almost full (as described above), and a second type message indicating that a first type of memory block is full (also as described above), depending on whether the amount of data stored in the first type of memory block satisfies (or the amount of remaining capacity of the first type of memory block is less than) a first threshold corresponding to the first type of message or a second threshold corresponding to the second type of message.

[0059] If the memory device determines at 420 that a memory block of the first type does not meet the threshold data amount, then at 430, the memory device may write data to the memory cells in the memory block of the first type. In some cases, if the memory device determines at 420 that a memory block of the first type meets the threshold data amount but still has blocks available for storage (e.g., if the memory block of the first type is not completely full), then in addition to sending an error message to the host device, the memory device may also write data to the memory cells in the memory block of the first type.

[0060] After writing data to the first type of memory block at 430, the memory device may subsequently identify or monitor the temperature of the memory device at 435. If the memory device determines that the temperature of the memory device has returned to the nominal operating range, then at 440, the memory device may move some or all of the data stored in the first type of memory block to a second type of memory block. In some cases, the memory device may then erase some or all of the contents of the first type of memory block to free the first type of memory block for subsequent data storage.

[0061] Figure 5 A simplified diagram of a system 500 supporting temperature-based memory management according to an example of this disclosure is shown. System 500 may include a device 505, which may include a processor 510, a system memory controller 515, and a memory device 520. For example, memory device 520 may be an instance of memory device 100. Processor 510 may be configured to coordinate operation with system memory controller 515 via bus 525. System memory controller 515 may be configured to operate together with processor 510 and memory device 520 via buses 525 and 530.

[0062] In some instances, memory device 520 may include one or more memory arrays 540, each of which may be coupled to a corresponding local memory controller 545. For example, in some cases, memory array 540 may be an array of NAND memory cells. In some cases, one or more memory arrays 540 may include memory blocks of a first type, and one or more memory arrays may include memory blocks of a second type. For example, memory array 540-a may include SLC memory cells, and memory array 540-n may include MLC, TLC, or QLC memory cells. In some cases, refer to Figure 4 The described operations may be performed by the local memory controller 545 and / or the system memory controller 515. In some cases, the device 505 may be coupled to an external host device 550, such as an external memory controller.

[0063] Local memory controller 545 can be configured to control the operation of memory array 540. Furthermore, local memory controller 545 can be configured to communicate with system memory controller 515 (e.g., to receive and transmit data and / or commands). Local memory controller 545 can support system memory controller 515 in controlling the operation of memory device 520 as described herein. In some cases, memory device 520 does not include system memory controller 515 and local memory controller 545, and host device 550 can perform the various functions described herein. Therefore, local memory controller 545 can be configured to communicate with system memory controller 515, with other local memory controllers 545, or directly with host device 550.

[0064] Figure 6 A block diagram 600 illustrates a memory device 605 supporting temperature-based memory management according to an example disclosed herein. The memory device 605 may be as described in the references... Figure 1 Examples of aspects of the described memory device. Memory device 605 may include an identification component 610, a command component 615, a type selection component 620, a memory access component 625, and a sensor component 630. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses or other conductive connections).

[0065] The identification component 610 can identify data to be written to a memory device comprising memory cells of the first type and memory cells of the second type. In some instances, after data has been written to one or more memory cells of the first type, the identification component 610 can identify second data to be written to the memory device.

[0066] Sensor assembly 630 can identify the temperature of the memory device. In some instances, sensor assembly 630 can determine that the temperature of the memory device is outside a temperature range. In some instances, sensor assembly 630 can identify a second temperature of the memory device. In some instances, sensor assembly 630 can determine that the second temperature of the memory device is within a temperature range.

[0067] In some instances, after data is written to one or more memory cells of the first type, sensor component 630 can identify a second temperature of the memory device. In some instances, sensor component 630 can determine that the second temperature of the memory device is within a temperature range. In some instances, sensor component 630 can determine that the temperature is below a first threshold. In some instances, sensor component 630 can determine that the temperature is above a second threshold.

[0068] In some instances, sensor component 630 may determine, based on receiving a write command, that a first value of the operating conditions of the memory device is outside the range associated with the operating conditions. In some instances, after data is written to one or more memory cells of the first type, sensor component 630 may determine that a second value of the operating conditions of the memory device is within the range.

[0069] In some instances, sensor assembly 630 may determine, based on receiving a second write command, that a third value of the operating conditions of the memory device is within range.

[0070] The type selection component 620 can select the type of memory cell from a set of memory cell types, including a first type and a second type, based on the temperature of the memory device. In some cases, the memory cells of the first type comprise NAND memory cells each configured to store a single corresponding bit. In some cases, the memory cells of the second type comprise NAND memory cells each configured to store a corresponding set of bits.

[0071] In some instances, the type selection component 620 may select a first type of memory cell based on a temperature outside a temperature range. In some instances, the type selection component 620 may select a second type of memory cell based on a second temperature within a temperature range.

[0072] In some instances, the type selection component 620 may select a first type of memory cell based on a temperature below a first threshold. In some instances, the type selection component 620 may select a second type of memory cell based on a temperature above a second threshold.

[0073] Command component 615 can receive write commands for data at a memory device containing memory cells of the first type and memory cells of the second type. In some instances, command component 615 can receive a second write command for second data at the memory device.

[0074] Memory access component 625 can write data to one or more memory cells of a selected type based on selecting the type of memory cell from a set of memory cell types. In some instances, memory access component 625 can write data to one or more memory cells of a first type based on determining that a first value of an operating condition is outside a range. In some instances, memory access component 625 can write data to one or more memory cells of a second type based on determining that a second value of an operating condition is within a range.

[0075] In some instances, memory access component 625 may write second data to one or more memory cells of the second type. In some instances, memory access component 625 may write data to one or more memory cells of the second type based on a second temperature being within a temperature range. In some instances, memory access component 625 may write second data to one or more memory cells of the second type based on a third value determining operating conditions being within a range.

[0076] In some instances, after data is written to one or more memory cells of the second type, memory access component 625 may erase at least a portion of the data from one or more memory cells of the first type.

[0077] In some instances, memory access component 625 may determine that the amount of data stored in the memory cells of the first type meets a threshold data amount. In some instances, memory access component 625 may indicate to the host device that the amount of data stored in the memory cells of the first type meets a threshold data amount.

[0078] In some instances, memory access component 625 may determine that the second amount of data stored in a memory cell of the first type satisfies a second threshold data amount, which is less than the second threshold data amount. In some instances, memory access component 625 may indicate to a host device that the second amount of data stored in a memory cell of the first type satisfies the second threshold data amount.

[0079] In some instances, the memory access component 625 may indicate the temperature characteristic to the host device based on determining that the amount of data stored in the memory cell of the first type meets a threshold data amount.

[0080] In some instances, memory access component 625 may determine that the available capacity of a first type of memory cell is below a threshold capacity. In some instances, memory access component 625 may indicate to the host device that the available capacity of a first type of memory cell is below a threshold capacity.

[0081] Figure 7 The illustrations present flowcharts illustrating one or more methods 700 supporting temperature-based memory management, based on examples disclosed herein. Operation of method 700 may be implemented by a memory device or its components as described herein. For example, operation of method 700 may be performed as described in the references... Figure 1 and 6 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0082] At 705, the memory device can identify data to be written to the memory device, wherein the memory device includes memory cells of a first type and memory cells of a second type. The operation of 705 can be performed according to the methods described herein. In some instances, aspects of the operation of 705 may be as described in references... Figure 6 The described identification component is executed.

[0083] At 710, the memory device can detect the temperature of the memory device. Operation of 710 can be performed according to the methods described herein. In some instances, aspects of the operation of 710 can be determined by reference to [reference needed]. Figure 6 The described sensor components are executed.

[0084] At 715, the memory device can select the type of memory cell from a set of memory cell types based on the temperature of the memory device, the set of memory cell types including a first type and a second type. The operation of 715 can be performed according to the method described herein. In some instances, aspects of the operation of 715 can be derived from, as referenced... Figure 6 The described type selection component is executed.

[0085] At 720, the memory device may write data to one or more memory cells of the selected type based on a set of memory cell types. The operation of 720 may be performed according to the methods described herein. In some instances, aspects of the operation of 720 may be as described in the references... Figure 6 The described memory access component is executed.

[0086] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: identifying data to be written to a memory device comprising memory cells of a first type and memory cells of a second type; identifying the temperature of the memory device; selecting a type of memory cell from a set of memory cell types based on the temperature of the memory device, the set of memory cell types including the first type and the second type; and writing data to one or more memory cells of the selected type based on the selection of the memory cell type from the set of memory cell types.

[0087] Method 700 and some instances of the device described herein may further include operations, features, components, or instructions for receiving write commands for data, wherein the temperature may be determined based on the received write command.

[0088] In some instances of method 700 and the device described herein, selecting the type of memory cell may include operations, features, components, or instructions for determining that the temperature of the memory device is outside a temperature range, and selecting a first type of memory cell based on the temperature being outside the temperature range.

[0089] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: identifying second data to be written to the memory device after writing data to one or more memory cells of the first type; identifying a second temperature of the memory device; determining that the second temperature of the memory device is within a temperature range; selecting memory cells of the second type based on the second temperature being within a temperature range; and writing the second data to one or more memory cells of the second type.

[0090] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: identifying a second temperature of the memory device after writing data to one or more memory cells of the first type; determining that the second temperature of the memory device is within a temperature range; and writing data to one or more memory cells of the second type based on the second temperature being within a temperature range.

[0091] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for erasing at least a portion of the data from one or more memory cells of the first type after writing data to one or more memory cells of the second type.

[0092] In some instances of method 700 and the device described herein, selecting the type of memory cell may include operations, features, components, or instructions for determining that the temperature may be below a first threshold and selecting a first type of memory cell based on the temperature being below the first threshold.

[0093] In some instances of method 700 and the device described herein, selecting the type of memory cell may include operations, features, components, or instructions for determining that the temperature may be higher than a second threshold and selecting a second type of memory cell based on the temperature being higher than the second threshold.

[0094] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: determining that the amount of data stored in the memory cells of the first type meets a threshold data amount, and instructing the host device that the amount of data stored in the memory cells of the first type meets the threshold data amount.

[0095] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: determining that a second amount of data stored in a memory cell of the first type satisfies a second threshold data amount, the threshold data amount being less than the second threshold data amount, and instructing a host device that the second amount of data stored in a memory cell of the first type satisfies the second threshold data amount.

[0096] Method 700 and some examples of the devices described herein may further include the characteristic of indicatively indicating a temperature to a host device based on determining that the amount of data stored in a memory cell of the first type meets a threshold data amount.

[0097] In some instances of method 700 and the device described herein, the first type of memory cell includes NAND memory cells each configured to store a single corresponding bit, and the second type of memory cell includes NAND memory cells each configured to store a set of corresponding bits.

[0098] Figure 8 The illustrations present flowcharts illustrating one or more methods 800 supporting temperature-based memory management, based on examples disclosed herein. Operation of method 800 may be implemented by a memory device or its components as described herein. For example, operation of method 800 may be performed as described in the references... Figure 1 and 6 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0099] At point 805, the memory device may receive a write command for data at a memory device comprising memory cells of the first type and memory cells of the second type. The operation of point 805 may be performed according to the method described herein. In some instances, aspects of the operation of point 805 may be as described in reference... Figure 6 The described command component is executed.

[0100] At 810, the memory device may determine, based on the receipt of a write command, that a first value of the operating conditions of the memory device is outside the range associated with the operating conditions. The operation of 810 may be performed according to the method described herein. In some instances, aspects of the operation of 810 may be determined by reference to... Figure 6 The described sensor components are executed.

[0101] At 815, the memory device can write data to one or more memory cells of the first type based on the determination that a first value of an operating condition is outside a range. The operation of 815 can be performed according to the method described herein. In some instances, aspects of the operation of 815 can be as described in reference... Figure 6 The described memory access component is executed.

[0102] At 820, after writing data to one or more memory cells of the first type, the memory device can determine that a second value of the operating conditions of the memory device is within a range. The operation of 820 can be performed according to the method described herein. In some instances, aspects of the operation of 820 can be derived from, as referenced... Figure 6 The described sensor components are executed.

[0103] At 825, the memory device can write data to one or more memory cells of the second type based on a second value determining that the operating conditions are within a range. The operation of 825 can be performed according to the method described herein. In some instances, aspects of the operation of 825 can be as described in reference... Figure 6 The described memory access component is executed.

[0104] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a write command for data at a memory device comprising memory cells of a first type and memory cells of a second type; determining, based on receiving the write command, that a first value of an operating condition of the memory device is outside a range associated with the operating condition; writing data to one or more memory cells of the first type based on determining that the first value of the operating condition is outside the range; determining, after writing data to one or more memory cells of the first type, that a second value of the operating condition of the memory device is within the range; and writing data to one or more memory cells of the second type based on determining that the second value of the operating condition is within the range.

[0105] Method 800 and some instances of the device described herein may further include operations, features, components, or instructions for: receiving a second write command for second data at a memory device, determining, based on receiving the second write command, that a third value of the operating conditions of the memory device is within range, and writing the second data to one or more memory cells of a second type based on determining that the third value of the operating conditions is within range.

[0106] Method 800 and some examples of the devices described herein may further include operations, features, components, or instructions for determining that the available capacity of a first type of memory cell may be lower than a threshold capacity, and indicating to a host device that the available capacity of the first type of memory cell may be lower than the threshold capacity.

[0107] It should be noted that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0108] Describe a device. The device may include a first type of memory cell, a second type of memory cell, a temperature sensor, and a controller coupled to the first type of memory cell, the second type of memory cell, and the temperature sensor, wherein the controller is operable to cause the device to: identify data to be written to the memory device; determine that the temperature indicated by the temperature sensor is outside a temperature range; and write the data to one or more first type of memory cells based on the temperature being outside the temperature range.

[0109] Some instances may further include write commands for receiving data, where data identification and temperature determination may be based on the received write command and may be outside a temperature range.

[0110] Some examples may further include: after writing data to one or more memory cells of the first type, identifying second data to be written to the memory device; determining that a second temperature indicated by a temperature sensor is within a temperature range; and writing the second data to one or more memory cells of the second type based on determining that the second temperature is within a temperature range.

[0111] Some examples may further include: after writing data to one or more memory cells of the first type, determining that a second temperature indicated by a temperature sensor is within a temperature range; and after determining that the second temperature is within a temperature range, writing data to one or more memory cells of the second type.

[0112] Some examples may further include: determining whether the number of first-type memory cells available for storing additional data may be below a threshold, and transmitting an indication to the host device that the number of first-type memory cells available for storing additional data may be below the threshold.

[0113] Some examples may further include: determining whether a memory cell of the first type can be used to store additional data, and transmitting an indication of whether a memory cell of the first type can be used to store additional data to a host device.

[0114] In some instances, a first type of memory cell may be configured to store a first amount of information per memory cell, and a second type of memory cell may be configured to store a second amount of information per memory cell, the second amount being greater than the first amount.

[0115] In some instances, the first type of memory cell comprises NAND memory cells each configured to store a single corresponding bit, and the second type of memory cell comprises NAND memory cells each configured to store a set of corresponding bits.

[0116] In some instances, a temperature sensor, a first-type memory cell, and a second-type memory cell may be included in the memory device.

[0117] In some instances, the controller may be contained within a memory device.

[0118] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0119] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" implies a connection to approximately 0V.

[0120] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, one or more intermediate components, such as switches or transistors, may be used to interrupt the signal flow between connected components for a period of time.

[0121] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between components via a conductive path, and in which a signal can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0122] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are separated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0123] As used in this paper, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to obtain the advantage of the feature.

[0124] The devices containing memory devices discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0125] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "disconnected" or "deactivated".

[0126] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0127] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0128] The various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0129] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed so that portions of the functionality are implemented in different physical locations. Moreover, as used herein, the word "or" used in the list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0130] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory device, comprising: Identify data to be written to the memory device comprising memory cells of a first type and memory cells of a second type; Identify the temperature of the memory device; It is determined that the temperature of the memory device is outside a temperature range; The memory cell of the first type is selected to store the data, at least in part, based on the fact that the temperature of the memory device is outside the temperature range. The data is written to one or more memory cells of the first type, at least in part, based on the selection of the first type; After the data is written to the one or more memory cells of the first type, a second temperature of the memory device is identified; Determining the second temperature of the memory device within the temperature range; and The data is written to one or more memory cells of the second type, at least in part, based on the second temperature within the temperature range.

2. The method according to claim 1, further comprising: A write command is received for the data, wherein the temperature is identified at least in part based on the receipt of the write command.

3. The method according to claim 1, further comprising: After the data is written to one or more memory cells of the second type, at least a portion of the data is erased from one or more memory cells of the first type.

4. The method according to claim 1, wherein: The memory cells of the first type include NAND memory cells each configured to store a single corresponding bit; and The memory cells of the second type include NAND memory cells each configured to store a plurality of corresponding bits.

5. A method for operating a memory device, comprising: Identify data to be written to the memory device comprising memory cells of a first type and memory cells of a second type; Identify the temperature of the memory device; It is determined that the temperature of the memory device is outside a temperature range; The memory cell of the first type is selected to store the data, at least in part, based on the fact that the temperature of the memory device is outside the temperature range. The data is written to one or more memory cells of the first type, at least in part, based on the selection of the first type; After the data is written to one or more of the memory cells of the first type, second data to be written to the memory device is identified; Identify a second temperature of the memory device; The second temperature of the memory device is determined to be within the temperature range; The memory cell of the second type is selected at least in part based on the second temperature within the temperature range; as well as The second data is written into one or more of the memory cells of the second type.

6. A method for operating a memory device, comprising: Identify data to be written to the memory device comprising memory cells of a first type and memory cells of a second type; Identify the temperature of the memory device; It is determined that the temperature is below a first threshold. The data is stored in a memory cell of the first type from a set of memory cell types, at least in part based on the temperature being below the first threshold. as well as The data is written to one or more memory cells of the first type, at least in part, based on selecting the first type from the group of memory cell types.

7. A method for operating a memory device, comprising: Identify data to be written to the memory device comprising memory cells of a first type and memory cells of a second type; Identify the temperature of the memory device; It is determined that the temperature is higher than the second threshold. The data is stored in a memory cell of the second type from a set of memory cell types, at least in part based on the temperature being higher than the second threshold. as well as The data is written to one or more memory cells of the first type, at least in part, based on selecting the first type from the group of memory cell types.

8. A method for operating a memory device, comprising: Identify data to be written to the memory device comprising memory cells of a first type and memory cells of a second type; Identify the temperature of the memory device; The type of memory cell is selected from a set of memory cell types, including the first type and the second type, based at least in part on the temperature of the memory device. The data is written to one or more memory cells of the selected type, at least in part, based on the selection of the type of memory cell from the set of memory cell types. Determine that the amount of data stored in the memory unit of the first type meets the threshold data amount; and The host device is instructed that the amount of data stored in the memory cell of the first type meets the threshold data amount.

9. The method of claim 8, further comprising: The second amount of data stored in the memory cell of the first type is determined to satisfy a second threshold data amount, wherein the threshold data amount is less than the second threshold data amount; as well as The host device is instructed that the amount of the second data stored in the memory cell of the first type meets the second threshold data amount.

10. The method of claim 8, further comprising: The characteristic of indicating the temperature to the host device is based at least in part on determining that the amount of data stored in the memory cell of the first type meets the threshold data amount.

11. A memory device comprising: First type of memory unit; Second type of memory unit; Temperature sensor; as well as A controller, coupled to the memory cell of the first type, the memory cell of the second type, and the temperature sensor, wherein the controller is operable to cause the memory device to: Identify the data to be written to the memory device; The temperature indicated by the temperature sensor is determined to be outside the temperature range; The data is written to one or more memory cells of the first type, at least in part, based on the temperature being outside the temperature range. After the data is written to one or more memory cells of the first type, a second temperature indicated by the temperature sensor is determined to be within the temperature range; as well as After determining the second temperature within the temperature range, the data is written to one or more memory cells of the second type.

12. The memory device of claim 11, wherein the controller is further operable to cause the memory device to: A write command is received for the data, wherein identifying the data and determining that the temperature is outside the temperature range is at least in part based on receiving the write command.

13. The memory device according to claim 11, wherein: The memory cells of the first type are configured to store a first amount of information per memory cell; and The memory cells of the second type are configured to store a second amount of information per memory cell, the second amount being greater than the first amount.

14. The memory device according to claim 11, wherein: The memory cells of the first type include NAND memory cells each configured to store a single corresponding bit; and The memory cells of the second type include NAND memory cells each configured to store a plurality of corresponding bits.

15. The memory device of claim 11, wherein the temperature sensor, the memory cell of the first type, and the memory cell of the second type are included in the memory device.

16. The memory device of claim 11, wherein the controller is included in the memory device.

17. A memory device comprising: First type of memory unit; Second type of memory unit; Temperature sensor; as well as A controller, coupled to the memory cell of the first type, the memory cell of the second type, and the temperature sensor, wherein the controller is operable to cause the memory device to: Identify the data to be written to the memory device; The temperature indicated by the temperature sensor is determined to be outside the temperature range; The data is written to one or more memory cells of the first type, at least in part, based on the temperature being outside the temperature range. After the data is written to one or more memory cells of the first type, second data to be written to the memory device is identified; The second temperature indicated by the temperature sensor is determined to be within the temperature range; as well as The second data is written to one or more memory cells of the second type based on the determination of the second temperature within the temperature range.

18. A memory device comprising: First type of memory unit; Second type of memory unit; Temperature sensor; as well as A controller, coupled to the memory cell of the first type, the memory cell of the second type, and the temperature sensor, wherein the controller is operable to cause the memory device to: Identify the data to be written to the memory device; The temperature indicated by the temperature sensor is determined to be outside the temperature range; The data is written to one or more memory cells of the first type, at least in part, based on the temperature being outside the temperature range. Determine whether the number of memory cells of the first type that can be used to store additional data is below a threshold; as well as An indication is transmitted to the host device that the number of the first type of memory cells capable of storing additional data is below the threshold.

19. A memory device comprising: First type of memory unit; Second type of memory unit; Temperature sensor; as well as A controller, coupled to the memory cell of the first type, the memory cell of the second type, and the temperature sensor, wherein the controller is operable to cause the memory device to: Identify the data to be written to the memory device; The temperature indicated by the temperature sensor is determined to be outside the temperature range; The data is written to one or more memory cells of the first type, at least in part, based on the temperature being outside the temperature range. It was determined that the memory unit of the first type could not be used to store additional data; as well as The instruction that the memory unit of the first type cannot be used to store additional data is transmitted to the host device.

20. A method for operating a memory device, comprising: A write command for data is received at the memory device comprising memory cells of the first type and memory cells of the second type; The first value of the operating conditions of the memory device is determined to be outside the range associated with the operating conditions, at least in part based on receiving the write command; The data is written to one or more memory cells of the first type, at least in part, based on the fact that the first value determining the operating condition is outside the range. After the data is written to the one or more memory cells of the first type, a second value of the operating condition of the memory device is determined to be within the range; The data is written to one or more memory cells of the second type, at least in part, based on the second value determining the operating conditions being within the range; A second write command for second data is received at the memory device; The third value of the operating conditions of the memory device is determined to be within the range, at least in part based on receiving the second write command; as well as The second data is written to one or more memory cells of the second type, at least in part, based on the third value determining the operating conditions being within the range.

21. The method of claim 20, further comprising: It is determined that the available capacity of the memory cell of the first type is lower than the threshold capacity; as well as Indicate to the host device that the available capacity of the memory cell of the first type is lower than the threshold capacity.

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