Display substrate and display device

Abstract

The present disclosure relates to a display substrate and a display device. The display substrate includes: a base substrate, including a display area and a non-display area located outside the display area and including a fan-out area; a signal line layer, arranged on the base substrate, and including a plurality of signal lines located in the fan-out area; a first metal layer, arranged on a side of the signal line layer away from the base substrate, and including a first power line located in the non-display area; a first electrode layer, located on a side of the first metal layer away from the base substrate, including a first electrode portion, the orthographic projection of the first electrode portion on the base substrate at least partially overlaps with the orthographic projection of the first power line, and is electrically connected to the first power line; and an organic insulating layer, located between the first metal layer and the first electrode layer, and having a groove located in the non-display area, the edge of the groove at least partially overlaps in a first overlap area between the orthographic projection of the base substrate and the orthographic projection of the fan-out area, and at least part of the first overlap area does not overlap with the orthographic projection of the first electrode portion on the base substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Flexible display panels (Flexible Display Panel) with organic light-emitting diodes (OLED) as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream direction of the current OLED industry. After the circuit and light-emitting devices are formed on the substrate, the chemical vapor deposition (CVD) process is used for packaging to protect the light-emitting devices and ensure that the light-emitting devices and other structures inside the panel do not undergo oxidation reactions with the outside world. Summary of the invention

[0003] In one aspect of the present disclosure, a display substrate is provided, comprising: a base substrate, comprising a display area and a non-display area located at the periphery of the display area, the non-display area comprising a fan-out area; a signal line layer, arranged on the base substrate, and comprising a plurality of signal lines located in the fan-out area; a first metal layer, arranged on a side of the signal line layer away from the base substrate, and comprising a first power line located in the non-display area; a first electrode layer, located on a side of the first metal layer away from the base substrate, and comprising a first electrode portion, an orthographic projection of the first electrode portion on the base substrate at least partially overlaps with an orthographic projection of the first power line on the base substrate, and the first electrode portion is electrically connected to the first power line; and an organic insulating layer, located between the first metal layer and the first electrode layer, and having a groove located in the non-display area, wherein an edge of the organic insulating layer at the groove at least partially overlaps between the orthographic projection of the base substrate and the orthographic projection of the fan-out area on the base substrate, and overlaps in a first overlapping area, and at least a portion of the first overlapping area does not overlap with the orthographic projection of the first electrode portion on the base substrate.

[0004] In some embodiments, the organic insulating layer is in direct contact with the first electrode layer.

[0005] In some embodiments, the display substrate also includes: a second metal layer located on a side of the first metal layer away from the base substrate, wherein the organic insulating layer includes: a first organic insulating layer located between the first metal layer and the second metal layer; and a second organic insulating layer located between the second metal layer and the first electrode layer, wherein the groove includes a second groove portion located in the second organic insulating layer.

[0006] In some embodiments, the display substrate also includes: a second metal layer located on a side of the first metal layer away from the base substrate, wherein the organic insulating layer includes: a first organic insulating layer located between the first metal layer and the second metal layer; and a second organic insulating layer located between the second metal layer and the first electrode layer, wherein the groove includes a first groove portion located in the first organic insulating layer and a second groove portion located in the second organic insulating layer.

[0007] In some embodiments, the display substrate further includes: a second metal layer located on a side of the first metal layer away from the base substrate, wherein the organic insulating layer includes: a first organic insulating layer located between the first metal layer and the second metal layer; and a second organic insulating layer located between the second metal layer and the first electrode layer, wherein the groove includes a first groove portion located in the first organic insulating layer, and the second organic insulating layer covers the upper side of the first groove portion.

[0008] In some embodiments, there are a plurality of grooves, and the second metal layer includes a second metal portion, and the second metal portion is electrically connected to the first power line and the first electrode portion through at least a portion of the grooves.

[0009] In some embodiments, the first electrode portion is located in the non-display area and at least partially surrounds the display area.

[0010] In some embodiments, the display area includes: a first boundary, a second boundary, a third boundary and a fourth boundary, the first boundary and the third boundary are arranged oppositely, the second boundary and the fourth boundary are arranged oppositely, the non-display area includes a first peripheral area located outside the first boundary, a second peripheral area located outside the second boundary, a third peripheral area located outside the third boundary and a fourth peripheral area located outside the fourth boundary, and the fan-out area is located in the fourth peripheral area, wherein the first electrode portion includes: a first part, which is continuously arranged in the first peripheral area, the second peripheral area and the third peripheral area; two second parts, which are located in the fourth peripheral area and are respectively connected to the first parts located in the first peripheral area and the third peripheral area, and extend in a direction parallel to the fourth boundary; two third parts, which are located in the fourth peripheral area and whose orthographic projection on the substrate overlaps with the fan-out area; two fourth parts, which are located in the fourth peripheral area, and the two ends of each of the two fourth parts are respectively connected to one of the two third parts and one of the two second parts; and a fifth part, which is located in the fourth peripheral area and connected between the two third parts and at least partially overlaps with the first power line.

[0011] In some embodiments, the width of each second portion in a direction perpendicular to the fourth boundary, the width of the fifth portion in a direction perpendicular to the fourth boundary, and the width of each fourth portion in a direction perpendicular to its own extension direction are all smaller than the width of each first portion in a direction perpendicular to its own extension direction, and are all larger than the width of each third portion in a direction perpendicular to the fourth boundary.

[0012] In some embodiments, an extending direction of each fourth portion forms an angle of 35 to 55 degrees with the fourth boundary.

[0013] In some embodiments, the fan-out region includes two fan-out sub-regions, the two fan-out sub-regions are symmetrical with respect to a symmetry axis perpendicular to the fourth boundary, the first electrode portions are symmetrical with respect to the symmetry axis, and the fifth portion is located between the two fan-out sub-regions.

[0014] In some embodiments, the first power line includes: a sixth portion, which is continuously arranged in the first peripheral area, the second peripheral area and the third peripheral area; two seventh portions, which are located in the fourth peripheral area and are respectively connected to the sixth portions located in the first peripheral area and the third peripheral area, and extend in a direction parallel to the fourth boundary; and an eighth portion, which is located in the fourth peripheral area and is located between the two seventh portions, wherein the orthographic projection of the sixth portion on the substrate substrate overlaps with and is electrically connected to the orthographic projection of the first portion on the substrate substrate, the orthographic projections of the two seventh portions on the substrate substrate overlap with and are electrically connected to the orthographic projections of the two second portions on the substrate substrate, respectively, and the orthographic projection of the eighth portion on the substrate substrate overlaps with the fifth portion and the fan-out area portion, and is electrically connected to the fifth portion.

[0015] In some embodiments, the sixth portion and the two seventh portions are symmetrical to each other with respect to a symmetry axis perpendicular to the fourth boundary, and the eighth portion is symmetrical to each other with respect to the symmetry axis and is T-shaped.

[0016] In some embodiments, the first metal layer further includes a second power line located in the fourth peripheral region, wherein an orthographic projection of the second power line on the substrate partially overlaps with the fan-out region and does not overlap with an orthographic projection of the first power line on the substrate.

[0017] In some embodiments, the signal line layer includes: a first signal line layer, which is arranged on the substrate and includes multiple first signal lines among the multiple signal lines; and a second signal line layer, which is arranged on a side of the first signal line layer away from the substrate and includes multiple second signal lines among the multiple signal lines, at least part of the multiple second signal lines extend in parallel with at least part of the multiple first signal lines and are arranged alternately, wherein, in a direction parallel to the substrate and perpendicular to the extension direction of the multiple first signal lines or the extension direction of the multiple second signal lines, the region between the multiple first signal lines and adjacent first signal lines and second signal lines among the multiple second signal lines is a spacing region, and the groove at least partially overlaps with the edge of the orthographic projection of the substrate and the spacing region between the orthographic projection of the substrate.

[0018] In some embodiments, the display substrate also includes: a display sub-pixel having a thin film transistor, a capacitor and an anode, the thin film transistor including a gate, a source and a drain, the capacitor including a first electrode plate and a second electrode plate, wherein the gate and the first electrode plate are in the same layer and made of the same material as the multiple first signal lines, the second electrode plate is in the same layer and made of the same material as the multiple second signal lines, and / or the source and the drain are part of the first metal layer, and / or the anode is part of the first electrode layer.

[0019] In some embodiments, the display substrate also includes: a second metal layer located on a side of the first metal layer away from the base substrate; and a connecting electrode located between the drain and the anode and electrically connected to the drain and the anode respectively, wherein the connecting electrode is part of the second metal layer.

[0020] In some embodiments, the display substrate further includes: an encapsulation layer, located on a side of the first electrode layer away from the base substrate, covering the display area and a portion of the non-display area.

[0021] In another aspect of the present disclosure, a display device is provided, comprising the aforementioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0023] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0024] Figure 1 is a schematic diagram of a hierarchical structure of an embodiment of a display substrate according to the present disclosure;

[0025] Figure 2Ais a schematic diagram of the partitions of a base substrate according to an embodiment of a display substrate of the present disclosure;

[0026] Figure 2B is a schematic diagram of a hierarchical structure corresponding to a display sub-pixel in an embodiment of a display substrate according to the present disclosure;

[0027] Figure 3A is a schematic layout diagram of an embodiment of a display substrate according to the present disclosure;

[0028] Figure 3B is a partial schematic diagram of a first electrode layer relative to a display area according to an embodiment of a display substrate of the present disclosure;

[0029] Figure 3C is a partial schematic diagram of a first power line relative to a display area in an embodiment of a display substrate according to the present disclosure;

[0030] Figure 4A-4C They are Figure 3A Schematic diagram of the hierarchical structure of the middle positions B1, B2 and B3 from the perspective along the groove extension direction;

[0031] Figure 4D yes Figure 3A A schematic diagram of the layout of the first electrode layer, the second organic insulating layer, the first organic insulating layer and the signal line layer at position B;

[0032] Figure 5A is a layout schematic diagram showing the overlap of the first overlap area of ​​the display substrate and the orthographic projection of the second metal layer on the base substrate in the comparative solution;

[0033] Figure 5B and Figure 5C They are Figure 5A Schematic diagram of the hierarchical structure of positions A1 and A2 from the perspective along the groove extension direction.

[0034] It should be understood that the size of each part shown in the accompanying drawings is not drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0035] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0036] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprise" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be an intermediate device between the specific device and the first device or the second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other device without an intermediate device, or may not be directly connected to the other device but have an intermediate device.

[0038] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0039] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0040] When the package fails (for example, the CVD structure breaks partially and produces gaps), the gaps in the organic layer or inorganic layer will become a water vapor path. Water vapor enters the panel through the cracks or gaps. When water vapor invades the organic material of the OLED, it will cause the organic material to oxidize and fail, and it will not emit light. As water vapor continues to invade through the gaps, the failure area gradually expands, causing a characteristic defect in the display device - a growing dark spot (GDS).

[0041] Research has found that there are a large number of signal lines led out of the display area. In order to reduce the space occupied by the signal lines, signal lines located in different layers and with smaller spacing are used to lead out in the fan-out area outside the AA area. Due to the difference in film thickness between adjacent signal lines, when the spacing area between adjacent signal lines overlaps with the edge of the organic layer trench used to achieve metal overlap between different layers or block water vapor, the metal layer formed on the upper side of the adjacent signal lines is prone to breakage due to the large difference in the film layer, causing the encapsulation layer formed on the metal layer by the CVD process to peel off or break, thereby increasing the risk of water vapor invading the circuit structure or the light-emitting material, thereby affecting the display effect and service life of the display device.

[0042] In view of this, embodiments of the present disclosure provide a display substrate and a display panel, which can improve the performance of a display device.

[0043] Figure 1 FIG. 4 is a schematic diagram of a hierarchical structure of a display substrate according to an embodiment of the present disclosure. Figure 2A 1 is a schematic diagram of partitions of a base substrate according to an embodiment of a display substrate disclosed herein. Figure 2B 1 is a schematic diagram of a hierarchical structure corresponding to display sub-pixels in an embodiment of a display substrate disclosed herein.

[0044] refer to Figure 1 and Figure 2A In some embodiments, the display substrate includes: a base substrate 10, a signal line layer 20, a first metal layer 30, an organic insulating layer 40 and a first electrode layer 50. Figure 2A In some embodiments, the base substrate 10 includes a display area 11 and a non-display area 12 located outside the display area 11 .

[0045] The display substrate may further include a plurality of display sub-pixels located in the display area 11 , each of which may display any color such as red, green, blue, or white, so that the display substrate may present a picture.

[0046] exist Figure 2A In the embodiment, the non-display area 12 may include a fan-out area 12a. The signal line layer 20 may include a plurality of signal lines located in the fan-out area 12a. Figure 2A In some embodiments, the non-display area 12 may further include a bending area 12b. The display substrate may be bent at the bending area 12b. In some embodiments, the fan-out area 12a may pass through the bending area 12b and partially overlap with the bending area 12b.

[0047] refer to Figure 2AIn some embodiments, the display area 11 includes: a first boundary 11a, a second boundary 11b, a third boundary 11c, and a fourth boundary 11d. The first boundary 11a and the third boundary 11c are arranged opposite to each other, and the second boundary 11b and the fourth boundary 11d are arranged opposite to each other. In some embodiments, the first boundary 11a is parallel to the third boundary 11c, and is perpendicular to the second boundary 11b and the fourth boundary 11d which are parallel to each other.

[0048] Through the above boundaries, the non-display area 12 may further include a plurality of peripheral areas. Figure 2A In the embodiment, the non-display area 12 includes a first peripheral area 121 located outside the first boundary 11a, a second peripheral area 122 located outside the second boundary 11b, a third peripheral area 123 located outside the third boundary 11c, and a fourth peripheral area 124 located outside the fourth boundary 11d. The fan-out area 12a is located in the fourth peripheral area 124. In some embodiments, the bending area 12b is also located in the fourth peripheral area 124.

[0049] exist Figure 1 In the embodiment, the signal line layer 20 may include a first signal line layer 21 and a second signal line layer 22. The first signal line layer 21 is disposed on the base substrate 10, and the second signal line layer 22 is disposed on a side of the first signal line layer 21 away from the base substrate 10. A portion of the plurality of signal lines included in the signal line layer 20 is located in the first signal line layer 21, and another portion is located in the second signal line layer 22. The signal lines in the first signal line layer 21 and the signal lines in the second signal line layer may be separated by an insulating layer.

[0050] refer to Figure 2B In some embodiments, the display sub-pixel has a thin film transistor, a capacitor, an anode 51, an organic light-emitting layer 62 and a cathode 61. The thin film transistor includes an active layer 71, a gate 72, a source 73 and a drain 74. The anode 51 is electrically connected to the drain 74 of the thin film transistor directly through a via, or is electrically connected to the drain 74 through a connecting electrode 75. The organic light-emitting layer 62 is located between the anode 51 and the cathode 61, and the cathode 61 is electrically connected to a common power line. The capacitor includes a first electrode 76 and a second electrode 77. In some embodiments, at least one of the multiple signal lines in the signal line layer 20 can be in the same layer and made of the same material as the gate 72 in the thin film transistor of the display sub-pixel, which allows part of the signal line and the gate 72 to be formed by the same patterning process, simplifying the processing procedure.

[0051] exist Figure 2BIn the embodiment, the base substrate 10 is covered with a buffer layer 23, and the active layer 71 is formed on the surface of the buffer layer 23. The first insulating layer 24 is located on the side of the buffer layer 23 away from the base substrate 10, and covers the active layer 71. The gate 72 and the first electrode 76 are formed on the surface of the first insulating layer 24, and the second insulating layer 25 is located on the side of the first insulating layer 24 away from the base substrate 10, and covers the gate 72 and the first electrode 76. The second electrode 77 is formed on the surface of the second insulating layer 25, and the third insulating layer 28 is located on the side of the second insulating layer 25 away from the base substrate 10, and covers the second electrode 77. The source 73 and the drain 74 are formed on the surface of the third insulating layer 28, and are electrically connected to the active layer 71 through vias, respectively. The passivation layer 33 is located on the side of the third insulating layer 28 away from the base substrate 10, and covers the source 73 and the drain 74.

[0052] The first organic insulating layer 40a is located on the side of the passivation layer 33 away from the base substrate 10, and the connecting electrode 75 is formed on the surface of the first organic insulating layer 40a and is electrically connected to the drain electrode 74 through a via hole. The second organic insulating layer 40b is located on the side of the first organic insulating layer 40a away from the base substrate 10, and the anode 51 is formed on the surface of the second organic insulating layer 40b and is electrically connected to the connecting electrode 75 through a via hole. The pixel definition layer 63 is formed on the surface of the second organic insulating layer 40b, and a portion of the anode 51 is exposed. The organic light-emitting layer 63 is formed on the anode 51, and the cathode 61 is formed on the organic light-emitting layer 63. The encapsulation layer 60 encapsulates the display substrate on the side of the cathode 61 away from the base substrate 10.

[0053] In other embodiments, the first signal lines in the first signal line layer 21 may be in the same layer and made of the same material as the gate electrode 72 in the thin film transistor and the first electrode plate 76 of the capacitor. The second signal lines in the second signal line layer 22 may be in the same layer and made of the same material as the second electrode plate 77 of the capacitor. This is conducive to using fewer patterning processes and simplifying the processing steps.

[0054] exist Figure 1 In the embodiment, the first metal layer 30 is disposed on a side of the signal line layer 20 away from the base substrate 10, the first electrode layer 50 is located on a side of the first metal layer 30 away from the base substrate 10, and the organic insulating layer 40 is located between the first metal layer 30 and the first electrode layer 50. In some embodiments, the organic insulating layer 40 is in direct contact with the first electrode layer 50.

[0055] In some embodiments, the source 73 and the drain 74 in the thin film transistor of the display sub-pixel are part of the first metal layer 30, so that the part of the first metal layer located in the non-display area and the source and drain located in the display area are formed by the same patterning process, simplifying the processing steps. In some embodiments, the anode 51 is part of the first electrode layer 50, so that the part of the first electrode layer located in the non-display area and the anode located in the display area are formed by the same patterning process, simplifying the processing steps.

[0056] refer to Figure 1 In some embodiments, the display substrate further includes an encapsulation layer 60. The encapsulation layer 60 may include at least one of an organic encapsulation layer and an inorganic encapsulation layer. The encapsulation layer 60 is located on the side of the first electrode layer 50 away from the base substrate 10, and may cover the display area 11 and part of the non-display area 12. For example, the encapsulation layer 60 covers the second electrode layer (e.g., cathode layer) of the display sub-pixel in the display area 11, and covers the part above the bending area 12b in the non-display area 12.

[0057] Figure 3A FIG. 4 is a schematic diagram showing a layout of a substrate according to an embodiment of the present disclosure. Figure 3B FIG. 1 is a partial schematic diagram of a first electrode layer relative to a display area in an embodiment of a display substrate according to the present disclosure. Figure 3C FIG. 1 is a partial schematic diagram of a first power line relative to a display area in an embodiment of a display substrate according to the present disclosure.

[0058] refer to Figure 3A-3C In some embodiments, the first metal layer 30 includes a first power line 31 and a second power line 32 located in the non-display area 12. During operation, the second power line 32 can be set to different voltages from the first power line 31, for example, the first power line 31 is set to a negative power voltage VSS, and the second power line 32 is set to a positive power voltage VDD.

[0059] refer to Figure 3A and Figure 3B In some embodiments, the first electrode portion is located in the non-display area and at least partially surrounds the display area. Figure 3B In the embodiment, the first electrode portion includes a first portion 50a, two second portions 50b, two third portions 50d, two fourth portions 50c and a fifth portion 50e.

[0060] refer to Figure 2A and Figure 3A ,exist Figure 3BIn the embodiment, the first portion 50a is continuously arranged in the first peripheral area 121, the second peripheral area 122 and the third peripheral area 123. The two second portions 50b are located in the fourth peripheral area 124, respectively connected to the first portions 50a located in the first peripheral area 121 and the third peripheral area 123, and extend in a direction parallel to the fourth boundary 11d. The two third portions 50d are located in the fourth peripheral area 124, and the orthographic projection of the substrate 10 coincides with the fan-out area 12a. The two fourth portions 50c are located in the fourth peripheral area 124, and the two ends of each of the two fourth portions 50c are respectively connected to one of the two third portions 30d and one of the two second portions 50b. The fifth portion 50e is located in the fourth peripheral area 124, and is connected between the two third portions 50d, and at least partially overlaps with the first power line 31.

[0061] refer to Figure 3B In some embodiments, the width w2 of each second portion 50b in the direction perpendicular to the fourth boundary 11d, the width w5 of the fifth portion 50e in the direction perpendicular to the fourth boundary 11d, and the minimum width w3 of each fourth portion 50c are all smaller than the width w1 of each first portion 50a in the direction perpendicular to the first boundary 11a or the third boundary 11c, and are all larger than the width w4 of each third portion 50d in the direction perpendicular to the fourth boundary 11d. In some embodiments, the display panel further includes a pixel definition layer, and a smaller width w4 is set, because the pixel definition layer covers the first electrode portion located outside the display area to promote water and oxygen protection of the fourth peripheral area.

[0062] In some embodiments, w1 is 1000-1100 μm, for example 1070 μm; w2 is 520-560 μm, for example 545 μm; w3 is 420-480 μm, for example 450 μm; w4 is 120-180 μm, for example 150 μm; w5 is 550-600 μm, for example 570 μm.

[0063] exist Figure 3B In the embodiment, the length direction of each fourth portion 50c and the fourth boundary 11d form an angle of 35 to 55 degrees, for example, 45 degrees. Such an inclined fourth portion can increase the area of ​​the first electrode portion and reduce the resistance.

[0064] refer to Figure 3B and Figure 3C In some embodiments, the fan-out region 12a includes two fan-out sub-regions. The two fan-out sub-regions are symmetrical with respect to an axis of symmetry (eg Figure 2AThe first electrode portions may be symmetrical with respect to the symmetry reference line 125 located in the middle of the display area and perpendicular to the fourth boundary 11a. Figure 3B In the embodiment, the first portion 50a, the two second portions 50b, the two third portions 50d and the two fourth portions 50c of the first electrode portion are all symmetrical relative to the symmetry axis. In addition, the fifth portion 50e is located between the two fan-out sub-regions and is symmetrical relative to the symmetry axis.

[0065] refer to Figure 3A and Figure 3C In some embodiments, the first power line includes: a sixth portion 31a, two seventh portions 31b and an eighth portion 31c. The sixth portion 31a is continuously arranged in the first peripheral area 121, the second peripheral area 122 and the third peripheral area 123. The two seventh portions 31b are located in the fourth peripheral area 124, connected to the sixth portion 31a located in the first peripheral area 121 and the third peripheral area 123, respectively, and extend in a direction parallel to the fourth boundary 11d. The eighth portion 31c is located in the fourth peripheral area 124 and between the two seventh portions 31b.

[0066] refer to Figures 3A-3C In some embodiments, the orthographic projection of the sixth portion 31a on the substrate substrate 10 partially overlaps with the orthographic projection of the first portion 50a on the substrate substrate 10 and is electrically connected, the orthographic projections of the two seventh portions 31b on the substrate substrate 10 respectively overlap with the orthographic projections of the two second portions 50b on the substrate substrate 10 and are electrically connected, and the orthographic projection of the eighth portion 31c on the substrate substrate 10 partially overlaps with the fifth portion 50e and the fan-out area 12a, and is electrically connected to the fifth portion 50e.

[0067] In addition, refer to Figure 3C In some embodiments, the sixth portion 31a is symmetrical with respect to a symmetry axis perpendicular to the fourth boundary, the two seventh portions 31b are symmetrical with respect to the symmetry axis, and the eighth portion 31c is symmetrical with respect to the symmetry axis and is T-shaped.

[0068] refer to Figure 3A and Figure 3C The orthographic projection of the second power line 32 on the base substrate 10 partially overlaps with the fan-out area 12a, and does not overlap with the orthographic projection of the eighth portion 31c on the base substrate.

[0069] An organic insulating layer 40 is provided between the first metal layer 30 and the first electrode layer 50. The first power line 31 or the second power line 32 and the first electrode layer 50 can be overlapped by providing a groove located in the non-display area 12 on the organic insulating layer 40 and penetrating the organic insulating layer 40 in a direction perpendicular to the base substrate 10. In addition, providing grooves at some positions can prevent water vapor from entering the display area, thereby reducing the adverse effects of water vapor on the display area.

[0070] In some embodiments, Figure 3A The grooves in the substrate include a first groove 41 and a second groove 42. The orthographic projection of the first groove 41 on the substrate substrate is located in the area between the adjacent fan-out sub-areas of at least two fan-out sub-areas included in the fan-out area 11a. The second groove 42 is horizontally arranged between the display area 11 and the bending area 11b, and its orthographic projection on the substrate substrate can partially overlap with the fan-out area 11a, the first electrode layer 40 and the second metal line 32. It should be noted that the grooves are not limited to being arranged in Figure 3A Position shown.

[0071] refer to Figure 3A In some embodiments, the groove can be configured such that: the groove at least partially overlaps between the orthographic projection of the base substrate 10 and the orthographic projection of the fan-out area 12a on the base substrate 10, and overlaps in a first overlapping area B4, and at least a portion of the first overlapping area B4 does not overlap with the first electrode layer 50 in the orthographic projection of the base substrate 10.

[0072] exist Figure 3A In the embodiment, the first overlap region B4 where the orthographic projection of the groove overlaps with the fan-out region 12a includes the overlapped portion of the orthographic projection of the second groove 42 and the fan-out region 12a (eg Figure 3A The orthographic projection of the first electrode layer 50 on the base substrate 10 does not include the first overlap area B4. This avoids the problem of overlap between the signal line layer in the fan-out area and the edge of the groove in the direction perpendicular to the base substrate.

[0073] Figure 4A-4C They are Figure 3A Schematic diagram of the hierarchical structure of positions B1, B2 and B3. Figure 4D yes Figure 3A Schematic diagram of the layout of the first electrode layer, the second organic insulating layer, the first organic insulating layer and the signal line layer at position B. Figure 5A It is a layout schematic diagram showing the overlap of the first overlap area of ​​the display substrate and the orthographic projection of the second metal layer on the base substrate in the comparison scheme. Figure 5B and Figure 5C They are Figure 5A Schematic diagram of the hierarchy of positions A1 and A2.

[0074] To better understand this issue, refer to Figure 5A If the orthographic projection of the first electrode layer 50 on the substrate overlaps with the first overlap region, for example Figure 5A If the positions A1 and A2 encircled by the dotted lines overlap, the multiple signal lines densely distributed in the signal line layer in the fan-out area and located in different layers are likely to cause a large film layer drop of the organic insulating layer at the edge of the groove, making the surface of the first electrode layer covering the inside and outside of the groove easy to be damaged or broken, and the stress after damage or breakage increases, and the adhesion between the encapsulation layer formed by the CVD process and the first electrode layer is weakened, resulting in cracks or shedding of the encapsulation layer. The cracks formed in this way may become water vapor paths that invade the circuit structure or light-emitting material of the display substrate, thereby affecting the display effect and life of the display substrate.

[0075] refer to Figure 5A and Figure 5B , from the perspective of looking down at the display substrate, the first groove 41, the signal line layer 20, the first power line 31 and the first electrode layer 50 overlap at position A1. Figure 5B In the hierarchical structure of the position A1, the signal line layer 20 includes a first signal line layer 21 and a second signal line layer 22. The first signal line layer 21 includes a plurality of first signal lines 21a and 21b among the plurality of signal lines, and the second signal line layer 22 includes a plurality of second signal lines 22a and 22b among the plurality of signal lines. At least part of the plurality of second signal lines 22a and 22b extends in parallel with at least part of the plurality of first signal lines 21a and 21b and is arranged alternately, for example Figure 5B In the figure, from left to right along the horizontal direction are the first signal line 21a, the second signal line 22a, the first signal line 21b and the second signal line 22b.

[0076] The first signal line and the second signal line are located in different signal line layers, respectively, and the signal lines in different layers may be separated by an insulating layer. Figure 5B In the embodiment, the base substrate 10 is covered with a buffer layer 23, and the first signal lines 21a and 21b are formed on the surface of the buffer layer 23. The signal line layer 20 further includes a first insulating layer 24 and a second insulating layer 25, the first insulating layer 24 covers the surfaces of the first signal lines 21a, 21b and the buffer layer 23, the second signal lines 22a and 22b are formed on the surface of the first insulating layer 24, and the second insulating layer 25 covers the surfaces of the second signal lines 22a, 22b and the first insulating layer 24.

[0077] refer to Figure 5B and Figure 5C The display substrate further includes a second metal layer 34. The first metal layer 30 and the second metal layer 34 may be separated by a passivation layer 33. Figure 5BIn the embodiment, the passivation layer 32 is located between the first power line 31 and the second metal layer 34. The first power line 31 is formed on the second insulating layer 25, and the passivation layer 33 has a first via hole at a position corresponding to the first groove 41, so that the second metal layer 34 is electrically connected to the first power line 31 through the first via hole.

[0078] exist Figure 5B In the fan-out region, the adjacent first signal line 21a and the second signal line 22a are located in different layers due to their small spacing and large film thickness difference, and the transition angle between the two is steep, which makes the non-flat layer material (such as an inorganic layer or a metal layer) formed above the two have a large slope difference. Here, the area between the adjacent first signal lines and the second signal lines in the plurality of first signal lines and the plurality of second signal lines parallel to the substrate and perpendicular to the extension direction of the plurality of first signal lines or the extension direction of the plurality of second signal lines is defined as the spacing area, for example Figure 5B The spacing area 26 is shown in the dashed box.

[0079] refer to Figure 5B and Figure 5C In some embodiments, the organic insulating layer 40 may include a second organic insulating layer 40a between the first electrode layer 50 and the second metal layer 34 and a first organic insulating layer 40b between the passivation layer 33 and the second metal layer 34. The first groove 41 is formed in the first organic insulating layer 40a and the second organic insulating layer 40b.

[0080] When the edge of the first groove 41 on the orthographic projection of the base substrate 10 at least partially overlaps with the spacing area 26 between the orthographic projections of the base substrate 10, at least one cross section of the first signal line 21a corresponds to the inside of the first groove 41, and at least one cross section of the second signal line 22a corresponds to the outside of the first groove 41. In other words, the edge of the first groove 41 may intersect with the adjacent first signal line and the second signal line, or be located between the first signal line and the second signal line and parallel to the first signal line or the second signal line.

[0081] There is no planarization layer material between the first electrode layer 50 and the second metal layer 34 and between the second metal layer 34 and the passivation layer 33 at the position corresponding to the bottom of the first groove 41, and there is a planarization layer material between the first electrode layer 50 and the second metal layer 34 at the position outside the first groove 41, which further increases the film thickness difference above the first signal line 21a and the second signal line 22a, which makes the first electrode layer 50 above the first signal line 21a and the second signal line 22a more likely to be damaged or broken at the position corresponding to the spacing area 26 due to the large film thickness difference and steep slope change. The damage or breakage of the first electrode layer 50 further weakens the adhesion between the encapsulation layer 60 and the first electrode layer 50, thereby causing the encapsulation layer 60 to fall off or break (for example, Figure 5B The crack 61 of the encapsulation layer 60 is shown.

[0082] refer to Figure 5A and Figure 5C Position A2 also has similar problems as position A1. From the perspective of looking down at the display substrate, the second groove 42, the signal line layer 20, the second power line 32 and the first electrode layer 50 overlap at position A2. Figure 5C In the hierarchical structure of the position A2, the second metal layer 34 is located between the passivation layer 33 and the signal line layer 20. The second power line 32 is insulated from the second metal layer 34 by the passivation layer 33 in the second groove 42. Since there is a large difference in film thickness above the first signal line 21a and the second signal line 22a, the first electrode layer 50 located above the first signal line 21a and the second signal line 22a becomes more likely to be damaged or broken at the position corresponding to the spacing area 26 due to the large difference in film thickness and the steeper slope change. The damage or breakage of the first electrode layer 50 further weakens the adhesion between the encapsulation layer 60 and the first electrode layer 50, thereby causing the encapsulation layer 60 to fall off or break (for example, Figure 5B The crack 61 of the encapsulation layer 60 is shown.

[0083] It can be understood from the above description that when the spacing area of ​​adjacent signal lines located in different layers within the signal line layer partially overlaps with the edge of the groove of the organic insulating layer, a large film thickness difference can be formed above the adjacent signal lines. Correspondingly, if the first electrode layer covers the inside and outside of the groove, the film thickness difference can easily cause damage or breakage of the first electrode layer. Therefore, when forming the first electrode layer, the embodiment of the present disclosure makes the orthographic projections of the first electrode layer, the groove and the signal line layer on the base substrate not overlap, thereby reducing or avoiding the risk of damage or breakage of the first electrode layer.

[0084] refer to Figure 3A , Figure 4A-4D , looking down at the display substrate, we can see that compared to Figure 5A The first electrode layer in Figure 3A The range covered by the first electrode layer 50 does not include the overlapped portion of the groove and the fan-out region. In other words, the first electrode layer 50 bypasses the overlapped portion of the groove and the fan-out region.

[0085] refer to Figure 3A In some embodiments, the orthographic projection of the first power line 31 on the base substrate 10 and the orthographic projection of the first electrode layer 50 on the base substrate 10 at least partially overlap in a second overlapping region. The fan-out region 12a may include at least two fan-out sub-regions, and the second overlapping region may be located in a spacing region between adjacent fan-out sub-regions of the at least two fan-out sub-regions.

[0086] For example, in Figure 3A In the embodiment, the eighth T-shaped portion of the first power line 31 is located between the two fan-out sub-areas, and its orthographic projection overlaps the two fan-out sub-areas slightly. The second overlapping area of ​​the orthographic projection of the first electrode layer 50 on the base substrate 10 and the orthographic projection of the eighth T-shaped portion on the base substrate 10 is rectangular. The orthographic projection of the first groove 41 included in the groove on the base substrate 10 is located in the second overlapping area. The first electrode layer 50 can overlap the first power line 31 in the first groove 41.

[0087] exist Figure 3A The position B1 marked by the dotted line does not correspond to the fan-out area, so there is no signal line layer. Its hierarchical structure is as follows Figure 4A Reference Figure 4A and Figure 4B In some embodiments, the display substrate further includes a second metal layer 34. The second metal layer 34 includes a second metal portion. The first metal layer 30 and the second metal layer 34 may be separated by a passivation layer 33. In some embodiments, the number of the grooves is multiple, such as a first groove 41 and a second groove 42. The second metal portion may be electrically connected to the first power line 31 and the first electrode portion through at least some of the grooves.

[0088] exist Figure 4A, the passivation layer 33 is located between the first power line 31 and the second metal layer 34. The first power line 31 is formed on the second insulating layer 25. The passivation layer 33 has a first via hole corresponding to the first groove 41, so that the first power line 31 is electrically connected to the second metal layer 34 through the first via hole. The inside of the first groove 41 is the encapsulation layer 60, the first electrode layer 50, the second metal layer 34, the first power line 31, the second insulating layer 25, the first insulating layer 24, the buffer layer 23 and the base substrate 10 from top to bottom. The outside of the first groove 41 is the encapsulation layer 60, the first electrode layer 50, the first organic insulating layer 40a, the second metal layer 34, the second organic insulating layer 40b, the passivation layer 33, the first power line 31, the second insulating layer 25, the first insulating layer 24, the buffer layer 23 and the base substrate 10 from top to bottom.

[0089] Compared with the film thickness difference formed by the signal lines located in different layers and close to each other in the fan-out area, although there is also a film thickness difference formed by the first organic insulating layer 40a, the second organic insulating layer 40b and the passivation layer 33 inside and outside the first groove 41, its slope changes more gently, so it is not easy to cause damage or breakage of the first electrode layer 50, thereby reducing the risk of breakage or falling off of the encapsulation layer 60, thereby reducing the risk of GDS, and improving the display effect and service life of the display device.

[0090] refer to Figure 3A and Figure 4B The orthographic projection of the second power line 32 on the base substrate 10 at least partially overlaps with the fan-out area 12a, and overlaps in a third overlapping area. The groove includes a second groove 42, and the orthographic projection of the second groove 42 on the base substrate 10 partially overlaps with the third overlapping area. The third overlapping area is located between the orthographic projection of the second groove 42 on the base substrate 10 and the display area 11.

[0091] for Figure 3A The position B2 marked by the dotted line, Figure 4B A schematic diagram of the hierarchy of position B2 is provided. Figure 4B The signal line layer 20 includes a first signal line layer 21 and a second signal line layer 22. The first signal line layer 21 includes a plurality of first signal lines 21a and 21b among the plurality of signal lines, and the second signal line layer 22 includes a plurality of second signal lines 22a and 22b among the plurality of signal lines. At least a portion of the plurality of second signal lines 22a and 22b extends in parallel with at least a portion of the plurality of first signal lines 21a and 21b and is arranged alternately.

[0092] The first signal line and the second signal line are located in different signal line layers, respectively, and the signal lines in different layers may be separated by an insulating layer. Figure 4BIn the embodiment, the base substrate 10 is covered with a buffer layer 23, and the first signal lines 21a and 21b are formed on the surface of the buffer layer 23. The signal line layer 20 further includes a first insulating layer 24 and a second insulating layer 25, the first insulating layer 24 covers the surfaces of the first signal lines 21a, 21b and the buffer layer 23, the second signal lines 22a and 22b are formed on the surface of the first insulating layer 24, and the second insulating layer 25 covers the surfaces of the second signal lines 22a, 22b and the first insulating layer 24.

[0093] The first metal layer 30 is separated from the second metal layer 34 by the passivation layer 32. For example, the passivation layer 32 is located between the second power line 32 and the second metal layer 34. The second power line 32 is formed on the second insulating layer 25. At a position corresponding to the second groove 42, the passivation layer 32 has a second via hole corresponding to the second groove 42, so that the second metal layer 34 is electrically connected to the second power line 32 through the second via hole.

[0094] At the position corresponding to the second groove 42, the orthographic projection of the spacing area between the first signal line 21a and the second signal line 22a on the base substrate at least partially overlaps with the edge of the orthographic projection of the second groove 42 on the base substrate 10. Although there is a difference in film thickness above the first signal line 21a and the second signal line 22a, since the first electrode layer 50 is not covered inside and outside the second groove 42, the first electrode layer 50 is prevented from being damaged or broken at the edge of the second groove 42.

[0095] refer to Figure 3A and Figure 4C , arbitrarily select a position where the first electrode layer 50, the second power line 32 and the fan-out area 12a overlap in the angle of looking down at the display substrate, such as position B3, at which there is no groove located in the organic insulating layer. Figure 4C , the second power line 32 is separated from the second metal layer 34 by the passivation layer 33. Although there are different film thickness differences above the first signal lines 21a, 21b and the second signal lines 22a, 22b that are adjacent and in different layers, the first organic insulating layer 40a between the first electrode layer 50 and the second metal layer 34 and the second organic insulating layer 40b between the second metal layer 34 and the passivation layer 33 respectively serve as planarization layers to improve the flatness above the first signal line and the second signal line, reduce or avoid the risk of damage to the first electrode layer 50, thereby reducing the risk of breakage or detachment of the encapsulation layer 60, thereby reducing the risk of GDS, and improving the display effect and service life of the display device.

[0096] refer to Figure 2B , Figure 3A-Figure 4CThe display substrate includes a first metal layer 30 and a second metal layer 34 located on a side of the first metal layer 30 away from the base substrate 10. In some embodiments, the display substrate further includes a connecting electrode 75. The connecting electrode 75 is located between the drain electrode 74 of the thin film transistor of the display sub-pixel and the anode electrode 51 of the display sub-pixel, and is electrically connected to the drain electrode 74 and the anode electrode 51 respectively.

[0097] In some embodiments, the connection electrode 75 is a part of the second metal layer 34, so that the part of the second metal layer 34 located in the non-display area can be formed by the same patterning process as the connection electrode 75 located in the display area, thereby simplifying the processing steps. The organic insulating layer 40 includes a first organic insulating layer 40a located between the first metal layer 30 and the second metal layer 34 and a second organic insulating layer 40b located between the second metal layer 34 and the first electrode layer 50.

[0098] refer to Figure 4D The groove includes a first groove portion located in the first organic insulating layer 40a and a second groove portion located in the second organic insulating layer 40b. Figure 4D In the figure, the two edges 43 of the first groove portion correspond to the solid material of the first organic insulating layer 40a, and the upper and lower sides of the two edges 43 correspond to the hollowed-out portion of the first organic insulating layer 40a. The two edges 44 of the second groove portion are located between the two edges 43 of the first groove portion, and the edge 44 at the lower right corner is a rectangle with a slightly smaller size. The two edges 44 correspond to the second organic insulating layer 40b, and the rectangle at the lower right corner corresponds to the hollowed-out portion of the second organic insulating layer 40b, while the other positions correspond to the solid material of the second organic insulating layer 40b.

[0099] The signal line layer 20 is an isosceles trapezoid in a top view, and the hypotenuse boundary 27 of the signal line layer 20 intersects with the edge 44 of the second groove portion at position C1, and intersects with the edge 43 of the first groove portion at position C2. As described above, signal lines of different layers in the signal line layer 20 are adjacent to each other, and when they intersect with the groove edge, it is easy to cause a greater thickness difference between the inside and outside of the groove. Therefore, at position C1, the second organic insulating layer 40b can be covered on the edge 43 of the first groove portion to make this position more flat.

[0100] At the C2 position, the signal line layer 20 intersects with the edge 43 of the first groove portion, and this position can be made flatter by covering the edge 43 of the first groove portion with the second organic insulating layer 40b, and correspondingly, the first electrode layer 50 is allowed to cover this position to avoid the problem of the first electrode portion covering it being easily broken due to the uneven edge 43 of the first groove portion.

[0101] exist Figure 4DAt the lower right position, the hollowed-out portion of the first groove portion and the hollowed-out portion of the second groove portion overlap, for example Figure 4D At position C3, since the first groove portion and the second groove portion at this position do not overlap with the signal line layer 20, the first electrode layer 50 is allowed to cover this position. Figure 4A , thereby avoiding the problem of the first electrode portion covering this position being easily broken.

[0102] In the above embodiments, the second metal layer 34 may be electrically connected to the first power line 31 through the first groove portion 43 , and to the first electrode portion through the second groove portion 44 .

[0103] The above display substrate embodiments of the present disclosure can be applied to various display devices. Therefore, the present disclosure also provides a display device, including the above display substrate. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0104] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0105] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a non-display area located outside the display area, wherein the non-display area comprises a fan-out area; A signal line layer, disposed on the substrate substrate and comprising a plurality of signal lines located in the fan-out area; A first metal layer is disposed on a side of the signal line layer away from the base substrate and includes a first power line located in the non-display area; A first electrode layer, located on a side of the first metal layer away from the base substrate, comprising a first electrode portion, an orthographic projection of the first electrode portion on the base substrate at least partially overlaps with an orthographic projection of the first power line on the base substrate, and the first electrode portion is electrically connected to the first power line; and An organic insulating layer is located between the first metal layer and the first electrode layer, and has a groove located in the non-display area, wherein an edge of the organic insulating layer at the groove at least partially overlaps between the orthographic projection of the base substrate and the orthographic projection of the fan-out area on the base substrate, and overlaps in a first overlapping area, and at least a portion of the first overlapping area does not overlap with the orthographic projection of the first electrode portion on the base substrate.

2. The display substrate according to claim 1, wherein: The organic insulating layer is in direct contact with the first electrode layer.

3. The display substrate according to claim 1, further comprising: A second metal layer is located on a side of the first metal layer away from the substrate. Wherein, the organic insulating layer comprises: a first organic insulating layer located between the first metal layer and the second metal layer; and a second organic insulating layer, located between the second metal layer and the first electrode layer, Wherein, the groove includes a second groove portion located in the second organic insulating layer.

4. The display substrate according to claim 1, further comprising: A second metal layer is located on a side of the first metal layer away from the substrate. Wherein, the organic insulating layer comprises: a first organic insulating layer located between the first metal layer and the second metal layer; and a second organic insulating layer, located between the second metal layer and the first electrode layer, The groove includes a first groove portion located in the first organic insulating layer and a second groove portion located in the second organic insulating layer.

5. The display substrate according to claim 1, further comprising: A second metal layer is located on a side of the first metal layer away from the substrate. Wherein, the organic insulating layer comprises: a first organic insulating layer located between the first metal layer and the second metal layer; and a second organic insulating layer, located between the second metal layer and the first electrode layer, The groove includes a first groove portion located in the first organic insulating layer, and the second organic insulating layer covers an upper side of the first groove portion.

6. The display substrate according to any one of claims 3 to 5, wherein: The number of the grooves is plural, and the second metal layer includes a second metal portion, and the second metal portion is electrically connected to the first power line and the first electrode portion through at least part of the grooves.

7. The display substrate according to claim 1, wherein: The first electrode portion is located in the non-display area and at least partially surrounds the display area.

8. The display substrate according to claim 1, wherein: The display area includes: a first boundary, a second boundary, a third boundary and a fourth boundary, the first boundary and the third boundary are arranged opposite to each other, the second boundary and the fourth boundary are arranged opposite to each other, the non-display area includes a first peripheral area located outside the first boundary, a second peripheral area located outside the second boundary, a third peripheral area located outside the third boundary and a fourth peripheral area located outside the fourth boundary, and the fan-out area is located in the fourth peripheral area. Wherein, the first electrode portion comprises: A first portion is continuously disposed in the first peripheral area, the second peripheral area, and the third peripheral area; Two second portions, located in the fourth peripheral area, connected to the first portions located in the first peripheral area and the third peripheral area respectively, and extending in a direction parallel to the fourth boundary; Two third portions are located in the fourth peripheral region, and their orthographic projections on the substrate overlap with the fan-out region; two fourth parts, located in the fourth peripheral area, and two ends of each of the two fourth parts are respectively connected to one of the two third parts and one of the two second parts; and The fifth portion is located in the fourth peripheral area and connected between the two third portions, and at least partially overlaps with the first power line.

9. The display substrate according to claim 8, wherein: The width of each second part in the direction perpendicular to the fourth boundary, the width of the fifth part in the direction perpendicular to the fourth boundary, and the width of each fourth part in the direction perpendicular to its own extension direction are all smaller than the width of each first part in the direction perpendicular to its own extension direction, and are all larger than the width of each third part in the direction perpendicular to the fourth boundary.

10. The display substrate according to claim 8, wherein: The included angle between the extending direction of each fourth portion and the fourth boundary is 35 to 55 degrees.

11. The display substrate according to claim 8, wherein: The fan-out region includes two fan-out sub-regions, the two fan-out sub-regions are symmetrical to each other with respect to a symmetry axis perpendicular to the fourth boundary, the first electrode portions are symmetrical to each other with respect to the symmetry axis, and the fifth portion is located between the two fan-out sub-regions.

12. The display substrate according to claim 8, wherein: The first power line comprises: A sixth portion is continuously disposed in the first peripheral area, the second peripheral area, and the third peripheral area; two seventh portions, located in the fourth peripheral region, connected to the sixth portions located in the first peripheral region and the third peripheral region, respectively, and extending in a direction parallel to the fourth boundary; and an eighth portion, located in the fourth peripheral area and between the two seventh portions, Among them, the orthographic projection of the sixth part on the substrate substrate overlaps with the orthographic projection of the first part on the substrate substrate and is electrically connected, the orthographic projections of the two seventh parts on the substrate substrate overlap with the orthographic projections of the two second parts on the substrate substrate respectively and are electrically connected, and the orthographic projection of the eighth part on the substrate substrate overlaps with the fifth part and the fan-out area, and is electrically connected to the fifth part.

13. The display substrate according to claim 12, wherein: The sixth portion and the two seventh portions are symmetrical to each other with respect to a symmetry axis perpendicular to the fourth boundary, and the eighth portion is symmetrical to each other with respect to the symmetry axis and is T-shaped.

14. The display substrate according to claim 12, wherein: The first metal layer further includes a second power line located in the fourth peripheral region, wherein an orthographic projection of the second power line on the base substrate partially overlaps with the fan-out region and does not overlap with an orthographic projection of the first power line on the base substrate.

15. The display substrate according to claim 1, wherein: The signal line layer comprises: a first signal line layer, disposed on the base substrate and comprising a plurality of first signal lines among the plurality of signal lines; and a second signal line layer, arranged on a side of the first signal line layer away from the substrate, and comprising a plurality of second signal lines among the plurality of signal lines, at least a portion of the plurality of second signal lines extending in parallel with at least a portion of the plurality of first signal lines and arranged alternately, In which, in a direction parallel to the base substrate and perpendicular to the extension direction of the multiple first signal lines or the extension direction of the multiple second signal lines, the area between adjacent first signal lines and second signal lines among the multiple first signal lines and the multiple second signal lines is a spacing area, and the edge of the orthographic projection of the base substrate and the spacing area at least partially overlap between the orthographic projection of the base substrate.

16. The display substrate according to claim 15, further comprising: The display sub-pixel comprises a thin film transistor, a capacitor and an anode, wherein the thin film transistor comprises a gate, a source and a drain, and the capacitor comprises a first plate and a second plate. Among them, the gate, the first electrode plate and the multiple first signal lines are in the same layer and made of the same material, the second electrode plate and the multiple second signal lines are in the same layer and made of the same material, and / or the source and drain are part of the first metal layer, and / or the anode is part of the first electrode layer.

17. The display substrate according to claim 16, further comprising: A second metal layer is located on a side of the first metal layer away from the substrate; and a connecting electrode, located between the drain electrode and the anode electrode, and electrically connected to the drain electrode and the anode electrode respectively, Wherein, the connecting electrode is a part of the second metal layer.

18. The display substrate according to claim 1, further comprising: The encapsulation layer is located on a side of the first electrode layer away from the base substrate, and covers the display area and a portion of the non-display area.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

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