Multiple flash translation layers at a memory device

Abstract

This application is directed to multiple flash translation layers (FTLs) at a memory device. Based on one or more characteristics of data, a first FTL can be configured to support mapping of data using a defined granularity, and a second FTL can be configured to support mapping of data using a granularity that is less than the defined granularity or mapping of data that does not match the defined granularity. The memory device can select between the FTLs to map data based on the one or more characteristics of the data, and can write the data to the memory device. The memory device can store a logical to physical mapping associated with the data, and other information, using the selected FTL.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 065,455, filed October 7, 2020, entitled “Multiple Flash Translation Layers at a Memory Device,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to multiple flash translation layers (FTLs) at memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] Describe a device. The device may include a memory array and a controller coupled to the memory array. The controller is configured to: cause the device to receive data and commands to store the data at the device; select a flash conversion layer for storing the data, at least in part based on the structure of the data, the flash conversion layer being selected between a first flash conversion layer and a second flash conversion layer associated with a data storage size smaller than the first flash conversion layer; and, at least in part based on the selection of the second flash conversion layer, store mapping information associated with the data at a subset of storage locations of the second flash conversion layer, the mapping information having a format corresponding to the second flash conversion layer.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive data and a command to store the data at the electronic device; select a flash conversion layer for storing the data, at least in part based on the structure of the data, the flash conversion layer being selected between a first flash conversion layer and a second flash conversion layer associated with a data storage size smaller than the first flash conversion layer; and, at least in part based on the selection of the second flash conversion layer, store mapping information associated with the data at a subset of storage locations of the second flash conversion layer, the mapping information having a format corresponding to the second flash conversion layer.

[0008] A method is described. The method can be performed by a memory device. The method may include: receiving data at the memory device and commands to store the data at the memory device; selecting a flash conversion layer for storing the data, at least in part based on the structure of the data, the flash conversion layer being selected between a first flash conversion layer and a second flash conversion layer associated with a data storage size smaller than the first flash conversion layer; and storing mapping information associated with the data, having a format corresponding to the second flash conversion layer, at a subset of storage locations of the second flash conversion layer, at least in part based on the selection of the second flash conversion layer. Attached Figure Description

[0009] Figure 1 Examples of systems supporting multiple flash transfer layers (FTLs) at a memory device are shown, according to the examples disclosed herein.

[0010] Figure 2 An example of an architecture supporting multiple FTLs at a memory device is shown, based on the examples disclosed herein.

[0011] Figure 3An example of a flowchart illustrating multiple FTLs at a supporting memory device according to the examples disclosed herein.

[0012] Figure 4 Examples of mapping schemes for multiple FTLs at a supporting memory device are shown, according to the examples disclosed herein.

[0013] Figure 5 A block diagram of a memory device supporting multiple FTLs at a memory device according to the examples disclosed herein is shown.

[0014] Figure 6 A flowchart illustrating one or more methods for supporting multiple FTLs at a memory device, based on examples disclosed herein. Detailed Implementation

[0015] A memory device may include a flash translation layer (FTL), which in particular supports data storage and management. For example, the FTL may perform logical-to-physical (L2P) address mapping, garbage collection, wear leveling, error correction code (ECC) procedures, bad block management, or other operations, or any combination thereof. In some cases, the FTL may support data mapping (e.g., L2P mapping) using defined granularity. For example, defined granularity can support increased space and time efficiency when managing L2P mapping, allowing data matching the defined granularity to be written and read with increased speed and accuracy. In some cases, data to be written to the memory device may be associated with a granularity smaller than the defined granularity. For example, the data may be smaller than the defined granularity, or it may be aligned such that a portion of the data is smaller than the defined granularity, or it may not match the physical granularity of one or more free physical addresses used to store the data. In these and other cases, the memory device may perform read, modify, and write operations to write data because the granularity associated with the data may not match the defined granularity. Read, modify, and write operations can introduce additional latency to read, modify, or write data, and may also increase write amplification and attenuation, which may reduce device life and device performance, as well as other drawbacks.

[0016] This disclosure provides techniques for including and using two or more File Transfer Layers (FTLs) within a memory device, wherein a first FTL (e.g., a primary FTL using a larger granularity) is configured to support data mapping using a defined granularity, and a second FTL (e.g., a secondary or smaller FTL) is configured to support data mapping using a granularity smaller than the defined granularity. For example, the first FTL can be used to map data matching the defined granularity, which may represent the majority of data stored at the memory device. The second FTL can be used to map other data that does not match the defined granularity. For example, if the data size is smaller than the defined granularity, or if the alignment of one or more subsets of data fails to match the data alignment of the first FTL, or if the size or alignment of the data fails to match the size or alignment of a free physical location (e.g., associated with the first FTL), then the memory device may select the second FTL to manage the data mapping (alone or in conjunction with the first FTL). Therefore, the memory device can select between FTLs to map data, for example, based on one or more characteristics of the data. Choosing between FTLs can support higher L2P efficiency, higher cache hit rate, and a reduced memory block budget for matching data with defined granularity, while reducing latency and overhead associated with writing data that does not match defined granularity (e.g., by eliminating or reducing read, modify, and write operations associated with using an FTL).

[0017] The features of this disclosure were initially described in reference to Figure 1 The system described herein is described in the context of the system described. Features of this disclosure are described in reference to... Figure 2-4 The device architecture, flowcharts, and mapping schemes described herein are presented in the context of the description. These and other features of this disclosure are further supported by references. Figure 5 and 6 The device diagrams and flowcharts describing the multiple FTLs at the memory device are shown and described with reference to these diagrams.

[0018] Figure 1 This is an example of a system 100 that supports multiple FTLs at a memory device, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any computing device that includes memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 A memory system 110 is shown, but it should be understood that the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, USB interfaces, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR), Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM socket interfaces), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR). In some instances, one or more of these interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 or memory device 140 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Although Figure 1 The example shows a memory device 130 and a memory device 140, but it should be understood that the memory system 110 may contain any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may not have memory devices 130 or memory devices 140.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with memory device 130 or memory device 140 to perform operations such as reading, writing, erasing, or refreshing data at memory device 130 or memory device 140, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or memory device 140 to execute such commands (e.g., at a memory array within said one or more memory devices 130 or memory device 140). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory device 130 or memory device 140. Furthermore, in some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 or 140 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with memory devices 130 or 140 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with memory device 130 or memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 130 or memory device 140.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130 or memory device 140, and may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130 or memory device 140) according to a cache strategy.

[0028] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135 or local controllers 145, which may be located within memory device 130 or memory device 140, respectively, to perform the functions belonging to memory system controller 115 herein. Generally, one or more functions belonging to memory system controller 115 herein may actually be performed by host system 105, local controller 135 or local controller 145, or any combination thereof, in some cases.

[0029] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells. In some instances, memory device 140 may support random access operations with reduced latency relative to memory device 130 (e.g., performed by host system 105), or may provide one or more other performance differences relative to memory device 130.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0031] In some instances, memory device 130 or memory device 140 may each include (e.g., on the same die or within the same package) a local controller 135 or a local controller 145, which may perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device and may include a memory array and associated circuitry combined with a local (e.g., on-die or within-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more memory dies 160. In some instances, memory die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each memory die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information. If each cell is configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if each cell is configured to store three bits of information, it may be referred to as a three-level cell (TLC); if each cell is configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0037] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to the remaining one or more pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data remaining in the old block 170 as invalid or obsolete and update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, such copying and remapping may be preferred, for example, for latency or wear considerations, to erase and rewrite the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0038] The L2P mapping table and other information may be managed by or contained within the FTL 180, which may perform, for example, L2P address mapping, garbage collection, wear leveling, ECC procedures and / or bad block management, and other instances. The FTL 180 may be contained within a portion of a controller, such as the memory system controller 115 or the local controller 135, or may be additionally or alternatively contained within the memory device 130 as separate logic or firmware.

[0039] Two or more FTLs 180 may be included as part of memory device 130 or memory system 110, wherein a first FTL 180 (e.g., a major FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity, and a second FTL 180 (e.g., a secondary FTL or smaller FTL 180) may be configured to support data mapping using a granularity smaller than the defined granularity. For example, if the size of the data is smaller than the defined granularity, or if the alignment of one or more subsets of data fails to match the data alignment of the first FTL 180, or if the size or alignment of the data fails to match the size or alignment of a free physical location (e.g., associated with the first FTL 180), then the memory device may select a second FTL 180 to manage the data mapping. Choosing between FTL 180s can support higher L2P efficiency, higher cache hit rate, and a reduced memory block budget for matching data with defined granularity, while reducing latency and overhead associated with writing data that does not match defined granularity (e.g., by eliminating or reducing read, modify, and write operations associated with using an FTL 180).

[0040] In some cases, L2P tables can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data due to a more recent or updated version of the data being stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has never been written to or has been erased.

[0041] In some cases, the memory system controller 115, local controller 135, or local controller 145 may perform operations on the memory device 130 or memory device 140 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called "garbage collection" may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations, including, for example, selecting block 170 containing valid and invalid data, selecting page 175 within the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Therefore, the number of blocks 170 that have been erased can be increased, making more blocks 170 available for storing subsequent data (e.g., data subsequently received from the host system 105).

[0042] System 100 may include any number of non-transitory computer-readable media supporting multiple FTLs at a memory device. For example, host system 105, memory system controller 115, memory device 130, or memory device 140 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions belonging to host system 105, memory system controller 115, memory device 130, or memory device 140 herein. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system controller 115, memory device 130 (e.g., local controller 135), or memory device 140 (e.g., local controller 145), may cause host system 105, memory system controller 115, memory device 130, or memory device 140 to perform one or more associated functions described herein.

[0043] Figure 2 An example of an architecture 200 supporting multiple FTLs at a memory device is shown, according to the examples disclosed herein. For example, refer to reference as follows. Figure 1 The corresponding memory device or memory system described herein, architecture 200 may represent device architecture 200 or system architecture 200. For example, architecture 200 may be implemented at memory device 205, which may represent a reference. Figure 1 An example of the described memory device 130. Although the examples described herein refer to memory device 205, it should be understood that the same examples can be applied to memory systems without departing from the scope of this disclosure.

[0044] Memory device 205 may include interface 210 (e.g., one or more pins, balls, or pads) that can or is capable of being coupled to a host system, a host device, or another source external to memory device 205. Memory device 205 may communicate with the host system or host device (e.g., or other external source) via interface 210, for example by receiving data and one or more commands from the host system or host device and transferring data to the host system or host device (e.g., in response to a read command). In one example, memory device 205 may receive a write command and data to be written to memory device 205 from the host system or host device. Memory device 205 may employ one or more techniques described herein to support writing received data to memory device 205 (e.g., writing to memory array 225 of memory device 205).

[0045] For reference Figure 1As described, memory device 205 may include FTL 220, which supports data storage and management. FTL 220 may be coupled to an interface and may also be coupled to or included in device controller 215. For example, FTL 220 may represent controller logic or software or any combination of logic or software separate from device controller 215.

[0046] When memory device 205 receives data and a command to write data (e.g., which may contain the logical address of the data), FTL 220 can determine the physical address (e.g., a free physical address) of the stored data (e.g., within memory array 225) and can store or update the L2P mapping that associates the logical address and physical address of the data. The size of the data can be referred to as a block write or block write size, and can represent the amount of data bits to be written to memory device 205 (e.g., to memory array 225). The physical address and logical address as described herein can also represent the physical block address (PBA) and logical block address (LBA), respectively.

[0047] In some cases, the FTL 220 (e.g., FTL 220-a) can support data mapping (e.g., L2P mapping) using a defined granularity (e.g., a data page or 32 kilobytes (kB) of data), which may be referred to as an FTL translation unit. Defined granularity can support increased space and time efficiency when managing L2P mapping (e.g., L2P tables), for example, by mapping physical addresses using the size of a data physical page (e.g., 16kB of data or four LBAs) or a multiple of the data physical page size (e.g., 64kB or larger) (e.g., multi-plane physical page blocks). Mapping information can be stored in a list of logical addresses and associated physical addresses, which can be configured for larger and faster data storage. For example, one physical address can be associated with four logical addresses (e.g., FTL translation units), allowing data matching the defined granularity to be written and read with increased speed and accuracy. In some cases, the host system or host device can indicate to the memory device 205 data to be written with a granularity smaller than the defined granularity. For example, data may be smaller than a defined granularity, alignment may be made such that a portion of the data is smaller than a defined granularity, or it may fail to match the physical granularity of one or more free physical addresses, even if the size or other characteristics are properly handled by FTL 220.

[0048] In these and other cases, memory device 205 (e.g., FTL 220-a of memory device 205) may perform read, modify, and write operations to write data (e.g., to include other previously written data in the write operation) because the granularity associated with the data may not match the defined granularity. However, using these other different techniques for read, modify, and write operations can introduce additional latency for writing data and may also increase write amplification and attenuation, which may reduce device lifetime and device performance.

[0049] This disclosure provides techniques for including two or more FTLs 220 within a memory device, wherein a first FTL 220-a (e.g., a primary FTL 220 using a larger granularity) is configured to support data mapping using a defined granularity, and a second FTL 220-b (e.g., a secondary FTL or smaller FTL 220) is configured to support data mapping using a granularity smaller than the defined granularity (e.g., 4kB or less). For example, FTL 220-a can be used to map data matching the defined granularity, which may represent a majority of the data stored at memory device 205. For example, the data may represent a relatively high number of sequential data or workloads, which may represent a relatively high number of larger data blocks and a relatively low number of smaller data blocks. FTL 220-b can be used to map data that does not match the defined granularity (e.g., associated with a smaller granularity).

[0050] Mapping data that does not match a defined granularity using FTL 220-b allows such data to be mapped without performing the read, modify, and write operations associated with FTL 220-a. For example, FTL 220-b can be configured to map data that may be smaller than a defined granularity, data that can be aligned such that a portion of the data is smaller than a defined granularity, or data with a physical granularity that may not match one or more free physical addresses, without performing read, modify, and write operations. Doing so can, for example, reduce latency, reduce write amplification and attrition, and increase device lifetime and performance by reducing the read, modify, and write operations associated with mapping data using FTL 220-a.

[0051] Therefore, memory device 205 may, for example, select between FTL 220-a and 220-b to map data (alone or in a combination) based on one or more characteristics of the data. Selecting between FTL 220-a and 220-b to manage data can support higher L2P efficiency, higher cache hit rates, and a reduced memory block budget for matching data at a defined granularity, while reducing latency and overhead associated with writing data that does not match the defined granularity (e.g., by eliminating or reducing read, modify, and write operations associated with using FTL 220-a). In some cases, memory device 205 may select one of FTL 220-a or 220-b to map data, for example, based on one or more characteristics of the data matching FTL 220-a or 220-b. In some cases, memory device 205 may select both FTL 220-a and FTL 220-b to map data. For example, a first part or subset of data may not match a defined granularity (e.g., based on one or more characteristics of the first part of the data) and can be mapped using FTL 220-b, while a second part or subset of data matches a defined granularity (e.g., based on one or more characteristics of the second part of the data) and can be mapped using FTL220-a.

[0052] FTL 220-b can be configured to manage data mapping (e.g., L2P mapping) at a granularity smaller than that of FTL 220-a. For example, memory device 205 may select FTL 220-b to manage data mapping if the data size is smaller than the defined granularity, if the alignment of one or more subsets of data fails to match the data alignment of FTL 220-a, or if the size or alignment of the data fails to match the size or alignment of a free physical location (e.g., associated with FTL 220-a). For details on selecting between FTL 220-a and FTL 220-b, refer to [reference needed]. Figure 3 Further description. The FTL 220-b may have a physical location for storing data mapped via the FTL 220-b, where the physical location may represent a temporary storage location for the data. The physical location may represent one or more memory cell blocks (e.g., SLC blocks or virtual blocks spanning all planes or dies) configured for data mapped via the FTL 220-b. Data written to the physical location can then be combined into larger data that can be managed by the FTL 220-a, for example, via read, modify, and write procedures, via sequential garbage collection, or through data aggregation. Combining data into larger data sets increases data efficiency and FTL efficiency by using the FTL 220-a to manage data.

[0053] The FTL 220-b can be configured to manage data mappings (e.g., L2P mappings) using one or more mapping schemes configurable with a format corresponding to the FTL 220-b. For example, the FTL 220-b can use any data structure to manage data mappings (e.g., to store L2P information), such as a binary tree or other tree, a hash table of physical and logical addresses, a flat list of logical and physical address pairs, or any combination thereof. Examples related to binary tree mapping schemes are referenced herein. Figure 4 Further description. For example, FTL 220-b may use SRAM (e.g., up to 256kB of SRAM) contained in or associated with memory array 225 to store data mappings in a portion of memory device 205.

[0054] If FTL 220-b is used to configure data to be written to memory device 205, then FTL 220-b can identify one or more logical addresses provided for the data by the host system or host device (e.g., via a write command). FTL 220-b can identify one or more physical addresses corresponding to the one or more logical addresses used to store the data, and can update the data mapping scheme such that the one or more logical addresses are associated with the one or more corresponding physical addresses. Memory device 205 (e.g., using device controller 215) can write data to the one or more physical addresses.

[0055] If memory device 205 receives a read command, for example, to read data, then FTL 220-b can identify (e.g., from the read command) one or more logical addresses associated with the data. FTL 220-b can use a data map (e.g., an L2P table) to look up said one or more logical addresses, and if the data is associated with FTL 220-b, then FTL 220-b can return one or more physical addresses corresponding to said one or more logical addresses (e.g., return to device controller 215). If the data is not associated with FTL 220-b, then FTL 220-b can return an indication that the data is not associated with the data map of FTL 220-b (e.g., return to device controller 215), and memory device 205 (e.g., device controller 215) can use FTL 220-a to look up and read the data (e.g., using a lookup mechanism associated with the main L2P table).

[0056] As described herein, some or all of the data stored using information associated with FTL 220-b can be rewritten to be associated with FTL 220-a. For example, a refresh may represent a portion of a garbage collection operation (e.g., associated with FTL 220-a) during which all data associated with FTL 220-b is rewritten to be associated with FTL 220-a. A refresh may occur when memory device 205 is powered off, when FTL 220-b reaches a threshold amount of entries, when a timer expires, or when any combination thereof occurs. Other rewriting techniques for data associated with FTL 220-b may involve rewriting a portion (e.g., but not all) of the data associated with FTL 220-b. For example, data associated with one or more logical or physical addresses may be identified by memory device 205 (e.g., device controller 215) for use in the rewriting process and may be rewritten from being associated with FTL 220-b to being associated with FTL 220-a.

[0057] Figure 3 An example of flowchart 300 is shown, illustrating support for multiple FTLs at a memory device according to the examples disclosed herein. Flowchart 300 may illustrate techniques for selecting a memory device between a first FTL and a second FTL to map data, for example, as described herein. Figure 2 As described. A memory device may represent a reference. Figure 1 and 2 Examples of described memory devices. A first FTL may represent an instance of an FTL configured to map to or have data with a defined granularity, and a second FTL may represent an instance of an FTL configured to map to or have data with a granularity smaller than the defined granularity. Flowchart 300 may illustrate techniques performed at the controller or other components (or a combination thereof) of the memory device, which may be performed, for example, in response to receiving a command and associated data, such as a write command, from a host system or host device (e.g., or from another source external to the memory device).

[0058] At point 305, data may be received (e.g., at a controller or interface) for writing to a memory device. Data may be received from a source external to the memory device (e.g., a host system or host device) within or relative to a write command. The memory device may identify one or more logical addresses of the data, wherein the size of the data may be based on the amount of logical addresses of the data, and wherein the logical addresses may be configured with data alignment or configuration. The memory device may evaluate the data to determine one or more characteristics of the data and determine whether said one or more characteristics of the data match a first FTL or a second FTL.

[0059] At 310, it can be determined (e.g., by the controller of the memory device) whether the data size matches a threshold data size for the first FTL. For example, the threshold may represent the size of the FTL translation unit of the first FTL, or it may represent a defined granularity of the first FTL. If the data size is greater than or equal to the threshold, the memory device can proceed to 315, for example, because the data can be matched to a data mapping technique of the first FTL based on the data size. If the data size is less than the threshold, the memory device can proceed to 330, and the data can be processed and stored using the second FTL, for example, because the data can be matched to a data mapping technique of the second FTL based on the data size (e.g., because the second FTL can be configured for smaller data sizes).

[0060] At 315, it can be determined (e.g., via the controller of the memory device) whether the data alignment matches the data alignment of the first FTL. The data may, for example, contain a number of logical addresses (e.g., LBAs), where the alignment of these logical addresses may or may not match the data alignment of the first FTL (e.g., containing a defined granularity). For example, the first FTL may be configured to process data using a defined granularity or a multiple of a defined granularity. Therefore, if the data contains logical addresses larger than the defined granularity but not a multiple of it, then the data alignment (e.g., at least for a portion of the data) may not match the alignment of the first FTL. For example, the defined granularity may represent four logical addresses (e.g., four LBAs), and the data may contain six logical addresses (e.g., six LBAs), such that four of the data logical addresses match the data alignment of the first FTL, while the remaining two logical addresses may not match.

[0061] Alternatively, data can be configured as data groups (e.g., chunks) for processing at the FTL, and the size of one of the data chunks may not match the defined granularity. For example, the defined granularity may represent four logical addresses (e.g., four LBAs), and data may be configured as a first chunk containing two logical addresses (e.g., two LBAs), a second chunk containing four logical addresses (e.g., four LBAs), and a third chunk containing two logical addresses (e.g., two LBAs). Data may be a multiple of the defined granularity (e.g., eight logical addresses may be a multiple of four logical addresses), but two of the data chunks may be smaller than the defined granularity (e.g., the first and third chunks) and may not match the data alignment of the first FTL.

[0062] In these and other instances, if the data alignment matches the data alignment of the first FTL, the memory device can proceed to step 320, for example, because the data can be matched to the data mapping technique of the first FTL based on the data alignment. Similarly, if the data alignment does not match the data alignment of the first FTL, the memory device can proceed to step 330, and the second FTL can be used to store data (e.g., or an unaligned subset of the data), for example, because the data (e.g., or an unaligned portion thereof) can be matched to the data mapping technique of the second FTL based on the data alignment (e.g., because the second FTL can be configured for data aligned with a smaller granularity).

[0063] At 320, it can be determined (e.g., via the controller of the memory device) whether the available storage for the data (e.g., a free physical address or PBA) matches the data alignment or size of the first FTL. As described herein, the data may contain a number of logical addresses (e.g., LBAs), wherein the alignment or size of one or more of the logical addresses may or may not match the available storage for the data associated with the first FTL.

[0064] For example, a first FTL may be associated with data storage at a defined physical address of a memory device array. The physical address may contain data pages within a data plane, wherein multiple (e.g., two) data planes may be contained in memory dies, and wherein multiple memory dies may be contained within a memory device. The memory device may be configured to store data using a writer that writes data to one or more pages within the plane.

[0065] When data is stored at the array using the first FTL, some physical addresses can be used, and when new data to be written to the memory device is received, the remaining physical addresses of the first FTL can be evaluated for storage. In some cases, the received data may contain an amount of data greater than the number of available pages in the memory device plane, and therefore the data may not match the available storage associated with the first FTL, and may be divided into smaller blocks to be written to the available pages and plane. Therefore, the smaller data may match the data size or alignment of the second FTL, and can be processed using the second FTL instead of the first FTL. In some cases, one or more of the smaller data blocks may match the size or alignment of the available storage of the first FTL, and can be processed accordingly, such that a first portion of the data can be processed using the first FTL, and a second portion of the data can be processed using the second FTL.

[0066] In these and other instances, if the alignment or size of the data matches the available storage associated with the first FTL, the memory device may proceed to step 325, for example, because the data may match the data mapping technique of the first FTL based on the size or alignment of the data relative to the available storage. Similarly, if the alignment or size of the data does not match the available storage associated with the first FTL, the memory device may proceed to step 330, and the second FTL may be used to store the data (e.g., a portion of the data), for example, because the data (e.g., a portion thereof) may match the data mapping technique of the second FTL based on the size or alignment of the data (e.g., because the second FTL may be configured for data associated with a smaller granularity).

[0067] At 325, if, for example, based on the determinations at 310, 315, and 320, data (e.g., a portion thereof) matches a first FTL in terms of size, alignment, or for available storage (e.g., a memory device may determine that data matches a first FTL based on the determinations at 310, 315, and 320), then the data (e.g., a portion thereof) can be processed or stored. It should be understood that the order of the determinations at 310, 315, and 320 is not limited to the examples described herein, and the techniques described with respect to 310, 315, and 320 may be performed in different orders or at different times without departing from the scope of this disclosure.

[0068] At 330, if, for example, based on a determination at one of 310, 315, or 320, data (e.g., a portion thereof) matches a second FTL in terms of size, alignment, or for available storage, then the data (e.g., a portion thereof) can be processed or stored. For example, a memory device can determine that the data matches a second FTL based on a determination at any of 310, 315, or 320 that the characteristics of the data do not match a first FTL.

[0069] Aspects of flowchart 300 may be implemented by a controller and other components. Alternatively, aspects of flowchart 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device or its controller). For example, the instructions, when executed by a controller (e.g., a memory device controller), may cause the controller to perform the operations of flowchart 300.

[0070] Figure 4 An example of a mapping scheme 400 for multiple FTLs at a supporting memory device is shown, according to the examples disclosed herein. Mapping scheme 400 may illustrate techniques for the memory device to store and access mapped data of the FTLs, for example, as described herein. Figure 2 As described. A memory device may represent a reference. Figure 1-3The described memory device instance, and the FTL may represent an instance of an FTL configured to map another FTL for the memory device to data associated with a granularity smaller than the defined granularity or having a granularity smaller than the defined granularity.

[0071] Mapping scheme 400 may represent an instance of a binary tree mapping scheme used to associate logical and physical addresses of data (e.g., for storing L2P information). Memory devices may use binary trees, for example, because they offer greater flexibility and a smaller address space for a smaller FTL compared to other mapping schemes. In the example described herein, mapping scheme 400 may be used to map data associated with a memory array of a specific size (e.g., one gigabyte (GB)), but it may also be used to map data associated with a memory array of any size.

[0072] In the example described herein, mapping scheme 400 can be used to map the logical address of data to the physical address of data within a memory array of one GB in size. After initializing the FTL (e.g., when initializing the memory device, such as after a power cycle), the memory array can divide the address space (e.g., logical address space) of the host system or host device (e.g., or other source external to the memory device) into four 256-megabyte (MB) ranges 405, where each range can be sequential and can contain different logical addresses. For example, range 405-a can contain logical addresses corresponding to megabytes numbered from 0 to 255, range 405-b can contain logical addresses corresponding to megabytes numbered from 256 to 511, range 405-c can contain logical addresses corresponding to megabytes numbered from 512 to 767, and range 405-d can contain logical addresses corresponding to megabytes numbered from 768 to 1023. Each range 405 can be associated with a set of nodes in the binary tree corresponding to the logical address within the corresponding range 405, and any address within range 405 (e.g., a physical address) can be addressed using two bytes or 16 information bits.

[0073] The memory device can define nodes 415 within the binary tree and allocate information structures to nodes 415. The information structure can include a logical address field, a physical address field, a left pointer field, and a right pointer field for each node 415 within the binary tree. Each field can contain two bytes or 16 information bits, such that a node 415 within the binary tree can contain eight bytes or 64 information bits. If 64kB of L2P mapping is used (e.g., 64kB of SRAM), then the FTL can store information for 8,192 nodes 415 of the binary tree in this manner. Similar structures, memory structures, or structures using different amounts of memory can also be implemented without departing from the scope of this disclosure.

[0074] If the memory device receives a write command to write data from a host system or host device (e.g., or from another source outside the memory device), then the memory device (e.g., the memory device's controller) can select between using an FTL and another FTL to store and map the data (e.g., as referenced). Figure 2 and 3 (As described). If FTL is selected, the memory device can identify the logical address associated with the data (e.g., as specified in the write command) and the range 405 associated with the logical address, and whether any node 415 has already been defined for range 405. For example, if root pointer 410 points to the first or initial node of range 405 (e.g., root pointers 410-a, 410-b, and 410-c point to nodes 415-a, 415-b, and 415-c, respectively), then a node can be defined. If node 415 is already defined, the memory device can determine whether the logical address is contained in the defined node 415. If the logical address is contained in the defined node 415, the memory device can update the associated physical address with the new physical address associated with the written data. If the logical address is not contained in the defined node 415, the memory device can construct or create a new node 415 for the logical address. Similarly, if range 405 does not contain any node 415 (e.g., range 405-b), then the memory device can construct or create a new node 415 for a logical address (e.g., the first node within range 405).

[0075] When constructing or creating information for node 415, the memory device may include indications of the logical address, physical address, left pointer 420, and right pointer 420 of the associated node. The logical and physical addresses may represent the logical and physical addresses of the data associated with node 415 (e.g., for L2P mapping). The left and right pointers 420 may each point to a corresponding child node 415 of node 415. For example, the left pointer 420 may point to a child node 415 added to the binary tree after node 415 and having a logical address preceding the logical address of node 415, and the right pointer 420 may point to a child node 415 added to the binary tree after node 415 and having a logical address following the logical address of node 415. In one instance, node 415-b may contain information indicating that the left pointer 420-b points to child node 415-e and the right pointer 420-c points to child node 415-f. Therefore, the logical address of node 415-b (e.g., the fifth LBA within range 405-c) can be after the logical address of node 415-e (e.g., the first LBA within range 405-c) but before the logical address of node 415-f (e.g., the tenth LBA within range 405-c).

[0076] When node 415 is created or initialized, node 415 may not have any child nodes 415, and the left and right pointers 420 may be blank or null until the corresponding child node 415 is added to the binary tree. For example, the right pointer 420 of node 415-a may be blank or null, as may the left and right pointers 420 of node 415-c. Similarly, the root pointer 410 of range 405 may be blank or null until the first or initial node is added to range 405. For example, the root pointer 410 of range 405-b may be blank or null.

[0077] The binary tree structure described herein can be used to look up or read data written to a memory device (e.g., data written using FTL). For example, see references... Figure 2 As described, the memory device can determine, for a read command, whether the data of the read command is associated with an FTL, another FTL, or both. This process can be performed, for example, by identifying the range 405 associated with each logical address indicated by the read command. The memory device can perform a binary search on the associated node 415 to determine whether the logical address is associated with an FTL (e.g., whether the logical address is contained in a binary tree). If the logical address is found in node 415 of the binary tree, the memory device can access the associated physical address from the information associated with node 415, and can access the physical address to execute the read command. If the logical address is not found in node 415 of the binary tree, the memory device can use a lookup mechanism associated with the other FTLs (e.g., to search the main L2P table).

[0078] The binary tree structure can also be refreshed or allowed to rewrite associated data to data locations associated with the other FTLs (e.g., as part of garbage collection). When a refresh is performed, the memory device (e.g., the memory device controller) can perform an ordered traversal of each set of nodes 415 (e.g., for each range 405) and can use the mapping information accessed therein to populate the mapping information of the other FTLs (e.g., larger-granularity FTLs), for example, for read and rewrite operations using the other FTLs. Any node 415 (e.g., all nodes 415) whose associated data is rewritten to a storage location associated with the other FTLs can be destructured (e.g., erased) so that the associated memory (e.g., SRAM memory) can be freed. In some cases, the memory device (e.g., the memory device controller) can use a bitmap (e.g., a hardware- or firmware-managed bitmap) indicating free or allocated nodes 415, which can be used to identify free or empty nodes 415. In some cases, each node 415 can be used once before a refresh (e.g., garbage collection), which simplifies operations associated with binary trees by removing the allocation or deallocation function for searching for free or empty nodes 415.

[0079] In some cases, binary trees can be stored in controller memory (e.g., SRAM) and can be operated using 256kB or less of controller memory (e.g., a node 415 with eight bytes of memory associated with it and 512MB of physical space available for data storage). For example, when the memory area associated with the FTL is at or near full capacity, a binary tree can use a smaller amount of controller memory if the memory area associated with the FTL is reduced and data is cleared from the memory area associated with the FTL using foreground garbage collection.

[0080] If the binary tree is not refreshed before the memory device is powered off or a power cycle is executed, then the binary tree information can be stored in the non-volatile memory of the memory device (e.g., as part of a power-off procedure). The information can be scanned or read when the memory device is powered on (e.g., as part of a power-on recovery process after a power outage), and the binary tree can be reconstructed (e.g., for each range 405). For example, the binary tree information can be re-stored in the corresponding location in SRAM, as before the power outage. In some cases, data blocks can be used when the binary tree is refreshed to indicate that the information in the binary tree and the associated data stored at the memory device are invalid.

[0081] Figure 5 A block diagram 500 illustrates a memory device 505 supporting multiple FTLs at a memory device according to an example disclosed herein. The memory device 505 may be a reference... Figure 1-4Examples of various aspects of the described memory device. Memory device 505 may include a data receiving component 510, an FTL selection component 515, a mapping information component 520, a data reading component 525, and a data rewriting component 530. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0082] The data receiving component 510 can receive data at the memory device and commands to store data at the memory device. In some cases, the command includes an indication of the logical address of the data.

[0083] FTL selection component 515 can select an FTL for storing data based on the structure of the data, the FTL being selected between a first FTL and a second FTL associated with a data storage size smaller than the first FTL. In some instances, FTL selection component 515 can determine that the size of the data is smaller than a threshold size of the data storage associated with the first FTL, wherein the structure of the data includes the size of the data.

[0084] In some instances, the FTL selection component 515 may determine that the alignment of one or more subsets of data fails to match the data alignment associated with the first FTL, wherein the structure of the data includes the alignment of the one or more subsets. In some instances, the FTL selection component 515 may determine that the size or alignment of data fails to match the size or alignment of one or more storage locations associated with the first FTL, wherein the structure of the data includes the size or alignment of the data.

[0085] The mapping information component 520 may store mapping information associated with data at a subset of storage locations of the second FTL based on the selection of the second FTL, the mapping information having a format corresponding to the second FTL. In some cases, the mapping information includes L2P address mappings, which may contain flat lists, hash tables, binary trees, or any combination thereof. In some cases, the binary tree may contain indications of one or more child nodes for each L2P address mapping.

[0086] Data reading component 525 can receive a second command to read second data stored in a memory device. In some instances, data reading component 525 can determine whether the second data is stored using mapping information from a second FTL based on receiving the second command. In some instances, data reading component 525 can read the second data based on determining whether the second data is stored using mapping information from a second FTL. In some instances, data reading component 525 can determine that the second data is stored using second mapping information from a second FTL.

[0087] In some instances, the data reading component 525 may read the second data using the second mapping information from the second FTL based on the determination that the second data is stored using the second mapping information from the second FTL. In some instances, the data reading component 525 may determine that the second data is not associated with the mapping information from the second FTL. In some instances, the data reading component 525 may read the second data using the second mapping information from the first FTL based on the determination that the second data is not associated with the mapping information from the second FTL.

[0088] Data rewriting component 530 can determine whether conditions are met for rewriting data at a memory device. In some instances, data rewriting component 530 can select a first FTL to rewrite data based on the determination that the conditions are met. In some instances, data rewriting component 530 can store second mapping information associated with the data at a subset of storage locations of the first FTL, the mapping information having a format corresponding to the first FTL, based on the selection of the first FTL. In some cases, the conditions include power cycling of the memory device, the number of entries in the mapping information of the second FTL, timer expiration, or any combination thereof.

[0089] Figure 6 A flowchart illustrating one or more methods 600 supporting multiple FTLs at a memory device, according to an example disclosed herein, is shown. Operation of method 600 may be implemented by a memory device or its components as described herein. For example, operation of method 600 may be provided by reference to... Figure 5 The described memory device performs the functions described herein. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0090] One or more aspects of method 600 may be implemented by a controller and other components. Alternatively, one or more aspects of method 600 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device). For example, the instructions, when executed by a controller (e.g., a memory controller), may cause the controller to perform the operation of one or more methods 600.

[0091] At 605, the memory device can receive data and commands to store data at the memory device. Operation 605 can be performed according to the method described herein. In some instances, aspects of operation 605 can be referenced. Figure 5 The described data receiving component is executed.

[0092] At 610, the memory device may select an FTL for storing data based on the structure of the data, the FTL being selected between a first FTL and a second FTL associated with a data storage size smaller than the first FTL. Operation 610 may be performed according to the method described herein. In some instances, aspects of operation 610 may be referenced from... Figure 5 The FTL selection component described is executed.

[0093] At 615, the memory device may store mapping information associated with data at a subset of storage locations of the second FTL based on the selection of the second FTL, the mapping information having a format corresponding to the second FTL. Operation 615 may be performed according to the method described herein. In some instances, aspects of operation 615 may be referenced from... Figure 5 The described mapping information component is executed.

[0094] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving data at a memory device and storing data at a memory device; selecting an FTL for storing the data based on the structure of the data, the FTL being selected between a first FTL and a second FTL associated with a data storage size smaller than the first FTL; and, based on the selection of the second FTL, storing mapping information associated with the data at a subset of storage locations of the second FTL, the mapping information having a format corresponding to the second FTL.

[0095] In some instances of the method 600 and apparatus described herein, selecting an FTL may include operations, features, components, or instructions for: determining that the size of the data may be less than a threshold size of the data storage associated with the first FTL, wherein the structure of the data includes the size of the data. In some instances of the method 600 and apparatus described herein, selecting an FTL may include operations, features, components, or instructions for: determining that the alignment of one or more subsets of the data fails to match the data alignment associated with the first FTL, wherein the structure of the data includes the alignment of said one or more subsets. In some instances of the method 600 and apparatus described herein, selecting an FTL may include operations, features, components, or instructions for: determining that the size or alignment of the data fails to match the size or alignment of one or more storage locations associated with the first FTL, wherein the structure of the data includes the size or alignment of the data.

[0096] Some instances of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: receiving a second command to read second data stored in a memory device; determining, based on receiving the second command, whether the second data can be stored using mapping information from a second FTL; and reading the second data based on determining whether the second data can be stored using mapping information from the second FTL.

[0097] Some instances of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: determining that second data can be stored using second mapping information from a second FTL, and reading the second data using the second mapping information from the second FTL based on the determination that the second data can be stored using the second mapping information from the second FTL. Some instances of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: determining that second data may not be associated with mapping information from a second FTL, and reading the second data using the second mapping information from a first FTL based on the determination that the second data may not be associated with mapping information from the second FTL.

[0098] Some examples of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: determining that conditions for rewriting data at a memory device can be met; selecting a first FTL to rewrite the data based on the determination that the conditions can be met; and storing second mapping information associated with the data at a subset of storage locations of the first FTL, the mapping information having a format corresponding to the first FTL, based on the selection of the first FTL. In some examples of the method 600 and apparatus described herein, the conditions include power cycling of the memory device, the number of entries in the mapping information of the second FTL, the expiration of a timer, or any combination thereof.

[0099] In some instances of the method 600 and device described herein, the mapping information includes L2P address mappings, which may comprise flat lists, hash tables, binary trees, or any combination thereof. In some instances of the method 600 and device described herein, the binary tree contains indications of one or more child nodes for each L2P address mapping. In some instances of the method 600 and device described herein, the command contains indications of the logical address of the data.

[0100] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0101] Describe an apparatus. The apparatus may include a memory array and a controller, the controller being coupled to the memory array and configured to: cause the apparatus to receive data and commands to store the data at the apparatus; select a File Time Limit (FTL) for storing the data based on the structure of the data, the FTL being selected between a first FTL and a second FTL associated with a data storage size smaller than the first FTL; and, based on the selection of the second FTL, store mapping information associated with the data at a subset of storage locations of the second FTL, the mapping information having a format corresponding to the second FTL.

[0102] In some instances of the device, the controller may be further configured to cause the device to determine that the size of the data may be less than a threshold size of the data storage associated with the first FTL, wherein the structure of the data includes the size of the data. In some instances of the device, the controller may be further configured to cause the device to determine that the alignment of one or more subsets of the data fails to match the data alignment associated with the first FTL, wherein the structure of the data includes the alignment of the one or more subsets. In some instances of the device, the controller may be further configured to cause the device to determine that the size or alignment of the data fails to match the size or alignment of one or more storage locations associated with the first FTL, wherein the structure of the data includes the size or alignment of the data.

[0103] In some instances of the device, the controller may be further configured to cause the device to receive a second command to read second data stored at the device, determine, based on receiving the second command, whether the second data can be stored using mapping information from the second FTL, and read the second data based on determining whether the second data can be stored using mapping information from the second FTL. In some instances of the device, the controller may be further configured to cause the device to determine that the second data can be stored using second mapping information from the second FTL, and read the second data using the second mapping information from the second FTL based on determining that the second data can be stored using the second mapping information from the second FTL. In some instances of the device, the controller may be further configured to cause the device to determine that the second data may not be associated with mapping information from the second FTL, and read the second data using the second mapping information from the first FTL based on determining that the second data may not be associated with mapping information from the second FTL.

[0104] In some instances of the device, the controller may be further configured to cause the device to determine that a condition for rewriting the data at the device can be met, select a first FTL to rewrite the data based on the determination that the condition can be met, and store second mapping information associated with the data at a subset of storage locations of the first FTL, the mapping information having a format corresponding to the first FTL, based on the selection of the first FTL. In some instances, the condition includes power cycling changes of the device, the number of entries in the mapping information of the second FTL, timer expiration, or any combination thereof.

[0105] In some instances, the mapping information includes L2P address mappings, which may contain flat lists, hash tables, binary trees, or any combination thereof. In some instances, the binary tree contains indications of one or more child nodes for each L2P address mapping. In some instances, the command contains indications of the logical address of the data.

[0106] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0107] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When, for example, one component of a controller couples other components together, that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0109] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0110] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0111] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0112] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0113] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a long dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0114] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0115] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0116] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that different parts of the functionality are implemented in different physical locations. And, as used herein (included in the claims), the word "or" used in a list of items (e.g., a list of items ending with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0117] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0118] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory array; as well as A controller, coupled to the memory array and configured to cause the device to: Commands to receive data and store the data at the device; It was determined that the alignment of the data failed to match the alignment of one or more storage locations associated with the first flash conversion layer; Based at least in part on the structure of the data including the alignment of the data, a second flash conversion layer for storing the data is selected, wherein the second flash conversion layer is associated with a data storage size different from that of the first flash conversion layer; as well as At least in part, based on the selection of the second flash conversion layer, mapping information associated with the data is stored at a subset of the storage locations of the second flash conversion layer, the mapping information having a format corresponding to the second flash conversion layer.

2. The device of claim 1, wherein the controller is further configured to cause the device to: The size of the data is determined to be less than a threshold size for data storage associated with the first flash conversion layer, wherein the structure of the data includes the size of the data.

3. The device of claim 1, wherein the controller is further configured to cause the device to: It is determined that the alignment of one or more subsets of the data fails to match the alignment of the data associated with the first flash conversion layer, wherein the structure of the data includes the alignment of the one or more subsets.

4. The device of claim 1, wherein the controller is further configured to cause the device to: The size of the data was determined to be mismatched with the size of the one or more storage locations associated with the first flash conversion layer, wherein the structure of the data includes the size of the data.

5. The device of claim 1, wherein the controller is further configured to cause the device to: Receive a second command to read second data stored at the device; At least in part based on receiving the second command, determine whether the second data is stored using the mapping information from the second flash conversion layer; and The second data is read at least in part based on determining whether the second data is stored using the mapping information from the second flash conversion layer.

6. The device of claim 5, wherein the controller is further configured to cause the device to: It is determined that the second data is stored using the second mapping information from the second flash conversion layer; and The second data is read using the second mapping information from the second flash conversion layer, at least in part, based on the determination that the second data is stored using the second mapping information from the second flash conversion layer.

7. The device of claim 5, wherein the controller is further configured to cause the device to: Determine that the second data is not associated with the mapping information from the second flash conversion layer; and The second data is read using the second mapping information from the first flash conversion layer, based at least in part on the determination that the second data is not associated with the mapping information from the second flash conversion layer.

8. The device of claim 1, wherein the controller is further configured to cause the device to: Determine if the conditions for rewriting the data at the device are met; The first flash conversion layer is selected to rewrite the data, at least in part, based on the determination that the conditions are met. as well as At least in part, based on the selection of the first flash conversion layer, second mapping information associated with the data is stored at a subset of the storage locations of the first flash conversion layer, the mapping information having a format corresponding to the first flash conversion layer.

9. The device of claim 8, wherein the conditions include power cyclic variation of the device, the number of entries of the mapping information of the second flash conversion layer, the expiration of a timer, or any combination thereof.

10. The device of claim 1, wherein the mapping information includes a logical-to-physical address mapping, the logical-to-physical address mapping including a flat list, a hash table, a binary tree, or any combination thereof.

11. The device of claim 10, wherein the binary tree includes indications of one or more child nodes for each of the logical-to-physical address mappings.

12. The device of claim 1, wherein the command includes an indication of the logical address of the data.

13. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Commands to receive data and store the data at the electronic device; It was determined that the alignment of the data failed to match the alignment of one or more storage locations associated with the first flash conversion layer; Based at least in part on the structure of the data including the alignment of the data, a second flash conversion layer for storing the data is selected, wherein the second flash conversion layer is associated with a data storage size different from that of the first flash conversion layer; as well as At least in part, based on the selection of the second flash conversion layer, mapping information associated with the data is stored at a subset of the storage locations of the second flash conversion layer, the mapping information having a format corresponding to the second flash conversion layer.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The size of the data is determined to be less than a threshold size for data storage associated with the first flash conversion layer, wherein the structure of the data includes the size of the data.

15. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: It is determined that the alignment of one or more subsets of the data fails to match the data alignment associated with the first flash conversion layer, wherein the structure of the data includes the alignment of the one or more subsets.

16. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: It is determined that the size of the data fails to match the size of one or more storage locations associated with the first flash conversion layer, wherein the structure of the data includes the size of the data.

17. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Receive a second command to read second data stored in the electronic device; At least in part based on receiving the second command, it is determined whether the second data is stored using the mapping information from the second flash conversion layer; as well as The second data is read at least in part based on determining whether the second data is stored using the mapping information from the second flash conversion layer.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: It is determined that the second data is stored using the second mapping information from the second flash conversion layer; and The second data is read using the second mapping information from the second flash conversion layer, at least in part, based on the determination that the second data is stored using the second mapping information from the second flash conversion layer.

19. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Determine that the second data is not associated with the mapping information from the second flash conversion layer; and The second data is read using the second mapping information from the first flash conversion layer, based at least in part on the determination that the second data is not associated with the mapping information from the second flash conversion layer.

20. A method executed by a memory device, the method comprising: Commands to receive data at the memory device and to store the data at the memory device; It was determined that the alignment of the data failed to match the alignment of one or more storage locations associated with the first flash conversion layer; Based at least in part on the structure of the data including the alignment of the data, a second flash conversion layer for storing the data is selected, wherein the second flash conversion layer is associated with a data storage size different from that of the first flash conversion layer; as well as At least in part, based on the selection of the second flash conversion layer, mapping information associated with the data is stored at a subset of the storage locations of the second flash conversion layer, the mapping information having a format corresponding to the second flash conversion layer.

Images