Method for Increasing the Process Window of the Contact Hole and Gate Bridging of a FinFET Device

Abstract

The present invention provides a method for increasing the contact hole and gate bridge process window of a FinFET device, providing a substrate, a fin structure formed on the substrate, the fin structure including a gate and an upper structure formed at the top of the gate, and a protective layer covering the surface of the fin structure; doping the protective layer so that the dielectric constant of the protective layer is reduced, the oxidation resistance and the etching resistance are enhanced; removing the upper structure at the top of the gate and the protective layer on the surface of the upper structure, retaining the protective layer on the side wall of the gate to form a sidewall structure, wherein the sidewall structure protects the gate. The present invention forms a SIOCN sidewall with low-k, oxidation resistance and etching characteristics by ion implantation on the SIOCN surface, thereby increasing the window of the contact hole and gate bridge process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for increasing the process window of the contact hole and gate bridging of a FinFET device. Background Art

[0002] As the device size continues to shrink, the process limits become more apparent, especially the short-circuit situation of the contact hole to the metal gate (MG). When entering the 14nm technology node, the distance between the contact hole and the gate continuously decreases, resulting in an increase in parasitic capacitance. The increase in parasitic capacitance not only reduces the sensitivity of the sensor but also causes the instability of the instrument operation, greatly affecting the AC characteristics of the device. In the FinFET process, SIOCN with a small dielectric constant (k~5) is often used instead of SIN (k~8) as the sidewall to reduce parasitic capacitance. However, because SIOCN has weak antioxidant properties, after being oxidized, it is easily consumed due to continuous wet / etch and other factors in subsequent integration steps, causing an increase in the gate, reducing the process window of the contact hole and metal gate bridging, and even directly causing the short-circuit of the device.

[0003] The SIOCN film is grown by atomic layer deposition method. Generally, the content of C element is adjusted by adjusting the flow rate and pressure of the carbon source, thereby adjusting the dielectric constant (ER) of the material. However, experiments have found that the C content can only be adjusted to about 8% at most and has reached the saturation state, and a higher C content cannot be achieved only by recipe adjustment.

[0004] A method for surface treatment of low-k SIOCN is needed to form a SIOCN sidewall with both low-k and antioxidant and etching characteristics to increase the process window of the contact hole and gate bridging. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for increasing the process window of the contact hole and gate bridging of a FinFET device, which is used to solve the problem in the prior art that a method for surface treatment of low-k SIOCN is needed to form a SIOCN sidewall with both low-k and antioxidant and etching characteristics to increase the process window of the contact hole and gate bridging.

[0006] To achieve the above purpose and other related purposes, the present invention provides a method for increasing the process window of the contact hole and gate bridging of a FinFET device, including:

[0007] Step 1: Provide a substrate, on which a fin structure is formed. The fin structure includes a gate and an upper structure formed on the top of the gate, and a protective layer covering the surface of the fin structure is formed.

[0008] Step 2: Dope the protective layer to reduce the dielectric constant, enhance the antioxidant property, and enhance the etching resistance of the protective layer;

[0009] Step 3: Remove the upper structure at the top of the gate and the protective layer on the surface of the upper structure, and retain the protective layer on the sidewall of the gate to form a sidewall structure, wherein the sidewall structure protects the gate.

[0010] Preferably, the upper structure in Step 1 includes an oxide layer formed on the surface of the top of the gate and a SIN layer formed on the top of the oxide layer.

[0011] Preferably, the doping method in Step 2 is at least one of forming by an IMP ion implantation machine or a DPX machine.

[0012] Preferably, the material of the protective layer in Step 1 is SIOCN.

[0013] Preferably, the protective layer in Step 1 is formed by atomic layer deposition.

[0014] Preferably, in Step 2, the ion doping depth is obtained through the energy of ion implantation; the doping concentration is obtained through the dose of doping ions.

[0015] Preferably, the doping ions in Step 2 are carbon ions.

[0016] Preferably, the ion concentration of the carbon ions in the protective layer is greater than 8%.

[0017] Preferably, the method for removing the upper structure at the top of the gate and the protective layer on the surface of the upper structure in Step 3 includes wet etching and heat treatment.

[0018] As described above, the method for increasing the process window of the contact hole and the gate bridge in the FinFET device of the present invention has the following beneficial effects:

[0019] By ion implanting the SIOCN surface, a SIOCN sidewall with both low-k and antioxidant and etching characteristics is formed, increasing the window of the contact hole and gate bridge process. Brief Description of the Drawings

[0020] Figure 1 It is shown as a schematic flow chart of the method of the present invention.

[0021] Figure 2 It is shown as a schematic diagram of the relationship between the dielectric constant of the protective layer in the embodiment of the present invention and the implantation energy and implantation dose;

[0022] Figure 3It shows a schematic cross-sectional view after forming a fin structure on the substrate according to an embodiment of the present invention;

[0023] Figure 4 It shows a schematic cross-sectional view of the structure after forming a protective layer according to an embodiment of the present invention;

[0024] Figure 5 It shows a schematic cross-sectional view of the structure after forming sidewalls according to an embodiment of the present invention;

[0025] Figure 6 It shows a schematic cross-sectional view of the structure after subsequent process flows according to an embodiment of the present invention. Detailed implementation manners

[0026] The following uses specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please refer to Figure 1 , a method provided by the present invention for increasing the bridging process window between the contact holes and the gate 21 of a FinFET device includes:

[0028] Step 1, please refer to Figure 3 , provide a substrate 1, on which a fin structure 2 is formed. The fin structure 2 includes a gate 21 and an upper structure formed on the top of the gate 21. The gate 21 is a metal gate 21, and a protective layer 3 covering the surface of the fin structure 2 is formed, and the structure as shown in Figure 4 can be obtained;

[0029] In a possible implementation manner, the upper structure in Step 1 includes an oxide layer 22 formed on the top surface of the gate 21, and a SIN layer 23 formed on the top of the oxide layer.

[0030] In a possible implementation manner, 3 in Step 1 is formed by atomic layer deposition, and the thickness of the protective layer 3 is designed as required in the actual process. It should be noted that this includes but is not limited to the ALD growth method, and all other thin film growth methods are included, and the specific method for generating the thin film is not specifically limited.

[0031] In a possible implementation manner, the material of the protective layer 3 in Step 1 is SIOCN.

[0032] Step 2: Dope the protective layer 3 to reduce its dielectric constant, enhance its antioxidant property and etching resistance. In one embodiment, the protective layer 3 is made of SIOCN material, which has weak antioxidant property. After being oxidized, it is likely to be consumed due to subsequent continuous wet / etch and other factors during the integration process, leading to an increase in the gate 21, a reduction in the process window for the bridging of the contact hole and the metal gate 21, and even a direct short circuit of the device. The doped protective layer 3 protects the metal gate 21.

[0033] In one possible implementation, the doping method in Step 2 is at least one of an IMP tool or a DPX tool. It should be noted that this includes but is not limited to IMP tools and DPX tools. All doping tools and processes can be included, and no specific limitation is imposed on the tool model.

[0034] In one possible implementation, the ion doping depth in Step 2 is obtained through the energy of ion implantation; the doping concentration is obtained through the dose of doped ions.

[0035] In one possible implementation, the doped ion in Step 2 is a carbon ion. It should be understood that the carbon ion is only a preferred implementation. Other types of ions can also be used for doping, as long as the dielectric constant, antioxidant property, and etching resistance of the doped protective layer meet the requirements.

[0036] In one possible implementation, the ion concentration of carbon ions in the protective layer 3 is greater than 8%. The 8% concentration is the C content that cannot be achieved by simply adjusting the recipe in the prior art.

[0037] In one possible implementation, please refer to Figure 2 , BL-No IMP is the concentration of C in the SIOCN layer when it reaches the saturation state in the prior art, and its concentration is 8.15%. The dielectric constant of the SIOCN layer is 8.15; 2K is the energy of ion implantation, 1E16 (1 * 10^16) is the dose during ion implantation, its ion concentration is 9.11%, and the dielectric constant is 0.86; 2K is the energy of ion implantation, 2E16 (2 * 10^16) is the dose during ion implantation, its ion concentration is 11.91%, and the dielectric constant is 0.21.

[0038] It can be seen from the experimental data that as the C injection concentration increases, the dielectric constant of the SIOCN layer continuously decreases.

[0039] Step 3: Remove the upper structure at the top of the gate 21 and the protective layer 3 on the surface of the upper structure, and retain the protective layer 3 on the sidewalls of the gate 21 to form a spacer structure, where the spacer structure protects the gate 21.

[0040] In a possible implementation manner, the method for removing the upper structure at the top of the gate 21 and the protective layer 3 on the surface of the upper structure in step three includes wet etching and heat treatment.

[0041] Specifically, please refer to Figure 5 , the SIN layer 23 in the fin structure 2 can be removed by etching, where the oxide layer 22 serves as an etching stop layer. After that, the oxide layer 22 on the gate 21 is removed by cleaning, and then the substrate 1 is further processed to obtain a Figure 6 bridging structure as shown.

[0042] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0043] In summary, in the present invention, by performing ion implantation on the SIOCN surface, a SIOCN sidewall with both low-k and antioxidant and etching characteristics is formed, increasing the window of the contact hole and gate bridging process. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0044] The above embodiments only exemplarily illustrate the principles and effects of the present invention, rather than being used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for increasing the process window of the contact hole and the gate in a FinFET device, characterized in that, it at least includes: Step 1: Provide a substrate, on which a fin structure is formed. The fin structure includes a gate and an upper structure formed on the top of the gate, and a protective layer covering the surface of the fin structure is formed. The protective layer is formed by atomic layer deposition, and the material of the protective layer is SIOCN; Step 2: Dope the protective layer. The doped ion is a carbon ion, and the ion concentration of the carbon ion in the protective layer is greater than 8%, so that the dielectric constant of the protective layer is reduced, the oxidation resistance is enhanced, and the etching resistance is enhanced; Step 3: Remove the upper structure on the top of the gate and the protective layer on the surface of the upper structure, and retain the protective layer on the sidewall of the gate to form a sidewall structure.

2. The method for increasing the process window of the contact hole and the gate in a FinFET device according to claim 1, characterized in that: The upper structure in Step 1 includes an oxide layer formed on the top surface of the gate and a SIN layer formed on the top of the oxide layer.

3. The method for increasing the process window of the contact hole and the gate in a FinFET device according to claim 1, characterized in that: The doping method in Step 2 is formed by using a DPX machine tool of an ion implantation machine tool.

4. The method for increasing the process window of the contact hole and the gate in a FinFET device according to claim 1, characterized in that: In Step 2, the ion doping depth is obtained through the energy of ion implantation; the doping concentration is obtained through the dose of doped ions.

5. The method for increasing the process window of the contact hole and the gate in a FinFET device according to claim 1, characterized in that: The method for removing the upper structure on the top of the gate and the protective layer on the surface of the upper structure in Step 3 includes wet etching and heat treatment.

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