A light-emitting diode and its application

Abstract

This invention proposes a light-emitting diode (LED) and its application, comprising: a substrate; a first semiconductor layer disposed on the substrate; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; a first conductive structure disposed on the first semiconductor layer; and a second conductive structure disposed on the second semiconductor layer; wherein the first conductive structure and the second conductive structure include an adhesive layer, a stretching layer, a stacked layer, and a solder layer disposed sequentially. The LED provided by this invention can improve the soldering effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a light-emitting diode and its applications. Background Technology

[0002] Light-emitting diodes (LEDs) are widely used in backlighting applications due to their energy efficiency, high clarity, and fast response time, making them ideal for various backlighting and display applications. However, flip-chip LEDs must be soldered onto a substrate. Poor substrate flatness leads to poor soldering, high void ratios, and increased failure rates. This is especially true for small LEDs, where the overall board requirements are even higher. Summary of the Invention

[0003] In view of the above-mentioned deficiencies of the prior art, the present invention proposes a light-emitting diode and its application, aiming to improve the defects caused by the stress generated by the thermal expansion during reflow soldering of light-emitting diodes.

[0004] To achieve the above and other objectives, the present invention provides a light-emitting diode (LED) comprising:

[0005] Substrate;

[0006] A first semiconductor layer is disposed on the substrate;

[0007] An active layer is disposed on the first semiconductor layer;

[0008] A second semiconductor layer is disposed on the active layer;

[0009] A first conductive structure is disposed on the first semiconductor layer; and

[0010] A second conductive structure is disposed on the second semiconductor layer;

[0011] The first conductive structure and the second conductive structure include an adhesive layer, a stretching layer, a stacked layer and a welding layer arranged sequentially.

[0012] Optionally, the first conductive structure further includes a leveling layer disposed on the semiconductor, wherein the leveling layer has a height of 900–1500 nm.

[0013] Optionally, the light-emitting diode further includes a transparent conductive layer disposed on the second semiconductor layer, and the second conductive structure disposed on the transparent conductive layer.

[0014] Optionally, the leveling layer is set at the same height as the transparent conductive layer.

[0015] Optionally, the material of the leveling layer is SiO2, SiNx, Al2O3, MgO or AlN.

[0016] Optionally, the adhesive layer of the first conductive structure is disposed on the leveling layer, and the adhesive layer of the second conductive structure is disposed on the transparent conductive layer.

[0017] Optionally, the adhesive layer is made of Cr, Ni, Ti or indium tin oxide.

[0018] Optionally, the material of the stretchable layer is a composite layer formed of an alloy of titanium and aluminum, an alloy of nickel and aluminum, an alloy of titanium and silver, or an alloy of nickel and silver.

[0019] Optionally, the material of the stacked layer is an alloy of platinum and titanium, or an alloy of titanium and nickel.

[0020] Optionally, the material of the weld layer is tin or a gold-tin alloy.

[0021] Optionally, the light-emitting diode is a miniature light-emitting diode.

[0022] The present invention also provides a light-emitting diode display, including the light-emitting diode as described above.

[0023] In summary, this invention proposes a light-emitting diode and its application, utilizing a specially designed electrode structure to give the electrode greater flexibility, which can adapt to defects caused by uneven substrate and stress generated by thermal expansion during reflow soldering, while reducing the encapsulation void rate. Attached Figure Description

[0024] Figure 1 : A schematic diagram of the semiconductor device structure in this embodiment.

[0025] Figure 2 : A schematic diagram of the transition cavity structure in this embodiment.

[0026] Figure 3 : Schematic diagram of the cleaning chamber structure in this embodiment.

[0027] Figure 4 : Schematic diagram of the preheating cavity structure in this embodiment.

[0028] Figure 5 : Schematic diagram of the growth chamber structure in this embodiment.

[0029] Figure 6 This is a simplified schematic diagram of the target material and backplate structure in this embodiment.

[0030] Figure 7 : A simplified schematic diagram of another semiconductor device structure in this embodiment.

[0031] Figure 8 : Schematic diagram of the deposition cavity structure in this embodiment.

[0032] Figure 9 : Schematic diagram of the structure of the first deposition chamber.

[0033] Figure 10 Schematic diagram of the diffuser plate.

[0034] Figure 11 : Schematic diagram of the first and second air intake pipes.

[0035] Figure 12 : Schematic diagram of the substrate inlet.

[0036] Figure 13 : Schematic diagram of the second pipeline.

[0037] Figure 14 : A schematic diagram of the structure of a semiconductor device.

[0038] Figure 15 : A semiconductor epitaxial structure with a hole injection layer.

[0039] Figure 16 : A schematic diagram of a polar surface and a non-polar surface.

[0040] Figure 17 : A diagram of a semiconductor epitaxial structure with a stable wavelength.

[0041] Figure 18 : A diagram of a semiconductor epitaxial structure with a resistive layer.

[0042] Figure 19 : Figure 18 The equivalent circuit diagram of the semiconductor epitaxial structure is shown.

[0043] Figure 20 : A schematic diagram of a miniature light-emitting diode structure.

[0044] Figure 21 : A schematic diagram of a large-angle micro light-emitting diode structure.

[0045] Figure 22 : A schematic diagram of a small-angle micro light-emitting diode structure.

[0046] Figure 23 : Figure 22 The diagram shows the shielding layer structure.

[0047] Figure 24 : A schematic diagram of a shielding layer covering both sides.

[0048] Figure 25 : A schematic diagram of a shielding layer covering all four sides.

[0049] Figure 26 : A schematic diagram of a micro light-emitting diode structure with a filler layer.

[0050] Figure 27 : Figure 26 The diagram shows the structure of the fill layer.

[0051] Figure 28 : Figure 26 The diagram shows the forces acting on a miniature light-emitting diode soldered onto a substrate.

[0052] Figure 29 : Schematic diagram of the emission angle of a micro LED structure without a filler layer.

[0053] Figure 30 : Figure 26 The diagram shows the emission angle of the miniature light-emitting diode.

[0054] Figure 31 : A schematic diagram of a miniature light-emitting diode with metal stacks on its electrodes.

[0055] Figure 32 : A schematic diagram of a miniature light-emitting diode with a special conductive structure.

[0056] Figure 33 : A schematic diagram of a miniature light-emitting diode with a waterproof protective layer.

[0057] Figure 34 : Figure 33 The diagram shows the structure of the protective film layer.

[0058] Figure 35 : Figure 33 Electron micrograph of the prominent structure shown.

[0059] Figure 36 : A schematic diagram showing the angle between the tangent at the edge of a droplet and the reference plane on surfaces with different hydrophobicities.

[0060] Figure 37 : A schematic diagram of a miniature light-emitting diode with a support layer between electrodes.

[0061] Figure 38 : A schematic diagram of a micro light-emitting diode transfer device.

[0062] Figure 39 Top view of the structure of a miniature light-emitting diode transfer device.

[0063] Figure 40 : A schematic diagram of a cutting groove in a miniature light-emitting diode transfer device.

[0064] Figure 41 : A schematic diagram of the cutting position of a miniature light-emitting diode transfer device.

[0065] Figure 42 : A schematic diagram of the structure of a miniature light-emitting diode display panel.

[0066] Figure 43 Top view of a miniature light-emitting diode display panel.

[0067] Figure 44 : A schematic diagram of the structure of an electronic device.

[0068] Figure 45 : A schematic diagram of a semiconductor device structure.

[0069] Figure 46 : A schematic diagram of a radio frequency module structure. Detailed Implementation

[0070] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0071] Please see Figure 1 This embodiment proposes a semiconductor device 100, which may be a chemical vapor deposition device, a physical vapor deposition device, or a combination of physical vapor deposition devices, chemical vapor deposition devices, or other semiconductor devices.

[0072] like Figure 1 As shown, in one embodiment of the present invention, a plurality of chambers are provided within the semiconductor device 100. In one embodiment, the semiconductor device 100 may include, for example, a transfer chamber 110, a preheating chamber 140, a cleaning chamber 130, a transition chamber 120, and a plurality of growth chambers 150. During the semiconductor device manufacturing process, the substrate can first be preheated and plasma cleaned. The cleaned substrate is then transferred to the growth chamber 150, where thin film growth is performed, followed by cooling.

[0073] like Figure 1As shown, in this embodiment, the transfer chamber 110 includes a substrate loading / unloading robotic arm 111, which is operable to transfer substrates between chambers. The size of the substrate loading / unloading robotic arm 111 can also be adjusted according to the spatial dimensions of different chambers. More specifically, the substrate loading / unloading robotic arm 111 may have dual substrate loading / unloading blades adapted to simultaneously transfer two substrates from one chamber to another. The substrates can be transferred between the transfer chamber 110 and other chambers via a slit valve 112. The movement of the substrate loading / unloading robotic arm 111 can be controlled by a motor drive system (not shown), which may include a servo motor or a stepper motor.

[0074] like Figure 1 In some embodiments, the semiconductor device further includes a manufacturing interface 113, which includes a cassette and a substrate loading and unloading robot (not shown). The cassette contains a substrate to be processed, and the substrate loading and unloading robot may include a substrate planning system to load the substrate in the cassette into the transition cavity 120, specifically, to place the substrate on a tray of a stage.

[0075] like Figure 1 In this embodiment, the preheating cavity 140 is connected to the transfer cavity 110. The preheating cavity 140 is located on the side wall of the transfer cavity 110. When the substrate enters the transition cavity 120, the substrate loading and unloading robot arm 111 in the transfer cavity 110 then transfers the substrate from the transition cavity 120 to the preheating cavity 140 for preheating and plasma cleaning.

[0076] like Figure 1 In this embodiment, a plurality of growth chambers 150 are provided on the side wall of the transfer chamber 110. After the substrate completes the corresponding process, the substrate loading and unloading robot arm 111 in the transfer chamber 110 transfers the substrate to the growth chamber 150 for operation. Since a uniform magnetic field is formed in the growth chamber 150, uniform sputtered ions can be formed on the surface of the substrate, thereby forming a uniform thin film on the substrate.

[0077] like Figure 2 In this embodiment, the transition cavity 120 is connected to the transfer cavity 110, and the transition cavity 120 is located between the manufacturing interface 113 and the transfer cavity 110. The transition cavity 120 provides a vacuum interface between the manufacturing interface 113 and the transfer cavity 110.

[0078] like Figure 1 and Figure 2In some embodiments, the transition cavity 120 can realize the processes of substrate transfer, preheating, and cleaning. The transition cavity 120 includes a housing 120a, which is, for example, a sealed cylinder, and has an exhaust port and a suction port on its sidewall. The transition cavity 120 is provided with multiple air passages, such as air inlets 128. By installing multiple air passages, such as air inlets 128, and a power supply within the transition cavity 120, the baking preheating and plasma cleaning processes are realized. A separate pump is used for gas pumping, making the entire process smoother and saving overall time.

[0079] like Figure 2 In some embodiments, a platform 122 is provided within the transition cavity 120, and the platform 122 is fixed to the bottom of the housing 120a by a lifting base motor 121. A tray 123 can be mounted on the platform 122, and a multi-layer open transfer box 124 can be mounted on the tray 123 to facilitate simultaneous transfer of trays. In this embodiment, the platform 122 can be, for example, cylindrical, rectangular, or other shapes, and can be fixed within the housing 120a by, for example, a lifting base motor 121. A laser sensor 125 can be installed inside the housing 120a. The transition cavity 120 allows multiple trays to enter simultaneously, requiring only one vacuuming at the beginning and one atmospheric filling at the end, saving the frequent filling and evacuation time during intermediate tray transfers and reducing the filling and evacuation time of the transmission nodes.

[0080] like Figure 1 and Figure 2 In some embodiments, the transition chamber 120 further includes an exhaust port connected to a vacuum pump 327, which evacuates the transition chamber 120. Multiple N2 gas paths are added to the transition chamber 120 to allow gas to enter, providing gas cooling instead of a cooling chamber when the chamber is not in use.

[0081] Please refer to the following: Figure 1 and Figure 2 In another embodiment of the present invention, the transition cavity 120 only performs the function of transferring the substrate, while the cleaning cavity 130 performs plasma cleaning and cooling of the substrate. In this embodiment, the cleaning cavity 130 is connected to the transfer cavity 110 and is located on the side wall of the transfer cavity 110. When the substrate enters the transition cavity 120, the substrate loading and unloading robot arm 111 in the transfer cavity 110 then transfers the substrate from the transition cavity 120 to the cleaning cavity 130 for cleaning. After a thin film is grown on the substrate, the substrate is transferred to the cleaning cavity 130 for cooling.

[0082] like Figure 3A substrate support assembly 131 is disposed within the cleaning chamber 130. The substrate support assembly 131 is located at the bottom of the cleaning chamber 130 and does not contact the cleaning chamber 130. The substrate support assembly 131 includes a platform electrode 1311 and an electrostatic chuck 1312. The electrostatic chuck 1312 is disposed on the platform electrode 1311 and is used to place a substrate. At least one substrate can be placed on the electrostatic chuck 1312. In some embodiments, multiple substrates can be placed on the electrostatic chuck 1312, and multiple substrates can be cleaned simultaneously, thereby improving work efficiency.

[0083] like Figure 3 In this embodiment, the substrate support assembly 131 is connected to a lifting and rotating mechanism 134. Specifically, the lifting and rotating mechanism 134 is connected to the platform electrode 1311. The lifting and rotating mechanism 134 can realize the lifting or rotating of the substrate support assembly 131, thereby indirectly realizing the lifting or rotating of the substrate. When the substrate support assembly 131 rotates and rises or falls, the distance between the substrate and the electrode 132 changes, thereby adjusting the electric field strength between the platform electrode 1311 and the electrode 132, so that the plasma can better clean the substrate.

[0084] like Figure 3 In this embodiment, the cleaning chamber 130 also includes an electrode 132, which is disposed above the substrate support assembly 131. The electrode 132 does not contact the top of the cleaning chamber 130. In some embodiments, the distance between the electrode 132 and the substrate support assembly 131 can be 2-25 cm. The electrode 132 is also connected to a lifting and rotating mechanism 133, which has the same structure as the lifting and rotating mechanism 134. When the electrode 132 rotates and rises or falls, the distance between the electrode 132 and the substrate changes to adjust the electric field strength between the electrode 132 and the substrate, so that the plasma can clean the substrate uniformly. When the electrode 132 and the substrate support assembly 131 rotate simultaneously, the rotation speed of the electrode 132 and the rotation speed of the substrate support assembly 131 can be the same or have a certain speed difference, so that the plasma cleans the substrate uniformly.

[0085] like Figure 3 In this embodiment, the substrate support assembly 131 is also connected to at least one radio frequency (RF) bias power supply 138, specifically, the RF bias power supply 138 is connected to the stage electrode 1311. The RF frequency of the RF bias power supply 138 can be high frequency, medium frequency, or low frequency. Both the RF power supply 137 and the RF bias power supply 138 are driven by a synchronization pulse, enabling them to switch on and off simultaneously, reducing the electronic temperature within the cleaning chamber 130. Furthermore, the synchronization pulse provides good control over the cleaning (etching depth) of densely packed areas of the substrate.

[0086] like Figure 3 In this embodiment, the cleaning chamber 130 further includes an air inlet located near the electrode 132. The air inlet is connected to a gas source 135, through which gas is supplied to the cleaning chamber 130. This gas is a precursor gas used in the cleaning application. In this embodiment, the cleaning chamber 130 also includes an exhaust port located near the substrate support assembly 131. This exhaust port is connected to a vacuum pump 136, which is used to extract gas from the cleaning chamber 130.

[0087] like Figure 1 , Figure 3 and Figure 4 As shown, in another embodiment of the present invention, during semiconductor fabrication, the substrate needs to be preheated in a preheating chamber 140 before growing a thin film on it. The preheated substrate is then transferred to a cleaning chamber 130 for cleaning, and the cleaned substrate is transferred to a growth chamber 150 for thin film growth. After thin film growth is complete, it is then transferred back to the cleaning chamber 130 for cooling. During the thin film formation process, heat loss due to preheating the substrate in the preheating chamber 140 and cleaning in the cleaning chamber 130 is likely. In this embodiment, a cleaning structure is added to the preheating chamber 140 to simultaneously perform plasma cleaning on the substrate while it is being preheated.

[0088] like Figure 4 As shown, in another embodiment of the present invention, the preheating chamber 140 includes a housing 140a, and a support 141 is provided at the bottom of the housing 140a. The support 141 may be, for example, a hollow structure. Then, the wires are placed in the internal structure of the support 141 and connected to the heater 142. In this embodiment, the support 141 may be, for example, a high-temperature resistant material.

[0089] like Figure 4 A heater 142 is installed inside the preheating chamber 140 and is fixed to the bracket 141. The heater 142 may include a chassis and a heating coil disposed at the bottom of the chassis. Multiple measuring points are also provided on the side of the tray 143 near the substrate 144, and these measuring points are connected to a temperature measuring device. The temperature measuring device may be located inside or outside the preheating chamber 140. The temperature on the substrate 144 can be measured in real time using this temperature measuring device, thereby controlling the surface temperature and thermal uniformity of the substrate 144.

[0090] like Figure 4At least one evacuation port may be provided at the bottom of the preheating chamber 140. This evacuation port is connected to a vacuum pump 145, which evacuates the preheating chamber 140 to obtain a vacuum state. At least one heater 142 is provided inside the preheating chamber 140. It should be noted that multiple heaters 142 may also be provided on the side wall of the preheating chamber 140 or on the top of the preheating chamber 140 to ensure the uniformity of the overall temperature of the preheating chamber 140.

[0091] Please refer to the following: Figure 4 At least one electrode 149 can be disposed at the top of the preheating cavity 140, above the substrate 144. The electrode 149 does not contact the top of the preheating cavity 140, and the distance between the electrode 149 and the substrate 144 can be 2–25 cm, for example, 10–20 cm, or 16–18 cm. The electrode 149 is also connected to a lifting and rotating mechanism 146, which can be coupled with… Figure 3 The lifting and rotating mechanism 133 in the middle has the same structure. When the electrode 149 rotates to rise or fall, the distance between the electrode 149 and the substrate changes to adjust the electric field strength between the electrode 149 and the substrate, so that the plasma can clean the substrate uniformly.

[0092] Please refer to the following: Figure 3 and Figure 4 A lifting and rotating mechanism 134 and an RF bias power supply 138 may also be provided on the support 141 and the heater 142. When the electrode 149 and the substrate 144 rotate simultaneously, the rotation speed of the electrode 149 and the rotation speed of the substrate 144 on the heater 142 may be the same or have a preset speed difference, so as to ensure uniform plasma cleaning of the substrate. The electrode 149 is also connected to at least one RF power supply 148, which... Figure 3 The RF power supply 148 shown has the same settings.

[0093] Please refer to the following: Figure 4 An air inlet is also provided on the side wall of the preheating chamber 140. The air inlet is close to the electrode 149 and is connected to a gas source 147. Gas is supplied to the preheating chamber 140 through the gas source 147. The gas is a precursor gas for cleaning applications.

[0094] Please refer to the following: Figure 1 , Figure 3 and Figure 4The plasma cleaning process needs to be carried out in a high-temperature, constant environment. A plasma cleaning device is installed in the preheating chamber 140, which can simultaneously perform plasma cleaning on the substrate while preheating it. After heating the substrate in the preheating chamber 140, it does not need to be transferred to the cleaning chamber 130 for cleaning. After preheating and cleaning in the preheating chamber 140, it can be directly transferred to the growth chamber 150 to form a thin film.

[0095] Please see Figures 5 to 7 The growth chamber 150 includes a growth chamber shell 151, a base 152, a target material 153, and a magnet 154. A circulating water cooling device 1508 is installed inside or on the sidewall of the growth chamber 150, such as... Figure 5 As shown. A base 152 may be disposed at the bottom end of the growth chamber housing 151, allowing one or more substrates 155 to be placed on the base 152. The base 152 may be formed of various materials, including silicon carbide or graphite coated with silicon carbide. The base 152 is also connected to a drive unit 156, which is connected to a control unit (not shown). The drive unit 156 is used to drive the base 152 to rise or fall. The drive unit 156 may employ a drive device such as a servo motor or a stepper motor. The control unit is used to control the drive unit 156 to drive the base 152 to rise during magnetron sputtering, so that the distance between the target 153 and the base 152 remains constant at a predetermined value.

[0096] Please see Figures 5 to 7 In this embodiment, the target 153 is disposed on the top of the growth chamber housing 151. The target 153 is electrically connected to a sputtering power supply (not shown). During magnetron sputtering, the sputtering power supply outputs sputtering power to the target 153, causing the plasma formed within the growth chamber housing 151 to etch the target 153. The target 153 has at least one surface portion composed of material to be sputtered and deposited on a substrate 155 disposed on a base 152. When the magnet 154 in the process chamber is the same size as the tray, for example, less than or equal to 330 mm, the aluminum nitride deposition thickness is relatively thin at the outer edge of the tray, which will affect the overall thickness uniformity. In this embodiment, the target 153 and the backplate 1509 are enlarged as a whole, and the diameter of the bombarded surface of the target 153 is set to be greater than or equal to, for example, 400 mm to 600 mm, so the diameter of the magnet operating coverage surface is greater than or equal to 400 mm to 600 mm. A protective ring 1510, which is a ceramic ring or a stainless steel ring, surrounds the target 153 and the backplate 1509 on the outside. In some embodiments, after the substrate 155 is loaded into the growth chamber housing 151, a continuous aluminum nitride film can be deposited on the substrate 155 using an aluminum-containing target and a nitrogen-containing processing gas. The processing gas used during the sputtering process may include, but is not limited to, nitrogen-containing gas and inert gas.

[0097] Please see Figures 5 to 7In this embodiment, the magnet 154 is located above the target 153. The magnet 154 rotates around the central axis of the target 153, and can rotate at any angle around the central axis of the target 153. In this embodiment, the magnet 154 is connected to a driving mechanism. The driving mechanism drives the magnet 154 to rotate and also to reciprocate up and down. The driving mechanism includes a first motor 157, a transmission rod 158, a second motor 159, and a lifting assembly. The first motor 157 is connected to the second motor 159 through the transmission rod 158. The first motor 157 can drive the second motor 159 to reciprocate up and down through the transmission rod 158. The first motor 157 can drive the transmission rod 158 to rotate in the forward or reverse direction to make the second motor 159 reciprocate. In this embodiment, the lifting assembly includes an outer shaft 1501 and an inner shaft 1502. A second motor 159 is connected to the inner shaft 1502 via an output shaft 1504, part of which is located within the outer shaft 1501. The second motor 159 can drive the inner shaft 1502 to rotate via the output shaft 1504. Simultaneously, a first motor 157 drives the second motor 159 to reciprocate up and down via a transmission rod 158. When both the first motor 157 and the second motor 159 are simultaneously activated, the inner shaft 1502 can perform both reciprocating up and down motion and rotational motion, thereby causing the magnet 154 on the inner shaft 1502 to move accordingly. When the first motor 157 is activated and the second motor 159 is deactivated, the inner shaft 1502 only performs reciprocating up and down motion. When the first motor 157 is deactivated and the second motor 159 is activated, the inner shaft 1502 only performs rotational motion. Thus, the operator can choose to turn the first motor 157 and / or the second motor 159 on or off depending on the situation.

[0098] Please see Figures 5 to 7 In some embodiments, when the magnet 154 rotates, the target 153 can remain stationary or rotate around its central axis, but a velocity difference exists between the target 153 and the magnet 154. The relative motion between the target 153 and the magnet 154 allows the magnetic field generated by the magnet 154 to uniformly scan the sputtering surface of the target 153. Furthermore, since the electric field and the magnetic field uniformly distributed on the sputtering surface of the target 153 act simultaneously on the secondary electrons in this embodiment, the trajectory of the secondary electrons can be adjusted to increase the number of collisions between the secondary electrons and argon atoms, resulting in the argon atoms near the sputtering surface of the target 153 being fully ionized to generate more argon ions. By bombarding the target 153 with more argon ions, the sputtering utilization rate and sputtering uniformity of the target 153 can be effectively improved, further enhancing the quality and uniformity of the deposited thin film.

[0099] In one embodiment of the present invention, for a semiconductor device whose preheating chamber can realize preheating and cleaning functions, this application also proposes a method of using the semiconductor device, including:

[0100] S11: Place the multi-layer open-type transfer box in the transition cavity onto the tray, and transfer the substrate to the preheating cavity;

[0101] S12: Preheat in the preheating chamber and pass gas through for plasma cleaning;

[0102] S13: Grow a thin film in the growth chamber;

[0103] S14: Gas is introduced into the cleaning chamber to cool the tray.

[0104] like Figure 1 and Figure 8 As shown, in one embodiment of the present invention, if the semiconductor device 100 is, for example, a chemical vapor deposition device, then multiple deposition chambers are provided on the sidewall of the transfer chamber 110. This embodiment shows four deposition chambers: a first deposition chamber 161, a second deposition chamber 162, a third deposition chamber 163, and a fourth deposition chamber 164. A robotic arm 311 within the transfer chamber 110 can sequentially feed a substrate or wafer into the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163, and the fourth deposition chamber 164 to form a thin film on the substrate or wafer. In this embodiment, at least one of the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163, and the fourth deposition chamber 164 is a detachable chamber, meaning that the chamber can be individually removed without affecting the operation of the entire semiconductor device 100. In this embodiment, for example, the first deposition chamber 161 is configured as a detachable chamber. In other embodiments, a single detachable chamber may be provided.

[0105] like Figure 9 As shown, Figure 9 The diagram shows a cross-sectional view of the first deposition chamber 161. As can be seen from the figure, the first deposition chamber 161 includes a main chamber 101, within which a base 102 is disposed. The base 102 can be located at the bottom of the main chamber 101. An radio frequency (RF) component 103 is disposed at the top of the main chamber 102, and the RF component 103 and the base 102 are positioned opposite each other. The RF component 103 and the base 102 form a plasma generation region. The main chamber 101 is made of, for example, stainless steel. In some embodiments, the RF component 103 can also be rotated during the deposition process, thereby resulting in more uniform thin film deposition.

[0106] like Figure 9 As shown, in some embodiments, the base 102 may also be connected to a rotating unit for rotating the base 102 during film deposition to further improve the thickness uniformity of the coating and the stress uniformity of the coating.

[0107] like Figure 9As shown, in some embodiments, a heating unit can also be provided on the back of the base 102 to heat the substrate. In some embodiments, the heating unit can be a radio frequency heater, an infrared radiation heater, or a resistance heater, etc., and can be selected according to the size and material of the main cavity 101. In the radio frequency heating method, the graphite base 102 is heated by the radio frequency coil through induced coupling. This heating method can be applied to large main cavities 101.

[0108] like Figure 9 As shown, in this embodiment, the radio frequency component 103 is also connected to a radio frequency power supply, which provides voltage to the radio frequency component 103 to ionize the reaction source gas into plasma.

[0109] like Figure 9 As shown, in this embodiment, an air inlet is further included at the top of the main cavity 101. An air inlet pipe 104 is connected to the air inlet, with one end of the air inlet pipe 104 connected to the air inlet and the other end of the air inlet pipe 104 connected to an external air source 105. Through the external air source 105, the air inlet pipe 104 and the air inlet can deliver the reaction gas into the main cavity 101.

[0110] like Figure 9 As shown, in this embodiment, the air inlet is located on one side of the radio frequency component 103, and the air inlet pipe 104 includes a first pipe 1041 and a second pipe 1042. One end of the first pipe 1041 is connected to an external air source 105, and the other end of the first pipe 1041 is connected to the second pipe 1042. The first pipe 1041 is connected to the second pipe 1042, for example, via a quick connector 107. The first pipe 1041 and the second pipe 1042 can be connected or disconnected by rotating the quick connector 107. A first valve body 106 is provided on the first pipe 106. When gas is supplied to the main cavity 101, the first valve body 106 is, for example, in an open state. When the cavity needs to be disassembled, the first valve body 106 is, for example, in a closed state, thereby preventing heavy metal dust from entering the cleanroom.

[0111] like Figure 9 and Figure 10 As shown, in this embodiment, one end of the second pipe 1042 extends into the main cavity 101, and a diffuser plate 108 is provided at one end of the second pipe 1042. The diffuser plate 108 has a plurality of diffusion holes 1081. The reactant gas can diffuse evenly into the main cavity 101 through the diffusion holes 1081. It should be noted that the diameters of these diffusion holes 1081 can be the same or different, and the arrangement density of these diffusion holes 1081 can also be changed.

[0112] like Figure 9 and Figure 11As shown, in some embodiments, multiple air inlets can be provided at the top of the main cavity 101, that is, multiple air inlet pipes 104 can be provided, such as a first air inlet pipe 104a and a second air inlet pipe 104b. The first air inlet pipe 104a can be connected to a first air inlet device, and the second air inlet pipe 104b can be connected to a second air inlet device. The first air inlet pipe 104a and the second air inlet pipe 104b are located on both sides of the main cavity 101, and the height of the first air inlet pipe 104a is greater than the height of the second air inlet pipe 104b. Since there is a height difference between the first air inlet pipe 104a and the second air inlet pipe 104b, the gas delivered to the main cavity 101 through the first air inlet pipe 104a and the second air inlet pipe 104b will not affect each other.

[0113] like Figure 9 As shown, in this embodiment, at least one exhaust port is provided at the bottom of the main cavity 101. One end of the exhaust pipe 109 is connected to the exhaust port, and the other end is connected to a vacuum pump 1013. The vacuum pump 1013 performs a vacuuming operation on the main cavity 101 to remove excess plasma, thereby reducing the probability of excess ions falling onto the thin film and improving the quality of the thin film. A second valve body 1014 is also provided at the bottom of the main cavity 101. The second valve body 1014 is located on the exhaust port. When vacuuming is performed, the second valve body 1014 is in the open state. When the deposition operation is completed, the second valve body 1014 can be in the closed state to prevent plasma from diffusing out.

[0114] like Figure 8 and Figure 12 As shown, in this embodiment, the main cavity 101 also includes a substrate inlet. The robotic arm in the transfer cavity 110 places the substrate into the main cavity 101 through the substrate inlet. The substrate inlet includes two telescopic doors 1011. When the two telescopic doors 1011 are open, the substrate inlet is opened. When the two telescopic doors 1011 are closed, the substrate outlet is closed. The main cavity 101 is also connected to a locking unit 1012. When the main cavity 101 is disassembled, the locking unit 1012 can keep the substrate inlet locked. That is, when the main cavity 101 is powered off, the locking unit 1012 can keep the substrate inlet closed or locked. When the substrate inlet is locked, it can prevent the remaining plasma in the main cavity 101 from diffusing into the cleanroom, thereby preventing heavy metal contamination of the cleanroom.

[0115] like Figure 9As shown, in this embodiment, the substrate inlet can also serve as a substrate outlet, meaning the robotic arm can place the substrate into or remove the substrate from the main cavity 101 through the substrate inlet. In some embodiments, the main cavity 101 may also include a substrate outlet, meaning the substrate outlet is positioned opposite to the substrate inlet. Therefore, when the robotic arm places the substrate into the main cavity 101 through the substrate inlet and then removes the substrate from the main cavity 101 through the substrate outlet, since the substrate outlet and substrate inlet are positioned opposite each other, heavy metal dust in the main cavity 101 will not diffuse into the cleanroom when the substrate outlet is opened, thus preventing cleanroom contamination.

[0116] like Figure 13 As shown, in some embodiments, the end of the second conduit 1042 may also be designed to be bent, with the bend facing between the radio frequency component 103 and the base 102, so that gas diffuses between the radio frequency component 103 and the base 102.

[0117] like Figure 1 and Figure 9 As shown, in this embodiment, the semiconductor device 100 includes a transfer cavity 110 and a detachable cavity. The robotic arm 311 in the transfer cavity 110 transfers or moves the substrate out of the detachable cavity. When the operation is completed in any cavity (including preheating, cleaning, deposition, growth, and cooling), the first valve and the second valve are closed, so that the gas in the gas source cannot enter the detachable cavity, and the reaction gas in the detachable cavity cannot be discharged from the exhaust port. At the same time, the substrate inlet of the detachable cavity is closed by the locking unit. Then the detachable cavity is moved to another cleanroom, the substrate inlet is opened, and the substrate is taken out, thereby avoiding heavy metal contamination of the original cleanroom. Then the detachable cavity can be maintained, and then the detachable cavity is placed outside the transfer cavity 310.

[0118] like Figure 14 In some embodiments, the coating system 180 of the semiconductor device 100 is provided with multiple reaction chambers 170. The reaction chambers 170 can be growth chambers in a physical vapor deposition (PVD) apparatus or deposition chambers in a chemical vapor deposition (CVD) apparatus. In this embodiment, the reaction chambers 170 include, for example, a first reaction chamber 171 and a second reaction chamber 172. Both the first and second reaction chambers 171 and 172 are provided with two door openings, such as a first door 173 and a second door 174. Each door corresponds to a substrate loading / unloading robotic arm 111 for transport, for example, a first robotic arm 111a corresponding to the first door 173 and a second robotic arm 111b corresponding to the second door 174. An air inlet pipe 183 and a transport track 181 are also provided on one side of the reaction chamber 170. The first and second reaction chambers 171 and 172 are connected by an opening and closing valve, which facilitates substrate transport and improves processing efficiency.

[0119] like Figure 14 As shown, the first chamber door 173 and the second chamber door 174 are disposed on the first reaction chamber 171 and the second reaction chamber 172. In some embodiments, the first chamber door 173 and the second chamber door 174 are disposed on the same side of the reaction chamber; in other embodiments, the first chamber door 173 and the second chamber door 174 are disposed on opposite sides of the reaction chamber. The specific structure of the first chamber door 173 and the second chamber door 174 can be as follows: Figure 12 The telescopic gate shown will not be described again here. In the actual thin film growth process, the first chamber gate 173 serves as the substrate inlet / outlet, and the second chamber gate 174 serves as the substrate outlet / inlet. Separating the substrate outlet from the substrate inlet reduces substrate contamination. The substrate loading / unloading robotic arms 111, corresponding to the chamber gates, include a first robotic arm 111a and a second robotic arm 111b. During substrate transfer, the first robotic arm 111a can, for example, pass through the first chamber gate 173 to transfer the substrate into the reaction chamber 170, and the second robotic arm 111b can, for example, pass through the second chamber gate 174 to transfer the substrate out of the reaction chamber 170. Having two robotic arms facilitates substrate pickup, simultaneous substrate transfer, and separation between the transfer and loading / unloading robotic arms 111, further reducing substrate contamination and improving the quality and uniformity of the deposited thin film.

[0120] like Figure 14 As shown, the base 152 (or base 102) is disposed at the top of the reaction chamber 170, and the target 153 (or radio frequency assembly 103) is disposed at the bottom of the reaction chamber 170. Figure 5 (or Figure 9 The positions of the reactants are reversed, with the reactants moving from bottom to top. In some embodiments, the base 152 has a fixing clip for fixing the substrate. In this embodiment, the base 152 is a magnetic base, allowing multiple magnetic bases to be placed on opposite sides of the target 153. In this case, the base 152 can directly adsorb the substrate onto the base 152 without the need for other structures to fix the substrate. The base 152 may be made of materials such as sapphire, silicon carbide, silicon, gallium nitride, diamond, lithium aluminate, zinc oxide, tungsten, copper, and / or aluminum gallium nitride, and a metal layer may be deposited on the base 152 to make the base 152 metallic. A magnet is provided inside the base 152 to give the base 152 an adsorption function. When the magnet rotates, the base 152 can rotate around its own central axis. When the magnet rotates, the base 152 can be driven to rotate around its own central axis by a power source such as an electric motor, so that the magnetic field generated by the magnet tightly attracts the base 152, further improving the quality and uniformity of the deposited film, and the size of the base 152 is, for example, 2-12 inches.

[0121] like Figure 14As shown, the transfer track 181 connects the reaction chamber 170 to other semiconductor devices, such as connecting the chamber door to other semiconductor devices, which may be cleaning devices, preheating devices, or other semiconductor devices. An inlet pipe 182 connects to an external gas source, which supplies gas into the reaction chamber 170 through the inlet pipe 182. The inlet pipe 182 may include a first inlet pipe and a second inlet pipe. The first inlet pipe connects to the first reaction chamber 171, and the second inlet pipe connects to the second reaction chamber 172. This inlet pipe design facilitates gas input and output.

[0122] The semiconductor device of this application can manufacture high-quality, pollution-free thin films, such as metal thin films, semiconductor thin films, insulating thin films, compound thin films, or thin films of other materials.

[0123] like Figure 15 As shown, in one embodiment of the present invention, when a semiconductor epitaxial structure 20 is manufactured using the semiconductor device disclosed herein, the semiconductor epitaxial structure 20 may include a substrate 200, and a first semiconductor layer 203, an active layer 204, and a second semiconductor structure 21 sequentially disposed on the substrate 200.

[0124] like Figure 15 As shown, the substrate 200 can be a sapphire substrate 200. In other embodiments, the substrate 200 can also be made of materials such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and lithium aluminate (LiAlO2).

[0125] like Figures 15 to 16 As shown, in some embodiments, the substrate 200 can be made of a crystal axis material without polarization reaction, the material of the substrate 200 having a crystal axis without piezoelectric effect, or a special planarization layer can be formed on the substrate 200 to select the crystal phase orientation of the substrate 200 and eliminate the influence of piezoelectric effect on the substrate 200. In some embodiments, the substrate 200 can be made of an N-plane (1100) or A-plane (1120) material, such as GaN, AlN, and InN. In other embodiments, when the substrate 200 is made of other substrates, such as silicon-based materials such as SiCO3 and SiC, a planarization layer can be formed on the substrate 200 to eliminate lattice defects. The material of the planarization layer can be a compound composed of a group IIA element and nitrogen, specifically, for example, a nonpolar AlN material or a nonpolar GaN material. By selecting a special crystal axis material or setting a planarization layer, the generation of lattice torsion in the substrate 200 when a large current is introduced can be avoided, which would lead to piezoelectric voids and cause thermal cracking of the material.

[0126] like Figure 15As shown, in some embodiments, to obtain a flat substrate 200 surface, after grinding and polishing the substrate 200 surface, stress marks are present on the substrate 200 surface, which can create defects with the semiconductor layer disposed thereon. The fragmented grains on the substrate 200 surface can be oxidized to form fragmented oxide, and then the fragmented oxide is cleaned using an oxide etching solution to obtain a flat substrate 200 surface. In a specific embodiment, the substrate 200 is, for example, a silicon substrate, which can undergo preliminary surface processing such as grinding or polishing to form silicon fragmented grains on the substrate 200 surface. The generation of fragmented grains causes stress marks on the crystal lattice, affecting crystal growth, and therefore requires treatment of the fragmented grains. In this embodiment, physical or chemical methods can be used to eliminate the influence of the fragmented grains. When using physical methods, the substrate 200 can be heated in a preheating chamber to reach, for example, 300-400 degrees Celsius, while oxygen or other oxides are introduced into the chamber to cause an oxidation reaction of the fragmented grains, generating fragmented oxide. When using chemical methods, oxidants such as hydrogen peroxide can be used to react with the fragmented particles to generate fragmented oxides. During the reaction, the oxidation rate can be increased by raising the temperature, for example, from 40 to 80 degrees Celsius. In this embodiment, the fragmented oxide is silicon dioxide. After oxidation, a dense silicon dioxide layer is formed on the surface of the substrate 200, which can be cleaned with an oxide etching solution to obtain a substrate 200 with a complete crystal structure, free of fragmented defects. In this embodiment, hydrofluoric acid or ammonium sulfide can be used to remove the fragmented oxide. In other embodiments, the substrate 200 material is not limited to silicon substrates; SiC substrates and other substrates can also be selected. Due to the different materials of the substrate 200, different methods can be used to oxidize the fragmented particles, and different solutions can be used to remove the fragmented oxide.

[0127] like Figure 15As shown, in some embodiments, a buffer layer 201 is disposed between the first semiconductor layer 203 and the substrate 200 to mitigate lattice mismatch between the first semiconductor layer 203 and the substrate 200, thereby preventing defects such as dislocations, stacking faults, or voids. The material of the buffer layer 201 can be, but is not limited to, materials such as aluminum nitride or gallium nitride, but the buffer layer 201 is insufficient to solve the lattice mismatch problem, thus generating voids. In this embodiment, by disposing of a transition metal layer between the substrate 200 and the buffer layer 201, the lattice mismatch problem between the first semiconductor layer 203 and the buffer layer 201 can be further mitigated. The material of the transition metal layer can be a Group IIA element, such as aluminum, as the lattice layer. After depositing the transition metal layer on the substrate 200, the transition metal layer is annealed to form an annealing interface between the surface of the silicon substrate 200 and the transition layer. During annealing, the cavity is filled with an inert gas, such as nitrogen. During the annealing process, at the interface between the transition metal layer and the substrate 200, a lattice transformation occurs between the metal Al in the transition metal layer and the Si in the substrate 200, thereby reducing defects such as dislocations that would result from directly growing the buffer layer 201 on the silicon substrate. The annealing temperature can be, for example, 400–600 degrees Celsius, the specific time can be, for example, 520 degrees Celsius, and the annealing time can be, for example, 5–30 minutes.

[0128] like Figure 15 As shown, in some embodiments, the buffer layer 201 includes, for example, periodic aluminum nitride layers and shielding layers. Since there are too many defects if only the aluminum nitride layer is used as the buffer layer, shielding layers can be periodically inserted within the aluminum nitride layer to block the defects and thus improve lattice defects. For example, the temperature of the reaction chamber can be set to, for example, 500–1000 degrees Celsius, and a buffer layer 201 with a thickness of, for example, 20–300 nm can be grown. Specifically, an aluminum nitride layer with a thickness of, for example, 10–25 nm can be grown first, and then growth can be stopped. At this time, the surface of the aluminum nitride layer is purged with nitrogen oxides or oxygen for 30–60 seconds, thereby forming an aluminum oxide layer with a thickness of, for example, 3–5 nm on the surface of the aluminum nitride layer as a shielding layer. The shielding layer is, for example, spherical aluminum oxide, placed at the defect location to block lattice defects. As the thickness of the buffer layer 201 increases, the number of lattice defects decreases, thereby improving the quality of the buffer layer 201. The nitrogen oxide can be nitrous oxide (N₂O) or nitrogen dioxide (NO₂). The aluminum nitride layer is grown repeatedly, and then a shielding layer is formed on the aluminum nitride layer, ultimately forming a buffer layer 201 with a thickness of, for example, 20–300 nm. Each shielding layer can mitigate lattice defects in the aluminum nitride layer above it, so that the greater the thickness of the buffer layer 201, the fewer defects there are. The specific thickness of the aluminum nitride layer grown each time can be set according to the required thickness of the buffer layer 201, and this application does not limit this.

[0129] like Figure 15As shown, in other embodiments, the buffer layer 201 is, for example, a gallium nitride layer. Specifically, ammonia and trimethylgallium (TMGa) are introduced into the reaction chamber at a temperature of, for example, 500–850°C, or 500–550°C, and a reaction chamber pressure of, for example, 100–650 Torr, or 200–500 Torr, to grow a layer of gallium nitride with a thickness of, for example, 200–400 angstroms or 400–600 angstroms on the substrate 200, thereby forming the buffer layer 201.

[0130] like Figure 15 As shown, after forming the buffer layer 201, an undoped gallium nitride layer 202 can be grown on the buffer layer 201. Specifically, ammonia and trimethylgallium (TMGa) can be introduced into the reaction chamber at temperatures of, for example, 1000–1200°C, or even 1050–1200°C, and reaction chamber pressures of, for example, 100–500 Torr, or even 200–500 Torr, thereby growing a gallium nitride layer with a thickness of, for example, 10,000–30,000 angstroms on the buffer layer 201, forming an undoped gallium nitride layer 202. By providing the buffer layer 201 and the undoped gallium nitride layer 202 between the substrate 200 and the first semiconductor layer 203, the lattice mismatch problem between the substrate 200 and the first semiconductor layer 203 can be mitigated, improving the quality of the semiconductor epitaxial structure 20.

[0131] like Figure 15 As shown, the first semiconductor layer 203 is, for example, a gallium nitride layer of the first type, specifically, an N-type gallium nitride layer, and the doping ions of the first semiconductor layer 203 can be silicon. In this embodiment, ammonia, trimethylgallium (TMGa), and silane (SiH4) are introduced into the reaction chamber at a temperature of, for example, 1000–1200°C, or even 1050–1200°C, and at a reaction chamber pressure of, for example, 100–600 Torr, or even 200–500 Torr, to grow an N-type gallium nitride layer with a thickness of, for example, 10,000–30,000 angstroms, or even, 20,000–40,000 angstroms, on the undoped gallium nitride layer 202. The silicon ion concentration in the first semiconductor layer 203 is, for example, 1 × 10⁻⁶. 18 ~7×10 18 atom / cm 3 For example, 8×10 18 ~2×10 19 atoms / cm3. In some embodiments, the first semiconductor layer 203 may be an N-type gallium nitride layer doped with silicon ions and a superlattice structure of an undoped gallium nitride layer. In other embodiments, the first semiconductor layer 203 may include an N-type gallium nitride layer and a superlattice structure disposed on the N-type gallium nitride.

[0132] like Figure 15 As shown, the active layer 204 is located on the first semiconductor layer 203. In this embodiment, the active layer 204 includes one or more alternating periodic quantum barrier layers and quantum well layers. The quantum barrier layer includes, for example, a GaN / AlGaN superlattice structure, and the quantum well layer includes, for example, InGaN. The thickness of the active layer 204 is, for example, 200 nm to 300 nm, and the thickness of each period of the quantum well layer is, for example, 3 nm to 4 nm, and the thickness of each period of the quantum barrier layer is, for example, 12 nm to 16 nm. The thickness of the GaN constituting the quantum barrier layer is, for example, 1.5 nm to 3 nm, and the thickness of the AlGaN constituting the quantum barrier layer is, for example, 1.5 nm to 3 nm. In this embodiment, the active layer 204 adopts a modulation-doped GaN / AlGaN superlattice structure, which can effectively guide the impulse current, allowing the pulse current to conduct laterally in the two-dimensional electron gas of the GaN / AlGaN structure, resulting in a more uniform pulse current density distribution and effectively improving the recombination efficiency of electrons and holes.

[0133] like Figure 15 As shown, a GaN layer with a thickness of 1 nm to 3 nm can be grown at a temperature of, for example, 810–860 °C and a pressure of, for example, 200–500 Torr. Then, a modulated-doped AlGaN layer with a thickness of, for example, 1 nm to 3 nm can be grown on the GaN. The GaN and AlGaN form a superlattice unit structure. Alternating and continuously growing 2–6 cycles of the superlattice unit structure can form a quantum barrier layer of the superlattice structure. After forming the quantum barrier layer, the growth conditions are changed to a temperature of, for example, 710–760 °C and a pressure of, for example, 200–500 Torr. An InGaN layer with a thickness of, for example, 2–6 nm can be grown on the quantum barrier layer to form a quantum well layer, wherein the indium source is, for example, trimethylindium (TMIn). Alternating and continuously growing 2–6 or 9–12 cycles of the quantum barrier layer and the quantum well layer can form the active layer 204.

[0134] like Figure 15 As shown, in some embodiments, the second semiconductor structure 21 may include a second semiconductor layer 205 and a hole injection layer 22, wherein the second semiconductor layer 205 is located on the active layer 204, and the hole injection layer 22 is located on the second semiconductor layer 205. The second semiconductor layer 205 is an electron blocking layer, which may be a type II gallium nitride layer, or a type II aluminum gallium nitride layer, or may be made of undoped or poorly doped magnesium AlGaN. In some embodiments, the second semiconductor layer 205 includes a P-type GaN layer and a P-type AlGaN layer with 3 to 10 cycle periods.

[0135] Specifically, such as Figure 15As shown, in one embodiment, the second semiconductor layer 205 is a P-type AlGaN layer. An AlGaN layer with a thickness of 5–10 nm can be grown on the active layer 204 under conditions such as a temperature of, for example, 700–950°C and a pressure of, for example, 50–500 Torr, to form a P-type AlGaN layer, wherein the Mg doping concentration is 0–1 × 10⁻⁶. 16 atom / cm3.

[0136] Specifically, such as Figure 15 As shown, in other embodiments, the second semiconductor layer 205 comprises a single-layer P-type GaN layer and a P-type AlGaN layer. A GaN layer with a thickness of, for example, 20-30 nm can be grown under conditions such as a temperature of, for example, 700-900°C and a pressure of, for example, 200-500 Torr, to form a P-type GaN layer, wherein the Mg doping concentration is 1 × 10⁻⁶. 19 ~1×10 20 atom / cm3. Then, under conditions of temperature, for example 800–950°C and pressure, for example 200–500 Torr, an AlGaN layer with a thickness of, for example 5–10 nm is grown on the P-type GaN layer to form a P-type AlGaN layer, wherein the Mg doping concentration is, for example, 1 × 10⁻⁶. 19 atom / cm3.

[0137] Specifically, such as Figure 15 As shown, in another embodiment, the second semiconductor layer 205 includes periodic P-type GaN layers and P-type AlGaN layers. A GaN layer with a thickness of, for example, 5-10 nm can be grown on the active layer 204 under conditions such as a temperature of, for example, 700-800°C and a pressure of, for example, 200-500 Torr, to form a P-type GaN layer, wherein the Mg doping concentration is 1 × 10⁻⁶ E⁻¹. 19 atom / cm3. Under conditions of temperature, for example, 700–950°C and pressure, for example, 50–500 Torr, AlGaN with a thickness of, for example, 5–10 nm is grown on a P-type GaN layer to form a P-type AlGaN layer, wherein the Mg doping concentration is 0–1 × 10E16 atom / cm3. P-type GaN layers and P-type AlGaN layers are then grown alternately and continuously for 3–10 cycles.

[0138] like Figure 15 As shown, the hole injection layer 22 is located on the second semiconductor layer 205, and the hole injection layer 22 includes undoped or lightly doped In. x Ga y N-layer, and / or doped In x Ga y N layers, namely the hole injection layer 22, include In x Ga yN layers, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1. Among them, undoped In... x Ga y The N layer is composed of undoped In. x Ga y N-layer, doped with In x Ga y The N-layer, for example, is composed of In doped with Mg. x Ga y Made of N.

[0139] like Figure 15 As shown, in one specific embodiment, the second semiconductor layer 205 is, for example, a p-type aluminum gallium nitride layer, and the hole injection layer 22 disposed thereon includes at least a first doped layer 206 and a second doped layer 207. The first doped layer 206 is located on the second semiconductor layer 205, and the second doped layer 207 is located on the first doped layer 206. The first doped layer 206 is an undoped or low-doped InxGayN layer, and the doping concentration of the first doped layer 206 is, for example, a first doping concentration. The second doped layer 207 is a doped InxGayN layer, and the doping concentration of the second doped layer 207 is, for example, a second doping concentration. The second semiconductor layer 205 has, for example, a third doping concentration. The first doping concentration is less than the second doping concentration, the third doping concentration is less than the second doping concentration, and the range of the first doping concentration is 0 to 1 × 10⁻⁶. 19 atom / cm 3 Furthermore, the thickness of the first doped layer 206 is less than the thickness of the second doped layer 207. For example, the thickness of the first doped layer 206 is 40% to 50% of the thickness of the second doped layer 207, specifically, for example, 30% of the thickness of the second doped layer 207.

[0140] like Figure 15 As shown, in another embodiment of the present invention, the hole injection layer 22 includes a first doped layer 206 and a second doped layer 207, wherein the first doped layer 206 is an undoped InxGayN layer and the second doped layer 207 is a doped InxGayN layer, that is, the first doping concentration of the first doped layer 206 is zero and the second doped layer 207 is an InxGayN layer doped with magnesium.

[0141] like Figure 15 As shown, in other embodiments, the hole injection layer 22 further includes a third doped layer located on the second doped layer 207. The third doped layer is, for example, InxGayN doped with magnesium, and the fourth doping concentration of the third doped layer is greater than the second doping concentration.

[0142] like Figure 15As shown, in a specific embodiment, the first doped layer 206 is an undoped InxGayN layer, the second doped layer 207 is a lightly doped InxGayN layer, and the third doped layer is a doped InxGayN layer. Then, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 – 500 Torr, GaN with a thickness of, for example, 2 - 5 nm is grown, and the formed undoped InxGayN layer is the first doped layer 206. Next, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 – 500 Torr, GaN with a thickness of, for example, 5 - 50 nm is grown, where the doping concentration of magnesium is, for example, 1×10 16 ~1×10 17 atom / cm3, and the formed lightly doped InxGayN layer is the second doped layer 207. Finally, under conditions such as a temperature of 800 - 950 °C and a pressure of 200 – 500 Torr, GaN with a thickness of, for example, 10 - 20 nm is grown, where the doping concentration of magnesium is 1×10 18 ~ 1×10 19 atom / cm3, and the formed doped InxGayN layer is the third doped layer.

[0143] As Figure 15 shown, in another embodiment of the present invention, the doped In x Ga y N layer includes, but is not limited to, the superposition of n layers of In x1 Ga y1 N, In x2 Ga y2 N, In x3 Ga y3 N, or an n - cycle loop of alternating In x1 Ga y1 N and In x2 Ga y2 N, where n ≥ 1, X3 < X2 < X1 ≤ 1, Xn <... < X3 < X2 < X1 ≤ 1. In a specific embodiment, N is equal to 3, X1 is equal to 1, X2 is equal to 0.2, and X3 is equal to 0.05, that is, the hole injection layer 22 includes successively arranged InN, In 0.2 Ga 0.8 N, In 0.05 Ga 0.95 N doped layers. The hole injection layer 22 described in the present invention can effectively increase the hole concentration of the epitaxial structure and improve the light - emitting efficiency.

[0144] As Figure 17As shown, in another embodiment of the present invention, a semiconductor epitaxial structure 20 with good high-wavelength stability is further provided, and the semiconductor epitaxial structure 20 is a green light epitaxial structure, and the active layer 204 includes, for example, a stress relaxation layer 208, a first active layer 209, and a second active layer 210. The first active layer 209 is located on the stress relaxation layer 208, and the second active layer 210 is located on the first active layer 209.

[0145] As Figure 17 shown, the material of the stress relaxation layer 208 is InxGa(1-x)N and GaN, where 0.17 < x < 0.35, and GaN is doped with silicon ions, and the doping concentration of the silicon ions is, for example, a, and the range of a is 5×10 17 ~1×10 18 atoms / cm 3 , and the thickness of the stress relaxation layer 208 is 3 - 40 nm. Specifically, the stress relaxation layer 208 may include periodically cycled quantum well layers and quantum barrier layers, and the growth period of the stress relaxation layer 208 is, for example, 2 - 6, or for example, 3. In this embodiment, ammonia gas (NH3) with a flow rate of, for example, 30000 - 60000 sccm, triethylgallium (TEGa) with a flow rate of 50 - 100 sccm, trimethylindium (TMIn) with a flow rate of 500 - 1000 sccm, and nitrogen gas (N2) with a flow rate of 100 - 130 L / min may be introduced under the conditions that the temperature is, for example, 750 - 950 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, so as to grow a 1 nm - 3 nm thick InGaN layer on the first semiconductor layer 203 to form a quantum well layer. Then, under the conditions that the temperature is, for example, 750 - 950 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, ammonia gas (NH3) with a flow rate of 30000 - 60000 sccm, trimethylgallium (TMGa) with a flow rate of 100 - 200 sccm, nitrogen gas (N2) with a flow rate of 100 - 130 L / min, and silane (SiH4) with a flow rate of 1 - 2 sccm may be introduced, so as to grow a 30 - 40 nm thick N-type GaN layer on the quantum well layer to form a quantum barrier layer. By repeating the growth of the quantum well layer and the quantum barrier layer for 2 - 6 cycles, the stress relaxation layer 208 can be obtained.

[0146] As Figure 17 shown, the first active layer 209 includes, for example, 3 - 8 periodically cycled barrier layers and well layers, and the specific number of cycles is, for example, 5. In some embodiments, the material of the barrier layer is, for example, AlzGa(1-z)N, where 0 ≤ z < 0.3, and the material of the well layer is, for example, InyGa(1-y)N, where 0.17 < y < 0.4. The barrier layer is doped with silicon ions, and the doping concentration of the silicon ions is b, and a > b, and the range of b is 5×10 16 ~1×10 17atoms / cm 3 . In other embodiments, the material of the barrier layer can also be GaN, or a superlattice layer with 2 to 6 alternating growth cycles of AlGaN and GaN. The thickness L1 of the barrier layer is, for example, 70 to 150 angstroms, or for example, 120 angstroms. In this embodiment, ammonia (NH3) with a flow rate of 50,000 - 70,000 sccm, triethylgallium (TEGa) with a flow rate of 200 - 1000 sccm, silane (SiH4) with a flow rate of 1 - 2 sccm, and nitrogen (N2) with a flow rate of 100 - 130 L / min can be introduced into the reaction chamber under the conditions that the temperature is, for example, 750 - 900 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, so as to grow a layer of N-type GaN with a thickness of 1 nm to 3 nm on the stress relief layer 208 to form the barrier layer. Further, under the conditions that the temperature is, for example, 710 - 760 °C and the reaction chamber pressure is, for example, 200 - 500 Torr, a layer of InGaN with a thickness of 2 - 6 nm is grown on the barrier layer to form the quantum well layer. Repeating the growth of the barrier layer and the quantum well layer for 3 - 8 cycles can form the first active layer 209.

[0147] As Figure 17 shown, the second active layer 210 includes 2 to 6 cycles of In u Ga 1-u N and GaN. The specific cycle is, for example, 3. The indium content of In u Ga 1-u N in the second active layer 210 is 0.17 < u < 0.40. The GaN in the second active layer 210 is doped with silicon ions, and the doping concentration of the silicon ions is c, and a > c > b. The range of c is 5 × 10 16 -1 × 10 17atoms / cm3 and c can be 1.4 times b. In one specific embodiment of the present invention, the second active layer 210 includes a quantum well layer made of N-type GaN and a quantum barrier layer made of InGaN. In other embodiments, the quantum well layer may also be a superlattice layer of undoped Si GaN and Si-doped GaN. In this embodiment, for example, at a temperature of 750–900°C and a reaction chamber pressure of 200–500 Torr, ammonia (NH3) at a flow rate of 50,000–70,000 sccm, triethylgallium (TEGa) at 200–1,000 sccm, silane (SiH4) at 1–2 sccm, and nitrogen (N2) at a flow rate of 100–130 L / min are introduced into the reaction chamber. A 1–3 nm N-type GaN layer is then grown on the first active layer 209 to form a quantum well layer. The thickness L2 of the quantum well layer ranges from 70–150 angstroms, and L1 > L2 = 100 angstroms. Further, at a temperature of 710–760°C and a reaction chamber pressure of 200–500 Torr, an InGaN layer with a thickness of 2–6 nm is grown on the quantum barrier layer to form a quantum well layer. By repeatedly growing quantum barrier and quantum well layers for 2 to 6 cycles, a second active layer 210 can be formed.

[0148] like Figure 17 As shown, the second semiconductor structure 21 includes a second semiconductor layer 205, a third semiconductor layer 211, and a fourth semiconductor layer 212, with the third semiconductor layer 211 located on the second semiconductor layer 205 and the fourth semiconductor layer 212 located on the third semiconductor layer 211. The second semiconductor layer 205 is a P-type AlGaN layer, and the third and fourth semiconductor layers 211 and 212 are P-type GaN layers. The P-type GaN layer is, for example, a Mg-doped GaN layer, and the doping concentration of the fourth semiconductor layer 212 is greater than that of the third semiconductor layer 211. In this embodiment, AlGaN with a thickness of 5–10 nm can be grown on the active layer 204 under conditions such as a temperature of, for example, 700–800 °C and a reaction chamber pressure of, for example, 200–500 Torr, to form the second semiconductor layer 205. The Mg doping concentration in the second semiconductor layer 205 is 1 × 10⁻⁶. 18 ~1×10 19 atom / cm3. Then, under conditions of, for example, a temperature of 800–950°C and a reaction chamber pressure of, for example, 200–500 Torr, GaN with a thickness of 20–30 nm is grown to form the third semiconductor layer 211. The Mg doping concentration is 1 × 10⁻⁶. 19 ~1×10 20atom / cm3. Finally, GaN with a thickness of 10-20 nm is grown under conditions such as a temperature of, for example, 800-950 °C and a reaction chamber pressure of, for example, 200-500 Torr, to form the fourth semiconductor layer 212. The Mg doping concentration is 1×10⁻⁶. 18 ~1×10 19 atom / cm3.

[0149] like Figure 18 As shown, in another embodiment of the present invention, to ensure that the formed light-emitting diode does not flicker due to excessively fast response, a resistor layer 214 with a special structure can be provided between the first semiconductor layer 203 and the active layer 204 to delay the diode's extinguishing time. Furthermore, the semiconductor epitaxial structure 20 with the resistor layer 214 can be fabricated into a light-emitting diode. When used with an energy-saving power supply, it can reduce the total on-time to save energy, while maintaining the same brightness perceived by the human eye, reducing the impact of flicker, and thus reducing the harm of strong light to the human eye.

[0150] like Figure 18 As shown, the first semiconductor layer 203 is a gallium nitride (GaN) layer 203, and a superlattice structure 213 is disposed on the GaN layer 203. A resistive layer 214 is disposed on the GaN layer 203, located between the GaN layer 203 and the superlattice structure 213. In this embodiment, the GaN layer 203 includes, for example, a lightly doped N-type GaN layer 203a and a heavily doped N-type GaN layer 203b. A resistive layer 214 is disposed on the heavily doped N-type GaN layer 203b, and a superlattice structure 213 is disposed on the resistive layer 214. The active layer 204 is located on the superlattice structure 213. The resistive layer 214 provided in this embodiment can slow down the discharge rate of the finally formed light-emitting diode (LED), prolong the discharge time of the LED, and avoid LED flickering caused by power instability or low duty cycle.

[0151] like Figure 18As shown, the material of the resistive layer 214 is, for example, AlxGa1-xN, where x < 0.15. The thickness of the resistive layer 214 is, for example, 50–200 nm, which avoids the problem of difficult growth control when the resistive layer 214 is too thin, and the problem of cracking when the resistive layer 214 is too thick. Multiple openings 215 are etched on the photoresist layer. The direction of the openings 215 is parallel to the growth direction of the resistive layer 214, and the diameter of the openings 215 is, for example, 3–20 μm. The spacing between adjacent openings 215 is, for example, 3–10 μm. In this embodiment, the resistive layer 214 can be generated by metal-organic chemical vapor deposition (MOCVD) under conditions such as a temperature of, for example, 700–900 °C and a pressure of, for example, 500 mbar, by introducing gases triethylgallium (TEGa), trimethylaluminum (TMAL), and ammonia (NH3) into the reaction chamber. After the resistive layer 214 is formed, an inductively coupled plasma etching method is used to etch the resistive layer 214 to form an opening 215, and the opening 215 penetrates the resistive layer 214 and contacts the heavily doped N-type gallium nitride layer 203b.

[0152] like Figure 19 The etched equivalent circuit of the semiconductor epitaxial structure 20 is shown, where C is the equivalent capacitance of the semiconductor epitaxial structure 20 without the addition of the resistive layer 214, R0 is the equivalent resistance of the semiconductor epitaxial structure 20 without the addition of the resistive layer 214, and R... L R is the equivalent resistance of resistive layer 214, and R L The number or diameter of the openings on the resistive layer 214 can be adjusted, where E is the voltage across the semiconductor epitaxial structure 20. The capacitor discharge formula is: Vt=E×(exp(-t / R*C)), and the capacitor discharge time is: t=RC×Ln[E / Vt], where R=R0+R L As shown in the formula above, the discharge time is directly proportional to the resistance R. The larger the resistance R, the more difficult it is for electrons to flow, and the longer the discharge time. R can be adjusted according to actual needs. L The size of the openings 215 can be adjusted to change the equivalent resistance of the resistive layer 214. The more openings there are and the larger their diameters, the smaller the equivalent resistance of the resistive layer 214. The openings can also restrict the outflow of current.

[0153] The high-quality thin film formed in this application can be applied to various semiconductor structures, electronic components or electronic devices, such as switching elements, power elements, radio frequency elements, light-emitting diodes, micro light-emitting diodes, display panels, mobile phones, watches, laptops, drop-on devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles or other electronic devices.

[0154] like Figure 20As shown, the invention in this embodiment and subsequent embodiments is applicable to micro light-emitting diodes, including microLEDs, miniLEDs, and other light-emitting diodes. This application uses a micro light-emitting diode as an example. The micro light-emitting diode includes a substrate 200 and a semiconductor epitaxial structure 20 disposed on the substrate 200. The semiconductor epitaxial structure 20 includes a first semiconductor layer 203, an active layer 204, and a second semiconductor structure 21. The micro light-emitting diode also includes a first electrode 226 connected to the first semiconductor layer 203 and a second electrode 227 connected to the second semiconductor structure 21. The substrate 200 is, for example, a sapphire substrate 200, and the semiconductor epitaxial structure 20 can be, for example, a sapphire substrate 200. Figure 15 , Figure 16 or Figure 17 The semiconductor epitaxial structure 20 is shown. In some embodiments, on one side of the semiconductor epitaxial structure 20, as... Figure 15 as well as Figure 16 As shown, a notch 23 can be provided, which is disposed on one side of the semiconductor epitaxial structure 20, and the bottom of the notch 23 contacts the first semiconductor layer 203. In some embodiments, the notch 23 contacts the surface of the first semiconductor layer 203. In other embodiments, the second semiconductor structure 21, the active layer 204, and part of the first semiconductor layer 203 can be etched to form the notch 23.

[0155] like Figure 20 As shown, a transparent conductive layer 220 is formed on the second semiconductor structure 21, covering the second semiconductor structure 21. The transparent conductive layer 220 can be made of materials such as indium tin oxide, gallium zinc oxide, zinc oxide, or indium zinc oxide. In some embodiments, the transparent conductive layer 220 covers a portion of the second semiconductor structure 21, and steps 228 are formed between the transparent conductive layer 220 and the second semiconductor layer on both sides of the transparent conductive layer 220. In other embodiments, the transparent conductive layer 220 can completely cover the second semiconductor structure 21. When a notch 23 is provided on the semiconductor epitaxial structure 20, the transparent conductive layer 220 can cover the first semiconductor layer 203.

[0156] like Figure 20As shown, after forming the transparent conductive layer 220, metal materials, such as titanium / titanium nitride barrier layers and tungsten, can be deposited on the first semiconductor layer 203 and the transparent conductive layer 220, respectively. A first conductive plug 221 is formed on the first semiconductor layer 203, and a second conductive plug 222 is formed on the transparent conductive layer 220. The first conductive plug 221 and the second conductive plug 222 are flush, with the first conductive plug 221 covering a portion of the first semiconductor layer 203 and the second conductive plug 222 covering a portion of the transparent conductive layer 220. In some embodiments, an opening can be formed on one side of the semiconductor epitaxial structure 20, with the bottom wall of the opening contacting the first semiconductor layer 203. An insulating material is laid on the sidewall of the opening, and the first conductive plug 221 is formed inside the opening and on the opening. In other embodiments, a notch 23 is provided on the semiconductor epitaxial structure 20, and the first conductive plug 221 can be formed directly on the notch 23.

[0157] like Figure 20 As shown, after forming the first conductive plug 221 and the second conductive plug 222, a reflective layer 223 and a protective layer 224 are sequentially deposited on the first semiconductor layer 203 and the transparent conductive layer 220. The reflective layer 223 covers the transparent conductive layer 220 and the step 228, and exposes a portion of the first conductive plug 221 and the second conductive plug 222. The protective layer 224 covers the reflective layer 223, as well as part or all of the first conductive plug 221 and the second conductive plug 222. After forming the reflective layer 223 and the protective layer 224, the protective layer 224, the reflective layer 223, and the semiconductor epitaxial structure 20 on the outside of the diode chip are etched to form a trench 229. An insulating layer 225 is deposited in the trench 229 and on the protective layer 224, and the insulating layer 225 completely covers the first conductive plug 221 and the second conductive plug 222. The insulating layer 225 and the protective layer 224 are etched to form an opening above the first conductive plug 221 and the second conductive plug 222, exposing a portion of the first conductive plug 221 and a portion of the second conductive plug 222. The area of ​​the opening is larger than the radial dimension of the first conductive plug 221 and the second conductive plug 222. Metal is deposited within the opening to form a first electrode 226 connected to the first conductive plug 221 and a second electrode 227 connected to the second conductive plug 222. After laser cutting and splitting, a miniature light-emitting diode is formed.

[0158] like Figure 21As shown, other structures can be added to the light-emitting diode (LED) to change the light emission direction of the micro LED. Specifically, the light emission direction of the micro LED can be changed according to specific needs. When the micro LED is used as a backlight, to reduce the light mixing distance and thus meet the ultra-thin requirements of electronic devices such as displays, a large-angle micro LED can be provided. In one embodiment, a light-diffusing stack 230 can be provided on the substrate 200 of the micro LED, located on the side opposite to the semiconductor epitaxial structure 20, to increase the light emission angle of the micro LED, making the angle of the micro LED greater than or equal to 160 degrees. For ease of description, this application defines the side where the semiconductor epitaxial structure 20 is located as the upper surface of the substrate 200, and the side of the substrate 200 opposite to the semiconductor epitaxial structure 20 as the lower surface.

[0159] like Figure 21 As shown, the diffused light stack 230 includes a light-guiding layer 231, a first reflective layer 232, a light oscillation layer 233, and a second reflective layer 234 disposed on the lower surface of the substrate 200. Specifically, the light-guiding layer 231 covers the lower surface of the light-guiding layer 232, and the refractive index of the light-guiding layer 231 is the same as the refractive index of the substrate 200, which ensures that the light is not deflected on the light-guiding layer 231. The thickness of the light-guiding layer 231 can be set according to the wavelength of the light emitted by the light-emitting layer and the thickness of the light-guiding layer 231, and the thickness of the light-guiding layer 231 conforms to the relationship: thickness of light-guiding layer 231 = wavelength / 4 × refractive index. In some embodiments, the substrate 200 is a sapphire substrate 200, and the refractive index of sapphire is 1.77. Then, the light-guiding layer 231 is made of aluminum oxide (Al2O3) or magnesium oxide (MgO), which has the same refractive index as sapphire. The thickness of the light-guiding layer 231 is, for example, 10-200 nm, or for example, 60-80 nm. In other embodiments, when the substrate 200 is made of other materials, the corresponding material of the light-guiding layer 231 and the corresponding thickness of the light-guiding layer 231 can be selected.

[0160] like Figure 21As shown, the first reflective layer 232 is located on the side of the light-guiding layer 231 opposite to the substrate 200, and the first reflective layer 232 covers the light-guiding layer 231. The first reflective layer 232 is a forward reflective layer 223, allowing light emitted from the direction of the substrate 200 to pass through the first reflective layer 232, and light emitted from the first reflective layer 232 relative to the direction of the substrate 200 will be reflected by the first reflective layer 232. In some embodiments, the first reflective layer 232 is a periodically grown titanium trioxide (Ti2O3) layer and silicon dioxide (SiO2) layer, and the first reflective layer 232 includes, for example, 4 to 6 cycles of Ti2O3 and SiO2, or for example, 5 cycles of Ti2O3 and SiO2. The titanium trioxide layer covers the light-guiding layer 231, and the thickness of the titanium trioxide layer is, for example, 55 to 60 nm, and the silicon dioxide layer covers the titanium trioxide layer, and the thickness of the silicon dioxide layer is, for example, 90 to 100 nm.

[0161] like Figure 21 As shown, the optical oscillation layer 233 is located on the side of the first reflective layer 232 opposite to the light-guiding layer 231, and the optical oscillation layer 233 covers the first reflective layer 232. The refractive index of the optical oscillation layer 233 is less than the refractive index of the substrate 200. In some embodiments, the optical oscillation layer 233 can be made of one or more of the following: silicon dioxide (SiO2) with a refractive index of 1.46, magnesium fluoride (MgF2) with a refractive index of 1.38, titanium nitride (TiN) with a refractive index of 1.351, or calcium fluoride (CaF2) with a refractive index of 1.433. The thickness of the optical oscillation layer 233 is, for example, 100-500 nm, or, for example, 300-400 nm. This avoids the optical oscillation layer 233 being too thick, which is prone to cracking, and the oscillation layer being too thin, which would result in too much brightness loss and a weak intensity of the light emitted by the micro-light-emitting diode.

[0162] like Figure 21 As shown, the second reflective layer 234 is located on the side of the optical oscillation layer 233 opposite to the first reflective layer 232, and the second reflective layer 234 covers the optical oscillation layer 233. The second reflective layer 234 is a reverse reflective layer 223. Light emitted from the second reflective layer 234 relative to the substrate 200 passes through it, and light emitted from the substrate 200 is reflected by the second reflective layer 234. In some embodiments, the second reflective layer 234 is a periodically grown silicon dioxide (SiO2) layer and titanium dioxide (Ti2O3) layer, and the second reflective layer 234 includes, for example, 2 to 3 cycles of SiO2 and Ti2O3, and the thickness of the silicon dioxide layer is, for example, 90 to 100 nm, and the titanium dioxide layer covers the silicon dioxide layer, and the thickness of the titanium dioxide layer is, for example, 55 to 60 nm.

[0163] like Figure 21As shown, by providing a light-diffusing stack 230 on the lower surface of the substrate 200 of the micro-light-emitting diode, when light emitted from the semiconductor epitaxial structure 20 passes sequentially through the light-guiding layer 231, the first reflective layer 232, and the light oscillation layer 233, it is reflected by the second reflective layer 234 and deflected within the light oscillation layer 233. When the light is reflected or by the first reflective layer 232, it is reflected again by the first reflective layer 232 and finally overflows from the side of the light oscillation layer 233. This results in the angle between the finally emitted light and the plane of the substrate 200 being greater than 160 degrees.

[0164] like Figure 22 As shown, in another embodiment, to avoid excessively large emission angles of the micro-light-emitting diodes (LEDs) during the formation of a display device or lighting device, which could cause interference between adjacent LEDs of different colors, a shielding layer 235 can be added to the outside of the substrate 200 to reduce the emission angle of the LEDs. In this embodiment, the emission angle can be reduced by forming a shielding layer 235 on the outside of the LEDs.

[0165] like Figure 22 As shown, the shielding layer 235 is disposed on the outside of the micro light-emitting diode, specifically as follows: Figure 23 , Figure 24 as well as Figure 25 As shown, the shielding layer 235 is disposed on the outer side of the substrate 200 and is attached to the sidewall of the substrate 200. The shielding layer 235 may cover one or more sides of the substrate 200, and the light emission range of the micro-light-emitting diode can be changed by disposing the shielding layer 235 at different positions on the sidewall of the substrate 200. In some embodiments, such as Figure 24 As shown, the shielding layer 235 can cover, for example, two opposite sides of the substrate 200, in which case the emission angle range of the micro LED is, for example, 90 to 115 degrees, with a maximum emission angle of, for example, 115 degrees. In other embodiments, such as Figure 25 As shown, the shielding layer 235 can cover, for example, four sides of the substrate 200. In this case, the emission angle range of the micro-LED is, for example, 90 to 105 degrees, with a maximum emission angle of, for example, 105 degrees. In other embodiments, the shielding layer 235 covers, for example, one side of the substrate 200. In this case, the emission angle range of the micro-LED is, for example, 90 to 120 degrees, with a maximum emission angle of, for example, 120 degrees. The shielding layer 235 covers, for example, three sides of the substrate 200. In this case, the emission angle range of the micro-LED is, for example, 90 to 110 degrees, with a maximum emission angle of, for example, 110 degrees.

[0166] like Figure 23The shielding layer 235 includes a reduction layer 236 and a coating layer 237, wherein the reduction layer 236 is formed by recrystallization and roughening of the surface of the sidewalls of the substrate 200. In this embodiment, the substrate 200 is, for example, a sapphire substrate 200, and the sidewalls of the substrate 200 can be recrystallized and roughened by laser edge scribing. The wavelength of the laser light is, for example, 800-1200 nm. The sapphire substrate 200 (Al2O3) is recrystallized into Al or AlO by laser, and the surface of the sidewalls of the substrate 200 after recrystallization is naturally roughened. Moreover, the recrystallized Al or AlO are both opaque layers and can reflect light, and the naturally roughened sidewalls of the substrate 200 can also increase reflection.

[0167] like Figure 22 and Figure 23 The coating layer 237 covers the reduction layer 236, and can be applied, for example, in a vacuum environment and at a pressure of, for example, 1 × 10⁻⁶. 3 ~9×10 3 Under torr conditions, a coating layer 237 is formed on the reduction layer 236 by vapor deposition or sputtering. The coating layer 237 comprises multiple composite layers, such as a first composite layer 238 and a second composite layer 239, with the second composite layer 239 covering the first composite layer 238. The coating layer 237 can be a metal composite layer or an oxide composite layer. In some embodiments, the material of the first composite layer 238 is Al, or Al and Ni, the material of the second composite layer 239 is Ti or Pt, and the thickness of the coating layer 237 is, for example, 20–300 nm. In other embodiments, the material of the first composite layer 238 is SiO2 or MgF2, the material of the second composite layer 239 is Ti2O5 or SiNx, and the thickness of the coating layer 237 is, for example, 50–100 nm. When the coating layer 237 is an oxide composite layer, it may include multiple cyclically arranged first composite layers 238 and second composite layers 239.

[0168] like Figure 26 As shown, in some embodiments, during the crystal growth process of the semiconductor epitaxial structure, the surface of the semiconductor epitaxial structure may have uneven defects, resulting in poor performance of the reflective layer 223. The micro light-emitting diode provided in this embodiment can fill the surface of the semiconductor epitaxial structure, while ensuring the stress balance of the overall film layer, avoiding cracking of the coating layer due to tensile stress, and also increasing the light emission effect.

[0169] like Figure 26 As shown, there are uneven defects on the surface where the semiconductor epitaxial structure 20 contacts the transparent conductive layer 220, which can... Figure 20 , Figure 21 or Figure 22Based on the micro light-emitting diode shown, a composite filler layer 240 is provided between the transparent conductive layer 220 and the reflective layer 223 to improve defects in the semiconductor epitaxial structure. A lamination layer 243 is provided between the protective layer 224 and the insulating layer 225 to ensure overall film stress balance and avoid film cracking due to tension.

[0170] like Figures 26 to 27 The leveling layer 240 is located on the side of the transparent conductive layer 220 opposite to the semiconductor epitaxial structure and covers the transparent conductive layer 220. The leveling layer 240 is transparent and non-conductive, and the particles in the leveling layer 240 are coarse at first and then fine at second. Specifically, the leveling layer 240 includes a first leveling layer 240a and a second leveling layer 240b. The first leveling layer 240a covers the transparent conductive layer 220, and its thickness is, for example, 200–500 nm, specifically, for example, 250 nm or 300 nm, to completely cover the defects on the semiconductor epitaxial structure. The second leveling layer 240b covers the first leveling layer 240a, and its thickness is, for example, 50–300 nm, to fill the gaps between the particles in the first leveling layer 240a.

[0171] like Figures 26 to 27 In this embodiment, a filler layer 240 can be formed on the transparent conductive layer 220 by PECVD deposition or evaporation, wherein the particle density of the first filler layer 240a is, for example, 3-4 g / cm³. 3 The material of the first filling layer 240a is, for example, alumina (Al2O3) or magnesium fluoride (MgF3), with a density of 3.5–3.9 g / cm³. 3 The density of magnesium fluoride is 3.148 g / cm³. 3 The particle density of the second leveling layer 240b is, for example, 1.5–3 g / cm³. 3 The material of the second leveling layer 240b is, for example, silicon dioxide (SiO2) or silicon nitride (SiN), with a density of 2.2 g / cm³. 3 The density of silicon nitride is 1.8–2.7 g / cm³. 3 The first leveling layer 240a is formed using coarse particles, which allows for fast plating. Then, fine particles are added to fill the gaps and form the second leveling layer 240b. This eliminates voids and ensures a high-quality film that is less prone to peeling.

[0172] like Figures 26 to 27The filler layer 240 has multiple openings 241 arranged in an array. For example, the openings 241 can be wet-etched using BOE etching solution or dry-etched using inductively coupled plasma (ICP) etching. The openings 241 are columnar and penetrate the first filler layer 240a and the second filler layer 240b. The cross-section of the opening 241 can be circular, square, polygonal, or other shapes. In this embodiment, the aperture of the opening 241 is, for example, 3–5 μm, and the spacing between adjacent openings 241 is, for example, 3–5 μm. The aperture and spacing between adjacent openings 241 prevent the openings 241 from being too small to meet process requirements, while also preventing the openings from being too large, resulting in a small contact area between the filler layer 240 and the conductive layer, which could lead to an excessively high voltage difference across the filler layer 240.

[0173] like Figure 26 As shown, a protective layer 224 covers the reflective layer 223, a lamination layer 243 covers the protective layer 224, and an insulating layer 225 covers the lamination layer 243. The lamination layer 243 includes a first lamination layer and a second lamination layer, with the second lamination layer covering the first lamination layer. At room temperature, the thickness ratio of the first lamination layer to the second lamination layer is, for example, 3:8. The thickness of the first and second lamination layers is, for example, 30–600 nm, to avoid the lamination layer 243 being too thin to function effectively, or too thick to cause cracking. In some embodiments, the lamination layer 243 includes, for example, one first lamination layer and, for example, one second lamination layer. In other embodiments, the lamination layer 243 includes multiple cyclically repeated first and second lamination layers.

[0174] like Figure 26 and Figure 27 As shown, a lamination layer 243 can be formed on the transparent conductive layer 220 by PECVD deposition or evaporation. The material of the first lamination layer is, for example, silicon dioxide (SiO2), and the material of the second lamination layer is, for example, titanium dioxide (TiO2) or Ti2O5.

[0175] Please combine Figure 26 and Figure 28As shown, when the micro-LED is mounted on the substrate 244, the first electrode 226 can be soldered to the substrate 244 via the first pad 245, and the second electrode 227 can be soldered to the substrate 244 via the second pad 246. When the substrate 244 exhibits compressive stress and the thin film disposed on the substrate 244 exhibits tensile stress, the two sides of the substrate 244 and the thin film will warp towards the thin film side. When the substrate 244 exhibits tensile stress and the thin film disposed on the substrate 244 exhibits compressive stress, the two sides of the substrate 244 and the thin film will warp towards the substrate 244 side. In this embodiment, the substrate 244 exhibits relatively small tensile stress at room temperature, while the stress variation of the lamination layer 243 thin film is as follows: when the thickness of the second lamination layer (TiO2 or Ti2O5) is 300 nm, it exhibits tensile stress at room temperature, for example, 114 MPa; when the thickness of the first lamination layer (SiO2) is 400 nm, it exhibits compressive stress at room temperature, for example, -56 MPa. Since the substrate 244 itself exhibits tensile stress in another direction, the thicknesses of the first and second lamination layers should be in a 3:8 ratio. At this ratio, the stress exhibited by the lamination layer 243 is nearly zero, with a slight additional compressive stress, which can offset the tensile stress exhibited by the substrate 244. At other temperatures, the substrate 244 may warp due to excessive stress. This can be addressed by adjusting the stress of the thin film to achieve equilibrium between the substrate 244 and the thin film on it.

[0176] like Figure 29 and Figure 30 As shown, to meet the high efficiency and energy-saving requirements of micro LEDs, the brightness of flip-chip LEDs needs to be increasingly higher. During the crystal growth process of semiconductor epitaxial structures, surface defects easily form, resulting in an uneven surface. This prevents the formation of a perfectly mirrored surface after the reflector is deposited, leading to dispersion and light concentration. Consequently, after encapsulation into white LEDs, the luminous efficiency is poor. The flip-chip micro LED provided in this embodiment, as... Figure 29 and Figure 30 As shown, a special composite leveling layer 240 is used to level the epitaxial surface and increase the vertical light reflection capability. At the same time, a lamination layer 243 is used to ensure the overall film stress balance and prevent the coating layer 237 from cracking due to tensile stress. These two designs also enhance the vertical light reflection capability required for flip-chip bonding, thereby increasing the light output efficiency.

[0177] like Figure 31As shown, miniature light-emitting diodes need to be soldered onto the circuit using solder pads. During soldering, voids can easily form between the solder pads and the electrodes. A specially shaped metal stack 250 can be formed on the electrodes to increase the yield of electrode solderability. In this embodiment, the thickness of the metal stack 250 is, for example, 20-100 μm, and includes a dielectric layer 251 and a flexible metal layer 252. The dielectric layer 251 is disposed on the first electrode 226 and the second electrode 227, and the flexible metal layer 252 is disposed on the dielectric layer 251. Specifically, the dielectric layer 251 is made of an alloy, and for example includes a nickel (Ni) layer, and an alloy of gold (Au) and tin (Sn). Under yellow light conditions, a nickel layer with a thickness of, for example, 10–15 nm, is first deposited or sputtered onto the first electrode 226 and the second electrode 227. Then, a gold-tin alloy layer with a thickness of, for example, 30–1000 nm, is deposited or sputtered onto the nickel layer to form a dielectric layer 251. The ratio of gold to tin in the gold-tin alloy is, for example, 80:20. The dielectric layer 251 has the same thickness at all points and is columnar in shape, specifically cylindrical. Forming a dielectric layer 251 on the first electrode 226 and the second electrode 227 prevents the diffusion of the soft metal layer 252.

[0178] like Figure 31 As shown, a flexible metal layer 252 is disposed on and covers the dielectric layer 251. The flexible metal layer 252 is made of metal or alloy, such as gold (Au), tin (Sn), or silver (Ag), or an alloy of tin (Sn). A metal or alloy with a thickness of, for example, 20–100 μm, can be deposited or sputtered onto the dielectric under yellow light conditions to form the flexible metal layer 252. As the thickness of the flexible metal layer 252 increases, its radius gradually decreases; specifically, the flexible metal layer 252 can be frustum-shaped. When the micro-LED is soldered to the pads, voids between the pads and electrodes can be easily eliminated. Furthermore, utilizing the properties of the flexible metal, uneven pad areas can be filled, and the window allowing for substrate warping can be enlarged, increasing product reliability.

[0179] like Figure 32As shown, in another embodiment, a special pad can replace the function of the conductive plug and electrode. For example, a first conductive structure 260 can replace the first conductive plug 221 and the first electrode 226, and a second conductive structure 261 can replace the second conductive plug 222. The first conductive structure 260 and the second conductive structure 261 are flexible, which can compensate for defects caused by uneven substrates and thermal expansion stress during reflow soldering, while reducing the package void ratio. In this embodiment, the first conductive structure 260 is electrically connected to the first semiconductor layer, and the second conductive structure 261 is electrically connected to the second semiconductor layer. The first conductive structure 260 includes a leveling layer 262, an adhesive layer 263, a stretching layer 264, a stack layer 265, and a solder layer 266, and the second conductive structure 261 includes an adhesive layer 263, a stretching layer 264, a stack layer 265, and a solder layer 266.

[0180] like Figure 32 As shown, a leveling layer 262 is disposed on the first semiconductor layer of the semiconductor epitaxial structure 20, and the height of the leveling layer 262 is equal to the height of the transparent conductive layer 220. By providing the leveling layer 262, the heights of the first conductive structure 260 and the second conductive structure 261 can be made equal, avoiding skewing. A leveling layer 262 can be deposited on the first semiconductor layer using chemical vapor deposition at a temperature of 200–300 degrees Celsius. The material of the leveling layer 262 is, for example, SiO2, SiNx, Al2O3, MgO, or AlN, and the thickness of the leveling layer 262 is, for example, 900–1500 nm, specifically the same as the height of the transparent conductive layer 220.

[0181] like Figure 32 As shown, the adhesive layer 263 of the first conductive structure 260 is disposed on the leveling layer 262, and the adhesive layer 263 of the second conductive structure 261 is disposed on the transparent conductive layer 220. The heights of the adhesive layers 263 of the first conductive structure 260 and the second conductive structure 261 are equal. An adhesive layer 263 can be vapor-deposited or sputtered onto the leveling layer 262 or the transparent conductive layer 220 under conditions of light exposure. The material of the adhesive layer 263 is, for example, Cr, Ni, Ti, or indium tin oxide (ITO), and the thickness of the adhesive layer 263 is, for example, 5–100 nm. The adhesive layer 263 is lower than the height of the insulating layer 225.

[0182] like Figure 32As shown, a stretching layer 264 is provided on the adhesive layer 263 of the first conductive structure 260 and the second conductive structure 261, and the heights of the stretching layer 264 on the first conductive structure 260 and the second conductive structure 261 are equal. A stretching layer 264 can be vapor-deposited or sputtered onto the adhesive layer 263 under ambient light conditions. Examples of the stretching layer 264 are composite layers formed of titanium and aluminum alloys (Ti / Al), nickel and aluminum alloys (Ni / Al), titanium and silver alloys (Ti / Ag), or nickel and silver alloys (Ni / Ag). The stretching layer 264 is higher than the insulating layer 225, and its thickness is, for example, (50–200)*N nm, where N ranges from 3 to 9. When the value of N is too small, the stretching layer 264 has no stretching effect; when the value of N is too large, the voltage of the stretching layer 264 is too high.

[0183] like Figure 32 As shown, a stacked layer 265 is disposed on the stretching layer 264 of the first conductive structure 260 and the second conductive structure 261, and the stacked layer 265 on the first conductive structure 260 and the stacked layer 265 on the second conductive structure 261 have the same height. A stacked layer 265 can be vapor-deposited or sputtered on the stretching layer 264 under ambient light conditions. The material of the stacked layer 265 is, for example, an alloy of platinum (Pt) and titanium (Ti), or an alloy of titanium (Ti) and nickel (Ni), and the thickness of the stacked layer 265 is, for example, 100–300 nm.

[0184] like Figure 32 As shown, a solder layer 266 is provided on the stacked layer 265 of the first conductive structure 260 and the second conductive structure 261, and the solder layer 266 on the first conductive structure 260 and the solder layer 266 on the second conductive structure 261 have the same height. A solder layer 266 can be vapor-deposited or sputtered on the stacked layer 265 under ambient light conditions. The material of the solder layer 266 is, for example, tin (Sn) or a gold-tin alloy (AuSn), and the thickness of the solder layer 266 is, for example, 80,000 to 100,000 nm.

[0185] like Figure 33 As shown, when miniature light-emitting diodes (LEDs) are used for backlighting and illumination, they often fail due to various adverse environmental conditions, especially the infiltration of moisture, which causes particularly severe damage. This invention provides a miniature LED with a special waterproof protective layer 270 on the light-emitting area and electrodes. This layer prevents moisture from remaining on the chip, keeping it dry and thus preventing moisture intrusion.

[0186] like Figure 33As shown, the waterproof protective layer 270 includes a protective film layer 271, a hydrophobic film layer 272, and a water barrier layer 273. The waterproof protective layer 270 is disposed on the transparent conductive layer 220 and a portion of the first electrode 226 and the second electrode 227. The hydrophobic film layer 272 is disposed on the waterproof protective layer 270, and the water barrier layer 273 is disposed on the hydrophobic film layer 272. Please refer to... Figure 32 As shown, the waterproof protective layer 270 covers the transparent conductive layer 220 and extends toward the first electrode 226 and the second electrode 227, covering the sidewalls and part of the top wall of the first electrode 226 and the second electrode 227. Figure 34 As shown, the protective film layer 271 includes a first waterproof protective layer 274, a second waterproof protective layer 275, and a third waterproof protective layer 276. The second waterproof protective layer 275 is disposed on the first waterproof protective layer 274, and the third waterproof protective layer 276 is disposed on the second waterproof protective layer 275. The first waterproof protective layer 274, the second waterproof protective layer 275, and the third waterproof protective layer 276 can be deposited separately using plasma-enhanced chemical vapor deposition. The first waterproof protective layer 274 is an oxide layer with a thickness of, for example, 100–300 nm. The second waterproof protective layer 275 is a gradient layer of oxide and nitride layers with a thickness of, for example, 20 nm. The third waterproof protective layer 276 is a nitride layer of a non-hydrophilic material with a thickness of, for example, 20–50 nm. Specifically, the material of the first waterproof protective layer 274 is, for example, silicon dioxide (SiO2), the material of the second waterproof protective layer 275 is, for example, silicon oxynitride (SiON), and the material of the third waterproof protective layer 276 is, for example, silicon nitride (SiNx).

[0187] like Figure 33 As shown, a hydrophobic film layer 272 is disposed on and covers the waterproof protective layer 270. The hydrophobic film layer 272 can be formed using electron beam evaporation, and its thickness is, for example, 2–5 μm. The hydrophobic film layer 272 is a superhydrophobic nitride layer, such as a metal nitride layer, specifically boron nitride (BN) or aluminum nitride (AlN), or other superhydrophobic metal nitride layers.

[0188] like Figure 33 and Figure 35As shown, a water barrier layer 273 is disposed on a hydrophobic film layer 272. Multiple protruding structures can be formed on the hydrophobic film layer 272 by annealing and recrystallizing it, thus forming the water barrier layer 273. The thickness of the water barrier layer 273 is greater than or equal to 1 μm, specifically, for example, 2 μm, and the thickness of the water barrier layer 273 is, for example, the height of the protruding structures. Specifically, a thicker hydrophobic film layer 272 can be formed during the formation of the hydrophobic film layer 272. Specifically, the thickness of the hydrophobic film layer 272 before annealing and crystallization is equal to the sum of the thickness of the finally formed hydrophobic film layer 272 and the thickness of the water barrier layer 273. After the hydrophobic film layer 272 is formed, the top of the hydrophobic film layer 272 is rapidly annealed at 200-300 degrees Celsius or in a furnace tube for 30-60 minutes to granulate the top surface of the hydrophobic film layer 272, forming a protruding structure. Multiple protruding structures constitute the water barrier layer 273.

[0189] like Figure 36 As shown in (a), the angle between the tangent at the edge of a droplet on a typical hydrophilic surface and the reference plane is less than 90 degrees, such as Figure 36 As shown in (b), the angle between the tangent at the edge of the hydrophobic surface droplet and the reference plane can range from, for example, 90-150 degrees. Figure 36 As shown in (c), the angle between the tangent of the droplet edge on the superhydrophobic surface and the reference plane is greater than 150 degrees. The hydrophobicity of the protective film layer 271 provided by the present invention gradually increases, a superhydrophobic surface is formed on the outermost layer of the protective film layer 271, and a water barrier layer 273 with a protruding structure is formed on the surface of the superhydrophobic metal nitride layer to further prevent water vapor intrusion.

[0190] like Figure 37 As shown, after transferring the light-emitting diode onto the display substrate, the substrate 200 needs to be peeled off to improve brightness. Because the electrodes are located on both sides of the semiconductor epitaxial structure, and there is a void between the two electrodes, peeling off the substrate 200 can easily cause cracks in the semiconductor epitaxial structure, resulting in leakage and LED failure. This invention provides a miniature light-emitting diode that prevents the semiconductor epitaxial structure from breaking during substrate 200 peeling.

[0191] like Figure 37As shown, this embodiment provides a miniature light-emitting diode (LED) with a support layer 280 formed between a first electrode 226 and a second electrode 227, filling the gap between the two electrodes. Specifically, the support layer 280 can be formed using vapor deposition, sputtering, or chemical vapor deposition, and the material of the support layer 280 is, for example, SiO2, SiNx, Al2O3, or a diamond-like carbon (DLC) film. The height of the support layer 280 is no higher than the first pad 245 and the second pad 246, and the thickness of the support layer 280 is, for example, 300–4000 nm. This miniature LED utilizes a special support layer 280 to provide support for any cracked portions, preventing further cracking, avoiding chip breakage, and also preventing leakage due to the diffusion of underlying flux or solder paste.

[0192] like Figure 38 After forming miniature light-emitting diodes (LEDs), multiple LEDs need to be transferred to a substrate. This invention provides a semiconductor device that can cut and transfer multiple miniature LEDs onto a substrate. In this embodiment, the semiconductor device is, for example, a miniature LED transfer apparatus. This apparatus has a matrix dicing bar that can separate multiple miniature LEDs on the substrate into independent wafers, and each wafer includes at least one Mini LED or Micro LED. A matrix suction cup can transfer the miniature LEDs onto the substrate. The miniature LED transfer apparatus provided in this embodiment can perform integrated cutting, improving work efficiency.

[0193] like Figure 38 As shown, the miniature LED transfer device includes a base 301, a cylindrical base 302 disposed above the base 301, and a slot provided inside the cylindrical base 302, the neutral line of which coincides with the neutral line of the cylindrical base 302. A lifting platform 303 is disposed within the slot, the top surface of the lifting platform 303 being higher than the top surface of the cylindrical base 302. A rotating platform 304 is disposed on the lifting platform 303, one end of a cantilever 305 is connected to the rotating platform 304, and a fixed arm 306 is connected to the end of the cantilever 305 away from the rotating platform 304. A transfer plate 308 is disposed below the fixed arm 306, and matrix cutting strips 309 and matrix suction cups 310 are fixed to the transfer plate 308, with the matrix suction cups 310 located between adjacent matrix cutting strips 309.

[0194] like Figure 38The base 301 is located at the bottom of the micro LED transfer device, providing support for the entire device. In some embodiments, to enable movement of the micro LED transfer device, the base 301 can be equipped with a set of wheels, which can be fitted with a stop plate. The wheels and the stop plate allow for flexible adjustment of the entire micro LED transfer device's position. A cylindrical base 302 can be positioned above the base 301, with a slot inside. A lifting platform 303, which can be cylindrical, is positioned within this slot. The top of the lifting platform 303 extends above the cylindrical base 302, and a lifting motor is installed inside the platform to control its vertical movement.

[0195] like Figure 38 A rotary table 304 is mounted on a lifting platform 303. The rotary table 304 can be cylindrical, and its central axis coincides with the central axis of the lifting platform 303. The diameter of the rotary table 304 is smaller than the diameter of the lifting platform 303. In some embodiments, a rotary motor is installed inside the rotary table 304, controlling the rotary table 304 to perform bidirectional circular motion. A cantilever 305 is connected to the side of the rotary table 304. The cantilever 305 is welded to the rotary table 304. The cantilever 305 can have a hollow internal structure and may be provided with reinforcing ribs. Driven by the rotary motor inside the rotary table 304, the cantilever 305 performs bidirectional circular motion along the movement trajectory line 314 at the end of the cantilever.

[0196] like Figure 38 and Figure 39 The transfer plate 308 is positioned below the fixed arm 306. Bolt holes are provided on the upper surface of the transfer plate 308 at positions corresponding to the fixed arm 306. The transfer plate 308 is connected to the fixed plate 306 via bolts 307. Driven by a rotary motor inside the rotary table 304, the transfer plate 308 performs bidirectional circular motion along the movement trajectory line 314 at the end of the cantilever 305, realizing the transfer of wafers in different processing cavities. A matrix dicing strip 309 and a matrix suction cup 310 are provided on the lower surface of the transfer plate 308. The transfer plate 308 and the matrix dicing strip 309 are fixed below the transfer plate 308, and the matrix suction cup 310 is located between adjacent matrix dicing strips 309. The matrix suction cup 310 can batch-extract and fix bare wafers 311 to be transferred to the target array substrate.

[0197] like Figure 38 and Figure 39The matrix cutting strips 309 and matrix suction cups 310 are fixed to the lower surface of the transfer plate 308. The matrix cutting strips 309 can be distributed in a grid pattern, and the matrix suction cups 310 are intersectingly arranged in the area between adjacent cutting strips of the matrix cutting strips 309. The height of the matrix suction cups 310 is less than the height of the matrix cutting strips. The ends of the matrix cutting strips 309 can be inverted trapezoidal structures, pyramidal structures, or combinations or integrations of other similar structures.

[0198] like Figure 38 and Figure 41 Wafer 311 undergoes different processing steps on stage 12, forming dicing grooves between adjacent wafers. These dicing grooves can be divided into transverse dicing grooves 315 and longitudinal dicing grooves 316, with the number varying depending on the number of wafers to be processed. In some embodiments, h1–h8 are transverse dicing grooves 315, and S1–S8 are longitudinal dicing grooves 316. A matrix dicing bar 309 corresponds to the transverse dicing grooves 315 and longitudinal dicing grooves 316, performing integrated dicing of wafer 311 and dividing different wafers 311 in both the transverse and longitudinal directions. Figure 39 As shown, a sawing force line 317 can be defined between adjacent wafers 311, and the cutting surface perpendicular to the sawing force line 317 is the stress concentration surface 318. The cutting force is applied by the sawing force line 317 to the stress concentration surface 318. After the cutting is completed, the matrix suction cup 310 adsorbs and fixes the wafers 311. The adsorbed wafers 311 move in a bidirectional circular motion along the cantilever end motion trajectory line 314 driven by the rotary motor of the rotary table 304 along the transfer plate 308. In other embodiments of the present invention, the matrix suction cup can be replaced with a matrix adsorption body that uses similar principles, such as mechanical gripping, adhesive bonding, electrostatic adsorption, gas adsorption, or electromagnetic adsorption, to achieve integrated cutting and transfer of the wafers 311.

[0199] like Figure 41 In this embodiment, the saw blade traverses the surface of wafer 311. For thin wafers, the saw blade lowers to the surface of the wafer to create a shallow groove extending to one-third of the wafer's thickness. The chip separation method still utilizes the cylindrical roller pressure applied as described in the dicing and diamond scribing methods.

[0200] like Figures 42 to 43 In some embodiments, after the micro-light-emitting diodes are transferred onto the substrate 244, a driving circuit 296 is disposed on the substrate 244, and the light-emitting diodes are connected to the driving circuit 296 via pads to form a micro-light-emitting diode display panel. In this embodiment, a micro-light-emitting diode display panel is also provided, including a substrate 244 and a micro-light-emitting diode with multiple nanopores disposed on the substrate 244, wherein quantum dots are disposed within the nanopores.

[0201] like Figures 42 to 43The micro-light-emitting diode in this embodiment includes a first semiconductor layer 291 and a second semiconductor layer 292 disposed on the first semiconductor layer 291. The first semiconductor layer 291 may be connected to electrodes, and the first semiconductor layer 291 is, for example, an N-type gallium nitride layer. The second semiconductor layer 292 is disposed on the first semiconductor layer 291, and the second semiconductor layer 292 is also a gallium nitride layer, and for example, an N-type gallium nitride layer. Multiple arrayed nanopores 293 are disposed on the second semiconductor layer 292. Specifically, the N-type gallium nitride layer can be immersed in an acidic solution and a bias voltage applied to form nanoscale pores in the N-type gallium nitride layer, thereby driving the electrochemical etching of the N-type gallium nitride layer to form the nanopores 293. The density and size of the nanopores 293 can be changed by changing the applied bias voltage or the silicon doping concentration in the GaN. The diameter of the nanopores 293 is, for example, 50–200 nm, and the spacing between adjacent nanopores 293 is, for example, 30–300 nm.

[0202] like Figures 42 to 43 In this embodiment, the nanopore 293 penetrates the second semiconductor layer 292. When no quantum dots are placed in the nanopore 293, the micro-LED emits ultraviolet or blue light. When red quantum dots 295 are placed in the nanopore 293, the micro-LED emits red light; when green quantum dots 294 are placed in the nanopore 293, the micro-LED emits green light. In some embodiments, the red quantum dots 295, green quantum dots 294, and empty nanopores 293 are arranged sequentially on the second semiconductor layer 292. In other embodiments, the second semiconductor layer 292 includes a plurality of sequentially arranged first-type light-emitting arrays, second-type light-emitting arrays, and third-type light-emitting arrays. In the first-type light-emitting array, the nanopores 293 are filled with red quantum dots 295; in the second-type light-emitting array, the nanopores 293 are filled with green quantum dots 294; and in the third-type light-emitting array, the nanopores 293 are empty. The first, second, and third types of light-emitting arrays are of equal shape and size to ensure more uniform light emission from the resulting micro-LEDs. The array length and width are, for example, 100–2000 nm. Placing quantum dots within the sub-nanopores 293 can improve the absorption rate of the quantum dots and extend their lifespan.

[0203] like Figures 42 to 43In forming the miniature LED display panel, a driving circuit 296 is provided on the substrate 244. The driving circuit 296 can be disposed on the surface of the substrate 244 or within the substrate 244. After the miniature LED is bonded to the substrate 244, the driving circuit 296 can drive the miniature LED to emit light. By providing nanopores 293 on the miniature LED and filling the nanopores 293 with quantum dots of different colors, the sorting of LEDs of different colors can be avoided, reducing production costs.

[0204] Please see Figure 44 This disclosure also provides an electronic device, which includes a micro LED display panel 300 and an electronic device body 301. The micro LED panel 300 is connected to the electronic device body 301, and the micro LED panel 300 includes a circuit board and multiple micro LED chips. The electronic device body 301 includes a controller 302, a memory 303, and a power supply 304. The power supply 304 converts AC mains power (220V AC) into DC power required by the controller 302 and the memory 303, and also provides power to the micro LED panel 300. The memory 303 is connected to the power supply 304 and is used to store relevant data for the operation of the electronic device. The controller 302 is connected to the power supply 304 and also to the memory 303. The power supply 304 supplies power to the controller 302, and the controller executes the program stored in the memory 303 to control the electronic device. Among them, electronic devices may include, for example, display panels, mobile phones, watches, laptops, projectile devices, charging devices, charging piles, virtual reality (VR) devices, augmented reality (AR) devices, portable electronic devices, game consoles or other electronic devices.

[0205] like Figure 45 As shown, when the semiconductor epitaxial structure of this disclosure is used to manufacture a semiconductor device, the semiconductor device includes a substrate 200, a buffer layer 201, a first semiconductor layer 203, a second semiconductor layer 205, a source 301, a drain 302, and a gate 303. The buffer layer 1401 is disposed on the substrate 200, the first semiconductor layer 203 is disposed on the buffer layer 201, the second semiconductor layer 205 is disposed on the first semiconductor layer 203, the source 301 is formed on the second semiconductor layer 205, the drain 302 is formed on the second semiconductor layer 205, and the gate 303 is formed on the second semiconductor layer 203 and located between the source 301 and the drain 302. A source doped region 303 and a drain doped region 304 are disposed on the second semiconductor layer 205, and the source doped region 303 and the drain doped region 304 are, for example, heavily N-type doped regions. The source 301 is disposed on the source doped region 303, and the drain 302 is disposed on the drain doped region 304.

[0206] like Figure 46When the semiconductor devices disclosed herein are used in a radio frequency (RF) module, the RF module includes the semiconductor devices. The RF module mainly includes a radio frequency (RF) switching device 311, an active RF device 314, a passive RF device 312, and a control device 313. The active RF device 314 can be the semiconductor device described in this application, and the passive RF device 312 can be a passive device such as a capacitor, resistor, or inductor. The RF switching device 311, the active RF device 314, the passive RF device 312, and the control device 313 are all formed on a semiconductor substrate 200.

[0207] The above description is merely a preferred embodiment of this application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the inventive concept. For example, technical solutions formed by replacing the above-mentioned features with technical features with similar functions disclosed in this application (but not limited to) each other.

[0208] Apart from the technical features described in the specification, the other technical features are known to those skilled in the art. To highlight the innovative features of this invention, the other technical features will not be described in detail here.

Claims

1. A light-emitting diode, characterized in that, include: Substrate; A first semiconductor layer is disposed on the substrate; An active layer is disposed on the first semiconductor layer; A second semiconductor layer is disposed on the active layer; A first conductive structure is disposed on the first semiconductor layer; as well as A second conductive structure is disposed on the second semiconductor layer; The first conductive structure and the second conductive structure include an adhesive layer, a stretching layer, a stacked layer and a welding layer arranged sequentially. The stretching layer is made of a composite layer formed by an alloy of titanium and aluminum, an alloy of nickel and aluminum, an alloy of titanium and silver, or an alloy of nickel and silver. The thickness of the stretching layer is (50~200)*N nm, where N ranges from 3 to 9. The stacked layer is made of an alloy of platinum and titanium, or an alloy of titanium and nickel. The light-emitting diode further includes a transparent conductive layer, which is disposed on the second semiconductor layer, and the second conductive structure is disposed on the transparent conductive layer; The first conductive structure further includes a leveling layer, which is disposed on the first semiconductor layer and is at the same height as the transparent conductive layer. The light-emitting diode further includes a leveling layer, which is located on the side of the transparent conductive layer relative to the semiconductor epitaxial structure and covers the transparent conductive layer. The particles in the leveling layer are coarse at first and then fine at second. The leveling layer includes a first leveling layer and a second leveling layer. The first leveling layer covers the transparent conductive layer, and the second leveling layer covers the first leveling layer to fill the gaps between the particles in the first leveling layer.

2. The light-emitting diode according to claim 1, characterized in that, The height of the leveling layer is 900~1500nm.

3. The light-emitting diode according to claim 1, characterized in that, The material of the leveling layer is SiO2, SiNx, Al2O3, MgO or AlN.

4. The light-emitting diode according to claim 1, characterized in that, The adhesive layer of the first conductive structure is disposed on the leveling layer, and the adhesive layer of the second conductive structure is disposed on the transparent conductive layer.

5. The light-emitting diode according to claim 1, characterized in that, The adhesive layer is made of Cr, Ni, Ti or indium tin oxide.

6. The light-emitting diode according to claim 1, characterized in that, The material of the weld layer is tin or a gold-tin alloy.

7. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode is a miniature light-emitting diode.

8. A light-emitting diode display, characterized in that, The light-emitting diode as described in claim 1, wherein the light-emitting diode comprises: Substrate; A first semiconductor layer is disposed on the substrate; An active layer is disposed on the first semiconductor layer; A second semiconductor layer is disposed on the active layer; A first conductive structure is disposed on the first semiconductor layer; and A second conductive structure is disposed on the second semiconductor layer; The first conductive structure and the second conductive structure include an adhesive layer, a stretching layer, a stacked layer and a welding layer arranged sequentially. The stretching layer is made of a composite layer formed by an alloy of titanium and aluminum, an alloy of nickel and aluminum, an alloy of titanium and silver, or an alloy of nickel and silver. The thickness of the stretching layer is (50~200)*N nm, where N ranges from 3 to 9. The stacked layer is made of an alloy of platinum and titanium, or an alloy of titanium and nickel. The light-emitting diode further includes a transparent conductive layer, which is disposed on the second semiconductor layer, and the second conductive structure is disposed on the transparent conductive layer; The first conductive structure further includes a leveling layer, which is disposed on the first semiconductor layer and is at the same height as the transparent conductive layer. The light-emitting diode further includes a leveling layer, which is located on the side of the transparent conductive layer relative to the semiconductor epitaxial structure and covers the transparent conductive layer. The particles in the leveling layer are coarse at first and then fine at second. The leveling layer includes a first leveling layer and a second leveling layer. The first leveling layer covers the transparent conductive layer, and the second leveling layer covers the first leveling layer to fill the gaps between the particles in the first leveling layer.

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