Semiconductor devices and their manufacturing methods

Abstract

This disclosure relates to semiconductor devices and methods for manufacturing the same. One method includes forming a fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate. A dummy gate structure is formed across the fin structure. An exposed second portion of the fin structure is removed. A selective etching process is performed using a gas mixture comprising a hydrogen-containing gas and a fluorine-containing gas to laterally recess the first semiconductor layers. Internal spacers are formed on opposite end faces of the laterally recessed first semiconductor layers. Source / drain epitaxial structures are formed on opposite end faces of the second semiconductor layers. The dummy gate structure is removed to expose a first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed around each second semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous one. Throughout IC development, functional density (the number of interconnect devices per chip area) has typically increased, while geometry (the smallest component (or line) that can be produced using manufacturing processes) has decreased. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate; forming a dummy gate structure across the fin structure such that the dummy gate structure covers a first portion of the fin structure while a second portion of the fin structure is exposed; removing the exposed second portion of the fin structure; after removing the second portion of the fin structure, performing a selective etching process using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas to laterally recess the first semiconductor layers in the first portion of the fin structure, wherein the selective etching process etches the first semiconductor layers at an etch rate faster than etching the second semiconductor layers; forming internal spacers on opposite end faces of the laterally recessed first semiconductor layers in the first portion of the fin structure; forming source / drain epitaxial structures on opposite end faces of the second semiconductor layers in the first portion of the fin structure; removing the dummy gate structure to expose the first portion of the fin structure; removing the laterally recessed first semiconductor layers in the exposed first portion of the fin structure while retaining the second semiconductor layers in the exposed first portion of the fin structure suspended above the substrate; and forming a gate structure to surround each suspended second semiconductor layer.

[0004] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate; patterning the stacked structure into a fin structure extending along a first direction; forming a dummy gate structure extending across the fin structure along a second direction perpendicular to the first direction; forming gate spacers on opposite sides of the dummy gate structure; removing the dummy gate structure to form a gate trench between the gate spacers; performing a hydrogen radical treatment on the first semiconductor layer and the second semiconductor layer of the fin structure in the gate trench to remove oxygen from the first semiconductor layer and the second semiconductor layer; after performing the hydrogen radical treatment, selectively removing the first semiconductor layer from the gate trench while retaining the second semiconductor layer suspended in the gate trench; and after selectively removing the first semiconductor layer from the gate trench, forming a gate structure in the gate trench.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a plurality of channel layers arranged vertically and horizontally at intervals on a substrate; a gate structure surrounding each of the plurality of channel layers; a source / drain epitaxial structure connected to the plurality of channel layers, wherein the plurality of channel layers include Si-H bonds at the interface between the source / drain epitaxial structure and the plurality of channel layers; and a plurality of internal spacers between the source / drain epitaxial structure and the gate structure. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1-21J Methods for manufacturing semiconductor devices at various stages are illustrated according to some embodiments of the present disclosure.

[0008] Figure 22 This is a side view of a processing tool according to some embodiments of the present disclosure.

[0009] Figure 23A and Figure 23B This is a flowchart of a method M for forming a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 24 This is a schematic diagram of chemical molecules used in hydrogen radical treatment and surface cleaning processes according to some embodiments of this disclosure.

[0011] Figure 25 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," "above," etc., are used herein to describe the relationship between one element or feature and another element (or feature) or feature (or feature) as shown in the figures. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative terms used herein may be interpreted accordingly.

[0014] As used herein, “approximately,” “about,” “close to,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The numerical quantities given here are approximate, meaning that the terms “approximately,” “about,” “close to,” or “substantially” can be inferred unless explicitly stated otherwise.

[0015] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0016] This disclosure relates to semiconductor devices and methods of forming the same. More specifically, some embodiments of this disclosure relate to GAA devices comprising an improved profile of nanosheets and internal spacers. The GAA devices proposed herein include p-type GAA devices or n-type GAA devices. Furthermore, GAA devices may have one or more channel regions (e.g., nanowires) associated with a single, continuous gate structure or multiple gate structures. Other examples of semiconductor devices that may benefit from aspects of this disclosure will be recognized by those skilled in the art.

[0017] Figure 1-21J Methods for manufacturing semiconductor devices at various stages are illustrated according to some embodiments of the present disclosure. In addition to semiconductor devices, Figure 1-21J The X, Y, and Z axis directions are also shown. In some embodiments, Figure 1-21J The semiconductor devices shown may be intermediate devices manufactured during the processing of an integrated circuit (IC) or a portion thereof, and may include static random access memory (SRAM), logic circuits, passive components (e.g., resistors, capacitors, and inductors) and / or active components (e.g., p-type field-effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors), other memory cells, and combinations thereof.

[0018] refer to Figure 1 A substrate 110 is provided, which may be part of a wafer. In some embodiments, substrate 110 may include silicon (Si). Optionally, substrate 110 may include germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, substrate 110 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Alternatively, substrate 110 may include a buried dielectric layer such as a buried oxide (BOX) layer, such as a buried dielectric layer formed by a technique called oxygen implantation separation (SIMOX), wafer bonding, SEG, or other suitable methods. In various embodiments, substrate 110 may include any of a variety of substrate structures and materials.

[0019] A stacked structure 120 is formed on a substrate 110 via epitaxy, such that the stacked structure 120 forms a crystalline layer. The stacked structure 120 includes alternately stacked first semiconductor layers 122 and second semiconductor layers 124. The first semiconductor layer 122 and the second semiconductor layer 124 are made of materials with different lattice constants and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layer 122 and the second semiconductor layer 124 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. Figure 1 In the configuration, five first semiconductor layers 122 and five second semiconductor layers 124 are arranged. However, the number of layers is not limited to five and can be as small as one (per layer), and in some embodiments, 2-10 layers of each of the first and second semiconductor layers are formed. The drive current of the GAA FET device can be adjusted by changing the number of stacked layers.

[0020] In some embodiments, the first semiconductor layer 122 may be a SiGe layer with a germanium atomic percentage greater than zero. In some embodiments, the germanium percentage of the first semiconductor layer 122 is in the range of about 15% to about 35%. In some embodiments, the thickness of the first semiconductor layer 122 is in the range of about 4 nm to about 7 nm.

[0021] In some embodiments, the second semiconductor layer 124 may be a pure silicon layer free of germanium. The second semiconductor layer 124 may also be a substantially pure silicon layer, for example, with a germanium atomic percentage of less than about 1%. Furthermore, the second semiconductor layer 124 may be intrinsic, undoped with p-type and n-type impurities. In some embodiments, the thickness of the second semiconductor layer 124 is in the range of about 8 nm to about 10.5 nm.

[0022] Subsequently, a mask layer 310 is formed on the stacked structure 120. In some embodiments, the mask layer 310 includes a first mask layer 312 and a second mask layer 314. The first mask layer 312 may be a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The second mask layer 314 may be made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD).

[0023] refer to Figure 2 Mask layer 310 (see...) Figure 1The mask layer 310 is patterned into a mask pattern using patterning operations including photolithography and etching. After patterning the mask layer 310, the stacked structure 120 is patterned using the patterned mask layer 310 as an etching mask (see [link]). Figure 1 This allows the stacked structure 120 to be patterned into fin structures 130 and grooves 102 extending in the X direction. Figure 2 In this configuration, two fin structures 130 are arranged in the Y direction. However, the number of fin structures is not limited to this and can be as small as one, or as many as three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 130 to improve pattern fidelity during patterning operations.

[0024] The trench 102 extends into the substrate 110 and has longitudinal directions that are substantially parallel to each other. The trench 102 forms a base 112 in the substrate 110, wherein the base 112 protrudes from the substrate 110, and fin structures 130 are formed on the base 112 of the substrate 110, respectively. Therefore, the remainder of the stacked structure 120 is alternatively referred to as the fin structure 130.

[0025] refer to Figure 3 After forming the fin structure 130, an insulating material layer 140 comprising one or more layers of insulating material is formed on the substrate, such that the fin structure 130 is completely embedded in the insulating material layer 140. The insulating material for the insulating material layer 140 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after forming the insulating material layer 140, particularly when the insulating material layer 140 is formed using flowable CVD. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method or an etch-back method, is performed to expose the upper surface of the uppermost second semiconductor layer 124 from the insulating material layer 140. In some embodiments, before forming the insulating layer 140, in Figure 2 A first liner layer 142 is formed on top of the structure. The first liner layer 142 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN).

[0026] refer to Figure 4 Insulating material layer 140 (see...) Figure 3The fin structure 130 is recessed to form an insulating layer 144, thereby exposing the upper portion of the fin structure 130. Through this operation, the fin structures 130 are electrically insulated from each other by the insulating layer 144, which is also referred to as an STI structure. In some embodiments, the insulating layer 140 is recessed until the bottommost first semiconductor layer 122 is exposed. The first semiconductor layer 122 is a sacrificial layer that is subsequently partially removed, and the second semiconductor layer 124 will serve as the channel region of the GAA FET.

[0027] refer to Figure 5 The sacrificial gate dielectric layer 150 is conformally formed on... Figure 4 The sacrificial gate dielectric layer 150 may comprise silicon dioxide, silicon nitride, a high-k dielectric material, or other suitable materials. In various examples, the sacrificial gate dielectric layer 150 may be deposited using ALD, CVD, subatmospheric pressure CVD (SACVD), flowable CVD, PVD, or other suitable processes. For example, the sacrificial gate dielectric layer 150 may be used to prevent damage to the fin structure 130 from subsequent processing (e.g., the formation of a subsequent dummy gate structure).

[0028] refer to Figure 6 At least one dummy gate structure 160 is formed on the sacrificial gate dielectric layer 150. The dummy gate structure 160 includes a dummy gate layer 162, a pad layer 164 formed on the dummy gate layer, and a mask layer 166 formed on the pad layer 164. The formation of the dummy gate structure 160 includes sequentially depositing the dummy gate layer, the pad layer, and the mask layer on the substrate 110; patterning the pad layer and the mask layer into patterned pad layer 164 and mask layer 166 using appropriate photolithography and etching techniques; and then using the pad layer 164 and mask layer 166 as a mask to pattern the dummy gate layer to form a patterned dummy gate layer 162. Thus, the dummy gate layer 162, the pad layer 164, and the mask layer 166 are referred to as the dummy gate structure 160. In some embodiments, the dummy gate layer 162 may be made of polysilicon (polycrystalline Si), polysilicon-germanium (polycrystalline SiGe), or other suitable materials. The pad layer 164 may be made of silicon nitride or other suitable materials, and the mask layer 166 may be made of silicon dioxide or other suitable materials. After patterning the dummy gate layer 162, the sacrificial gate dielectric layer 150 is also patterned to expose a portion of the fin structure 130, thereby defining the source / drain (S / D) region. In this disclosure, the source and drain are interchangeable and their structures are substantially the same.

[0029] refer to Figure 7The blanket layer 170' of the insulating material used for the sidewall spacers is conformally formed using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or subatmospheric chemical vapor deposition (SACVD). Figure 6 Structurally, the capping layer 170' is deposited conformally such that it has substantially equal thickness on the vertical surfaces (e.g., sidewalls), horizontal surfaces, and top of the dummy gate structure 160. In some embodiments, the insulating material of the capping layer 170' is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, or combinations thereof.

[0030] refer to Figure 8A and Figure 8B ,in Figure 8B It is along Figure 8A The cross-sectional view of line BB in the image is shown. Then, the capping layer 170' is etched using an anisotropic process (see...). Figure 7 A gate spacer 172 is formed on the opposite sidewall of the dummy gate structure 160, and a fin sidewall spacer 174 is formed on the opposite sidewall of the fin structure 130. The exposed portion of the fin structure 130 extending laterally beyond the gate spacer 172 is then etched using one or more etching steps with one or more suitable etchants, which etch silicon and silicon germanium at a faster etch rate than the spacer material (e.g., a nitride-based material).

[0031] Gate spacer 172 and fin sidewall spacer 174 may include a sealing spacer and a main spacer (not shown). The sealing spacer may be formed on the sidewall of the dummy gate structure 160, and the main spacer may be formed on the sealing spacer. In some embodiments, anisotropic processes may be controlled such that no fin sidewall spacer 174 is present on the insulating layer 144. The anisotropic etching performed on the capping layer 170' may be, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from the horizontal surface, leaving a dielectric spacer layer on vertical surfaces such as the sidewalls of the dummy gate structure 160 and the exposed sidewalls of the fin structure 130.

[0032] In some embodiments, the exposed portion of the fin structure 130 is removed to form the recess 132 by using a strained source / drain (SSD) etching process. The SSD etching process can be performed in various ways. In some embodiments, the SSD etching process can be performed by dry chemical etching utilizing a plasma source and a reactive gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer-coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc., and the reactive gas can be a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, etc.), chloride (Cl2), hydrogen bromide (HBr), oxygen (O2), etc., or combinations thereof. In some other embodiments, the SSD etching process can be performed by wet chemical etching, such as ammonium peroxide mixtures (APM), NH4OH, TMAH, combinations thereof, etc. In still other embodiments, the SSD etching step can be performed by a combination of dry chemical etching and wet chemical etching.

[0033] In some embodiments, when oxygen is involved in the SSD etching process, some oxygen atoms may be unintentionally doped into the remaining semiconductor layers 122 and 124, forming oxygen impurities and / or oxide materials (e.g., SiO2). x and / or GeO x )(See Figure 9B This results in the remaining semiconductor layers 122 and 124 comprising oxygen impurities and / or oxides. Furthermore, native oxides (e.g., Figure 9B The oxide layer 105 shown may be formed on the exposed surfaces of the remaining semiconductor layers 122 and 124 after the SSD etching process.

[0034] Once the SSD etching process is complete, a hydrogen radical treatment is performed on the remaining first semiconductor layer 122 and second semiconductor layer 124 to remove oxygen therein. In some embodiments, a method such as... Figure 22 The processing tool 400 shown is used to perform hydrogen radical treatment. (Reference) Figure 9A and Figure 22 In some embodiments, including Figure 8AA wafer W with a specific structure is arranged in a processing tool 400 to perform a hydrogen radical process 350. The processing tool 400 includes a processing chamber 410 having chamber walls 412. The processing chamber 410 is closed by a movable cover (or lid) 420 and includes a base assembly 430, which can be raised and lowered on an axis 435 by actuating a base lifting assembly. One or more remote plasma sources 440 are located above the processing chamber 410 to provide remote plasma into the processing chamber 410 via gas lines 450 and gas distribution plates 455. During operation of the processing tool 400, the base assembly 430 supports the wafer W within the processing chamber 410. One or more plasma materials are supplied to the processing chamber 410 from the remote plasma sources 440.

[0035] Figure 9B-9D This indicates the hydrogen radical treatment 350 according to some embodiments. Figure 9A An enlarged view of a portion of the etched first semiconductor layer 122 and second semiconductor layer 124 shown. (Reference) Figure 9B-9D and Figure 22 As described above, in some embodiments, hydrogen radical treatment 350 is performed using processing tool 400. A wafer W is disposed on a substrate assembly 430, and hydrogen radicals 910 generated by ionized hydrogen-containing gas (e.g., H2 or other suitable hydrogen-containing gas) are introduced into the processing chamber 410 from a remote plasma source 440. The hydrogen radicals 910 react with oxides 920 in the remaining semiconductor layers 122 and 124 to form -OH 930, thereby removing oxygen (e.g., in the form of H2O 935 or other suitable forms) from the remaining first semiconductor layer 122 and second semiconductor layer 124. More specifically, the hydrogen radicals 910 have reacting with oxides 920 in the first semiconductor layer 122 and second semiconductor layer 124 (e.g., SiO2). x and GeO x The low activation energy of the 920 reaction. Furthermore, the small size of the hydrogen radical 910 facilitates deep penetration into the first semiconductor layer 122 and the second semiconductor layer 124 to react with the oxide 920. Thus, the hydrogen radical 910 can be used as a promising candidate for removing oxygen deep within the semiconductor layers 122 and 124 (e.g., removing oxygen at a depth of at least 2 nm in the SiGe layer), which will be discussed below. Figure 24To elaborate further. After hydrogen radical treatment 350, the thickness of oxide layer 105 (native oxide) remains substantially unchanged. In some embodiments, the remote plasma power of the remote plasma source 440 used to provide hydrogen radicals is in the range of about 500 W to about 5000 W. If the remote plasma power is less than about 500 W, oxygen in the remaining first semiconductor layer 122 and second semiconductor layer 124 may not be effectively removed; if the remote plasma power is greater than about 5000 W, the remote plasma may damage the structure formed on wafer W.

[0036] In some embodiments, the processing temperature can be adjusted during the hydrogen radical treatment 350. For example, the movable cover 420 and / or chamber wall 412 include heaters to regulate the temperature of the processing chamber 410 (and wafer W). The processing tool 400 may further include a cooler 470 to regulate the temperature of the pedestal assembly 430 (and wafer W). For example, the cooler 470 may deliver cooling liquid to the pedestal assembly 430 via a pipe 475. In some embodiments, the processing temperature of the processing chamber 410 is in the range of about 80 degrees Celsius to about 350 degrees Celsius, and the processing temperature of the pedestal assembly 430 is in the range of about 80 degrees Celsius to about 350 degrees Celsius to activate hydrogen radicals. If the processing temperature exceeds the above range, oxygen in the remaining first semiconductor layer 122 and second semiconductor layer 124 may not be effectively removed.

[0037] In some embodiments, the processing tool 400 further includes a pressure controller 460 to control the pressure of the processing chamber 410 via a valve 465. In some embodiments, when the wafer W is located in the processing chamber 410, a vacuum is applied to the processing chamber 410 via the pressure controller 460 to remove oxygen and moisture, such that the pressure controller 460 is configured to control the pressure inside the processing chamber 410. In some embodiments, during the hydrogen radical treatment 350, the processing pressure of the processing chamber 410 is in the range of about 500 mT to about 10000 mT. If the processing pressure exceeds the above range, it may be impossible to effectively remove oxygen from the remaining first semiconductor layer 122 and second semiconductor layer 124.

[0038] like Figure 9A As shown, the hydrogen radical treatment 350 is configured to remove oxygen from the remaining first semiconductor layer 122 and second semiconductor layer 124. If the SSD etching process is performed in an oxygen-free environment and / or without oxygen, the hydrogen radical treatment 350 can be omitted.

[0039] refer to Figure 10AAfter removing oxygen from the first semiconductor layer 122 and the second semiconductor layer 124 using hydrogen radical treatment 350, if native oxides are natively formed on the semiconductor surface after the hydrogen radical treatment 350 is completed, a surface cleaning process 360 may be performed to remove the remaining native oxides on the exposed surfaces of the first semiconductor layer 122 and the second semiconductor layer 124 (e.g., Figure 9B-9D The oxide layer 105 shown.

[0040] Figure 10B-10D This indicates that during the surface cleaning process 360 according to some embodiments Figure 10A An enlarged view of a portion of the etched first semiconductor layer 122 and second semiconductor layer 124 is shown. Figure 10E This is the band structure diagram of SiO2 with / without NH3 gas during the 360° surface cleaning process. (Reference) Figure 10B-10D And 22. In some embodiments, the surface cleaning process 360 includes applying a gas mixture 960 of hydrofluoric acid gas (HF gas) and NH3 gas to the surfaces of the first semiconductor layer 122 and the second semiconductor layer 124 for approximately tens of seconds. Using NH3 gas as a catalyst reduces the interaction between the etching gas (e.g., in this case, the HF+NH3 gas mixture 960) and the oxide of the oxide layer 105 (i.e., SiO2). x and GeO x The activation energy of the chemical reaction between the two (see Figure 10E) allows for more efficient removal of native oxides. The surface cleaning process 360 can be a dry (e.g., HF vapor and / or H-containing gas (e.g., NH3) annealing) or a wet (e.g., HF immersion) etching process.

[0041] refer to Figure 10A and Figure 22 In some embodiments, the cleaning process 360 is performed in the processing tool 400. That is, the hydrogen radical treatment 350 and the cleaning process 360 are performed in situ, which in turn reduces (oxygen) contamination of the remaining first semiconductor layer 122 and second semiconductor layer 124.

[0042] As used herein, the term "in-situ" is used to describe processing performed while the wafer or substrate is held within a processing system (e.g., including a load-locking chamber, a transfer chamber, a processing chamber, or any other fluid-coupled chamber), and wherein, for example, the processing system allows the wafer W to be held under vacuum conditions. Therefore, the term "in-situ" can also generally be used to refer to processes in which the device or wafer W being processed is not exposed to an external environment (e.g., outside the processing system).

[0043] Prior to surface cleaning process 360, remote plasma source 440 stops supplying plasma (e.g., stops supplying hydrogen radicals), and heaters in movable cover 420, chamber wall 412, and / or cooler 470 control the temperature of processing chamber 410 to perform surface cleaning process 360. Furthermore, pressure in processing chamber 410 is regulated by pressure controller 460 for use in cleaning process 360. In some embodiments, the processing temperature of processing chamber 410 is in the range of about 80 degrees Celsius to about 250 degrees Celsius, and the processing temperature of base assembly 430 is in the range of about 0 degrees Celsius to about 250 degrees Celsius to perform cleaning process 360. In some embodiments, the pressure in processing chamber 410 during cleaning process 360 is in the range of about 20 mT to about 10000 mT. If the processing temperature / pressure exceeds the above ranges, native oxides may not be effectively removed.

[0044] In some embodiments, the processing tool 400 further includes gas sources 480a-480c, configured to inject different reactive gases into the processing chamber 410. For example, during the surface cleaning process 360, HF gas is injected from gas source 480a and NH3 gas is injected from gas source 480b to remove native oxides. In some embodiments, gas sources 480a-480c are connected to a gas distribution plate 455 via gas lines 485, such that the gases injected from gas sources 480a-480c can be uniformly distributed in the processing chamber 410.

[0045] like Figure 10A The surface cleaning process 360 shown is configured to remove native oxides from the surfaces of the remaining first semiconductor layer 122 and second semiconductor layer 124. If no or almost no native oxides are formed on the surfaces of the remaining first semiconductor layer 122 and second semiconductor layer 124, the surface cleaning process 360 can be omitted. Furthermore, in some other embodiments, the surface cleaning process 360 can be performed prior to the hydrogen radical treatment 350.

[0046] Figure 24 This is a schematic diagram of chemical molecules used in hydrogen radical treatment 350 and surface cleaning process 360 according to some embodiments of this disclosure. In some embodiments, hydrogen radical treatment 350 is performed using hydrogen radicals 910, and surface cleaning process 360 is performed using a gas mixture 960 comprising HF gas and NH3 gas. Figure 24 As shown, hydrogen radical 910 can react with oxide 920 (e.g., SiO2). x and / or GeO x The reaction forms -OH 930. Hydrogen radical 910 and SiO2. xThe activation energy of the reaction between them is 0.15 eV to 0.19 eV (e.g., about 0.17 eV), and the hydrogen radical 910 reacts with GeO. x The activation energy for the reaction is from about 0.00 eV to about 0.03 eV (e.g., about 0.00 eV). That is, hydrogen radical 910 readily reacts with oxides. Therefore, hydrogen radical 910 can be used to remove oxygen from the first semiconductor layer 122 and the second semiconductor layer 124 (see...). Figure 9D ).

[0047] Furthermore, the gas mixture 960, including HF and NH3 gases, can react with oxide 920 to form -OH 930 and NH3 970. The gas mixture 960 and SiO x The activation energy of the reaction between them is from about 1.75 eV to about 1.9 eV (e.g., about 1.81 eV), and the gas mixture 960 with GeO x The activation energy of the reaction between them is about 2.5 eV to about 2.8 eV (e.g., about 2.69 eV). Thus, the gas mixture 960 can be used to remove native oxides formed on the surfaces of the first semiconductor layer 122 and the second semiconductor layer 124.

[0048] Furthermore, the hydrogen radical 910 has a radius of about 0.08 nm to about 0.15 nm (e.g., about 0.11 nm), and the gas mixture 960 has dimensions D1 and D2, where dimension D1 is about 0.35 nm to about 0.48 nm (e.g., about 0.40 nm), and dimension D2 is about 0.25 nm to about 0.29 nm (e.g., about 0.27 nm). Because the size of the hydrogen radical 910 is smaller than the size of the HF / NH3 gas mixture 960, the hydrogen radical 910 can penetrate deeper into the first semiconductor layer 122 and the second semiconductor layer 124 than the HF / NH3 gas mixture 960. Therefore, the hydrogen radical 910 can be used as an oxide deep within the Si layer and SiGe layer (e.g., SiO2 at least 2 nm deep in the Si layer and SiGe layer). x / GeO x The reaction is a promising candidate for removing oxygen impurities deep within the Si and SiGe layers. Conversely, the gas mixture 960 can be used as a suitable candidate for removing native oxides on the surface of the Si and SiGe layers when native oxidation occurs after the completion of the hydrogen radical treatment 350, and / or when native oxides remain on the Si / SiGe surface during the hydrogen radical treatment 350.

[0049] refer to Figure 11A-11C ,in Figure 11B It is along Figure 11A A cross-sectional view taken from line BB in the diagram. Figure 11C It is along Figure 11B The top view is taken by line CC. The first semiconductor layer 122 is horizontally recessed (etched) to form a recess 125, such that the second semiconductor layer 124 extends laterally beyond the opposite end face of the first semiconductor layer 122. In some embodiments, such as Figure 11B As shown, the end face 123 of the first semiconductor layer 122 can be substantially perpendicularly aligned with the side surface of the dummy gate layer 162. Here, "substantially perpendicularly aligned" means that the horizontal offset is less than about 1 nm.

[0050] In some embodiments, the first semiconductor layer 122 is etched / dug using a selective chemical dry etching (CDE) process 370, which is tailored to remove the first semiconductor layer 122 while the second semiconductor layer 124 remains substantially intact. Figure 11D illustrates the process during the selective chemical dry etching process 370 according to some embodiments. Figure 11B An enlarged view of a portion of the etched first semiconductor layer 122 and second semiconductor layer 124. In some embodiments, the selective chemical dry etching process 370 may include a gas mixture 980 of a fluorine-containing gas (e.g., fluorine (F2) gas) and a hydrogen-containing gas (e.g., hydrofluoric acid (HF) gas). In some embodiments where the first semiconductor layer 122 comprises SiGe and the second semiconductor layer 124 comprises Si, the fluorine-containing gas and the hydrogen-containing gas react with the first semiconductor layer 122 (in this case, SiGe) as shown by the following equations (1) and (2):

[0051] GeF3 + SiF3 → GeF2 + SiF4(g) [E A The voltage ranges from about 0.28 eV to about 0.32 eV (e.g., about 0.30 eV)[1]

[0052] GeH2F + SiHF2 → SiF2 + GeH3F(g) [E A The voltage ranges from approximately 0.93 eV to approximately 0.97 eV (e.g., approximately 0.95 eV) [2]

[0053] Here, EA is the activation energy of the corresponding reaction, and SiF4 and GeH3F gases can be discharged. Equation (1) represents the migration of F from Ge to Si, and equation (2) represents the removal of Ge by HF.

[0054] The fluorine-containing gas and the hydrogen-containing gas further react with the second semiconductor layer 124 (in this case, Si), as shown in the following equation (3):

[0055] SiF3 + SiF3 → SiF2 + SiF4(g) [E AThe voltage ranges from approximately 1.48 eV to approximately 1.52 eV (e.g., approximately 1.50 eV)[(3)]

[0056] EA is the activation energy of the corresponding reaction and can release SiF4 gas.

[0057] As shown in equations (1)-(3), since the activation energies of equations (1) and (2) are lower than that of equation (3), the reactions described in equations (1) and (2) are more easily activated than the reactions described in equation (3). That is, the gas mixture 980 containing fluorine and hydrogen gases reacts more readily with the first semiconductor layer 122 (i.e., the SiGe layer) compared to the second semiconductor layer 124 (i.e., the Si layer). Figure 11E As shown. Thus, during the selective chemical dry etching process 370, the etching rate of the first semiconductor layer 122 is much higher than that of the second semiconductor layer 124. For example, using a gas mixture containing fluorine and hydrogen as the etching gas, the loss of the second semiconductor layer (Si layer) 124 (i.e., the depth of the recesses formed in the second semiconductor layer 124) is about 1 nm less. If F radicals are used to etch the second semiconductor layer 124, the loss of the second semiconductor layer 124 can be greater than about 1.5 nm.

[0058] Furthermore, since the activation energy of equation (3) is higher than that of equations (1) and (2), SiF2H- can be retained on the sidewall 126 of the second semiconductor layer 124. Thus, SiF2H- can be detected on the sidewall 126 of the second semiconductor layer 124. Alternatively, the second semiconductor layer 124 may include F and / or H on its sidewall 126. Alternatively, the second semiconductor layer 124 may include Si-H bonds and / or Si-F bonds on its sidewall 126.

[0059] Figure 11F-11L This is according to some other embodiments during the selective chemical dry etching process 370. Figure 11B An enlarged view of a portion of the etched fin structure shown. Figure 11F-11L In the process, a recess 132 is formed in the etched fin structure 130, such that the etched fin structure 130 is cut into at least two parts. Figure 11F In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 20 at approximately 40 degrees Celsius. Figure 11G In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 40 at approximately 40 degrees Celsius. Figure 11HIn this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 60 at approximately 40 degrees Celsius. Figure 11I In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 80 at approximately 40 degrees Celsius. Figure 11J In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 40 degrees Celsius. Figure 11K In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 60 degrees Celsius. Figure 11L In the process, a selective chemical dry etching process 370 is performed at a temperature of approximately 80 degrees Celsius.

[0060] In some embodiments, equations (1)-(3) are satisfied within a temperature range of about 0 degrees Celsius to about 90 degrees Celsius, or within a temperature range of about 20 degrees Celsius to about 80 degrees Celsius. That is, with good etch selectivity between the first semiconductor layer 122 and the second semiconductor layer 124, Figures 11A and 124 can be executed at room temperature (e.g., about 20 degrees Celsius) or higher. Figure 11B The selective chemical dry etching process 370 shown is as follows (e.g.) Figure 11J-11L (as shown), which facilitates chamber maintenance (for mass production). In some embodiments, a selective chemical dry etching process 370 is performed at a temperature ranging from about 20 degrees Celsius to about 65 degrees Celsius, thereby producing good silicon loss control.

[0061] In some embodiments, by using Figure 22 The processing tool 400 horizontally recesses the first semiconductor layer 122. That is, the cleaning process 360 and the selective chemical dry etching process 370 of the first semiconductor layer 122 are performed in situ, which in turn prevents (oxygen) contamination of the remaining first semiconductor layer 122 and second semiconductor layer 124.

[0062] Prior to the selective chemical dry etching process 370, gas sources 480a and 480b cease supplying gas, and heaters in the movable cover 420, chamber wall 412, and / or cooler 470 control the temperature 410 of the processing chamber for the recess process. Furthermore, the pressure of the processing chamber 410 is regulated by a pressure controller 460 to process the recess process. In some embodiments, the processing temperature of the processing chamber 410 is in the range of about 80 degrees Celsius to about 250 degrees Celsius, and the processing temperature of the base assembly 430 is in the range of about 20 degrees Celsius to about 100 degrees Celsius to perform the selective chemical dry etching process 370. In some embodiments, the processing pressure of the processing chamber 410 is in the range of about 20 mT to about 10000 mT during the selective chemical dry etching process 370. If the processing temperature / pressure is outside the above ranges, the selective chemical dry etching process 370 may not have good etch selectivity between the first semiconductor layer 122 and the second semiconductor layer 124.

[0063] During the selective chemical dry etching process 370, a hydrogen-containing gas (e.g., HF gas) is injected from a gas source 480a, and a fluorine-containing gas (e.g., F2 gas) is injected from a gas source 480c to recess the first semiconductor layer 122. In some embodiments, the flow rate ratio of the hydrogen-containing gas to the fluorine-containing gas (e.g., HF gas / F2 gas) can be in the range of about 0.2 to about 120. The selection of the HF gas to F2 gas flow rate ratio depends on the desired depth variation of the recess 125. For example, as... Figure 11M As shown, when the gas ratio is between 0.2 and about 50, the depth variation of recess 125 is less than about 15%, and when the gas ratio is between 20 and about 120, the depth variation of recess 125 is less than about 6%. In some embodiments, the depth variation of recess 125 increases when the gas ratio is greater than about 120 and less than about 20. For example, when the gas ratio is greater than about 120, the lower recess 125 is much deeper than the upper recess 125. In some other embodiments, when the flow rate ratio is about 0 (i.e., HF gas is omitted), the depth variation of recess 125 is greater than about 35%. In some embodiments, gas source 480a provides hydrogen-containing gas at a flow rate of about 5 sccm to about 5000 sccm, and gas source 480c provides fluorine-containing gas at a flow rate of about 5 sccm to about 5000 sccm.

[0064] In some embodiments, the end face 123 of the recessed first semiconductor layer 122 is as follows: Figure 11CThe plan view shown may have a curved corner 123c. The lateral distance 123d (also referred to as the undesired smiling profile) between the farthest points of the curved corner 123c of the end face 123 is at least attributed to the processing temperature (of the processing chamber 410) during the selective chemical dry etching process 370. For example, as the processing temperature increases, the lateral distance 123d between the farthest points of the curved corner 123c of the end face 123 decreases. In some embodiments, such as Figure 11N As shown, Figure 11N The probability of the lateral distance being less than about 2 nm and less than about 3 nm is shown at different processing temperatures. When the processing temperature is in the range of about 30 degrees Celsius to about 90 degrees Celsius, the lateral distance 123d can be less than about 3 nm, for example, less than about 2 nm. Thus, increasing the processing temperature improves the smile problem of the first semiconductor layer 122.

[0065] In some embodiments of the selective chemical dry etching process 370, where the etching gases include HF and F2 gases, surface native oxides on the SiGe layer and / or oxygen impurities deep within the SiGe layer may block the etching gases, potentially slowing down the etching rate of the selective chemical dry etching process 370. However, due to hydrogen radical treatment 350 (see...) Figure 9A ) and / or surface cleaning process 360 (see Figure 10A As previously described, removing oxygen impurities deep within the SiGe layer and / or native surface oxides on the SiGe layer can improve the etching rate of the selective chemical dry etching process 370. In some other embodiments, the hydrogen radical treatment 350 and / or surface cleaning process 360 can be omitted as described above.

[0066] refer to Figure 12A and Figure 12B ,in Figure 12B It is along Figure 12A The cross-sectional view taken from line BB in the diagram. Figure 11A and Figure 11B A dielectric material layer 180' is formed on top of the structure. In some embodiments, the dielectric material layer 180' comprises a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, or combinations thereof, and differs from the material of the gate spacer 172. In some embodiments, the dielectric material layer 180' is silicon nitride. Figure 12B As shown, the dielectric material layer 180' can completely fill the recess 125. The dielectric material layer 180' can be formed using CVD, PVD, ALD or other suitable processes, including LPCVD and PECVD.

[0067] Figure 12C-12IThis is according to some other embodiments during the selective chemical dry etching process 370. Figure 12B An enlarged view of a portion of the etched fin structure shown. Figure 12C-12I In the process, a recess 132 is formed in the etched fin structure 130, such that the etched fin structure 130 is cut into at least two parts. Figure 12C In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 20 at approximately 40 degrees Celsius. Figure 12D In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 40 at approximately 40 degrees Celsius. Figure 12E In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 60 at approximately 40 degrees Celsius. Figure 12F In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 80 at approximately 40 degrees Celsius. Figure 12G In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 40 degrees Celsius. Figure 12H In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 60 degrees Celsius. Figure 12I In the process, a selective chemical dry etching process 370 is performed at a temperature of approximately 80 degrees Celsius.

[0068] refer to Figure 13A and Figure 13B ,in Figure 13B It is along Figure 13A The cross-sectional view taken from line BB in the diagram. By etching the dielectric material layer 180', the recesses 125 of the semiconductor layer 122 are respectively (see Figure 11B Internal spacers 180 are formed within the [structure / process]. The etching operation includes one or more wet and / or dry etching operations. In some embodiments, the etching is isotropic etching. For example... Figure 13B As shown, the internal spacer 180 can completely fill the recess 125.

[0069] refer to Figure 13C ,in Figure 13C It is along Figure 13B The top view is taken by line CC. The internal spacer 180 may inherit the outline of the recess 125 (see...). Figure 11CThis allows the inner surface 182 of the inner spacer 180 to have a curvature angle 182c. The lateral distance 182d between the farthest points of the curvature angle 182c of the inner surface 182 (i.e., the interface between the inner spacer 180 and the first semiconductor layer 122) is less than about 3 nm, for example, less than about 2 nm.

[0070] Figure 13D-13J This is according to some other embodiments during the selective chemical dry etching process 370. Figure 13B An enlarged view of a portion of the etched fin structure shown. Figure 13D-13J In the process, a recess 132 is formed in the etched fin structure 130, such that the etched fin structure 130 is cut into at least two parts. Figure 13D In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 20 at approximately 40 degrees Celsius. Figure 13E In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 40 at approximately 40 degrees Celsius. Figure 13F In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 60 at approximately 40 degrees Celsius. Figure 13G In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 80 at approximately 40 degrees Celsius. Figure 13H In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 40 degrees Celsius. Figure 13I In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 60 degrees Celsius. Figure 13J In the process, a selective chemical dry etching process 370 is performed at a temperature of approximately 80 degrees Celsius.

[0071] refer to Figure 14 The source / drain (S / D) epitaxial structure 190 is epitaxially grown from the base 112 between the fin sidewall spacers 174. The S / D epitaxial structure 190 includes one or more layers of Si, SiP, SiC, and SiCp for an n-channel FET, or one or more layers of Si, SiGe, and Ge for a p-channel FET. The S / D epitaxial structure 190 is formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE). Figure 14 In some embodiments shown, the S / D epitaxial structures 190 grown from adjacent bases 112 of substrate 110 are merged over the insulating layer 144, and in some embodiments, voids are formed. In some other embodiments, the S / D epitaxial structures 190 grown from adjacent bases 112 are not merged.

[0072] refer to Figure 15 .exist Figure 14 A contact etch stop layer (CESL) 210 is conformally formed on the structure. In some embodiments, CESL 210 may be one or more stress layers. In some embodiments, CESL 210 has tensile stress and is formed of Si3N4. In some other embodiments, CESL 210 comprises a material such as oxide nitride. In still other embodiments, CESL 210 may have a composite structure comprising multiple layers, such as a silicon nitride layer overlying a silicon oxide layer. CESL 210 can be formed using plasma-enhanced CVD (PECVD); however, other suitable methods such as low-pressure CVD (LPCVD), atomic layer deposition (ALD), etc., may also be used.

[0073] Then, an interlayer dielectric (ILD) 220 is formed on CESL 210. The ILD 220 can be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the ILD 220 comprises silicon oxide. In some other embodiments, the ILD 220 may comprise silicon oxynitride, silicon nitride, compounds comprising Si, O, C, and / or H (e.g., silicon oxide, SiCOH, and SiOC), low-k materials, or organic materials (e.g., polymers). After the formation of the ILD 220, a planarization operation such as CMP is performed to remove the pad layer 164 and the mask layer 166 (see [link to documentation]). Figure 14 ), and exposes the dummy gate layer 162.

[0074] refer to Figure 16 Then remove the dummy gate layer 162 and the sacrificial gate dielectric layer 150 (see...). Figure 15 This exposes the first semiconductor layer 122 and the second semiconductor layer 124. During the removal of the dummy gate layer 162, the ILD 220 protects the S / D epitaxial structure 190. The dummy gate layer 162 can be removed using plasma dry etching and / or wet etching. When the dummy gate layer 162 is polysilicon and the ILD 220 is silicon oxide, the dummy gate layer 162 can be selectively removed using a wet etchant such as a TMAH solution. The dummy gate layer 162 can be removed using plasma dry etching and / or wet etching. Subsequently, the sacrificial gate dielectric layer 150 is also removed. Thus, the first semiconductor layer 122 and the second semiconductor layer 124 are exposed.

[0075] refer to Figure 17In some embodiments, an alternative hydrogen radical treatment 350' may be performed on the first semiconductor layer 122 and the second semiconductor layer 124 to remove oxygen deep within the first semiconductor layer 122 and the second semiconductor layer 124. In some embodiments, methods such as... Figure 22 The processing tool 400 shown is used to perform hydrogen radical treatment 350'. Hydrogen radical treatment 350' may be similar to or the same as hydrogen radical treatment 350 in FIG9A, and therefore its detailed description will not be repeated here. If the first semiconductor layer 122 and the second semiconductor layer 124 do not contain oxygen impurities / oxides, or contain negligible oxygen impurities / oxides, then hydrogen radical treatment 350' may be omitted.

[0076] refer to Figure 18 In some embodiments, an alternative surface cleaning process 360' may be performed on the first semiconductor layer 122 and the second semiconductor layer 124 to remove native oxides from the exposed surfaces of the first semiconductor layer 122 and the second semiconductor layer 124. In some embodiments, a surface cleaning process 360' may be used, such as... Figure 22 The processing tool 400 shown is used to perform surface cleaning process 360'. Cleaning process 360' can be used with... Figure 10A The cleaning process 360 is similar to or the same as that described above, and therefore will not be repeated here in detail. If the first semiconductor layer 122 and the second semiconductor layer 124 do not contain native oxides or contain negligible native oxides, the cleaning process 360' can be omitted.

[0077] refer to Figure 19A and 19B ,in Figure 19B It is along Figure 19A The cross-sectional view taken from line BB in the diagram. The first semiconductor layer 122 in the fin structure 130 (as shown in the image) is removed. Figure 18 As shown), nanosheets (or nanowires, nanorods, or nanopillars) are formed to create the second semiconductor layer 124. The first semiconductor layer 122 can be removed or etched using an etchant that selectively etches the first semiconductor layer 122 at a faster etch rate than the second semiconductor layer 124. For example, another selective chemical dry etching process 370' can be performed to remove the first semiconductor layer 122. In some embodiments, a process such as... Figure 22 The processing tool 400 shown is used to perform a selective chemical dry etching process 370'. The selective chemical dry etching process 370' can be used with... Figure 11A The selective chemical dry etching process 370 is similar to or the same as that used, and therefore its detailed description will not be repeated here.

[0078] Similarly, SiF2H- can be retained on the exposed surface 127 of the second semiconductor layer 124. Thus, SiF2H- can be detected on the exposed surface 127 of the second semiconductor layer 124. Alternatively, the second semiconductor layer 124 may include F or H on the exposed surface 127. Alternatively, the second semiconductor layer 124 may include Si-H bonds and / or Si-F bonds on the exposed surface 127.

[0079] exist Figure 19B In this process, since the internal spacer 180 is made of a material that is etch-selective to the first semiconductor layer 122, the internal spacer 180 protects the S / D epitaxial structure 190 from the etchant used in etching the first semiconductor layer 122.

[0080] refer to Figures 20A-20C ,in Figure 20B It is along Figure 20A A cross-sectional view taken from line BB in the diagram. Figure 20C It is along Figure 20A A cross-sectional view taken from line CC. A gate structure 230 is formed and / or filled between gate spacers 172 or internal spacers 180. That is, the gate structure 230 surrounds (encircles) the semiconductor layer 124. Gate spacers 172 are disposed on the opposite side of the gate structure 230. The gate structure 230 includes a gate dielectric layer 232 and a gate electrode 234. The gate electrode 234 includes one or more work function metal layers and fill metal. The gate dielectric layer 232 is formed conformally. That is, the gate dielectric layer 232 contacts the isolation structure 144 and the second semiconductor layer 124, wherein the second semiconductor layer 124 is referred to as the channel of the semiconductor device. Furthermore, the gate dielectric layer 232 surrounds the second semiconductor layer 124, and the space between the second semiconductor layers 124 is retained after the gate dielectric layer 232 is deposited. In some embodiments, the gate dielectric layer 232 comprises a high-k material (k greater than 7), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), alumina hafnium oxide (HfAlO2), silicon hafnium oxide (HfSiO2), aluminum oxide (Al2O3), or other suitable materials. In some embodiments, the gate dielectric layer 232 can be formed by performing an ALD process or other suitable processes.

[0081] In some embodiments, a work function metal layer is conformally formed on the gate dielectric layer 232 and surrounds the second semiconductor layer 124. The work function metal layer may comprise materials such as TiN, TaN, TiAlSi, TiSiN, TiAl, TaAl, or other suitable materials. In some embodiments, the work function metal layer may be formed by performing an ALD process or other suitable process.

[0082] The remaining space between the gate spacers 172 and the internal spacers 180 is filled with fill metal. That is, one or more work function metal layers contact and are located between the gate dielectric layer 232 and the fill metal. The fill metal may include materials such as tungsten or aluminum. After depositing the gate dielectric layer 232 and the gate electrode 234, a planarization process such as CMP can then be performed to remove excess portions of the gate dielectric layer 232 and the gate electrode 234 to form the gate structure 230.

[0083] refer to Figures 21A-21C ,in Figure 21B It is along Figure 21A A cross-sectional view taken from line BB in the diagram. Figure 21C It is along Figure 21A The image shows a cross-sectional view taken from line CC. ILD 220 is patterned to form trench 222 on the opposite side of gate structure 230, and then CESL 210 is patterned to expose the S / D epitaxial layer. In some embodiments, multiple etching processes are performed to pattern ILD 220 and CESL 210. The etching processes include dry etching processes, wet etching processes, or combinations thereof.

[0084] Contacts 240 are then formed in trench 222. Thus, contacts 240 contact the S / D epitaxial structure 190. In some embodiments, contacts 330 may be made of metal, such as W, Co, Ru, Al, Cu, or other suitable materials. After the deposition of contacts 240, a planarization process, such as chemical mechanical planarization (CMP), may be performed. In some embodiments, a metal alloy layer (e.g., silicide) may be formed between contacts 240 and the S / D epitaxial structure 190. Furthermore, a barrier layer may be formed in trench 222 prior to the formation of contacts 240. The barrier layer may be made of TiN, TaN, or a combination thereof.

[0085] exist Figure 21A In this context, the semiconductor device can be an (HGAA) transistor 100. For example... Figure 21B As shown, transistor 100 includes a second semiconductor layer 124 as its channel, and each of the second semiconductor layers 124 is surrounded by a gate structure 230. The outer edge (or sidewall) 126 of the (topmost) second semiconductor layer 124 is substantially vertically aligned with the outer edge 173 of the gate spacer 172. Here, "substantially vertically aligned" means a horizontal offset of less than about 1.2 nm. As described above, Figure 11AThe selective chemical dry etching process 370 removes almost no material from the second semiconductor layer 124, so that the length of the second semiconductor layer 124 remains essentially unchanged after the selective chemical dry etching process 370, thereby improving the electromobility of the transistor 100 and expanding the epitaxial growth window for forming the S / D epitaxial layer. The gate structure 230 includes a gate dielectric layer 232 and a gate electrode 234. The dielectric layer 232 surrounds (encircles) the semiconductor layer 124.

[0086] In some embodiments, the thickness T1 (in the Z-axis direction) of each second semiconductor layer 124 is in the range of about 8 nm to about 10.5 nm. In some embodiments, the thickness T1 of each second semiconductor layer 124 may vary slightly in the X-axis direction. For example, due to Figure 19A In the selective chemical dry etching process 370' shown, the central portion of the second semiconductor layer 124 may be slightly thinner than the edge portions of the same second semiconductor layer 124. In some embodiments, the thickness variation of the second semiconductor layer 124 ((distance between the highest and lowest points of the surface) / (twice the thickness T1)) is, for example, greater than 0 and less than about 0.5 nm. The thickness variation is a measure of surface uniformity. Reducing the thickness variation increases the surface uniformity of the second semiconductor layer 124. The surface of the second semiconductor layer 124 is smooth (due to...). Figure 19A The selective chemical dry etching process 370' shown in the figure is beneficial to the electromobility and quality improvement of the gate structure 230.

[0087] As described above, SiF2H- can be retained at the interface 126 (i.e., the sidewall 126 of the second semiconductor layer 124) between the second semiconductor layer 124 and the S / D epitaxial structure 190. Thus, SiF2H- can be detected at the interface 126. Alternatively, the second semiconductor layer 124 may include F and / or H at the interface 126. Alternatively, the second semiconductor layer 124 may include Si-H bonds and / or Si-F bonds at the interface 126.

[0088] Similarly, SiF2H- may be retained at the interface 127 (i.e., the surface 127 of the second semiconductor layer 124) between the second semiconductor layer 124 and the gate structure 230. Thus, SiF2H- can be detected at the interface 127. Alternatively, the second semiconductor layer 124 may include F and / or H at the interface 127. Alternatively, the second semiconductor layer 124 may include Si-H bonds and / or Si-F bonds at the interface 127.

[0089] Transistor 100 also includes an internal spacer 180 between gate structure 230 and S / D epitaxial layer to isolate gate structure 230 and S / D epitaxial layer. The internal spacer 180 reduces the RC delay of transistor 100 and improves ring oscillator (RO) performance. In some embodiments, the thickness T2 of the internal spacer 180 (in the Y-axis direction) is in the range of about 5 nm to about 65 nm. Furthermore, each internal spacer 180 has its own thickness T2, and the variation of these thicknesses T2 is less than about 6%. For example, if the thickness T2 of one of the internal spacers 180 is about 8 nm, then the thickness T2 of the other internal spacer 180 is in the range of about 7.5 nm to about 8.5 nm. Thus, the thickness T2 of the internal spacers 180 is substantially uniform. This is because during the selective chemical dry etching process 370, fluorine-containing gas and hydrogen-containing gas uniformly etch the first semiconductor layer 122 (see...). Figure 11A and 11B Furthermore, in some embodiments, a hydrogen radical treatment 350 is performed prior to the selective chemical dry etching process 370 (see [link to documentation]). Figure 9A ) and / or cleaning process 360 (see Figure 10A Removal of oxygen impurities and / or oxides facilitates the effective recessing / etching of the first semiconductor layer 122.

[0090] Figure 21D-21J This is according to some other embodiments during the selective chemical dry etching process 370. Figure 21B An enlarged view of a portion of the etched fin structure shown. Figure 21D In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 20 at approximately 40 degrees Celsius. Figure 21E In this process, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 40 at approximately 40 degrees Celsius. Figure 21F In Figure 21G, a selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 60 at approximately 40 degrees Celsius. In Figure 21G, the selective chemical dry etching process 370 is performed using a gas mixture of F2 gas and HF gas at a flow rate ratio of approximately 80 at approximately 40 degrees Celsius. Figure 21H In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 40 degrees Celsius. Figure 21I In this process, a selective chemical dry etching process 370 is performed at a temperature of approximately 60 degrees Celsius. Figure 21J In the process, a selective chemical dry etching process 370 is performed at a temperature of approximately 80 degrees Celsius.

[0091] Figure 23A and Figure 23B This is a flowchart of a method M for forming a semiconductor device according to some embodiments of the present disclosure. Although method M is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or actions may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0092] At frame S12, a fin structure comprising a first semiconductor layer and a second semiconductor layer is formed on the substrate, wherein the first semiconductor layer and the second semiconductor layer are stacked alternately. Figure 1-2 A perspective view corresponding to some embodiments of the action in block S12 is shown. At block S14, an insulating layer is formed to surround the fin structure. Figure 3-4 A perspective view corresponding to some embodiments of the action in block S14 is shown. At block S16, a first gate structure is formed over the fin structure. Figure 5-6 A perspective view corresponding to some embodiments of the action in block S16 is shown. At block S18, portions of the first semiconductor layer and the second semiconductor layer exposed by the first gate structure are removed. Figure 8A and Figure 8B Perspective and cross-sectional views of some embodiments corresponding to the actions in block S18 are shown. At block S20, hydrogen radical treatment is performed on the remaining first and second semiconductor layers. Figure 9A A perspective view corresponding to some embodiments of the action in block S20 is shown. At block S22, a surface cleaning process is performed on the remaining first and second semiconductor layers. Figure 10A A perspective view corresponding to some embodiments of the action in block S22 is shown. At block S24, a first semiconductor layer is recessed using a hydrogen-containing gas. Figure 11A and Figure 11B Perspective and cross-sectional views of some embodiments corresponding to the action in block S24 are shown. At block S26, internal spacers are formed on the sidewalls of the recessed first semiconductor layer. Figures 12A-13B Perspective and cross-sectional views of some embodiments corresponding to the action in block S26 are shown. At block S28, an epitaxial structure is formed on the opposite side of the second semiconductor layer. Figure 14 A perspective view corresponding to some embodiments of the action in block S28 is shown. At block S30, the first gate structure is removed. Figure 16A perspective view corresponding to some embodiments of the action in block S30 is shown. At block S32, hydrogen radical treatment is performed on the remaining first and second semiconductor layers. Figure 17 A perspective view corresponding to some embodiments of the action in block S32 is shown. At block S34, a surface cleaning process is performed on the remaining first and second semiconductor layers. Figure 18 A perspective view corresponding to some embodiments of the action in block S34 is shown. At block S36, a hydrogen-containing gas is used to remove the first semiconductor layer. Figure 19A and Figure 19B Perspective and cross-sectional views of some embodiments corresponding to the action in block S36 are shown. At block S38, a second gate structure is formed to surround the second semiconductor layer. Figures 20A-20C Perspective and cross-sectional views of some embodiments corresponding to the action in block S38 are shown. At block S40, a contact is formed over the extension structure. Figures 21A-21C Perspective views and cross-sectional views corresponding to some embodiments of the action in block S40 are shown. In some embodiments, blocks S20, S22, S32 and / or S34 may be omitted.

[0093] Figure 25 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 25 The difference between the semiconductor device in Figure 21B and the one in Figure 21B is related to the shape of the second semiconductor layer 124. Figure 25 In this process, the second semiconductor layers 124a-124e have different lengths. For example, second semiconductor layer 124a is shorter than second semiconductor layer 124b, second semiconductor layer 124b is shorter than second semiconductor layer 124c, second semiconductor layer 124c is shorter than second semiconductor layer 124d, and second semiconductor layer 124d is shorter than second semiconductor layer 124e. However, the internal spacers 180 have substantially the same thickness. Figure 25 Other relevant structural details of semiconductor devices and Figures 21A-21C The semiconductor devices are similar or identical, therefore, the description in this regard will not be repeated.

[0094] Based on the above discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor are all embodiments required to have a particular advantage. One advantage is that the selective chemical dry etching process improves the profile of the recessed first semiconductor layer, resulting in a uniform profile for the internal spacers formed on each side of the first semiconductor layer. Another advantage is that the selective chemical dry etching process also improves the profile (e.g., surface roughness) of the second semiconductor layer (channel), thereby improving both the electromobility and quality of the gate structure. Furthermore, with good etch selectivity between the first and second semiconductor layers, the selective chemical dry etching process can be performed at higher temperatures, which is beneficial for chamber maintenance (for mass production).

[0095] According to some embodiments, a method includes forming a fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate. A dummy gate structure is formed across the fin structure such that the dummy gate structure covers a first portion of the fin structure while a second portion of the fin structure is exposed. The exposed second portion of the fin structure is removed. After removing the second portion of the fin structure, a selective etching process is performed using a gas mixture comprising a hydrogen-containing gas and a fluorine-containing gas to laterally recess the first semiconductor layers in the first portion of the fin structure. The selective etching process etches the first semiconductor layers at an etch rate faster than that used to etch the second semiconductor layers. Internal spacers are formed on opposite end faces of the laterally recessed first semiconductor layers in the first portion of the fin structure. Source / drain epitaxial structures are formed on opposite end faces of the second semiconductor layers in the first portion of the fin structure. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers in the exposed first portion of the fin structure are removed while the second semiconductor layers in the exposed first portion of the fin structure are suspended above the substrate. A gate structure is formed around each suspended second semiconductor layer.

[0096] According to some embodiments, a method includes: forming a stacked structure of alternating first semiconductor layers and second semiconductor layers on a substrate. The stacked structure is patterned as a fin structure extending along a first direction. A dummy gate structure is formed, extending across the fin structure along a second direction substantially perpendicular to the first direction. An exposed second portion of the fin structure is removed. Gate spacers are formed on opposite sides of the dummy gate structure, respectively. The dummy gate structure is removed to form a gate trench between the gate spacers. A hydrogen radical treatment is performed on the first and second semiconductor layers of the fin structure in the gate trench to remove oxygen from the first and second semiconductor layers. After performing the hydrogen radical treatment, the first semiconductor layer is selectively removed from the gate trench, while the second semiconductor layer remains suspended in the gate trench. After selectively removing the first semiconductor layer from the gate trench, a gate structure is formed in the gate trench.

[0097] According to some embodiments, a device includes forming a plurality of channel layers, a gate structure, a source / drain epitaxial structure, and a plurality of internal spacers. The channel layers are arranged vertically and horizontally on a substrate in a spaced-apart manner. The gate structure surrounds each of the plurality of channel layers. The source / drain epitaxial structure is connected to the plurality of channel layers. The plurality of channel layers include Si-H bonds at the interface between the source / drain epitaxial structure and the plurality of channel layers. The internal spacers are located between the source / drain epitaxial structure and the gate structure.

[0098] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of this disclosure.

[0099] Example 1. A method of manufacturing a semiconductor device, comprising: forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate; forming a dummy gate structure across the fin structure such that the dummy gate structure covers a first portion of the fin structure while a second portion of the fin structure is exposed; removing the exposed second portion of the fin structure; after removing the second portion of the fin structure, performing a selective etching process using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas to laterally recess the first semiconductor layers in the first portion of the fin structure, wherein the selective etching process etches the first semiconductor layers at an etch rate faster than etching the second semiconductor layers; forming internal spacers on opposite end faces of the laterally recessed first semiconductor layers in the first portion of the fin structure; forming source / drain epitaxial structures on opposite end faces of the second semiconductor layers in the first portion of the fin structure; removing the dummy gate structure to expose the first portion of the fin structure; removing the laterally recessed first semiconductor layers in the exposed first portion of the fin structure while retaining the second semiconductor layers in the exposed first portion of the fin structure suspended above the substrate; and forming a gate structure to surround each suspended second semiconductor layer.

[0100] Example 2. The method according to Example 1, wherein the hydrogen-containing gas is HF gas.

[0101] Example 3. The method according to Example 1, wherein the flow rate ratio of the hydrogen-containing gas to the fluorine-containing gas is 20% to 80%.

[0102] Example 4. The method according to Example 1, wherein the temperature for performing the selective etching process is in the range of 0 degrees Celsius to 90 degrees Celsius.

[0103] Example 5. The method according to Example 1 further includes: performing a hydrogen radical treatment on the first semiconductor layer and the second semiconductor layer before performing the selective etching process.

[0104] Example 6. The method according to Example 5, wherein the hydrogen radical treatment and the selective etching process are performed in the same processing chamber.

[0105] Example 7. The method according to Example 5, wherein performing the hydrogen radical treatment includes: providing hydrogen radicals to the first semiconductor layer and the second semiconductor layer.

[0106] Example 8. The method according to Example 5, wherein the power used to provide the hydrogen radical is in the range of 500W to 5000W.

[0107] Example 9. The method according to Example 1, wherein the exposed second portion of the fin structure is removed by using an etching process with an oxygen-containing gas mixture.

[0108] Example 10. A method of manufacturing a semiconductor device, comprising: forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate; patterning the stacked structure into a fin structure extending along a first direction; forming a dummy gate structure extending across the fin structure along a second direction perpendicular to the first direction; forming gate spacers on opposite sides of the dummy gate structure; removing the dummy gate structure to form a gate trench between the gate spacers; performing a hydrogen radical treatment on the first semiconductor layers and the second semiconductor layers of the fin structure in the gate trench to remove oxygen from the first semiconductor layers and the second semiconductor layers; after performing the hydrogen radical treatment, selectively removing the first semiconductor layer from the gate trench while retaining the second semiconductor layer suspended in the gate trench; and after selectively removing the first semiconductor layer from the gate trench, forming a gate structure in the gate trench.

[0109] Example 11. The method according to Example 10, wherein the selective removal of the first semiconductor layer from the gate trench is performed in situ relative to the hydrogen radical treatment.

[0110] Example 12. The method according to Example 10 further includes: removing native oxides on the surface of the first semiconductor layer before selectively removing the first semiconductor layer from the gate trench.

[0111] Example 13. The method according to Example 12, wherein the removal of native oxides on the surface of the first semiconductor layer is performed using HF gas.

[0112] Example 14. The method according to Example 12, wherein the removal of native oxides on the surface of the first semiconductor layer is performed using NH3 gas as a catalyst.

[0113] Example 15. The method according to Example 12, wherein the selective removal of the first semiconductor layer from the gate trench relative to the native oxide on the surface on which the first semiconductor layer is removed is performed in situ.

[0114] Example 16. The method according to Example 10, wherein the selective removal of the first semiconductor layer is performed by using a gas mixture of F2 gas and HF gas.

[0115] Example 17. A semiconductor device comprising: a plurality of channel layers disposed vertically and horizontally on a substrate at intervals; a gate structure surrounding each of the plurality of channel layers; a source / drain epitaxial structure connected to the plurality of channel layers, wherein the plurality of channel layers include Si-H bonds at an interface between the source / drain epitaxial structure and the plurality of channel layers; and a plurality of internal spacers between the source / drain epitaxial structure and the gate structure.

[0116] Example 18. The semiconductor device according to Example 17, wherein the channel layer further includes Si-F bonds at the interface between the source / drain epitaxial structure and the channel layer.

[0117] Example 19. The semiconductor device according to Example 17, wherein the channel layer further includes SiF2H- at the interface between the source / drain epitaxial structure and the channel layer.

[0118] Example 20. The semiconductor device according to Example 17, wherein the thickness variation of each of the channel layers is greater than 0 and less than 0.5 nm.

Claims

1. A method for manufacturing a semiconductor device, comprising: A fin structure is formed, which includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately on a substrate; A dummy gate structure is formed across the fin structure such that the dummy gate structure covers a first portion of the fin structure while a second portion of the fin structure is exposed; Remove the exposed second portion of the fin structure; Hydrogen radical treatment is performed on the first semiconductor layer and the second semiconductor layer to remove oxygen from the first semiconductor layer and the second semiconductor layer; After performing the hydrogen radical treatment, a selective etching process is performed using a gas mixture including hydrogen-containing gas and fluorine-containing gas to laterally recess the first semiconductor layer in the first portion of the fin structure, wherein the selective etching process etches the first semiconductor layer at a faster etching rate than etching the second semiconductor layer. An internal spacer is formed on the opposite end face of the first semiconductor layer, which is laterally recessed, in the first part of the fin structure; A source / drain epitaxial structure is formed on the opposite end face of the second semiconductor layer in the first part of the fin structure; Remove the dummy gate structure to expose a first portion of the fin structure; Remove the laterally recessed first semiconductor layer from the exposed first portion of the fin structure, while retaining the second semiconductor layer in the exposed first portion of the fin structure suspended above the substrate; and A gate structure is formed to surround each suspended second semiconductor layer.

2. The method according to claim 1, wherein, The hydrogen-containing gas is HF gas.

3. The method according to claim 1, wherein, The flow rate ratio of the hydrogen-containing gas to the fluorine-containing gas is 20% to 80%.

4. The method according to claim 1, wherein, The temperature used to perform the selective etching process is in the range of 0 to 90 degrees Celsius.

5. The method according to claim 1, wherein, The hydrogen radical treatment and the selective etching process are performed in the same processing chamber.

6. The method according to claim 1, wherein, Performing the hydrogen radical treatment includes providing hydrogen radicals to the first semiconductor layer and the second semiconductor layer.

7. The method according to claim 1, wherein, The power used to provide the hydrogen radicals is in the range of 500 W to 5000 W.

8. The method according to claim 1, wherein, The second exposed portion of the fin structure was removed by using an etching process with an oxygen-containing gas mixture.

9. A method for manufacturing a semiconductor device, comprising: A stacked structure of multiple first semiconductor layers and multiple second semiconductor layers alternately stacked on a substrate is formed; The stacked structure is patterned into a fin structure extending along a first direction; A dummy gate structure is formed, which extends across the fin structure along a second direction perpendicular to the first direction; Gate spacers are formed on opposite sides of the dummy gate structure; Remove the dummy gate structure to form a gate trench between the gate spacers; Hydrogen radical treatment is performed on the first semiconductor layer and the second semiconductor layer of the fin structure in the gate trench to remove oxygen from the first semiconductor layer and the second semiconductor layer; After performing the hydrogen radical treatment, the first semiconductor layer is selectively removed from the gate trench while the second semiconductor layer is suspended in the gate trench. as well as After selectively removing the first semiconductor layer from the gate trench, a gate structure is formed in the gate trench.

10. The method according to claim 9, wherein, The selective removal of the first semiconductor layer from the gate trench is performed in situ relative to the hydrogen radical treatment.

11. The method of claim 9, further comprising: Before selectively removing the first semiconductor layer from the gate trench, the native oxide on the surface of the first semiconductor layer is removed.

12. The method according to claim 11, wherein, The removal of native oxides from the surface of the first semiconductor layer is performed using HF gas.

13. The method according to claim 11, wherein, The removal of native oxides from the surface of the first semiconductor layer is performed using NH3 gas as a catalyst.

14. The method according to claim 11, wherein, The selective removal of the first semiconductor layer from the gate trench is performed in situ relative to the native oxide on the surface on which the first semiconductor layer is removed.

15. The method according to claim 9, wherein, The selective removal of the first semiconductor layer is performed by using a gas mixture of F2 gas and HF gas.

Images