Chip package structure, electronic device, three-dimensional memory and storage system

Abstract

This application provides a chip packaging structure, electronic device, three-dimensional memory, and storage system. The chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding, thereby reducing the complexity of the chip packaging process and solving the problem of the lack of a simple chip packaging process in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to a chip packaging structure, electronic device, three-dimensional memory and storage system. Background Technology

[0002] like Figure 1 As shown, during the chip packaging process, the chip leads 10 need to be bonded to the substrate. However, there are many leads 10, and their arrangement is complex, making the bonding process quite difficult.

[0003] Therefore, a simple chip packaging process is urgently needed.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a chip packaging structure, electronic device, three-dimensional memory and storage system to solve the problem of the lack of a simple chip packaging process in the prior art.

[0006] According to one aspect of the present invention, a chip packaging structure is provided, comprising: a chip, the chip including a first body structure and a plurality of first pins located on a predetermined surface of the first body structure; and a substrate located on the predetermined surface, the substrate including a second body structure and a plurality of spaced second pins located in the second body structure, the second pins being connected to the first pins in a one-to-one correspondence.

[0007] Optionally, the second body structure has a plurality of spaced mounting spaces, at least a portion of the second pin is located in the mounting space, the second pin and the mounting space correspond one-to-one, the surface of the second body structure has a plurality of first openings, the first openings correspond one-to-one with the mounting spaces, the first openings expose a predetermined portion of the surface of the second pin, and the first pin is connected to the predetermined portion through the first opening.

[0008] Optionally, the second pin includes a first conductive portion and a second conductive portion, a first portion of the first conductive portion being located within the mounting space, a second portion of the first conductive portion protruding from the sidewall of the substrate and connected to the second conductive portion, and the second conductive portion being located on the sidewall of the substrate.

[0009] Optionally, the surface of the second body structure has a plurality of second openings, each of which corresponds to one of the mounting spaces and communicates with the first opening. The width of the second opening in a first predetermined direction is smaller than the width of the first opening in the first predetermined direction. The second opening exposes a portion of the surface of the first conductive part. The first predetermined direction is parallel to the surface of the second body structure and parallel to the sidewall of the second body structure.

[0010] Optionally, the first opening is adapted to the first pin.

[0011] Optionally, there are multiple chips and multiple substrates, and the chips and substrates are alternately arranged along a second predetermined direction, which is the thickness direction of the chips.

[0012] Optionally, the packaging structure includes at least one packaging section, each packaging section including a plurality of the chips and a substrate, the substrate being located on the predetermined surface of the plurality of the chips, and in the case of a plurality of packaging sections, the plurality of packaging sections are stacked.

[0013] Optionally, the plurality of second pins are composed of a first group of pins and a second group of pins. Each second pin in the first group of pins includes a third conductive portion and a fourth conductive portion. Each second pin in the second group of pins includes the third conductive portion, which is located within the mounting space and connected to the fourth conductive portion. The fourth conductive portion is located on the sidewall of the substrate. The second pins in the first group of pins and the second pins in the second group of pins are alternately arranged. The second body structure also includes bonding leads, which connect the second pin of the first group of pins of one chip to the second pin of the second group of pins of another chip.

[0014] Optionally, the chip is a three-dimensional memory chip.

[0015] According to another aspect of the present invention, an electronic device is also provided, including a chip packaging structure, wherein the chip packaging structure is any of the chip packaging structures described above.

[0016] According to another aspect of the present invention, a three-dimensional memory is also provided, including a chip packaging structure, wherein the chip packaging structure is any of the chip packaging structures described above.

[0017] According to another aspect of the present invention, a storage system is also provided, including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0018] In this embodiment of the invention, the chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located in the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared with the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding from the chip to the substrate, thereby reducing the process difficulty of chip packaging and solving the problem of the lack of a simple chip packaging process in the prior art. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide an alternative understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 A schematic diagram of a chip packaging structure in the prior art is shown;

[0021] Figure 2 A top view of a chip according to an embodiment of this application is shown;

[0022] Figure 3 A left view of a chip according to an embodiment of this application is shown;

[0023] Figure 4 A top view of a substrate according to an embodiment of this application is shown;

[0024] Figure 5 A left view of a substrate according to an embodiment of this application is shown;

[0025] Figure 6 A cross-sectional view of a chip packaging structure according to an embodiment of this application is shown;

[0026] Figure 7 A top view of another substrate according to an embodiment of this application is shown;

[0027] Figure 8 A left view of another substrate according to an embodiment of this application is shown;

[0028] Figure 9 A left view of another chip packaging structure according to an embodiment of this application is shown;

[0029] Figure 10A top view of yet another substrate according to an embodiment of this application is shown;

[0030] Figure 11 A left view of yet another chip package structure according to an embodiment of this application is shown.

[0031] The above figures include the following reference numerals:

[0032] 10. Lead wire; 11. First body structure; 12. First pin; 13. Second body structure; 14. Second pin; 15. First conductive part; 16. Second conductive part; 17. Chip; 18. Substrate; 19. First set of pins; 20. Second set of pins; 21. Third conductive part; 22. Fourth conductive part; 23. Bonding lead wire. Detailed Implementation

[0033] It should be noted that the following detailed descriptions are illustrative and intended to provide optional explanations for this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0034] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0035] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0036] As described in the background section, there is a lack of a simple chip packaging process in the prior art. In order to solve the above problems, a typical embodiment of this application provides a chip packaging structure, electronic device, three-dimensional memory and storage system.

[0037] According to embodiments of this application, a chip packaging structure is provided. This semiconductor structure includes a chip and a substrate, wherein... Figure 2 and Figure 3 Top and left views of a chip according to an embodiment of this application are shown respectively, as follows: Figure 2 and Figure 3As shown, the chip includes a first body structure 11 and a plurality of first pins 12 located on a predetermined surface of the first body structure; Figure 4 and Figure 5 Top and left views of the substrate of an embodiment of this application are shown respectively, as follows: Figure 4 and Figure 5 As shown, the substrate is located on the predetermined surface, and the substrate includes a second body structure 13 and a plurality of spaced second pins 14 located in the second body structure, as shown. Figure 6 As shown, the second pin 14 is connected to the first pin 12 in a one-to-one correspondence.

[0038] The aforementioned chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to existing technologies that require a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding, thereby reducing the complexity of the chip packaging process and solving the problem of the lack of a simple chip packaging process in existing technologies.

[0039] The aforementioned predetermined surface can be the upper or lower surface other than the sidewall of the chip, and the position of the aforementioned first pin can be set according to actual needs.

[0040] The materials of the first pin and the second pin can be the same or different. The materials of the first pin and the second pin can be copper, but are not limited to copper. They can also be other materials. Those skilled in the art can choose according to the actual situation.

[0041] In the embodiments of this application, such as Figure 4As shown, the second body structure 13 has multiple spaced mounting spaces. At least a portion of the second pin 14 is located within the mounting spaces, with each second pin 14 corresponding to a different mounting space. The surface of the second body structure 13 has multiple first openings, each corresponding to a different mounting space. These first openings expose a predetermined portion of the surface of the second pin 14, which is then connected to the predetermined portion through the first opening. In this embodiment, the second body structure has multiple mounting spaces for placing the second pin. The second pin is located inside the second body structure, which further reduces interference between the second pins. The surface of the second body structure also has multiple first openings, exposing a predetermined portion of the surface of the second pin. The first pin is connected to the predetermined portion, and the connected first pin is located within the second body structure. Thus, both the first pin and the second pin are located within the second body structure and are not exposed to the external environment. Therefore, it is unnecessary to fill the connection between the first pin and the second pin with insulating material, further simplifying the chip packaging process.

[0042] In another embodiment of this application, Figure 7 and Figure 8 The top and left views of another substrate according to an embodiment of this application are shown respectively, as follows: Figure 7 and Figure 8 As shown, the second pin includes a first conductive portion 15 and a second conductive portion 16. A first portion of the first conductive portion 15 is located within the mounting space, and a second portion of the first conductive portion 15 protrudes from the sidewall of the substrate and connects to the second conductive portion 16. The second conductive portion 16 is located on the sidewall of the substrate. In this embodiment, the second pin includes a first conductive portion and a second conductive portion. The first portion of the first conductive portion is located within the mounting space, and the second conductive portion is located on the sidewall of the substrate, making the second pin an "L"-shaped structure. This makes it easier for the chip package structure to connect with other electronic components in a circuit, facilitating user operation.

[0043] In another embodiment of this application, such as Figure 7 and Figure 8As shown, the surface of the second body structure has multiple second openings, each corresponding to a mounting space and communicating with a first opening. The width of each second opening in a first predetermined direction is smaller than the width of the first opening in the same direction. These second openings expose a portion of the surface of the first conductive portion 15. The first predetermined direction is parallel to the surface of the second body structure and parallel to its sidewalls. In this embodiment, the surface of the second body structure also has multiple second openings communicating with the first opening, facilitating the snap-fitting of the chip and substrate together, thereby making the connection between the chip and substrate tighter.

[0044] To further simplify the process, in another embodiment of this application, the first opening is adapted to the first pin. The adaptation of the first opening to the first pin means that the first opening and the first pin have the same size, allowing the first pin to snap into the first opening without falling out. This eliminates the need for soldering the first and second pins; subsequent heat treatment of the chip and substrate is sufficient to fix them together, further simplifying the process.

[0045] Of course, in practical applications, the size of the first opening may not be the same as the size of the first pin. In this way, only the first pin and the second pin need to be soldered to connect the chip and the substrate together.

[0046] In another embodiment of this application, such as Figure 9 As shown, there are multiple chips 17 and multiple substrates 18. The chips 17 and substrates 18 are alternately arranged along a second predetermined direction, which is the thickness direction of the chips 17. In this embodiment, when there are multiple chips and multiple substrates, a stacked packaging method can be used to alternately stack the chips and substrates, thereby reducing the chip area and further improving the electrical performance of the chip.

[0047] In order to further improve the electrical performance of the chip, in another embodiment of this application, the above-mentioned packaging structure includes at least one packaging part, and one of the above-mentioned packaging parts includes a plurality of the above-mentioned chips and a substrate. The substrate is located on the predetermined surface of the plurality of the above-mentioned chips. When there are multiple packaging parts, the multiple packaging parts are stacked.

[0048] In another embodiment of this application, such as Figure 10 and Figure 11As shown, the plurality of the aforementioned second pins are composed of a first group of pins 19 and a second group of pins 20. Each of the aforementioned second pins in the first group of pins 19 includes a third conductive part 21 and a fourth conductive part 22. Each of the aforementioned second pins in the second group of pins 20 includes the aforementioned third conductive part 21. The aforementioned third conductive part 21 is located within the aforementioned mounting space. The aforementioned third conductive part 21 is connected to the aforementioned fourth conductive part 22. The aforementioned fourth conductive part 22 is located on the side wall of the aforementioned substrate. The aforementioned second pins in the aforementioned first group of pins 19 and the aforementioned second pins in the aforementioned second group of pins 20 are alternately arranged. The aforementioned second body structure also includes a bonding wire 23, which connects a second pin in the aforementioned first group of pins 19 and a second pin in the aforementioned second group of pins 20. In this embodiment, the first group of pins includes a third conductive portion and a fourth conductive portion, the second group of pins includes a third conductive portion located within the mounting space, and the fourth conductive portion located on the sidewall of the substrate. The second body structure also includes bonding wires, which connect a second pin in the first group of pins and a second pin in the second group of pins. Because the bonding wires connect pins with the same function, the number of fourth conductive portions on the sidewall of the substrate is reduced, further reducing interference between pins and thus further improving the electrical performance of the chip.

[0049] In another embodiment of this application, the chip is a three-dimensional memory chip.

[0050] Of course, in practical applications, the above-mentioned chip is not limited to a three-dimensional memory chip, but can also be other chips, and other chips can also be packaged using the packaging structure of this application.

[0051] According to an embodiment of this application, an electronic device is also provided, including a chip packaging structure, wherein the chip packaging structure is any of the above-described chip packaging structures.

[0052] The aforementioned electronic device includes a chip packaging structure, which is any of the aforementioned chip packaging structures. The chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding from the chip to the substrate, thereby reducing the complexity of the chip packaging process and solving the problem of the lack of a simple chip packaging process in the prior art.

[0053] According to an embodiment of this application, a three-dimensional memory is also provided, including a chip packaging structure, wherein the chip packaging structure is any of the above-described chip packaging structures.

[0054] The aforementioned three-dimensional memory includes a chip packaging structure, which can be any of the aforementioned chip packaging structures. The chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding from the chip to the substrate, thereby reducing the complexity of the chip packaging process and solving the problem of the lack of a simple chip packaging process in the prior art.

[0055] According to an embodiment of this application, a storage system is also provided, including a storage controller and the aforementioned three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0056] The aforementioned storage system includes a storage controller and a three-dimensional memory configured to store data. The storage controller is coupled to the three-dimensional memory and configured to control it. The three-dimensional memory also includes a chip packaging structure, which can be any of the aforementioned chip packaging structures. This chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within it. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding, thereby reducing the complexity of the chip packaging process and solving the problem of the lack of a simple chip packaging process in the prior art.

[0057] Of course, in practical applications, the electronic devices mentioned above are not limited to the types mentioned above, and can also be other electronic devices.

[0058] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0059] 1) The chip packaging structure of this application includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located in the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared with the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution does not require wire bonding from the chip to the substrate, thereby reducing the process difficulty of chip packaging and solving the problem of the lack of a simple chip packaging process in the prior art.

[0060] 2) The electronic device of this application includes a chip packaging structure, wherein the chip packaging structure is any of the aforementioned chip packaging structures. The chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding from the chip to the substrate, thereby reducing the process difficulty of chip packaging and solving the problem of the lack of a simple chip packaging process in the prior art.

[0061] 3) The three-dimensional memory of this application includes a chip packaging structure, wherein the chip packaging structure is any of the aforementioned chip packaging structures. The chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located within the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding from the chip to the substrate, thereby reducing the technological difficulty of chip packaging and solving the problem of the lack of a simple chip packaging process in the prior art.

[0062] 4) The storage system of this application includes a storage controller and the aforementioned three-dimensional memory. The three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory. The aforementioned three-dimensional memory includes a chip packaging structure, which can be any of the aforementioned chip packaging structures. The chip packaging structure includes a chip and a substrate. The chip includes a first body structure and a plurality of first pins located on a predetermined surface of the first body structure. The substrate is located on the predetermined surface and includes a second body structure and a plurality of spaced-apart second pins located in the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. In this chip packaging structure, the substrate is located on the predetermined surface of the chip, and the second pins of the substrate are connected to the first pins of the chip in a one-to-one correspondence. The first pins do not need to be wire-bonded to the second pins. Compared to the prior art, which requires a large number of wires to bond from the chip to the substrate, this solution eliminates the need for wire bonding from the chip to the substrate, thereby reducing the difficulty of the chip packaging process and solving the problem of the lack of a simple chip packaging process in the prior art.

[0063] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip packaging structure, characterized in that, include: A chip, the chip including a first body structure and a plurality of first pins located on a predetermined surface of the first body structure; A substrate is located on the predetermined surface. The substrate includes a second body structure and a plurality of spaced second pins located in the second body structure. The second pins are connected to the first pins in a one-to-one correspondence. The second body structure has a plurality of spaced mounting spaces. The plurality of second pins are composed of a first group of pins and a second group of pins. Each second pin in the first group of pins includes a third conductive part and a fourth conductive part that are interconnected. Each second pin in the second group of pins includes the third conductive part, which is located within the mounting space. The fourth conductive part is located on the side wall of the substrate. The second pins in the first group of pins and the second pins in the second group of pins are alternately arranged. The second body structure also includes a bonding wire, which connects a second pin in the first group of pins and a second pin in the second group of pins.

2. The chip package structure of claim 1, wherein, At least a portion of the second pin is located in the mounting space, and the second pin and the mounting space correspond one-to-one. The surface of the second body structure has a plurality of first openings, and the first openings correspond one-to-one with the mounting spaces. The first openings expose a predetermined portion of the surface of the second pin, and the first pin is connected to the predetermined portion through the first opening.

3. The chip package structure of claim 2, wherein, The first opening is adapted to the first pin.

4. The chip package structure of claim 2, wherein, There are multiple chips and multiple substrates. The chips and substrates are alternately arranged along a second predetermined direction, which is the thickness direction of the chips.

5. The chip package structure of claim 2, wherein, The packaging structure includes at least one packaging section, each packaging section including a plurality of chips and a substrate, the substrate being located on a predetermined surface of the plurality of chips, and in the case of a plurality of packaging sections, the plurality of packaging sections are stacked.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that, The chip is a three-dimensional memory chip.

7. An electronic device comprising a chip package structure, characterized by The chip packaging structure is the chip packaging structure according to any one of claims 1 to 5.

8. A three-dimensional memory, comprising a chip package structure, characterized in that, The chip packaging structure is the chip packaging structure according to any one of claims 1 to 5.

9. A storage system, characterized by The device includes a storage controller and the three-dimensional memory of claim 8, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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