Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The preparation method comprises: forming a stack structure on a substrate; forming a plurality of top selection gate cut group extending towards the substrate direction and arranged along a first direction in the stack structure, at least one top selection gate cut group comprising a plurality of top selection gate cuts arranged along a second direction, and a spacing region between adjacent top selection gate cuts, the first direction and the second direction being perpendicular to the stacking direction of the stack structure and intersecting each other; forming an initial dummy channel hole extending towards the substrate direction in the spacing region; and forming a dummy channel hole extending towards the substrate direction via the initial dummy channel hole. The application provides a three-dimensional memory and a preparation method thereof, which is beneficial to optimizing the pattern topography of the dummy channel hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and methods for its fabrication. Background Technology

[0002] With the increasing demand for high storage density and large storage capacity, three-dimensional memory (e.g., 3D NAND memory) has emerged. In some examples, three-dimensional memory includes a core region and a stepped region. The core region is used to form stacked memory cells, and the stepped region is used to form conductive channels for the word lines leading out of the memory cells.

[0003] In some fabrication processes, top selected gate notches and dummy channel vias can be formed in stepped regions. Due to the spatial relationship between the top selected gate notches and dummy channel vias and the sequence of fabrication processes, the dummy channel vias may be under-etched, thus affecting their pattern morphology. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory. The method includes: forming a stacked structure on a substrate; forming a plurality of top select gate cutout groups extending toward the substrate and disposed along a first direction in the stacked structure, at least one top select gate cutout group including a plurality of top select gate cutouts disposed along a second direction, with a spacing region between adjacent top select gate cutouts, the first direction and the second direction being perpendicular to the stacking direction of the stacked structure and intersecting each other; forming an initial dummy channel via extending toward the substrate in the spacing region; and forming a dummy channel via extending toward the substrate through the initial dummy channel via.

[0005] In some implementations, the initial dummy channel hole and the top selection gate cutout have a predetermined spacing distance.

[0006] In some implementations, the dummy channel hole overlaps with the top selection grid cutout.

[0007] In some implementations, in the first direction, the dummy channel aperture overlaps with the top select gate cutout by 150 nm.

[0008] In some embodiments, the step of forming an initial dummy channel via extending toward the substrate includes: forming a hard mask layer that fills the top selected gate cutout and covers the stacked structure; forming an initial dummy channel via pattern in the hard mask layer; and forming the initial dummy channel via pattern.

[0009] In some embodiments, the fabrication method further includes: removing the hard mask layer; and forming a dielectric material layer that fills the dummy channel holes and the top selected gate cutout and covers the stacked structure.

[0010] This application also provides a method for fabricating a three-dimensional memory. The method includes: forming a stacked structure on a substrate; forming a plurality of top select gate cutouts extending toward the substrate and disposed along a first direction in the stacked structure, at least one top select gate cutout including a plurality of first cutouts disposed along a second direction and a plurality of second cutouts located between adjacent first cutouts, the first direction and the second direction being perpendicular to the stacking direction of the stacked structure and intersecting each other; and forming dummy channel holes extending toward the substrate in regions corresponding to the second cutouts.

[0011] In some embodiments, the step of forming a dummy channel via extending toward the substrate includes: forming an initial dummy channel via extending toward the substrate in a region corresponding to the second cut; and forming a dummy channel via extending toward the substrate through the initial dummy channel via.

[0012] In some embodiments, the step of forming an initial dummy channel via extending toward the substrate includes: forming a hard mask layer that fills the top selected gate cutout and covers the stacked structure; forming an initial dummy channel via pattern in the hard mask layer; and forming the initial dummy channel via pattern.

[0013] In some embodiments, the fabrication method further includes: removing the hard mask layer; and forming a dielectric material layer that fills the dummy channel holes and the top selected gate cutout and covers the stacked structure.

[0014] This application also provides a three-dimensional memory. The three-dimensional memory includes: a semiconductor layer; a stacked structure; a plurality of top select gate cutout structures that pass through the stacked structure and extend toward the semiconductor layer and are disposed along a first direction, each top select gate cutout structure including: a plurality of first cutout structures disposed along a second direction and a plurality of second cutout structures located between adjacent first cutout structures, the first direction and the second direction being perpendicular to the stacking direction of the stacked structure and intersecting each other; and a dummy channel structure formed in the region corresponding to the second cutout structure and extending toward the semiconductor layer.

[0015] In some implementations, the cross-sectional area of ​​the second cut structure is larger than the cross-sectional area of ​​the dummy channel structure in a plane perpendicular to the stacking direction.

[0016] According to the three-dimensional memory and its fabrication method provided in this application, by first forming an initial dummy channel hole extending towards the substrate in the spacing region between adjacent top selected gate cuts, and then forming the dummy channel hole, it is beneficial to reduce the risk of over-etching of the dummy channel hole in the second direction, thereby facilitating the optimization of the pattern morphology of the dummy channel hole. Alternatively, by forming the dummy channel hole in the region corresponding to the second cut, it is beneficial to optimize the pattern morphology of the dummy channel hole. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0018] Figure 1 This is a flowchart of a method for preparing a three-dimensional memory according to an embodiment of this application;

[0019] Figures 2A to 2D This is a top view schematic diagram of the process of fabricating a three-dimensional memory according to an embodiment of this application;

[0020] Figures 3A to 3F This is a cross-sectional schematic diagram of the process of fabricating a three-dimensional memory according to an embodiment of this application;

[0021] Figure 4A and Figure 4B These are a top view schematic diagram and a top electron microscope image of a three-dimensional memory fabrication method according to another embodiment of this application, after the top selection gate notch and dummy channel hole are formed;

[0022] Figures 5A to 5C This is a cross-sectional schematic diagram of the process of forming a gate gap and "gate replacement" according to an embodiment of this application;

[0023] Figure 6 This is a flowchart of a method for fabricating a three-dimensional memory according to another embodiment of this application; and

[0024] Figures 7A to 7C This is a top view schematic diagram of the fabrication process of a three-dimensional memory according to another embodiment of this application. Detailed Implementation

[0025] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0026] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0027] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0028] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 1 As shown, the method 1000 for fabricating a three-dimensional memory includes the following steps:

[0031] S110, forming a stacked structure on the substrate;

[0032] S120, forming a plurality of top select gate cutout groups extending toward the substrate direction and disposed along a first direction, at least one top select gate cutout group including a plurality of top select gate cutouts disposed along a second direction, with a spacing region between adjacent top select gate cutouts, the first direction and the second direction being perpendicular to the stacking direction of the stacked structure and intersecting each other.

[0033] S130, an initial dummy channel hole extending toward the substrate is formed in the spacer region;

[0034] S140, through the initial dummy channel via, forms a dummy channel via extending toward the substrate.

[0035] It should be understood that the steps shown in preparation method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described]. Figure 1 The execution is performed in the order shown. Figures 2A to 2D This is a top view schematic diagram of the process of fabricating a three-dimensional memory according to the embodiment of this application 1000. Figures 3A to 3F This is a cross-sectional schematic diagram of the fabrication process of the three-dimensional memory fabrication method 1000 according to an embodiment of this application. The following is in conjunction with... Figures 2A to 3FThe steps S110 to S140 described above are further described.

[0036] Preparation method 1000 begins with step S110, such as Figure 2A and Figure 3A As shown, the semiconductor structure 100a can be an intermediate structure after step S110 in the fabrication method 1000 of the three-dimensional memory. Figure 3A Can be Figure 2A A schematic cross-sectional view of a portion of the semiconductor structure 100a along section line I-I' is shown.

[0037] In some embodiments of step S110, the substrate 111 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof. Exemplarily, the substrate 111 may be used to provide mechanical support for structures formed thereon, such as stacked structures 121a and channel structures 131. Exemplarily, the substrate 111 may be removed in subsequent processes, such that the formed three-dimensional memory does not include the substrate 111. Exemplarily, the general space occupied by the substrate 111 may be replaced by a newly formed semiconductor layer, the material of which may be, for example, polycrystalline silicon.

[0038] In some embodiments, the stacked structure 121a may be formed on the substrate 111. The stacked structure 121a may include a plurality of dielectric layers (e.g., 122a and 122b) and a plurality of dielectric sacrificial layers (e.g., 123a and 123b) alternately stacked in a direction perpendicular to or substantially perpendicular to the substrate 111. The number of stacked layers of dielectric layers and dielectric sacrificial layers in the stacked structure 121a may be, for example, 8 layers, 32 layers, 64 layers, 128 layers, etc. The more stacked layers the stacked structure 121a has, the higher the integration density and the more memory cells it forms. The number of stacked layers and the stacking height of the stacked structure 121a can be designed according to actual memory requirements, and this application does not specifically limit this.

[0039] In some implementations, multiple dielectric sacrificial layers (e.g., 123a and 123b) may be replaced with multiple conductive layers (e.g., 128, reference 123b) in subsequent processes. Figure 5CThe multiple dielectric sacrificial layers (e.g., 122a and 122b) serve as control gates for memory cells and word lines for multiple memory cells. Exemplarily, during the process of removing multiple dielectric sacrificial layers (e.g., 123a and 123b), the multiple dielectric layers (e.g., 122a and 122b) and the multiple dielectric sacrificial layers (e.g., 123a and 123b) may have different etch selectivity ratios. Optionally, the material of the multiple dielectric layers (e.g., 122a and 122b) may include, for example, silicon oxide, and the material of the multiple dielectric sacrificial layers (e.g., 123a and 123b) may include, for example, silicon nitride.

[0040] It should be understood that although this application employs a method in which multiple dielectric sacrificial layers are subsequently replaced by conductive materials to form a conductive layer, the method of forming a conductive layer in this application is not limited to this. It can also be achieved by, for example, directly and alternately stacking dielectric layers and conductive layers.

[0041] In some embodiments, multiple channel structures (e.g., 131) may be arranged in a two-dimensional array within a core region A on a plane parallel to the substrate 111. For example, they may be arranged at predetermined intervals along a first direction D1 and a second direction D2, respectively. Exemplarily, each channel structure may have the same internal structure. For example, the channel structure 131 extends through a stacked structure 121a, including, for example, multiple dielectric layers (e.g., 122a and 122b) and multiple dielectric sacrificial layers (e.g., 123a and 123b) that are alternately stacked, and extends into the substrate 111 in a direction toward the substrate 111, for example, a direction perpendicular to or substantially perpendicular to the substrate 111. Exemplarily, the channel structure 131 may have a generally cylindrical, frustum-shaped, or prism-shaped outline, and may include outer wall structures of a functional layer 132 and a channel layer 133 arranged sequentially from the outside in. Optionally, the functional layer 132 may include a charge blocking layer, a charge trapping layer, and a tunneling layer (not shown) arranged sequentially from the outside in. The materials of the charge blocking layer, charge trapping layer, and tunneling layer may sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide, thereby forming a functional layer 132 with an ONO structure. The material of the channel layer 133 may include semiconductor materials such as silicon (e.g., amorphous silicon, polycrystalline silicon, monocrystalline silicon).

[0042] It is understandable that the functional layer 132 and the channel layer 133 in the channel structure 131 are related to the subsequently formed conductive layer 128 in the stacked structure 121a (see reference). Figure 5C The portion corresponding to the spatial locations of the dielectric sacrificial layers 123a and 123b, along with a portion of the conductive layer, together form the memory cell 135. Exemplarily, multiple memory cells (e.g., 135) are arranged in series in a direction perpendicular or substantially perpendicular to the substrate 111 to form a memory string. Optionally, the memory string may also include selection transistors located at its two ends.

[0043] In some embodiments, the channel structure 131 includes an epitaxial layer 134 located near the substrate 111. Exemplarily, the channel layer 133 extends through the functional layer 132 and contacts the epitaxial layer 134, thereby electrically connecting the channel layer 133 of a plurality of memory cells (e.g., 135) arranged in the extension direction of the channel structure 131 to the substrate 111 via the epitaxial layer 134. Exemplarily, the substrate 111 may serve as an electrically coupled region for a plurality of memory strings.

[0044] In some embodiments, the stepped structure may be formed at the edge or middle of the stacked structure 121a, such as the side or middle of the memory plane. Exemplarily, in a direction perpendicular to the substrate 111, a pair of dielectric layers 122a and dielectric sacrificial layers 123a away from the substrate 111 partially cover an adjacent pair of dielectric layers 122b and dielectric sacrificial layers 123b closer to the substrate 111, such that the dielectric sacrificial layer 123b closer to the substrate 111 has a region exposed to the adjacent pair of dielectric layers 122a and dielectric sacrificial layers 123a away from the substrate 111. The exposed region of the dielectric sacrificial layer 123b (i.e., the exposed region of the conductive layer 128) can serve as an electrical connection region for word line contacts formed in subsequent processes. Optionally, the space of the stepped structure away from the substrate 111 may be filled with at least one insulating material 112, such as silicon oxide, silicon nitride, or silicon oxynitride. It should be noted that the area corresponding to the stepped structure can be referred to as stepped region B. Within stepped region B, multiple top selection gate cutouts (e.g., 141-1 and 141-2) and multiple dummy channel holes (e.g., 151b) will also be formed, as described below (see reference). Figure 2D ).

[0045] In some implementations, such as Figure 3B As shown, prior to step S120, a first hard mask layer 124 can be formed over the stacked structure 121a using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, a first photoresist layer 125 can be formed over the first hard mask layer 124 using, for example, a spin-coating process. The first hard mask layer 124 can serve, for example, as an etching mask layer for the plurality of top select gate cutouts (e.g., 141-1 to 141-3) to be formed in step S120 described below, to obtain a plurality of top select gate cutouts (e.g., 141-1 to 141-3) with high-resolution pattern morphology. Exemplarily, the first hard mask layer 124 and the first photoresist layer 125 can be retained and removed after the formation of the plurality of top select gate cutouts (e.g., 141-1 to 141-3) (see reference). Figure 2B ).

[0046] Preparation method 1000 proceeds to step S120, such as Figure 2Band Figure 3C As shown, the semiconductor structure 100b can be an intermediate structure after step S120 in the fabrication method 1000 of the three-dimensional memory. Figure 3C Can be Figure 2B A schematic cross-sectional view of a portion of the semiconductor structure 100b along section line Ⅱ-Ⅱ' is shown.

[0047] In some embodiments, a first photoresist layer 125 and a first hard mask layer 124 (see reference) can be used. Figure 3B The system employs photolithography and etching processes (e.g., dry etching and wet etching) to create a plurality of top select gate cutouts (e.g., 140-1, 140-2, and 140-3) extending in a direction toward substrate 111 (e.g., perpendicular to substrate 111) and disposed along a first direction D1. For example, top select gate group 140-1 includes a plurality of top select gate cutouts (e.g., 141-1 and 141-2) disposed along a second direction D2. It should be noted that the first direction D1 and the second direction D2 can be two intersecting directions with any angle.

[0048] In some embodiments, within the stepped region B, adjacent top selection gate cutouts 141-1 and 141-2 may have a predetermined spacing distance, and the area between adjacent top selection gate cutouts 141-1 and 141-2 may be referred to as the spacing region 142. Exemplarily, each top selection gate cutout (e.g., 141-1 or 141-2) may extend along a second direction D2. Exemplarily, in the second direction D2, the size of the spacing region 142 may be smaller than the size of the top selection gate cutouts 141-1 or 141-2. Exemplarily, in the first direction D1, the plurality of top selection gate cutouts (e.g., 141-1 and 141-2) in the top selection gate cutout group 140-2 are of the same size.

[0049] In some embodiments, within the core region A, the top selection gate cutouts 141-3 in the top selection gate cutout group 140-2 may have a continuous extension length. As will be described below, a dielectric material layer 152 (see reference) is filled within the plurality of top selection gate cutouts (e.g., 141-1 to 141-3). Figure 3FMultiple top-select gate cutout structures are formed, for example, to separate the dielectric sacrificial layer 123a located on both sides of a portion of the stacked structure 121a, so that the dielectric sacrificial layer 123a, which is replaced by a conductive layer in a subsequent process, is electrically isolated, thereby enabling the electrically isolated conductive layer to independently control the corresponding top-select transistor. Optionally, the top-select gate cutouts 141-3 may overlap with some channel structures (e.g., 132). In one example, the arrangement of multiple channel structures within the core region A can be designed such that the top-select gate cutouts (e.g., 141-3) within the core region A extend between adjacent channel structures (not shown), which is not specifically limited in this application.

[0050] In some implementations, additional top selection gate cutout groups (e.g., 140-3) may be formed, for example, through mask design during the process of forming multiple top selection gate cutout groups (e.g., 140-1 and 140-2). Exemplarily, within the core region A and the stepped region B, multiple top selection gate cutouts (e.g., 143-1 and 143-2) in top selection gate cutout group 140-3 have a spacing distance between them to form a spacing region 144. Exemplarily, in the second direction D2, the size of the spacing region 144 between top selection gate cutouts 143-1 and 143-2 in top selection gate cutout group 140-3 is larger than the size of either top selection gate cutout 143-1 or 143-2. ​​Exemplarily, in the first direction D1, the sizes of the individual top selection gate cutouts located in different top selection gate cutout groups are different; for example, in the first direction D1, the size of top selection gate cutout 143-2 is larger than the size of top selection gate cutout 141-2.

[0051] In some implementations, such as Figure 3D As shown, prior to step S130, a second hard mask layer 126 may be formed over the stacked structure 121a using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, a second photoresist layer 127 may be formed over the second hard mask layer 126 using, for example, a spin-coating process. The second hard mask layer 126 may serve as an etching mask layer for, for example, a plurality of initial dummy vias (e.g., 151a) to be formed in step S130 described below, to obtain a plurality of dummy vias (e.g., 151b) with a high-resolution pattern morphology. Exemplarily, the second hard mask layer 126 and the second photoresist layer 127 may be retained and removed after the formation of the plurality of dummy vias (e.g., 151b). Exemplarily, during the process of forming the second hard mask layer 126 over the stacked structure 121a, the material of the second hard mask layer 126 will non-densely fill within a plurality of top select gate cutouts (e.g., 141-1).

[0052] Preparation method 1000 proceeds to step S130, such as Figure 2C As shown, the semiconductor structure 100c can be an intermediate structure after step S130 in the fabrication method 1000 of the three-dimensional memory.

[0053] In some embodiments, a second photoresist layer 127 and a second hard mask layer 126 (see reference) may be used. Figure 3D The initial dummy channel hole 151a is formed in the spacer region 124 within the stepped region B, for example, using photolithography and etching processes (e.g., dry etching and wet etching processes), extending along the direction of the substrate 111. For example, the pattern of the initial dummy channel hole 151a is first transferred to the hard mask layer 126 using photolithography, and then the initial dummy channel hole 151a extending along the direction of the substrate 111 (e.g., perpendicular to the direction of the substrate 111) is formed through the initial dummy channel hole pattern in the hard mask layer 126 using, for example, dry or wet etching processes. In this step, the initial dummy channel hole 151a has a spacing distance (in the second direction D2) between it and the two top select gate cutouts 141-1 and 141-2 adjacent to the spacer region 124 where it is located. In other words, the initial dummy channel hole 151a does not overlap with the adjacent top select gate cutouts 141-1 and 141-2. For example, the initial dummy channel structure 151a extends toward the substrate 111 with a length less than the distance from the opening of the dummy channel hole 151a to the substrate 111.

[0054] Preparation method 1000 proceeds to step S140, such as Figure 2D and 3E As shown, the semiconductor structure 100d can be an intermediate structure after step S140 in the fabrication method 1000 of the three-dimensional memory. Figure 3E Can be Figure 2D The diagram shows a cross-sectional view of a portion of the semiconductor structure 100d along section line Ⅱ-Ⅱ'.

[0055] In some implementations, the hard mask layer 126 may be retained within the stacked structure 121a and the top select gate notch 141-1 (see reference). Figure 3D The hard mask layer 126 may have an initial pattern of dummy channel holes 151a. Exemplarily, the dummy channel holes 151a may be further etched using, for example, dry or wet etching processes until dummy channel holes 151b with predetermined design dimensions are formed. After the above processing, for example, for some dummy channel holes near the core region A, they can be separated from the conductive layer 128 (see reference) in a stepped structure with a higher height. Figure 5C ) runs through the entire stacked structure 121a, and for some dummy channel holes in the stepped structure far from the core region A, it can be seen from the conductive layer 128 (reference) in the stepped structure with a lower height. Figure 5CThe hard mask layer 126 may penetrate a portion of the stacked structure 121a, for example, sequentially penetrating the insulating material 112 and the stacked structure 121a. Alternatively, the hard mask layer 126 may be removed after the dummy channel via 151b is formed.

[0056] In some embodiments, during the process from forming the initial dummy channel via 151a to forming the dummy channel via 151b, the cross-sectional dimension of the initial dummy channel via 151a in a plane parallel to, for example, the substrate 111 gradually increases, and the extension length of the initial dummy channel via 151a in the direction toward the substrate 111 also gradually increases. Optionally, in the direction parallel to the substrate 111, the dummy channel via 151b overlaps with its adjacent top select gate cutouts 141-1 and 141-2, for example, in the second direction D2, the overlap dimension is 150 nm.

[0057] Figure 4A and Figure 4B These are a top view and a top electron microscope image showing the formation of the top selection gate notch 1 and the dummy channel hole 2 in a method for fabricating a three-dimensional memory according to another embodiment of this application. Figure 4A As shown, compared to the top selection gate cutouts 141-1 and 141-2 described in this application above, the top selection gate cutout 1 extends along the second direction D2 within the stepped region B'. In other words, within the stepped region B', the top selection gate cutout 1 has a continuous elongated shape extending along the second direction D2. During the process of forming the dummy channel hole 2 after forming the top selection gate cutout 1, for example, in a process where an initial dummy channel hole (not shown) is first formed and its cross-sectional size and extension length are gradually increased, the etching material (e.g., etching gas) may over-etch the initial dummy channel hole along the second direction D2 via the top selection gate cutout 1, thereby causing the finally formed dummy channel hole 2 to have a sharp corner along the second direction D2 (see reference). Figure 4B This will affect the pattern morphology of the dummy channel hole 2. In addition, it will reduce the spacing between adjacent dummy channel holes in the second direction D2.

[0058] In the embodiments of this application, reference is made again. Figure 2CSince the initial dummy channel hole 151a has a spacing distance from the adjacent top selection gate cutouts 141-1 and 141-2, the etching material (e.g., etching gas) will not cause the initial dummy channel hole 151a to be over-etched along the second direction D2 via the top selection gate cutouts 141-1 and 141-2. Furthermore, during the process of forming the initial dummy channel hole 151a to forming the dummy channel hole 151b, although the final dummy channel hole 151b overlaps with the adjacent top selection gate cutouts 141-1 and 141-2, as described above, the stage where the overlap begins is a later stage in the process of forming the initial dummy channel hole 151a to forming the dummy channel hole 151b. The etching material (e.g., etching gas) makes the probability of the initial dummy channel hole 151a being over-etched along the second direction D2 relatively small, which is beneficial to optimizing the pattern morphology of the final dummy channel hole 151b and to maintaining a predetermined spacing distance between adjacent dummy channel holes 151b in the second direction D2.

[0059] After the preparation method 1000 proceeds to step S150, as follows: Figure 3F As shown, the method further includes the following steps. In some embodiments, a dielectric material layer 152 may be formed within a plurality of top-selective gate notches (e.g., 141-1 to 141-3 and 143-1 to 143-2) and a plurality of dummy channel vias (e.g., 151b) using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the material of the dielectric material layer 152 may include, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0060] In some embodiments, during the process of forming the dielectric material layer 152 within a plurality of top-selective gate cutouts (e.g., 141-1 to 141-3 and 143-1 to 143-2) and a plurality of dummy channel vias (e.g., 151b), the dielectric material layer 152 may cover the top of the stacked structure 121a. Alternatively, a process such as chemical mechanical polishing (CMP) may be used to planarize the surface of the portion of the dielectric material layer 152 located above the stacked structure 121a.

[0061] Figures 5A to 5C This is a cross-sectional schematic diagram of the gate gap formation and "gate replacement" process according to an embodiment of this application. After forming the dielectric filling layer 152, as... Figure 5A As shown, a portion of the dielectric material layer 152 located above the stacked structure 121a can be removed using photolithography and etching processes (e.g., dry etching and wet etching) to expose the etch mark structure 161. Exemplarily, the etch mark structure 161 can serve, for example, as a subsequently formed gate slot 171 (see reference). Figure 5BThe photolithographic alignment structure is used to ensure the accuracy of the positional relationship between the gate gap 171 and other existing structures.

[0062] In some exemplary embodiments, after forming the top select gate notch 141-1, a dielectric material (e.g., a first dielectric material) is filled into the top select gate notch 141-1, and then a dummy channel via 151b is formed through the first dielectric material and at least part of the stack structure 121a. Further, a dielectric material (e.g., a second dielectric material) is filled into the dummy channel via 151b. Without adding, for example, a CMP process, the first and second dielectric materials are formed above the stack structure 121a in two separate filling processes, resulting in a thicker dielectric material (i.e., the first and second dielectric materials) above the stack structure 121a.

[0063] In some embodiments, a third photoresist layer (not shown) may be formed over the stacked structure 121a using a spin coating process, for example, and this third photoresist layer may fill the gaps in the exposed photolithographic marker structure 161. In the exemplary embodiments described above, if the dielectric material (i.e., the first dielectric material and the second dielectric material) over the stacked structure 121a is thick, the photoresist material may collapse towards the gap, resulting in the photolithographic marker structure 161 breaking. According to embodiments of this application, by forming multiple top selection gate notches (e.g., 141-1 to 141-3) and multiple dummy channel vias (e.g., 151b), and then using a single filling process to make the dielectric material over the stacked structure 121a thinner, the risk of the photolithographic marker structure 161 breaking is reduced.

[0064] In some implementations, such as Figure 5B As shown, a gate gap 171, for example, sequentially penetrating the dielectric material 152 and the stacked structure 121a to the substrate 111, can be formed using photolithography and etching processes (e.g., dry etching and wet etching). The gate gap 171 can serve, for example, as a channel for etching materials (e.g., etchants) during a "gate replacement" process. For example, multiple dielectric sacrificial layers (e.g., 123c) in the stacked structure 121a can be removed via the gate gap 171 to form a sacrificial gap (not shown). Further, a conductive material can be filled within the sacrificial gap using a thin-film deposition process such as CVD, PCV, ALD, or any combination thereof to form multiple conductive layers (e.g., 128), such as... Figure 5C As shown.

[0065] Figure 6 This is a flowchart of a method 2000 for fabricating a three-dimensional memory according to another embodiment of this application. For example... Figure 6As shown, the method for fabricating a three-dimensional memory 2000 includes the following steps:

[0066] S210, forming a stacked structure on the substrate;

[0067] S220, forming a plurality of top selection gate cutouts extending toward the substrate and disposed along a first direction, at least one top selection gate cutout including a plurality of first cutouts disposed along a second direction and a plurality of second cutouts located between adjacent first cutouts, the first direction and the second direction being perpendicular to the stacking direction of the stacked structure and intersecting each other;

[0068] S230, within the area of ​​the second cut, a dummy channel hole is formed that passes through at least part of the stacked structure.

[0069] It should be understood that the steps shown in preparation method 2000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described]. Figure 6 The execution is performed in the order shown. Figures 7A to 7C This is a top view schematic diagram of the fabrication process of a three-dimensional memory according to another embodiment of this application, namely, the fabrication method. Details identical to those described in the fabrication method will not be repeated here.

[0070] The following is combined with Figures 7A to 7C The steps S210 to S230 described above are further described.

[0071] Preparation method 2000 proceeds to step S220, such as Figure 7A As shown, the semiconductor structure 200a can be an intermediate structure after step S220 in the three-dimensional memory fabrication method 2000. Exemplarily, it can be formed by employing, for example, photolithography and etching processes (e.g., dry etching and wet etching processes) extending toward the substrate direction (e.g., perpendicular to...). Figure 7A (shown in the direction) and multiple top selection grid cutouts (e.g., 240-1, 240-2 and 240-3) set along the first direction D1.

[0072] In some embodiments, within the stepped region B, the top selection gate cutout 240 includes a plurality of first cutouts (e.g., 241-1 and 241-2) arranged along the second direction D2 and a plurality of second cutouts (e.g., 242) located between adjacent first cutouts 241-1 and 241-2. It should be noted that the first direction D1 and the second direction D2 can be two intersecting directions with any angle. Exemplarily, the plurality of first cutouts (e.g., 241-1 and 241-2) are of the same size in the first direction D1. Exemplarily, the area corresponding to the second cutout 242 can be used to form an initial dummy channel hole 251a (see reference). Figure 7B ) and dummy channel hole 252b (reference) Figure 7C The cross-sectional shape of the second cut 242 in the plane parallel to the substrate is not specifically limited herein, and may be, for example, circular, rectangular, or other irregular shapes. For example, the cross-sectional shape of the second cut 242 in the plane parallel to the substrate may be square, and the dimension of the second cut 242 in the first direction D1 is larger than the dimension of the plurality of first cuts (e.g., 241-1 and 241-2) in the first direction D1.

[0073] Preparation method 2000 proceeds to step S230, such as Figure 7B As shown, the semiconductor structure 200b can be an intermediate structure in step S230 of the three-dimensional memory fabrication method 2000. Exemplarily, photolithography and etching processes (e.g., dry etching and wet etching processes) can be used to form an initial dummy channel hole 251a extending along the substrate direction in the region corresponding to the second notch 242. The initial dummy channel hole 251a has a spacing distance from the boundary of the second notch 242. In other words, the boundary of the second notch 242 surrounds the initial dummy channel hole 251a, and the initial dummy channel hole 251a overlaps with the second notch 242.

[0074] In some implementations, such as Figure 7C As shown, the semiconductor structure 200c can be an intermediate structure after step S230 in the three-dimensional memory fabrication method 2000. Exemplarily, this is achieved by forming an initial dummy channel hole 251a extending toward the substrate (see reference). Figure 7B After that, the dummy channel hole 251a can be further etched using, for example, dry or wet etching processes, until a dummy channel hole 251b with a predetermined design size is formed.

[0075] In some embodiments, the dummy channel hole 251b remains within the region corresponding to the second notch 242 in the direction parallel to the substrate; in other words, the boundary of the second notch 242 surrounds the dummy channel hole 251b. Therefore, the dummy channel hole 251b does not overlap with its adjacent first notches 241-1 and 241-2.

[0076] In the embodiments of this application, reference is made again. Figure 7B Since the initial dummy channel hole 251a is located in the region corresponding to the second cut 142, the etching material (e.g., etching gas) will cause the initial dummy channel hole 251a to be over-etched (uniformly) away from its boundary through the second cut 242. This helps to reduce the risk of over-etching in the second direction D2 and helps to optimize the pattern morphology of the final dummy channel hole.

[0077] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, including: A stacked structure is formed on the substrate; In the stacked structure, a plurality of top select gate cutout groups are formed extending toward the substrate and disposed along a first direction. At least one of the top select gate cutout groups includes a plurality of top select gate cutouts disposed along a second direction. There is a gap region between adjacent top select gate cutouts. The first direction and the second direction are perpendicular to the stacking direction of the stacked structure and intersect each other. Within the spaced region, an initial dummy channel hole extending toward the substrate is formed, wherein the initial dummy channel hole has a predetermined spacing distance from the top select gate cutout; as well as A virtual channel extending toward the substrate is formed by increasing the cross-sectional dimension of the initial virtual channel in a plane parallel to the substrate and increasing the extension dimension in the direction toward the substrate via the initial virtual channel.

2. The preparation method according to claim 1, wherein, The dummy channel hole overlaps with the top selection grid cutout.

3. The preparation method according to claim 2, wherein, In the first direction, the dummy channel aperture overlaps with the top selected gate cutout by 150 nm.

4. The preparation method according to claim 1, wherein, The step of forming an initial dummy channel via extending toward the substrate includes: A hard mask layer is formed to fill the top selected gate cutout and cover the stacked structure; An initial dummy channel pattern is formed in the hard mask layer; and The initial dummy channel hole is formed through the initial dummy channel hole pattern.

5. The preparation method according to claim 4, wherein, The preparation method further includes: Remove the hard mask layer; and A dielectric material layer is formed to fill the dummy channel holes and the top selected gate cutout and cover the stacked structure.

6. A method for fabricating a three-dimensional memory, including: A stacked structure is formed on the substrate; In the stacked structure, a plurality of top selection gate cutouts extending toward the substrate and disposed along a first direction are formed. At least one of the top selection gate cutouts includes a plurality of first cutouts disposed along a second direction and a plurality of second cutouts located between adjacent first cutouts. The first direction and the second direction are perpendicular to the stacking direction of the stacked structure and intersect each other. as well as In the region corresponding to the second notch, an initial dummy channel hole extending toward the substrate is formed, wherein the initial dummy channel hole has a spacing distance from the boundary of the second notch; and A virtual channel extending toward the substrate is formed by increasing the cross-sectional dimension of the initial virtual channel in a plane parallel to the substrate and increasing the extension dimension in the direction toward the substrate via the initial virtual channel. In this case, on a plane perpendicular to the stacking direction, the cross-sectional area of ​​the second cut is greater than the cross-sectional area of ​​the dummy channel hole.

7. The preparation method according to claim 6, wherein, The step of forming an initial dummy channel via extending toward the substrate includes: A hard mask layer is formed to fill the top selected gate cutout and cover the stacked structure; An initial dummy channel pattern is formed in the hard mask layer; and The initial dummy channel hole is formed through the initial dummy channel hole pattern.

8. The preparation method according to claim 7, further comprising: Remove the hard mask layer; as well as A dielectric material layer is formed to fill the dummy channel holes and the top selected gate cutout and cover the stacked structure.

9. A three-dimensional memory, including: Semiconductor layer; Stacked structure; Multiple top-select gate cutout structures extend through the stacked structure toward the semiconductor layer and are disposed along a first direction. Each top-select gate cutout structure includes: multiple first cutout structures disposed along a second direction and multiple second cutout structures located between adjacent first cutout structures. The first direction and the second direction are perpendicular to the stacking direction of the stacked structure and intersect each other. A virtual channel structure is formed in the region corresponding to the second notch structure and extends toward the semiconductor layer. In a plane perpendicular to the stacking direction, the cross-sectional area of ​​the second cut structure is greater than the cross-sectional area of ​​the dummy channel structure.

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