A semiconductor device, a manufacturing method thereof, a memory, and a storage system

Abstract

The application discloses a semiconductor device and a preparation method thereof, a memory and a storage system. A stack layer including alternately-stacked interlayer sacrificial layers and interlayer insulating layers is formed on a substrate, and a plurality of rows of first channel holes penetrating through the stack layer are formed. Then, the interlayer sacrificial layers are etched through the first channel holes to form first cavities around the first channel holes. Finally, a gate layer is filled in the first cavities. The application replaces the interlayer sacrificial layers around each hole with the gate layer through the first channel holes, and the process difficulty is low and air gaps are not easily formed.

Description

Technical Field

[0001] This invention relates generally to electronic devices, and more specifically to a semiconductor device and a method for fabricating the same, a memory and a storage system. Background Technology

[0002] Since 3D NAND technology was applied to actual production, people's pursuit of capacity and cost has led to an increase in the number of stacked layers, from 24 layers to the current 100 layers, and in the future 200 and 300 layers.

[0003] As the number of stacked layers increases, and the stacked layers thinner and the channel via size increases, the difficulty of gate layer filling also increases. For example, air gaps are generated during gate layer filling, leading to fluorine diffusion within the gate layer. Fluorine gas in the gate layer diffuses into the upper and lower interlayer insulating layers, into the channel structure, and into the array common source. Fluorine can corrode or attack these structures, causing damage and leading to leakage and failure. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, a memory and a storage system, which aims to reduce the difficulty of filling the gate layer and thus solve the problem of air gaps in the gate layer.

[0005] In a first aspect, the present invention provides a method for fabricating a semiconductor device, the method comprising:

[0006] Provide substrate;

[0007] A stacked layer is formed on the substrate, the stacked layer comprising alternating layers of interlayer sacrificial layers and interlayer insulating layers;

[0008] Multiple rows of first channel holes are formed that penetrate the stacked layers;

[0009] The interlayer sacrificial layer is etched through the first channel hole to form a first cavity around the first channel hole;

[0010] A gate layer is formed in the first cavity.

[0011] More preferably, the multiple rows of first channel holes are divided into multiple groups of first channel holes at intervals, and the distance between adjacent groups of first channel holes is greater than the distance between any two adjacent first channel holes within a first channel hole group.

[0012] More preferably, after the step of etching the interlayer sacrificial layer through the first channel hole, an inter-row support structure is also formed on both sides of the multiple rows of first channel holes.

[0013] More preferably, after forming the inter-row support structure, the preparation method further includes:

[0014] The row support structure is oxidized.

[0015] More preferably, after the step of etching the interlayer sacrificial layer through the first channel hole, a portion of the interlayer sacrificial layer between adjacent groups of the first channel holes is retained to form a plurality of spaced-apart intergroup support structures.

[0016] More preferably, the preparation method further includes:

[0017] At least one second channel hole is formed between any two adjacent groups of the first channel hole groups;

[0018] The interlayer sacrificial layer is etched through the second channel hole to form a second cavity around the second channel hole, the second cavity being in communication with the first cavity;

[0019] The gate layer is formed in the first cavity and the second cavity.

[0020] More preferably, the number of second channel holes between any two adjacent groups of first channel holes is multiple, and the distance between two adjacent second channel holes is greater than the distance between two adjacent first channel holes, and the distance between two adjacent second channel holes is greater than the distance between two adjacent first channel holes and the second channel holes.

[0021] More preferably, the second channel hole separates the inter-group support structure.

[0022] More preferably, after forming the inter-group support structure, the preparation method further includes:

[0023] The inter-group support structure is oxidized.

[0024] More preferably, the multiple rows of first channel holes are evenly divided into multiple groups of first channel hole groups.

[0025] More preferably, the number of the multiple rows of first channel holes is 9 rows, and 3 rows of first channel holes form a group.

[0026] More preferably, prior to the step of forming the gate layer in the first cavity and the second cavity, the fabrication method further includes:

[0027] A first high-K dielectric layer and a first barrier layer are sequentially deposited in the first cavity and the second cavity.

[0028] More preferably, the gate layer has a first side exposed to the first or second channel hole, and the interlayer insulating layer has a second side exposed to the first or second channel hole; after the step of forming the gate layer in the first cavity and the second cavity, the fabrication method further includes:

[0029] A second barrier layer is formed on the first side of the gate layer;

[0030] A second high-K dielectric layer and a spacer insulating layer are sequentially formed on the surface of the second barrier layer and the second side of the interlayer insulating layer.

[0031] More preferably, after the step of sequentially forming a second high-k dielectric layer and a spacer insulating layer on the surface of the second barrier layer and the second side of the interlayer insulating layer, the preparation method further includes: forming a first channel structure and a second channel structure in the first channel hole and the second channel hole, respectively.

[0032] In a second aspect, the present invention provides a semiconductor device, the semiconductor device comprising:

[0033] Substrate;

[0034] A stacked structure located on the substrate, the stacked structure comprising alternately stacked gate layers and interlayer insulating layers;

[0035] The stacked structure has multiple rows of first channel structures, which are divided into multiple groups of first channel structures at intervals.

[0036] A support structure located between two adjacent interlayer insulating layers and connected to the gate layer.

[0037] More preferably, the support structure includes inter-row support structures located on both outer sides of the multi-row first channel structure, and inter-group support structures located between two adjacent groups of the first channel structure.

[0038] More preferably, the inter-group distance between adjacent first channel structure groups is greater than the inter-hole distance between any two adjacent first channel structures within the first channel structure group.

[0039] More preferably, the semiconductor device further includes:

[0040] At least one second channel structure located between any two adjacent groups of the first channel structure;

[0041] The second channel structure separates the inter-group support structure.

[0042] More preferably, the number of second channel structures between any two adjacent groups of first channel structures is multiple, and the distance between two adjacent second channel structures is greater than the hole distance between any two adjacent first channel structures within the first channel structure group; the distance between two adjacent second channel structures is greater than the distance between two adjacent first channel structures and the second channel structure.

[0043] More preferably, the multi-row first channel structure is divided into multiple groups of first channel structure groups.

[0044] More preferably, the number of the multi-row first channel structure is 9 rows, and 3 rows of the first channel structure form a group.

[0045] More preferably, the semiconductor device further includes:

[0046] A first high-k dielectric layer is located between the gate layer and the interlayer insulating layer, and between the gate layer and the support structure;

[0047] A first barrier layer is located between the gate layer and the first high-k dielectric layer.

[0048] More preferably, the semiconductor device further includes:

[0049] A second barrier layer is located between the gate layer and the first channel structure or the second channel structure;

[0050] The second high-K dielectric layer is located between the second barrier layer and the first channel structure or the second channel structure.

[0051] A spacer insulating layer is located between the second high-K dielectric layer and the first or second channel structure, between the interlayer insulating layer and the first or second channel structure, and at the bottom of the first and second channel structures.

[0052] Thirdly, the present invention provides a memory comprising:

[0053] The semiconductor device as described in any one of items 15-23 above;

[0054] The peripheral circuit is electrically connected to the semiconductor device.

[0055] Fourthly, the present invention provides a storage system, comprising:

[0056] The memory as described in the third aspect;

[0057] A controller, electrically connected to the memory, is used to control the memory to store data.

[0058] The beneficial effects of this invention are: it provides a semiconductor device and its fabrication method, a memory, and a memory system. First, a stacked layer comprising alternating layers of interlayer sacrificial layers and interlayer insulating layers is formed on a substrate. Then, multiple rows of first channel vias are formed penetrating the stacked layer. Next, the interlayer sacrificial layers are etched through the first channel vias to form first cavities surrounding the first channel vias. Finally, a gate layer is filled into the first cavity. This invention uses the first channel vias to replace the interlayer sacrificial layers around each via with replacement gate layers, resulting in a lower process difficulty and less likelihood of forming air gaps. Attached Figure Description

[0059] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0060] Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor device provided in this invention.

[0061] Figures 2-6 This is a schematic diagram of the semiconductor device provided in the embodiment of the present invention during the fabrication process;

[0062] Figure 7 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor device along point AA;

[0063] Figure 8 This is provided by the embodiments of the present invention. Figure 4 A schematic diagram of the cross-sectional structure of the semiconductor device along point AA;

[0064] Figure 9 This is provided by the embodiments of the present invention. Figure 5 A schematic diagram of the cross-sectional structure of the semiconductor device along point AA;

[0065] Figures 10-11 This is a schematic diagram of the fabrication process of the semiconductor device provided in the embodiment of the present invention after the formation of the support structure and before the formation of the gate layer;

[0066] Figures 12-14 This is a schematic diagram of the fabrication process of the semiconductor device provided in the embodiment of the present invention after the formation of the gate layer;

[0067] Figure 15 This is a schematic diagram of the arrangement structure of the first channel hole and the second channel hole provided in an embodiment of the present invention;

[0068] Figure 16This is a schematic diagram of the structure of the semiconductor device provided in the embodiment of the present invention;

[0069] Figure 17 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention;

[0070] Figure 18 This is a schematic diagram of the storage system provided in an embodiment of the present invention. Detailed Implementation

[0071] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0072] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0073] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0074] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0075] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate.

[0076] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0077] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor device provided in this invention. Please also refer to... Figures 2-6 , Figures 2-6 This is a schematic diagram of the semiconductor device provided in the embodiment of the present invention during the fabrication process. The fabrication method includes the following steps S1-S6.

[0078] Please see Figure 1 Steps S1-S3 and Figure 2 ,as well as Figure 7 , Figure 7 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor device along point AA. It should be noted that... Figure 2 What is displayed is Figure 7 A schematic diagram of the cross-sectional structure of a semiconductor device along the XY plane parallel to the substrate at the interlayer sacrificial layer.

[0079] Step S1: Provide substrate 10.

[0080] Step S2: A stacked layer 20 is formed on the substrate 10, the stacked layer 20 including an interlayer sacrificial layer 201 and an interlayer insulating layer 202 that are alternately stacked.

[0081] like Figure 7 As shown, the substrate 10 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor substrate can also be a substrate containing other elemental semiconductors or compound semiconductors, and can also be a stacked layer, such as Si / SiGe.

[0082] The stacked layer 20 includes an interlayer insulating layer 202 and an interlayer sacrificial layer 201 alternately stacked along a direction perpendicular to the substrate 10 (Z). The interlayer insulating layer 202 can be silicon oxide, and the interlayer sacrificial layer 201 can be silicon nitride. The interlayer insulating layer 202 and the interlayer sacrificial layer 201 have different etching selectivity. The methods for forming the interlayer insulating layer 202 and the interlayer sacrificial layer 201 include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0083] The interlayer sacrificial layer 201 will be replaced by the gate layer in subsequent processes. The number of stacked layers can be, for example, 8, 32, 64, or even higher (e.g., more than 200 layers). The more layers stacked, the higher the integration density of the memory device. However, the more layers stacked, the smaller the spacing between the channel structures and the thinner the interlayer sacrificial layer 201. The cavity formed after removing the interlayer sacrificial layer 201 through the gate line gap is very small. Therefore, when the gate layer is deposited to a certain thickness on the inner wall of the cavity through the gate line gap, it is easy to seal prematurely, which can easily lead to air gaps.

[0084] Step S3: Form multiple rows of first channel holes 30 penetrating the stacked layer 20.

[0085] In one embodiment, the multiple rows of first channel vias 30 are divided into multiple groups of first channel vias 301 spaced apart. During the process of forming the first channel vias 30, at least one second channel via 40 can be formed simultaneously between any two adjacent groups of first channel vias 301. Therefore, it can be said that the at least one second channel via 40 separates the multiple rows of first channel vias 30 into multiple groups of first channel vias 301. Specifically, a photomask can be used to etch the stacked layer 20 to form the first channel vias 30 and the second channel vias 40 penetrating the stacked layer 20 along a direction perpendicular to the substrate 10 (Z).

[0086] In one specific embodiment, the first channel hole 30 and the second channel hole 40 are arranged as follows: Figure 2 As shown, the number of second channel holes 40 between any two adjacent groups of the first channel hole groups 301 is multiple (e.g., 2). Furthermore, the multiple second channel holes 40 can be arranged in one or more rows. When the second channel holes 40 are arranged in one row or multiple rows and the multiple rows of second channel holes 40 are adjacent, the second channel holes 40 separate the multiple rows of first channel holes 30 into two groups; when the second channel holes 40 are arranged in multiple rows, but each row is distributed between two adjacent groups of the first channel holes 301, the second channel holes 40 separate the multiple rows of first channel holes 30 into at least three groups.

[0087] Furthermore, the multiple rows of first channel holes 30 are evenly divided into multiple groups of first channel hole groups 301. A row of second channel holes 40 can be located between two adjacent groups of first channel hole groups 301. Therefore, when there are a total of 2 rows of second channel holes 40, the multiple rows of first channel holes 30 can be separated into 3 groups.

[0088] For example, in a product with 9 rows of holes, that is, the number of the multiple rows of first channel holes 30 is 9 rows, and the number of second channel holes 40 is 2 rows. These 2 rows of second channel holes 40 can evenly separate the 9 rows of first channel holes 30 into 3 groups, that is, divide the 3 rows of first channel holes 30 into one group.

[0089] In one specific embodiment, the distance between two adjacent groups of the first channel hole groups 301 is equal and equal to the inter-group distance D1; the distance between any two adjacent first channel holes 30 in each group of the first channel hole groups 301 is equal and equal to the inter-hole distance D2; the inter-group distance D1 is greater than the inter-hole distance D2.

[0090] Therefore, in this embodiment, the arrangement of the channel holes is different from the existing arrangement of 9 rows of holes. A second channel hole 40 is added between the multiple rows of first channel holes 30 (dividing the multiple rows of first channel holes 30 into multiple groups of first channel hole groups 301), and the inter-group distance D1 of the first channel hole groups 301 is increased.

[0091] It is understood that, within the first channel hole group 301, the spacing between two adjacent second channel holes 40 is equal to D3. In one specific embodiment, the inter-hole distance D2 between two adjacent first channel holes 30 is less than the distance D3 between two adjacent second channel holes 40. The distance D3 between two adjacent second channel holes 40 is greater than the distance D4 between two adjacent first channel holes 30 and second channel holes 40. That is, the arrangement of the first channel holes 30 is denser, and the arrangement of the second channel holes 40 is sparser, which allows for more space between the second channel holes 40.

[0092] Furthermore, the distance between the second channel hole 40 and the adjacent first channel hole 30 can be equal to the hole distance D2 between two adjacent first channel holes 30 in each group.

[0093] In another embodiment, please refer to Figure 15 , Figure 15 This is a schematic diagram of the arrangement structure of the first and second channel holes provided in an embodiment of the present invention. This embodiment is related to... Figure 2 The difference in the Chinese embodiment is that the number of second channel holes 40 between any two adjacent groups of first channel hole groups 301 is 1.

[0094] Please see Figure 1Step S4 and Figure 3 .

[0095] Step S4: Etch the interlayer sacrificial layer 201 through the first channel hole 30 to form a first cavity around the first channel hole 30.

[0096] In one embodiment, during the process of etching the interlayer sacrificial layer 201 through the first via 30, the interlayer sacrificial layer 201 can be simultaneously etched through the second via 40 to form a second cavity communicating with the first cavity. The first cavity and the second cavity communicate to form cavity 2011.

[0097] Specifically, the etchant enters through the first via 30 and the second via 40 to etch a portion of the interlayer sacrificial layer 201 surrounding the first via 30 and the second via 40. Since the spacing between the first vias 30 in each group of first vias 301 is uniform, the etching time can be controlled to etch the interlayer sacrificial layer 201 around the first vias 30 and the second via 40 to form cavities 2011, which are connected between the interlayer sacrificial layers 201. However, due to the large intergroup distance D1 and the considerable distance between the second vias 40, some interlayer sacrificial layers 201 are not etched. The retained interlayer sacrificial layers 201 form a support structure 2010, which includes: row support structures 2012 located on both outer sides of the multiple rows of first vias 30; and multiple spaced-apart intergroup support structures 2013. Among them, the inter-group support structure 2013 is located between two adjacent groups of first channel hole groups 301, but is separated by the second channel hole 40.

[0098] Among them, the inter-group support structure 2013 and the inter-row support structure 2012 can support the overall structure during the etching process of the inter-layer sacrificial layer 201.

[0099] Please see Figure 4 and Figure 8 , Figure 8 This is provided by the embodiments of the present invention. Figure 4 A schematic diagram of the cross-sectional structure of the semiconductor device along point AA.

[0100] In one embodiment, after step S4, the method for fabricating the semiconductor device may further include: oxidizing the inter-row support structure 2012 and the inter-group support structure 2013 into a support structure 203.

[0101] Specifically, an oxidation process can be used to oxidize the row support structure 2012 and the group support structure 2013 into silicon oxide through the first channel hole 30 and the second channel hole 40, so as to serve as a support structure 203, in order to prevent the interlayer insulating layer 202 from collapsing after the interlayer sacrificial layer 201 is etched.

[0102] The support structure 203 includes: a row support structure 2031 located on both sides of the multiple rows of first channel holes 30; and a group support structure 2032 between the second channel holes 40, wherein the group support structure 2032 is separated by the second channel holes 40.

[0103] It should be noted that, from Figure 8 As can be seen, the middle interlayer insulation layer 202 appears to be suspended because the cross-section is exactly at the channel hole. In fact, each interlayer insulation layer 202 is connected where there is no channel hole.

[0104] Please see Figure 1 Step S5 and Figure 5 ,as well as Figure 9 , Figure 9 This is provided by the embodiments of the present invention. Figure 5 A schematic diagram of the cross-sectional structure of the semiconductor device along point AA.

[0105] Step S5: Form a gate layer 2014 in the first cavity.

[0106] In one embodiment, during the process of forming the gate layer 2014 in the first cavity, the gate layer 2014 can be formed simultaneously in the second cavity, that is, the gate layer 2014 is deposited in the cavity 2011.

[0107] Specifically, a gate layer 2014 (e.g., tungsten) is deposited on the inner wall of the cavity 2011 through the first channel via 30 and the second channel via 40. Since the gate layer 2014 is not deposited on the channel structure, it does not cause premature sealing, and therefore no air gap is generated during the filling process. The material of the gate layer 2014 can include metals such as tungsten (W), and can also include polysilicon or metal silicides, such as metal silicides selected from cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), W, and titanium (Ti). After the gate layer 2014 is formed, the interlayer insulating layer 202 and the gate layer 2014 form a stacked structure 20a.

[0108] like Figure 5 As shown, the second channel hole 40 is also surrounded by a gate layer 2014, so that the gate layers 2014 of all channel holes are connected in the same layer.

[0109] After forming the gate layer 2014, the fabrication method may further include subjecting the gate layer 2014 to high-temperature treatment to release fluorine gas. Specifically, high-temperature treatment may be used to release fluorine gas.

[0110] In one embodiment, prior to step S5, the fabrication method further includes: sequentially depositing a first high-K dielectric layer 50 and a first barrier layer 60 within the cavity 2011, wherein the first high-K dielectric layer 50 contacts the support structure 203 and the interlayer insulating layer 202, and the first barrier layer 60 surrounds the gate layer 2014. The material of the first high-K dielectric layer 50 may include at least one of aluminum oxide (Al2O3) and hafnium oxide (HfO2), and the material of the first barrier layer 60 may be titanium nitride or tungsten nitride.

[0111] Please see Figures 10-11 , Figures 10-11 This is a schematic diagram of the semiconductor device fabrication process provided in this embodiment of the invention, after the formation of the support structure and before the formation of the gate layer.

[0112] like Figure 10 As shown, before step S5, a first high-K dielectric layer 50 and a first barrier material 61 are sequentially deposited in the cavity 2011. The first high-K dielectric layer 50 and the first barrier material 61 also cover the upper surface of the top interlayer insulating layer 202.

[0113] like Figure 11 As shown, a gate material 20141 is then deposited on the surface of the first barrier material 61, the gate material 20141 also covering the upper surface of the top interlayer insulating layer 202.

[0114] When forming the gate layer 2014, for Figure 11 The first barrier material 61 and the gate material 20141 in the cavity 2011 are etched, leaving only the first barrier material 61 and the gate material 20141 located in the cavity 2011. Figure 9 As shown, the first barrier material 61 located in the cavity 2011 serves as the first barrier layer 60, and the gate material 20141 located in the cavity 2011 serves as the gate layer 2014.

[0115] Please see Figures 12-14 , Figures 12-14 This is a schematic diagram of the semiconductor device fabrication process after the formation of the gate layer, as provided in the embodiments of the present invention.

[0116] like Figure 9 As shown, after forming the gate layer 2014, the gate layer 2014 has a first side exposed to the first channel via 30 or the second channel via 40. The interlayer insulating layer 202 has a second side exposed to the first channel via 30 or the second channel via 40. The fabrication method further includes: forming a second barrier layer 70 on the first side of the gate layer 2014. Figure 12 A second high-k dielectric layer 80 is sequentially formed on the surface of the second barrier layer 70 and the second side surface of the interlayer insulating layer 202. Figure 13 ) and spacer insulation layer 90 ( Figure 14 In other words, the second high-K dielectric layer 80 also covers the exposed surface of the first high-K dielectric layer 50.

[0117] In one specific embodiment, the second barrier layer 70 and the second high-K dielectric layer 80 may be located within the cavity 2011 or may just fill the cavity 2011.

[0118] like Figure 14 As shown, after forming the spacer insulating layer 90, a first channel structure 31 and a second channel structure 41 are then formed in the first channel hole 30 and the second channel hole 40, respectively. Figure 14 The second channel structure 41 is not shown in the image; please refer to [link / reference]. Figure 6 When the second barrier layer 70 and the second high-K dielectric layer 80 are located within the cavity 2011, the spacer insulating layer 90 can fill the remaining cavity to flatten the sidewalls of the channel hole, facilitating the subsequent formation of the channel structure on the flat sidewalls. The spacer insulating layer 90 is located between the second high-K dielectric layer 80 and the first channel structure 31 (or the first channel hole 30) or the second channel structure 41 (or the second channel hole 40). The spacer insulating layer 90 is also located between the interlayer insulating layer 202 and the first channel structure 31 (or the first channel hole 30) or the second channel structure 41 (or the second channel hole 40), and the spacer insulating layer 90 is also located at the bottom of the first channel structure 31 (or the first channel hole 30) and the second channel structure 41 (or the second channel hole 40).

[0119] The steps of forming the first channel structure 31 and the second channel structure 41 may specifically include: sequentially forming a storage layer 311 and a channel layer 312 on the surface of the spacer insulating layer 90; and forming a dielectric layer 313 on the surface of the channel layer 312, filling the first channel hole 30 and the second channel hole 40. The storage layer 311 includes a charge blocking layer, a charge trapping layer, and a tunneling layer (not shown in the figure) sequentially formed on the surface of the spacer insulating layer 90. The arrangement of the first channel structure 31 and the second channel structure 41 is as follows: Figure 6 As shown.

[0120] The exemplary materials for the barrier insulating layer and the tunneling insulating layer are silicon oxide and the exemplary material for the charge trapping layer is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The exemplary structure of the channel layer 312 is polycrystalline silicon, and the dielectric layer 313 can be silicon oxide, but it is understood that these layers can be made of other materials.

[0121] In the semiconductor device fabrication method provided by this invention, the increasing number of stacked layers 20 results in high channel hole density, small spacing between them, and a small thickness of the interlayer sacrificial layer 201. This breaks away from the traditional method of replacing the interlayer sacrificial layer 201 with the gate layer 2014 through the gate line gap. Instead, the interlayer sacrificial layer 201 is removed and the gate layer 2014 is filled through the first channel hole 30 and the second channel hole 40. This process effectively solves the problem of air gaps generated during gate layer 2014 filling, thereby reducing the diffusion of fluorine gas from the air gaps and reducing a series of problems caused by fluorine diffusion. Furthermore, in the replacement process from the first channel hole 30 and the second channel hole 40, to avoid the collapse of the interlayer insulating layer 202, this invention redesigns the channel hole arrangement (adding a second channel hole 40 and adjusting the spacing), thereby forming a support structure 203 at larger spacing points during the etching of the interlayer sacrificial layer 201 to achieve a supporting effect.

[0122] In existing technologies, the replacement process using gate line slots involves first forming the channel structure and then removing the interlayer sacrificial layer 201 to fill the gate layer 2014. If the etching time for the interlayer sacrificial layer 201 is too short, it cannot be completely removed, resulting in residue. If the etching time is too long, it may etch into the channel structure, damaging it. The fabrication method provided in this embodiment performs the replacement process before forming the channel structure, thus avoiding damage to the channel structure. Moreover, etching the interlayer sacrificial layer 201 through the channel vias allows for the formation of cavities 2011 connecting the layers in a shorter time, effectively reducing the residue of the interlayer sacrificial layer 201. Furthermore, the fabrication method provided in this embodiment can save on the gate line slot-related processes, allowing the source to be formed using other processes.

[0123] This invention also provides a semiconductor device, which can be fabricated using the method described in the above embodiments. (See also...) Figure 6 and Figure 14 .

[0124] The semiconductor device includes: a substrate 10; a stacked structure 20a located on the substrate 10, the stacked structure 20a including alternating gate layers 2014 and interlayer insulating layers 202; multiple rows of first channel structures 31 penetrating the stacked structure 20a, the multiple rows of first channel structures 31 being divided into multiple groups of first channel structures 301 spaced apart; and a support structure 203 located between two adjacent interlayer insulating layers 202 and connected to the gate layer 2014.

[0125] In one specific embodiment, the support structure 203 includes inter-row support structures 2031 located on both outer sides of the multiple rows of first channel structures 31, and inter-group support structures 2032 located between adjacent groups of first channel structures 301. The material of the support structure 203 can be silicon nitride or silicon oxide.

[0126] The inter-group distance D1 between two adjacent groups of the first channel structure group 301 is greater than the inter-hole distance D2 between any two adjacent first channel structures 31 in each group of the first channel structure group 301.

[0127] In one embodiment, the semiconductor device further includes at least one second channel structure 41 located between any two adjacent groups of the first channel structures 301. The second channel structure 41 separates the inter-group support structure 2032.

[0128] The number of second channel structures 41 between any two adjacent groups of first channel structures 31 is multiple. Furthermore, the distance D3 between two adjacent second channel structures 41 is greater than the hole distance D2 between any two adjacent first channel structures 31 within the first channel structure group 301. The distance D3 between two adjacent second channel structures 41 is greater than the distance D4 between two adjacent first channel structures 31 and two adjacent second channel structures 41.

[0129] In one embodiment, the multiple rows of first channel structures 31 are evenly divided into multiple groups of first channel structure groups 301. For example, the number of multiple rows of first channel structures 31 is 9 rows, with 3 rows of first channel structures 31 forming one group. The second channel structures 41 are 2 rows, with each row of second channel structures 41 located between two adjacent groups of first channel structure groups 301.

[0130] The semiconductor device may further include a first high-k dielectric layer 50 and a first barrier layer 60, wherein the first high-k dielectric layer 50 is located between the gate layer 2014 and the interlayer insulating layer 202, and between the gate layer 2014 and the support structure 203. The first barrier layer 60 is located between the gate layer 2014 and the first high-k dielectric layer 50.

[0131] The semiconductor device may further include: a second barrier layer 70 located between the gate layer 2014 and the first channel structure 31 or the second channel structure 41; a second high-k dielectric layer 80 located between the second barrier layer 70 and the first channel structure 31 or the second channel structure 41; a spacer insulating layer 90 located between the second high-k dielectric layer 80 and the first channel structure 31 or the second channel structure 41, an interlayer insulating layer 202 located between the first channel structure 31 or the second channel structure 41, and the bottom of the first channel structure 31 and the second channel structure 41.

[0132] In this embodiment, the first channel structure 31 includes a storage layer 311, a channel layer 312, and a dielectric layer 313 sequentially located on the surface of the spacer insulating layer 90; the second channel structure 41 includes the storage layer, the channel layer, and the dielectric layer sequentially located on the surface of the spacer insulating layer 90.

[0133] Please see Figure 16 , Figure 16 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention.

[0134] The semiconductor device 100a is based on Figure 14 The structure of the semiconductor device in the product, wherein the semiconductor device 100a is related to... Figure 14 The same reference numerals indicate the same structure, and will not be described again here. This embodiment only applies to semiconductor device 100a and... Figure 14 The differences between semiconductor devices will be explained.

[0135] The substrate at the end of the channel structure 31 in the semiconductor device 100a is removed, and the storage layer 311 at its end is removed to expose the channel layer 312. The semiconductor device 100a also includes a common source layer 10a covering the channel layer 312 and the stacked structure 20a, and a peripheral circuit chip 10b bonded to the side of the stacked structure 20a opposite to the common source layer 10a.

[0136] The semiconductor device provided in this embodiment of the invention has a special arrangement of the first channel structure 31 and the second channel structure 41, so that a support structure 203 can be formed at a large channel hole spacing, so as to reduce the collapse caused by removing the interlayer sacrificial layer 201 through the channel hole.

[0137] Please see Figure 17 , Figure 17 This is a schematic diagram of the structure of a memory provided in an embodiment of the present invention. The memory 500 can be a three-dimensional memory, such as a 3D NAND or 3D NOR memory.

[0138] The memory 500 includes a semiconductor device 501 and peripheral circuitry 502. The semiconductor device 501 can be any of the semiconductor devices described in the above embodiments, and the peripheral circuitry 502 can be a CMOS (Complementary Metal-Oxide-Semiconductor). The peripheral circuitry 502 is electrically connected to the semiconductor device 501 to transmit signals. The peripheral circuitry 502 can be used for logic operations and to control and detect the switching states of each memory cell in the semiconductor device 501 via metal interconnects, thereby enabling data storage and retrieval.

[0139] The semiconductor device 501 includes: a substrate; a stacked structure on the substrate, the stacked structure including alternating gate layers and interlayer insulating layers; multiple rows of first channel structures penetrating the stacked structure, the multiple rows of first channel structures being divided into multiple groups of first channel structures spaced apart; and a support structure located between two adjacent interlayer insulating layers and connected to the gate layer.

[0140] Please see Figure 18 , Figure 18 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. The storage system 600 includes a memory 601 and a controller 602. The memory 601 can be any of the memory in the above embodiments, and the memory 601 can include any of the semiconductor devices in the above embodiments. The controller 602 is electrically connected to the memory 601 and is used to control the memory 601 to store data. The memory 601 can perform data storage operations based on the control of the controller 602.

[0141] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0142] The semiconductor device in the memory 601 includes: a substrate; a stacked structure on the substrate, the stacked structure including alternately stacked gate layers and interlayer insulating layers; multiple rows of first channel structures penetrating the stacked structure, the multiple rows of first channel structures being divided into multiple groups of spaced first channel structures; and a support structure located between two adjacent interlayer insulating layers and connected to the gate layer.

[0143] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: Provide substrate; A stacked layer is formed on the substrate, the stacked layer comprising alternating layers of interlayer sacrificial layers and interlayer insulating layers; Multiple rows of first channel holes are formed that penetrate the stacked layers, and the multiple rows of first channel holes are divided into multiple groups of first channel holes at intervals; The interlayer sacrificial layer is etched through the first channel hole to form a first cavity and an inter-group support structure around the first channel hole. The first cavities around the multiple rows of first channel holes are interconnected. The inter-group support structure is located between two adjacent groups of first channel holes and between two adjacent interlayer insulating layers. A gate layer is formed in the first cavity.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The distance between adjacent first channel hole groups is greater than the distance between any two adjacent first channel holes within the first channel hole group.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, After the step of etching the interlayer sacrificial layer through the first channel hole, an inter-row support structure is also formed on both sides of the multiple rows of first channel holes.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, After forming the inter-row support structure, the preparation method further includes: The row support structure is oxidized.

5. The method for fabricating a semiconductor device according to claim 2, characterized in that, After the step of etching the interlayer sacrificial layer through the first channel hole, a portion of the interlayer sacrificial layer between adjacent groups of the first channel holes is retained to form a plurality of spaced-apart intergroup support structures.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The preparation method further includes: At least one second channel hole is formed between any two adjacent groups of the first channel hole groups; The interlayer sacrificial layer is etched through the second channel hole to form a second cavity around the second channel hole, the second cavity being in communication with the first cavity; The gate layer is formed in the first cavity and the second cavity.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The number of second channel holes between any two adjacent groups of first channel holes is multiple, and the distance between two adjacent second channel holes is greater than the distance between two adjacent first channel holes, and the distance between two adjacent second channel holes is greater than the distance between two adjacent first channel holes and the second channel holes.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, The second channel hole separates the inter-group support structure.

9. The method for fabricating a semiconductor device according to claim 5, characterized in that, After forming the inter-group support structure, the preparation method further includes: The inter-group support structure is oxidized.

10. The method for fabricating a semiconductor device according to claim 6, characterized in that, The multiple rows of first channel holes are divided into multiple groups of first channel hole groups on average.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The number of rows of first channel holes is 9, and 3 rows of first channel holes form a group.

12. The method for fabricating a semiconductor device according to claim 6, characterized in that, Prior to the step of forming the gate layer in the first cavity and the second cavity, the fabrication method further includes: A first high-K dielectric layer and a first barrier layer are sequentially deposited in the first cavity and the second cavity.

13. The method for fabricating a semiconductor device according to claim 6, characterized in that, The gate layer has a first side exposed to the first or second channel hole, and the interlayer insulating layer has a second side exposed to the first or second channel hole; after the step of forming the gate layer in the first cavity and the second cavity, the fabrication method further includes: A second barrier layer is formed on the first side of the gate layer; A second high-K dielectric layer and a spacer insulating layer are sequentially formed on the surface of the second barrier layer and the second side of the interlayer insulating layer.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, After the step of sequentially forming a second high-k dielectric layer and a spacer insulating layer on the surface of the second barrier layer and the second side of the interlayer insulating layer, the preparation method further includes: forming a first channel structure and a second channel structure in the first channel hole and the second channel hole, respectively.

15. A semiconductor device, characterized in that, The semiconductor device includes: Substrate; A stacked structure located on the substrate, the stacked structure comprising alternately stacked gate layers and interlayer insulating layers; The stacked structure has multiple rows of first channel structures, which are divided into multiple groups of first channel structures at intervals, and the gate layers around the multiple rows of first channel structures are interconnected. A support structure located between two adjacent interlayer insulating layers and connected to the gate layer, the support structure including an intergroup support structure located between two adjacent first channel structure groups.

16. The semiconductor device according to claim 15, characterized in that, The support structure includes inter-row support structures located on both sides of the multi-row first channel structure.

17. The semiconductor device according to claim 16, characterized in that, The distance between adjacent first channel structure groups is greater than the distance between holes between any two adjacent first channel structures within the first channel structure group.

18. The semiconductor device according to claim 16, characterized in that, The semiconductor device further includes: At least one second channel structure located between any two adjacent groups of the first channel structure; The second channel structure separates the inter-group support structure.

19. The semiconductor device according to claim 18, characterized in that, The number of second channel structures between any two adjacent groups of first channel structures is multiple, and the distance between two adjacent second channel structures is greater than the hole distance between any two adjacent first channel structures within the first channel structure group; the distance between two adjacent second channel structures is greater than the distance between two adjacent first channel structures and the second channel structure.

20. The semiconductor device according to claim 15, characterized in that, The multi-row first channel structure is divided into multiple groups of first channel structure groups on average.

21. The semiconductor device according to claim 20, characterized in that, The number of the multi-row first channel structure is 9 rows, and 3 rows of the first channel structure form a group.

22. The semiconductor device according to claim 15, characterized in that, The semiconductor device further includes: A first high-k dielectric layer is located between the gate layer and the interlayer insulating layer, and between the gate layer and the support structure; A first barrier layer is located between the gate layer and the first high-k dielectric layer.

23. The semiconductor device according to claim 22, characterized in that, The semiconductor device further includes: A second barrier layer is located between the gate layer and the first channel structure or the second channel structure; The second high-K dielectric layer is located between the second barrier layer and the first channel structure or the second channel structure. A spacer insulating layer is located between the second high-K dielectric layer and the first or second channel structure, between the interlayer insulating layer and the first or second channel structure, and at the bottom of the first and second channel structures.

24. A memory, characterized in that, include: The semiconductor device as described in any one of claims 15-23; The peripheral circuit is electrically connected to the semiconductor device.

25. A storage system, characterized in that, include: The memory as described in claim 24; A controller, electrically connected to the memory, is used to control the memory to store data.

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