Display device

Abstract

A display device is provided. The display device includes a substrate including a first display area, a second display area, and a third display area arranged along a row direction, a first pixel row extending in the row direction on the substrate and including a first pixel circuit portion superposed with the second display area and the third display area, a second pixel row extending in the row direction and including a second pixel circuit portion superposed with the third display area, a display element superposed with the first display area, and a bridge line adjacent to the second pixel row, superposed with the second display area, and connecting the first pixel circuit portion and the display element.

Description

Technical Field

[0001] Some aspects of embodiments of the present invention generally relate to display devices. Background Technology

[0002] Display devices typically include pixel circuitry, driving circuitry, and display elements. The pixel circuitry assembly and the driving circuitry assembly can be formed using the same metal layer. Furthermore, portions of the pixel circuitry can be stacked with the display area of ​​the display device, and portions of the driving circuitry can be stacked with the peripheral area of ​​the display device. The display element is positioned at the pixel circuitry and within the display area of ​​the display device. The driving circuitry provides driving signals to the pixel circuitry, the pixel circuitry provides driving current to the display element, and the display element can generate light to display an image. Efforts have been made to increase the display area where the display element is located.

[0003] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0004] Aspects of some exemplary embodiments of the present disclosure include a display device.

[0005] Additional aspects and features of some embodiments of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0006] A display device according to some embodiments includes: a substrate including a first display area, a second display area, a third display area, a fourth display area, and a fifth display area arranged in a row direction; a circuit layer on the substrate; and a display layer on the circuit layer. The circuit layer may include a plurality of pixel circuit rows extending in the row direction and arranged in the column direction, and the display layer may include a plurality of display element rows extending in the row direction and arranged in the column direction. Each of the odd-numbered pixel circuit rows included in the pixel circuit rows may include a first pixel circuit portion superimposed on a second display area, and each of the even-numbered pixel circuit rows included in the pixel circuit rows may include a second pixel circuit portion superimposed on a fourth display area.

[0007] According to some embodiments, the circuit layer may further include a first driving circuit portion superimposed on the first display area, and each of the odd-numbered display element rows in the display element rows may include a first display element superimposed on the first display area.

[0008] According to some embodiments, the first display element can be connected to the first pixel circuit portion via a first bridge connection.

[0009] According to some embodiments, the first bridge wire can be superimposed on the second display area.

[0010] According to some embodiments, the first bridge connection may be adjacent to the even-numbered pixel circuit rows.

[0011] According to some embodiments, the circuit layer may further include a second driving circuit portion superimposed on the fifth display area, and each of the even-numbered display element rows in the display element rows may include a second display element superimposed on the fifth display area.

[0012] According to some embodiments, the second display element can be connected to the second pixel circuit portion via a second bridge connection.

[0013] According to some embodiments, the second bridge wire can be superimposed on the fourth display area.

[0014] According to some embodiments, the second bridge connection may be adjacent to the odd-numbered pixel circuit rows.

[0015] According to some embodiments, each of the odd-numbered pixel circuit rows may further include a third pixel circuit portion superimposed on the third display area, and each of the odd-numbered display element rows may include a third display element superimposed on the third display area.

[0016] According to some embodiments, the third display element may be connected to the third pixel circuit portion.

[0017] According to some embodiments, each of the even-numbered pixel circuit rows may further include a fourth pixel circuit portion superimposed on the third display area, and each of the even-numbered display element rows in the display element rows may include a fourth display element superimposed on the third display area.

[0018] According to some embodiments, the fourth display element may be connected to the fourth pixel circuit portion.

[0019] According to some embodiments, the circuit layer may also include multiple gate lines connected between the first driving circuit portion and the second driving circuit portion.

[0020] According to some embodiments, the gate line can provide a gate signal to the pixel circuit row.

[0021] According to some embodiments, the circuit layer may further include: a first dummy circuit portion included in each of the odd-numbered pixel circuit rows; and a second dummy circuit portion included in each of the even-numbered pixel circuit rows.

[0022] According to some embodiments, the first dummy circuit portion can be superimposed on the fourth display area, and the second dummy circuit portion can be superimposed on the second display area.

[0023] According to some embodiments, the gate line can provide a gate signal to a first dummy circuit portion and a second dummy circuit portion.

[0024] A display device according to some embodiments includes: a substrate including a first display area, a second display area, and a third display area arranged in a row direction; a first pixel row on the substrate, extending in the row direction, and including a first pixel circuit portion superimposed on the second display area and the third display area; a second pixel row extending in the row direction, and including a second pixel circuit portion superimposed on the third display area; a display element superimposed on the first display area; and a bridging wire adjacent to the second pixel row, superimposed on the second display area, and connecting the first pixel circuit portion and the display element.

[0025] According to some embodiments, the display device may further include a driving circuit portion superimposed on the substrate and the first display area, and the display element may be on the driving circuit portion.

[0026] Therefore, a display device according to some embodiments may include a circuit layer and a display layer on the circuit layer. The circuit layer may include rows of pixel circuits and driving circuit portions, and the display layer may include rows of display elements. The driving circuit portions and rows of display elements may be stacked on top of each other in a first display area and a fifth display area of ​​the display device. Therefore, the display area of ​​the display device can be increased.

[0027] Additionally, the pixel circuit rows may include odd-numbered pixel circuit rows and even-numbered pixel circuit rows. Odd-numbered pixel circuit rows may include a first pixel circuit portion superimposed on a second display area (e.g., the left side of a third display area), and even-numbered pixel circuit rows may include a second pixel circuit portion superimposed on a fourth display area (e.g., the right side of a third display area). The first pixel circuit portion can be connected to a first display element via a first bridge connection, and the second pixel circuit portion can be connected to a second display element via a second bridge connection. On the left side of the odd-numbered pixel circuit rows, a first coupling phenomenon may occur between the driving circuit portion and the first display element; on the right side of the odd-numbered pixel circuit rows, a second coupling phenomenon may occur between the second bridge connection and the gate line. Furthermore, the second coupling phenomenon may occur on the left side of the even-numbered pixel circuit rows, and the first coupling phenomenon may occur on the right side of the even-numbered pixel circuit rows. Therefore, the deviation between the parasitic capacitance of the gate lines in odd-numbered pixel circuit rows and the parasitic capacitance of the gate lines in even-numbered pixel circuit rows can be reduced. Therefore, the brightness difference between the brightness of odd-numbered pixel circuit rows and the brightness of even-numbered pixel circuit rows can be reduced, thus improving defects perceived by horizontal lines on the display device.

[0028] It will be understood that the foregoing general description and the following detailed description are provided as examples, are illustrative, and are intended to provide further explanation of the invention in accordance with the appended claims and their equivalents. Attached Figure Description

[0029] The accompanying drawings illustrate embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0030] Figure 1 This is a plan view showing a display device according to some embodiments.

[0031] Figure 2 This illustrates some embodiments. Figure 1 A cross-sectional view of an example of a stacked structure of a display device.

[0032] Figure 3 It is shown that, according to some embodiments, it includes Figure 1 A circuit diagram of an example of a pixel circuit section and display element in a display device.

[0033] Figure 4 It is shown that, according to some embodiments, it includes Figure 1 A plan view of an example of a circuit layer in a display device.

[0034] Figure 5 It is shown that, according to some embodiments, it includes Figure 1 A plan view of an example of the circuit layer and display layer in a display device.

[0035] Figure 6 According to some embodiments Figure 5 A magnified view of region A.

[0036] Figure 7 According to some embodiments Figure 5 A magnified view of region B.

[0037] Figure 8 It is according to some embodiments along Figure 6 A sectional view taken by line I-I'.

[0038] Figure 9 It is according to some embodiments along Figure 6 The sectional view taken from line II-II'.

[0039] Figure 10 It is shown that, according to some embodiments, it includes Figure 1 A cross-sectional view of an example of a dummy circuit section in a display device.

[0040] Figure 11It is shown that, according to some embodiments, it includes Figure 1 A cross-sectional view of another example of a dummy circuit portion in a display device. Detailed Implementation

[0041] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a more thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms, serving as non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, a particular shape, construction, and characteristic of one embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0042] Unless otherwise stated, the illustrated embodiments are to be understood as providing features of varying details that can be used to implement the inventive concept in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0043] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, etc. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, a particular sequence of processes may be performed differently than the sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0044] When an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0045] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0046] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. The spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture, in addition to those depicted in the drawings. For example, if the device in the drawings is flipped, then an element described as “below” or “under” another element or feature would subsequently be oriented “above” said other element or feature. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, the terms “comprising,” “including,” and / or variations thereof, when used in this specification, indicate the presence of stated features, integrals, steps, operations, elements, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus allowing for the interpretation of inherent biases in measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0049] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0050] Figure 1 This is a plan view showing a display device according to some embodiments. Figure 2 It is shown Figure 1 A cross-sectional view of an example of a stacked structure of a display device. Figure 3 It is shown that it includes Figure 1 A circuit diagram of an example of a pixel circuit section and display element in a display device.

[0051] Reference Figure 1 and Figure 2 According to some embodiments, the display device 10 may include a substrate SUB, a circuit layer 1000, and a display layer 2000.

[0052] The base SUB may include a first display area DA1, a second display area DA2, a third display area DA3, a fourth display area DA4, and a fifth display area DA5. The first display area DA1, the second display area DA2, the third display area DA3, the fourth display area DA4, and the fifth display area DA5 may be arranged side-by-side in a first direction D1. Furthermore, each of the first display area DA1, the second display area DA2, the third display area DA3, the fourth display area DA4, and the fifth display area DA5 may extend in a second direction D2 orthogonal to the first direction D1. For example, the first direction D1 may be a row direction, and the second direction D2 may be a column direction.

[0053] The circuit layer 1000 may be positioned on the substrate SUB. The circuit layer 1000 may include multiple pixel circuit portions (e.g., Figure 4 The pixel circuit portion (PCP) and the driving circuit portion are included. According to some embodiments, the pixel circuit portion (PCP) may be stacked with the second display area DA2, the third display area DA3, and the fourth display area DA4, and the driving circuit portion may be stacked with the first display area DA1 and the fifth display area DA5.

[0054] The pixel circuit section (PCP) can receive drive signals from the drive circuit section. For example, the drive signals can be gate signals (GS), data voltages (DATA), etc. For instance, the gate signal (GS) can include a first gate signal (GW), a second gate signal (GC), a third gate signal (GB), and a transmit control signal (EM). The pixel circuit section (PCP) can provide drive current to the display layer 2000 via bridging connections.

[0055] Display layer 2000 can be positioned on circuit layer 1000. Display layer 2000 can be stacked with first display area DA1, second display area DA2, third display area DA3, fourth display area DA4, and fifth display area DA5. Display layer 2000 may include multiple display elements (e.g., Figure 5 The display element DE. In other words, the display element DE can be stacked with the first display area DA1, the second display area DA2, the third display area DA3, the fourth display area DA4, and the fifth display area DA5. The display element DE can receive drive current from the pixel circuit section PCP. The display element DE can generate light with brightness according to the drive current.

[0056] The driving circuit section can provide driving signals to the pixel circuit section PCP. According to some embodiments, the driving circuit section may include a first gate driver GDV1, a second gate driver GDV2, a data driver DDV, and a controller CON. The first gate driver GDV1 can provide a gate signal to the pixel circuit section PCP. The second gate driver GDV2 can provide a gate signal or a transmit control signal to the pixel circuit section PCP. The data driver DDV can provide a data voltage DATA to the pixel circuit section PCP. The controller CON can control the first gate driver GDV1, the second gate driver GDV2, and the data driver DDV. For example, the first gate driver GDV1 and the second gate driver GDV2 can be formed on a substrate SUB and can be included in circuit layer 1000. The data driver DDV and the controller CON can be formed on a flexible printed circuit board (FPCB) positioned on the substrate SUB.

[0057] A pixel circuit portion PCP and a display element DE electrically connected to the pixel circuit portion PCP can constitute a pixel PX. For example, a first pixel circuit portion PCP1 and a first display element DE1 electrically connected to the first pixel circuit portion PCP1 can constitute a first pixel PX1.

[0058] Pixels PX can be arranged in a matrix structure on the substrate SUB. For example, pixels PX can be classified as a first pixel PX1 superimposed on (or located within) a first display area DA1, a second pixel PX2 superimposed on (or located within) a second display area DA2, a third pixel PX3 superimposed on (or located within) a third display area DA3, a fourth pixel PX4 superimposed on (or located within) a fourth display area DA4, and a fifth pixel PX5 superimposed on (or located within) a fifth display area DA5. However, the number of display areas according to embodiments of the present disclosure is not limited to this. Figure 1 The quantities shown are not limited to those specified in this disclosure, and some embodiments may include additional or fewer display areas without departing from the spirit and scope of embodiments according to this disclosure.

[0059] Furthermore, multiple pixel rows can be defined, and these pixel rows can be divided into odd-numbered pixel rows (ODP) and even-numbered pixel rows (EVP). The odd-numbered pixel rows (ODP) can include odd-numbered pixel circuit rows (e.g., Figure 4 Odd-numbered pixel circuit rows (OPC) and odd-numbered display element rows (e.g., Figure 5Odd-numbered display element rows (ODE). For example, pixel circuit portions (PCP) located in odd-numbered pixel circuit rows (OPC) and display elements (DE) located in odd-numbered display element rows (ODE) can constitute pixels located in odd-numbered pixel rows (ODP). Additionally, even-numbered pixel rows (EVP) can include even-numbered pixel circuit rows (e.g., Figure 4 Even-numbered pixel circuit rows (EPC) and even-numbered display element rows (e.g., Figure 5 (Even-numbered display element rows EDE). For example, the pixel circuit portion PCP located in the even-numbered pixel circuit row EPC and the display element DE located in the even-numbered display element row EDE can constitute a pixel located in the even-numbered pixel row EVP.

[0060] like Figure 2 As shown, the display device 10 may have a structure in which a substrate SUB, a circuit layer 1000, and a display layer 2000 are sequentially stacked. For example, the circuit layer 1000 may be formed by stacking an active pattern 1100, a first conductive pattern 1200, a second conductive pattern 1300, a third conductive pattern 1400, and a fourth conductive pattern 1500. Additionally, the display layer 2000 may be formed by stacking a first electrode 2100, an emitter layer 2200, and a second electrode 2300. Therefore, the circuit layer 1000 and the display layer 2000 may be stacked with a first display region DA1, a second display region DA2, a third display region DA3, a fourth display region DA4, and a fifth display region DA5. For example, a first gate driver GDV1 and a second gate driver GDV2 may be stacked with the display layer 2000 in the first display region DA1 and the fifth display region DA5.

[0061] Reference Figure 3 The first pixel PX1 can generate light through the first pixel circuit portion PCP1 and the first display element DE1. Furthermore, each of the second pixel PX2, the third pixel PX3, the fourth pixel PX4, and the fifth pixel PX5 can have a connection structure substantially the same as that of the first pixel PX1. The connection structure between the first pixel circuit portion PCP1 constituting the first pixel PX1 and the first display element DE1 will be described below.

[0062] According to some embodiments, the first pixel circuit portion PCP1 can be as follows: Figure 3 The diagram shows a plurality of transistors and at least one storage capacitor, but embodiments according to this disclosure are not necessarily limited to... Figure 3 The number, construction, and type of components shown herein, and some embodiments may include additional components, fewer components, or components with different arrangements without departing from the spirit and scope of embodiments according to this disclosure.

[0063] According to some embodiments, for example, the first pixel circuit portion PCP1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST. The first transistor T1 can be referred to as a driving transistor, the second transistor T2 as a switching transistor, the third transistor T3 as a compensation transistor, the fourth transistor T4 as an initialization transistor, the fifth transistor T5 and the sixth transistor T6 as emitter control transistors, and the seventh transistor T7 as an anode initialization transistor.

[0064] The first transistor T1 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1 may be connected to a storage capacitor CST. The first terminal of the first transistor T1 may receive a high power voltage ELVDD. The second terminal of the first transistor T1 may be connected to a sixth transistor T6. The first transistor T1 may generate a drive current based on the high power voltage ELVDD and the data voltage DATA.

[0065] The second transistor T2 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2 can receive a first gate signal GW via a gate line. The first terminal of the second transistor T2 can receive a data voltage DATA. The second terminal of the second transistor T2 can provide the data voltage DATA to the first transistor T1.

[0066] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the second transistor T2 is a PMOS transistor, it can be turned off when the first gate signal GW has a positive voltage level and turned on when the first gate signal GW has a negative voltage level.

[0067] The third transistor T3 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the third transistor T3 may receive a first gate signal GW. The first terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1, and the second terminal of the third transistor T3 may be connected to the gate terminal of the first transistor T1.

[0068] The third transistor T3 can be turned on or off in response to the first gate signal GW. For example, when the third transistor T3 is a PMOS transistor, it can be turned on when the first gate signal GW has a negative voltage level and turned off when the first gate signal GW has a positive voltage level. During the period when the third transistor T3 is turned on in response to the first gate signal GW, it can be diode-connected to the first transistor T1. Therefore, the third transistor T3 can compensate for the threshold voltage of the first transistor T1.

[0069] The fourth transistor T4 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fourth transistor T4 may receive a second gate signal GC. The fourth transistor T4 may transmit an initialization voltage VINT to the gate terminal of the first transistor T1.

[0070] The fourth transistor T4 can be turned on or off in response to the second gate signal GC. For example, when the fourth transistor T4 is a PMOS transistor, it can be turned on when the second gate signal GC has a negative voltage level and turned off when the second gate signal GC has a positive voltage level.

[0071] When the fourth transistor T4 turns on in response to the second gate signal GC, the initialization voltage VINT can be provided to the gate terminal of the first transistor T1. Therefore, the gate terminal of the first transistor T1 can be initialized to the initialization voltage VINT.

[0072] The fifth transistor T5 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5 may receive a transmit control signal EM. The first terminal of the fifth transistor T5 may receive a high power voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first transistor T1. When the fifth transistor T5 is turned on in response to the transmit control signal EM, the fifth transistor T5 may provide the high power voltage ELVDD to the first transistor T1.

[0073] The sixth transistor T6 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6 may receive a transmit control signal EM. The first terminal of the sixth transistor T6 may be connected to the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the first display element DE1. When the sixth transistor T6 is turned on in response to the transmit control signal EM, the sixth transistor T6 can transmit drive current to the first display element DE1 through the first node N1.

[0074] The seventh transistor T7 may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7 may receive a third gate signal GB. The second terminal of the seventh transistor T7 may receive an initialization voltage VINT. The first terminal of the seventh transistor T7 may be connected to a first display element DE1. When the seventh transistor T7 is turned on in response to the third gate signal GB, the seventh transistor T7 may provide the initialization voltage VINT to the first display element DE1. Therefore, the seventh transistor T7 may initialize the first terminal of the first display element DE1 to the initialization voltage VINT.

[0075] The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive a high power voltage ELVDD. During the inactive period of the first gate signal GW, the storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor T1.

[0076] The first display element DE1 may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the first display element DE1 may receive a drive current, and the second terminal may receive a low power voltage ELVSS. The first display element DE1 may generate light with a brightness corresponding to the drive current.

[0077] Figure 4 It is shown that it includes Figure 1 A plan view of an example of a circuit layer in a display device. Figure 5 It is shown that it includes Figure 1 A plan view of an example of the circuit layer and display layer in a display device.

[0078] Reference Figure 4 The circuit layer 1000 may include a pixel circuit row PCR, a first gate driver GDV1, and a second gate driver GDV2.

[0079] The pixel circuit row PCR can be positioned on the substrate SUB and can be superimposed on the second display area DA2, the third display area DA3, and the fourth display area DA4. The pixel circuit row PCR can have a repeating structure. For example, the pixel circuit row PCR can extend in a first direction D1 and can be arranged in a second direction D2.

[0080] The pixel circuit row (PCR) can include odd-numbered pixel circuit rows (OPC) and even-numbered pixel circuit rows (EPC). The odd-numbered pixel circuit row (OPC) can include a first pixel circuit portion (PCP1), a second pixel circuit portion (PCP2), and a first dummy circuit portion (DCP1). The first pixel circuit portion (PCP1) can be superimposed on a second display area (DA2). The second pixel circuit portion (PCP2) can be superimposed on a third display area (DA3). The first dummy circuit portion (DCP1) can be superimposed on a fourth display area (DA4). The first pixel circuit portion (PCP1) and the second pixel circuit portion (PCP2) can be connected to a display element, while the first dummy circuit portion (DCP1) can be unconnected to a display element. Conversely, the even-numbered pixel circuit row (EPC) can include a third pixel circuit portion (PCP3), a fourth pixel circuit portion (PCP4), and a second dummy circuit portion (DCP2). The third pixel circuit portion (PCP3) can be superimposed on the third display area (DA3). The fourth pixel circuit portion (PCP4) can be superimposed on the fourth display area (DA4). The second dummy circuit portion (DCP2) can be superimposed on the second display area (DA2). The third pixel circuit section PCP3 and the fourth pixel circuit section PCP4 can be connected to the display element, while the second dummy circuit section DCP2 can be left unconnected to the display element.

[0081] The first gate driver GDV1 can be stacked with the first display area DA1, and the second gate driver GDV2 can be stacked with the fifth display area DA5. According to some embodiments, the circuit layer 1000 may further include multiple gate lines GL connected between the first gate driver GDV1 and the second gate driver GDV2. The gate lines GL extend in a first direction D1 and can be arranged in a second direction D2. The gate lines GL can extend through the pixel circuit portion PCP and can provide gate signals to the pixel circuit portion PCP. Additionally, although... Figure 4 The diagram illustrates a single gate line GL positioned within a pixel circuit row PCR, but the number of gate lines GL is not limited to this. For example, multiple gate lines GL can be positioned within a pixel circuit row PCR.

[0082] Reference Figure 5 The display layer 2000 may include display element rows DER.

[0083] The display element row DER can be positioned on the circuit layer 1000 and can be superimposed on the first display area DA1, the second display area DA2, and the third display area DA3, or on the third display area DA3, the fourth display area DA4, and the fifth display area DA5. The display element row DER can have a repeating structure. For example, the display element row DER can extend in the first direction D1 and can be arranged in the second direction D2.

[0084] The display element row DER can include odd-numbered display element rows ODE and even-numbered display element rows EDE. The odd-numbered display element row ODE can include a first display element DE1, a second display element DE2, and a third display element DE3. The first display element DE1 can be superimposed on a first display area DA1. The second display element DE2 can be superimposed on a second display area DA2. The third display element DE3 can be superimposed on a third display area DA3. Additionally, the even-numbered display element row EDE can include a fourth display element DE4, a fifth display element DE5, and a sixth display element DE6. The fourth display element DE4 can be superimposed on a third display area DA3. The fifth display element DE5 can be superimposed on a fourth display area DA4. The sixth display element DE6 can be superimposed on a fifth display area DA5.

[0085] Figure 6 yes Figure 5 A magnified view of region A. Figure 7 yes Figure 5 A magnified view of region B. For example, Figure 6 This is an enlarged view showing the odd-numbered and even-numbered pixel rows arranged on the left side of the display device. Figure 7 This is an enlarged view showing the odd-numbered and even-numbered pixel rows arranged on the right side of the display device.

[0086] Reference Figure 6 The pixel circuit section PCP can be connected to the display element DE via a bridge wire.

[0087] For example, the second pixel circuit section PCP2 can be connected to the third display element DE3 via the first connecting pad CPD1. Each of the bridging wires can have substantially the same construction as the first connecting pad CPD1. In other words, the first connecting pad CPD1 and the bridging wires can be connected to... Figure 3 The first node N1 shown corresponds to this. However, while the first connecting pad CPD1 connects the second pixel circuit portion PCP2 and the third display element DE3 that are stacked on top of each other, the bridging wire can connect pixel circuit portions and display elements that are not stacked on top of each other.

[0088] For example, the first bridge wire BRD1 can connect the first pixel circuit portion PCP11 and the first display element DE11 to each other. The second bridge wire BRD2 can connect the first pixel circuit portion PCP12 and the first display element DE12 to each other. The third bridge wire BRD3 can connect the first pixel circuit portion PCP13 and the second display element DE2 to each other. Therefore, the drive current can be transmitted through each of the first bridge wire BRD1, the second bridge wire BRD2, and the third bridge wire BRD3. Therefore, the drive voltage corresponding to the drive current can be applied to each of the first bridge wire BRD1, the second bridge wire BRD2, and the third bridge wire BRD3.

[0089] According to some embodiments, the first bridge wire BRD1, the second bridge wire BRD2, and the third bridge wire BRD3 can be superimposed on the first display area DA1 and the second display area DA2. Additionally, the first bridge wire BRD1, the second bridge wire BRD2, and the third bridge wire BRD3 can be adjacent to the even-numbered pixel row EVP. In other words, the first bridge wire BRD1, the second bridge wire BRD2, and the third bridge wire BRD3 can be adjacent to the even-numbered pixel circuit row EPC.

[0090] Reference Figure 7 The pixel circuit section PCP can be connected to the display element DE via a bridge wire.

[0091] For example, the third pixel circuit section PCP3 can be connected to the fourth display element DE4 via the second connecting pad CPD2. Each of the bridging lines can have substantially the same construction as the second connecting pad CPD2. However, while the second connecting pad CPD2 connects the third pixel circuit section PCP3 and the fourth display element DE4, which are stacked on top of each other, the bridging lines can connect pixel circuit sections and display elements that are not stacked on top of each other.

[0092] For example, the fourth bridge connection BRD4 can connect the fourth pixel circuit section PCP41 and the sixth display element DE61. The fifth bridge connection BRD5 can connect the fourth pixel circuit section PCP42 and the sixth display element DE62. The sixth bridge connection BRD6 can connect the fourth pixel circuit section PCP43 and the fifth display element DE5. Therefore, the drive current can be transmitted through each of the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6. Therefore, the drive voltage corresponding to the drive current can be applied to each of the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6.

[0093] According to some embodiments, the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6 can be stacked with the fourth display area DA4 and the fifth display area DA5. Additionally, the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6 can be adjacent to the odd-numbered pixel row ODP. In other words, the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6 can be adjacent to the odd-numbered pixel circuit row OPC.

[0094] Return to reference Figure 6 and Figure 7On the left side of the odd-numbered pixel row ODP, a first coupling phenomenon may occur between the first gate driver GDV1 and the first display element DE1. On the right side of the odd-numbered pixel row ODP, a second coupling phenomenon may occur between the gate line GL and the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6. Additionally, on the left side of the even-numbered pixel row EVP, a second coupling phenomenon may occur between the gate line GL and the first bridge connection BRD1, the second bridge connection BRD2, and the third bridge connection BRD3. On the right side of the even-numbered pixel row EVP, a first coupling phenomenon may occur between the second gate driver GDV2 and the sixth display element DE6. In other words, both the first and second coupling phenomena may occur in the odd-numbered pixel row ODP, and both may occur in the even-numbered pixel row EVP. Therefore, the deviation between the parasitic capacitance of the gate line GL located in the odd-numbered pixel row ODP and the parasitic capacitance of the gate line GL located in the even-numbered pixel row EVP can be reduced. Furthermore, the second coupling phenomenon can be suppressed by arranging a dummy circuit portion below the bridge connection. Therefore, the deviation between the parasitic capacitance of the gate line GL located in the odd-numbered pixel row ODP and the parasitic capacitance of the gate line GL located in the even-numbered pixel row EVP can be further reduced.

[0095] Figure 8 It is along Figure 6 A sectional view taken by line I-I'. Figure 9 It is along Figure 6 A sectional view taken from line II-II'. For example, Figure 8 This is a cross-sectional view showing the display device 10 superimposed on the third display area DA3. Figure 9 This is a cross-sectional view showing the display device 10 superimposed with the first display area DA1 and the second display area DA2.

[0096] Reference Figure 2 , Figure 3 , Figure 6 and Figure 8 , Figure 8 This can be a cross-sectional view of the display device 10 stacked with the third display area DA3. The substrate SUB can include glass, quartz, plastic, etc. According to some embodiments, the substrate SUB can include plastic, so the display device 10 can have flexible properties. In this case, the substrate SUB can have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. For example, the organic film layer can be formed using an organic material such as polyimide, and the barrier layer can be formed using an inorganic material.

[0097] A buffer layer (BFR) can be positioned on the substrate (SUB). The buffer layer (BFR) can prevent or reduce the diffusion of metal atoms, impurities, or other contaminants from the substrate (SUB) into the active pattern 1100. In addition, the buffer layer (BFR) can control the rate of heat supplied during the crystallization process used to form the active pattern 1100.

[0098] The active pattern 1100 can be positioned on the buffer layer BFR. For example, the active pattern 1100 can be formed of amorphous silicon, polycrystalline silicon, or oxide semiconductor.

[0099] According to some embodiments, the active pattern 1100 may include a first active pattern 1110, a second active pattern 1120, and a third active pattern 1130. The first active pattern 1110, the second active pattern 1120, and the third active pattern 1130 may be connected to each other.

[0100] The first gate insulating layer GI1 may cover the active pattern 1100 and may be positioned on the buffer layer BFR. The first gate insulating layer GI1 may include an insulating material. For example, the first gate insulating layer GI1 may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, etc.

[0101] The first conductive pattern 1200 may be positioned on the first gate insulating layer GI1. The first conductive pattern 1200 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. For example, the first conductive pattern 1200 is silver (“Ag”), silver-containing alloys, molybdenum (“Mo”), molybdenum-containing alloys, aluminum (“Al”), aluminum-containing alloys, aluminum nitride (“AlN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), etc.

[0102] According to some embodiments, the first conductive pattern 1200 may include a first gate electrode 1210, a second gate electrode 1220, and a third gate electrode 1230. For example, a gate line GL may correspond to at least one of the first gate electrode 1210 and the third gate electrode 1230. For example, when a first gate signal GW is provided to the gate line GL, the third gate electrode 1230 may be a portion of the gate line GL. Alternatively, when a light emission control signal EM is provided to the gate line GL, the first gate electrode 1210 may be a portion of the gate line GL.

[0103] According to some embodiments, the first active pattern 1110 and the first gate electrode 1210 can form a sixth transistor T6, the second active pattern 1120 and the second gate electrode 1220 can form a first transistor T1, and the third active pattern 1130 and the third gate electrode 1230 can form a second transistor T2.

[0104] The second gate insulating layer GI2 may cover the first conductive pattern 1200 and may be positioned on the first gate insulating layer GI1. The second gate insulating layer GI2 may include an insulating material.

[0105] The second conductive pattern 1300 can be positioned on the second gate insulating layer GI2. The second conductive pattern 1300 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0106] According to some embodiments, the second conductive pattern 1300 may include a first capacitor electrode 1310. The first capacitor electrode 1310 may be stacked with the second gate electrode 1220 and together with the second gate electrode 1220 may form a storage capacitor CST.

[0107] The interlayer insulating layer (ILD) may cover the second conductive pattern 1300 and may be positioned on the second gate insulating layer GI2. The interlayer insulating layer (ILD) may include an insulating material.

[0108] The third conductive pattern 1400 can be positioned on the interlayer insulating layer (ILD). The third conductive pattern 1400 can include metals, alloys, conductive metal oxides, transparent conductive materials, etc.

[0109] According to some embodiments, the third conductive pattern 1400 may include a first connecting line 1410, a second connecting line 1420, a third connecting line 1430, and a fourth connecting line 1440. The first connecting line 1410 may contact the first active pattern 1110, and the second connecting line 1420 may contact the first active pattern 1110 and the second active pattern 1120. Additionally, the third connecting line 1430 may contact the second active pattern 1120 and the third active pattern 1130, and the fourth connecting line 1440 may contact the third active pattern 1130.

[0110] For example, the fourth connection line 1440 can provide a data voltage DATA to the third active pattern 1130. The data voltage DATA can be transmitted to the second active pattern 1120 based on the first gate signal GW provided to the third gate electrode 1230. The drive current can be generated based on the voltage of the second gate electrode 1220 and the data voltage DATA. The drive current can be transmitted to the first connection line 1410.

[0111] The first via insulating layer VIA1 may cover the third conductive pattern 1400 and may be positioned on the interlayer insulating layer ILD. The first via insulating layer VIA1 may include an organic insulating material. For example, the first via insulating layer VIA1 may include a photoresist, polyacrylic resin, polyimide resin, acrylic resin, etc.

[0112] The fourth conductive pattern 1500 may be positioned on the first via insulating layer VIA1. The fourth conductive pattern 1500 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. According to some embodiments, the fourth conductive pattern 1500 may include a first connection pad CPD1. The first connection pad CPD1 may receive drive current.

[0113] The second via insulating layer VIA2 may cover the fourth conductive pattern 1500 and may be positioned on the first via insulating layer VIA1. The second via insulating layer VIA2 may include an organic insulating material.

[0114] The first electrode 2110 can be positioned on the second via insulating layer VIA2. The first electrode 2110 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. For example, the first electrode 2110 may have an island shape. Drive current can be provided to the first electrode 2110 through the first connecting pad CPD1.

[0115] The pixel defining layer (PDL) can be positioned on the second via insulating layer (VIA2). An opening exposing a portion of the first electrode 2110 can be formed in the pixel defining layer (PDL).

[0116] The emitting layer 2210 can be positioned on the first electrode 2110. The emitting layer 2210 can fill the opening. The emitting layer 2210 can generate light with brightness based on the amount of driving current.

[0117] The second electrode 2300 can be positioned on the emitter layer 2210. The second electrode 2300 may include a metal, alloy, conductive metal oxide, transparent conductive material, etc. For example, the second electrode 2300 may have a plate shape. A low power voltage ELVSS can be provided to the second electrode 2300.

[0118] Reference Figure 2 , Figure 3 , Figure 6 and Figure 9The active pattern 1100 may further include a fourth active pattern 1140, a fifth active pattern 1150, and a sixth active pattern 1160; the first conductive pattern 1200 may further include a fourth gate electrode 1240, a fifth gate electrode 1250, and a sixth gate electrode 1260; the second conductive pattern 1300 may further include a second capacitor electrode 1320; and the third conductive pattern 1400 may further include a fifth connecting line 1450, a sixth connecting line 1460, a seventh connecting line 1470, and an eighth connecting line 1480. Additionally, the first electrode 2120, the pixel defining layer PDL, the emitter layer 2220, and the second electrode 2300 may be positioned on the second via insulating layer VIA2. However, the fourth active pattern 1140, the fifth active pattern 1150, the sixth active pattern 1160, the fourth gate electrode 1240, the fifth gate electrode 1250, the sixth gate electrode 1260, the second capacitor electrode 1320, the fifth connecting line 1450, the sixth connecting line 1460, the seventh connecting line 1470, the eighth connecting line 1480, the first electrode 2120, the pixel defining layer PDL, the emitter layer 2220, and the second electrode 2300 can be referenced above. Figure 8 The corresponding components described are basically the same.

[0119] The fourth conductive pattern 1500 may also include a second bridge wire BRD2. The second bridge wire BRD2 may connect the fifth connecting line 1450 and the first electrode 2120. In other words, the second bridge wire BRD2 may connect the first pixel circuit section PCP12 and the first display element DE12. Drive current can be provided to the first electrode 2120 through the second bridge wire BRD2.

[0120] Additionally, the bridging wire can be positioned on the first via insulating layer VIA1. Therefore, the dummy circuit portion can be formed using an active pattern 1100, a first conductive pattern 1200, a second conductive pattern 1300, and a third conductive pattern 1400 superimposed on the bridging wire. For example, the second dummy circuit portion DCP2 can be formed using an active pattern 1100, a first conductive pattern 1200, a second conductive pattern 1300, and a third conductive pattern 1400 superimposed on the second bridging wire BRD2.

[0121] Figure 10 It is shown that it includes Figure 1 A cross-sectional view of an example of a dummy circuit section in a display device. Figure 11 It is shown that it includes Figure 1 A cross-sectional view of another example of a dummy circuit portion in a display device. For example, Figure 10 and Figure 11 It can be Figure 9 The diagram shown is an enlarged view of region C and can be an example diagram used to explain the structure of the dummy circuit section.

[0122] Reference Figure 2 , Figure 6 and Figure 10 The second dummy circuit section DCP2 may include an active pattern 1100, a first conductive pattern 1200, a second conductive pattern 1300, and a third conductive pattern 1400. For example, the second dummy circuit section DCP2 may include a first dummy active pattern 1111, a second dummy active pattern 1121, a third dummy active pattern 1131, a first dummy gate electrode 1211, a second dummy gate electrode 1221, a third dummy gate electrode 1231, a dummy capacitor electrode 1311, a first dummy connection line 1411, a second dummy connection line 1421, a third dummy connection line 1431, and a fourth dummy connection line 1441. The first dummy active pattern 1111, the second dummy active pattern 1121, the third dummy active pattern 1131, the first dummy gate electrode 1211, the second dummy gate electrode 1221, the third dummy gate electrode 1231, the dummy capacitor electrode 1311, the first dummy connecting line 1411, the second dummy connecting line 1421, the third dummy connecting line 1431, and the fourth dummy connecting line 1441 can be substantially the same as the reference. Figure 8 The described first active pattern 1110, second active pattern 1120, third active pattern 1130, first gate electrode 1210, second gate electrode 1220, third gate electrode 1230, first capacitor electrode 1310, first connection line 1410, second connection line 1420, third connection line 1430, and fourth connection line 1440 correspond to each other. In other words, the data voltage DATA can be provided to the fourth dummy connection line 1441, the transmit control signal EM can be provided to the first dummy gate electrode 1211, and the first gate signal GW can be provided to the third dummy gate electrode 1231.

[0123] The second dummy circuit section DCP2 may not include connection patterns and bridging wires. In other words, the second dummy circuit section DCP2 may not be connected to the display element.

[0124] Reference Figure 2 , Figure 6 and Figure 11 The second dummy circuit portion DCP2 may include a first conductive pattern 1200, a second conductive pattern 1300, and a third conductive pattern 1400. For example, the second dummy circuit portion DCP2 may include a first dummy gate electrode 1211, a third dummy gate electrode 1231, a dummy capacitor electrode 1311, a first dummy connection line 1411, a second dummy connection line 1421, a third dummy connection line 1431, and a fourth dummy connection line 1441. In other words, the second dummy circuit portion DCP2 may not include the first dummy active pattern 1111, the second dummy active pattern 1121, the third dummy active pattern 1131, the second dummy gate electrode 1221, connection patterns, and bridging lines.

[0125] The display device 10 according to some embodiments of the present invention may include a pixel circuit row (PCR), a display element row (DER), and a driving circuit portion. The pixel circuit row (PCR) may include an odd-numbered pixel circuit row (OPC) and an even-numbered pixel circuit row (EPC). The odd-numbered pixel circuit row (OPC) may include a first pixel circuit portion (PCP1) superimposed on a second display area (DA2) and a first dummy circuit portion (DCP1) superimposed on a fourth display area (DA4). The even-numbered pixel circuit row (EPC) may include a second dummy circuit portion (DCP2) superimposed on the second display area (DA2) and a fourth pixel circuit portion (PCP4) superimposed on the fourth display area (DA4). The display element row (DER) may include an odd-numbered display element row (ODE) and an even-numbered display element row (EDE). The odd-numbered display element row (ODE) may include a first display element (DE1) superimposed on a first display area (DA1), and the even-numbered display element row (EDE) may include a sixth display element (DE6) superimposed on a fifth display area (DA5). A first bridge wire (BRD1), a second bridge wire (BRD2), and a third bridge wire (BRD3) may be superimposed on the first display area (DA1) and the second display area (DA2), and may be adjacent to the even-numbered pixel circuit row (EPC). The fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6 can be stacked with the fourth display area DA4 and the fifth display area DA5, and can be adjacent to the odd-numbered pixel circuit OPC. The driving circuit section may include a first gate driver GDV1 stacked with the first display area DA1 and a second gate driver GDV2 stacked with the fifth display area DA5.

[0126] The first coupling phenomenon may occur on the left side of the odd-numbered pixel row ODP, and the second coupling phenomenon may occur on the right side of the odd-numbered pixel row ODP. Furthermore, the second coupling phenomenon may occur on the left side of the even-numbered pixel row EVP, and the first coupling phenomenon may occur on the right side of the even-numbered pixel row EVP. Therefore, the deviation between the parasitic capacitance of the gate line GL located in the odd-numbered pixel row ODP and the parasitic capacitance of the gate line GL located in the even-numbered pixel row EVP can be reduced. Therefore, the brightness difference between the brightness of the odd-numbered pixel row ODP and the brightness of the even-numbered pixel row EVP can be reduced, thus improving the defects perceived by horizontal lines on the display device 10.

[0127] Furthermore, the second dummy circuit section DCP2 can be positioned below the first bridge connection BRD1, the second bridge connection BRD2, and the third bridge connection BRD3, while the first dummy circuit section DCP1 can be positioned below the fourth bridge connection BRD4, the fifth bridge connection BRD5, and the sixth bridge connection BRD6. Because of the positioning of the first dummy circuit section DCP1 and the second dummy circuit section DCP2, the second coupling phenomenon can be suppressed. Therefore, the deviation between the parasitic capacitance of the gate line GL located in the odd-numbered pixel row ODP and the parasitic capacitance of the gate line GL located in the even-numbered pixel row EVP can be further reduced.

[0128] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, and the scope of embodiments according to the invention includes those defined in the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: The substrate includes a first display area, a second display area, a third display area, a fourth display area, and a fifth display area arranged along the row direction; Circuit layer, on the substrate; as well as The display layer, on the circuit layer The circuit layer includes: Multiple rows of pixel circuits extend in the row direction and are arranged along the column direction. The display layer includes: Multiple rows of display elements extend in the row direction and are arranged along the column direction. Each of the odd-numbered pixel circuit rows in the pixel circuit rows includes a first pixel circuit portion that overlaps with the second display area, and Each of the even-numbered pixel circuit rows in the pixel circuit rows includes a second pixel circuit portion that is superimposed on the fourth display area.

2. The display device as claimed in claim 1, wherein, The circuit layer further includes a first driving circuit portion superimposed on the first display area, and Each of the odd-numbered rows of display elements included in the rows of display elements includes a first display element superimposed on the first display area.

3. The display device as claimed in claim 2, wherein, The first display element is connected to the first pixel circuit section via a first bridge wire.

4. The display device as claimed in claim 3, wherein, The first bridging wire is superimposed on the second display area.

5. The display device as claimed in claim 3, wherein, The first bridge wire is adjacent to the even-numbered pixel circuit row.

6. The display device as claimed in claim 3, wherein, The circuit layer also includes a second driving circuit portion superimposed on the fifth display area, and Each of the even-numbered rows of display elements included in the rows of display elements includes a second display element superimposed on the fifth display area.

7. The display device as claimed in claim 6, wherein, The second display element is connected to the second pixel circuit section via a second bridge wire.

8. The display device as claimed in claim 7, wherein, The second bridge wire is superimposed on the fourth display area.

9. The display device as claimed in claim 7, wherein, The second bridge connection is adjacent to the odd-numbered pixel circuit row.

10. The display device as claimed in claim 1, wherein, Each of the odd-numbered pixel circuit rows also includes a third pixel circuit portion superimposed on the third display area, and Each of the odd-numbered rows of display elements included in the rows of display elements includes a third display element superimposed on the third display area.

11. The display device as claimed in claim 10, wherein, The third display element is connected to the third pixel circuit section.

12. The display device as claimed in claim 10, wherein, Each of the even-numbered pixel circuit rows also includes a fourth pixel circuit portion superimposed on the third display area, and Each of the even-numbered rows of display elements included in the rows of display elements includes a fourth display element superimposed on the third display area.

13. The display device as claimed in claim 12, wherein, The fourth display element is connected to the fourth pixel circuit section.

14. The display device as claimed in claim 1, wherein, The circuit layer also includes multiple gate lines connected between the first driving circuit section and the second driving circuit section.

15. The display device as claimed in claim 14, wherein, The gate line provides a gate signal to the pixel circuit row.

16. The display device as claimed in claim 15, wherein, The circuit layer further includes: The first dummy circuit portion is included in each of the odd-numbered pixel circuit rows; and The second dummy circuit portion is included in each of the even-numbered pixel circuit rows.

17. The display device as claimed in claim 16, wherein, The first dummy circuit portion is superimposed on the fourth display area, and The second dummy circuit portion is superimposed on the second display area.

18. The display device as claimed in claim 16, wherein, The gate line provides the gate signal to the first dummy circuit portion and the second dummy circuit portion.

19. A display device, the display device comprising: The substrate includes a first display area, a second display area, and a third display area arranged along the row direction; A first pixel row extends on the substrate in the row direction and includes a first pixel circuit portion superimposed on the second display area and the third display area; The second pixel row extends in the row direction and includes a second pixel circuit portion superimposed on the third display area; The display element is superimposed on the first display area; as well as A bridging wire is placed adjacent to the second pixel row, superimposed on the second display area, and connects the first pixel circuit portion and the display element.

20. The display device of claim 19, further comprising: The driving circuitry is located on the substrate and is superimposed on the first display area. The display element is located on the driving circuit section.

Images