A wafer-level packaged infrared thermopile array sensor and a method for preparing the same

Abstract

The invention discloses a wafer-level packaged infrared thermopile array sensor and a preparation method thereof, which is characterized in that a thermal isolation groove, a through hole and an isolation wall are provided on the sensor wafer, and an isolation wall is provided on the filter wafer, the through hole is connected to the PAD device and introduced to the back of the wafer; the isolation wall is arranged in the thermal isolation groove to surround the thermopile pixel; the thermal isolation groove is arranged between two adjacent thermopile pixels, so that each pixel is isolated by the A isolation wall; the isolation wall is provided with a reflection layer to reflect infrared radiation to the absorption layer of the thermopile pixel, and a bonding layer is provided on the top of the isolation wall, and the two bonding layers bond the sensor wafer and the filter wafer together through vacuum hot pressing to encapsulate into an infrared thermopile array sensor. Compared with the prior art, the present invention has the advantages of reducing thermal crosstalk and infrared radiation crosstalk, improving the energy utilization rate of the sensor, and can be directly applied to the scene where the infrared target is the human body.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS and semiconductor integrated packaging, in particular to a wafer-level packaged infrared thermopile array sensor capable of achieving thermal isolation and infrared radiation isolation and a preparation method thereof. Background Art

[0002] Micro-electro-mechanical systems (MEMS) are developed on the basis of microelectronics manufacturing technology. They integrate a variety of micro-processing technologies and can achieve miniaturization, mass production and low cost of sensors. They have become the object of great development in the country.

[0003] Infrared thermopile sensors use MEMS technology to achieve non-contact measurement of infrared radiation from infrared targets, so they have a large number of applications in human body temperature measurement. Arranging individual infrared thermopile sensors in an array can obtain thermal images of infrared targets.

[0004] The infrared thermopile array sensor of the prior art has the problems of thermal crosstalk and infrared crosstalk, which reduces the resolution of the array sensor and the obtained infrared image has poor clarity and contrast. Resolution is an important metric for measuring images. The thermal crosstalk problem comes from the small spacing between the sensors in the array, which causes heat conduction between the two, and the heat conduction interferes with the signals of the two. Infrared crosstalk is caused by the infrared radiation entering the part between adjacent sensors, then being reflected, and finally entering the absorption layer of other sensors, which causes interference, and the infrared radiation that does not belong to this position enters the absorption layer of the sensor at that position through a series of reflections. Summary of the invention

[0005] The purpose of the present invention is to provide a wafer-level packaged infrared thermopile array sensor and a preparation method thereof in view of the deficiencies in the prior art. A method of arranging a thermal isolation groove and an isolation wall on the infrared thermopile array sensor and etching the back to release the thermopile structure is adopted to reduce thermal crosstalk and infrared radiation crosstalk and improve resolution. A conductive through hole is established through TSV technology, and a PAD of the thermopile sensor is introduced into the back side of the wafer so that it can be connected to a PCB board of a back-end circuit through surface mounting technology. A filter wafer coated with an infrared anti-reflection film and a sensor wafer are wafer-level packaged to greatly reduce the sensor area. The sensor viewing angle can be changed by changing the height of the isolation wall. If the viewing angle is to be further reduced, the present invention establishes an isolation wall on the filter wafer, and the isolation wall of the wafer is bonded to the isolation wall of the sensor wafer to reduce the viewing angle.

[0006] The specific technical scheme for achieving the purpose of the present invention is: a wafer-level packaged infrared thermopile array sensor, comprising an infrared thermopile array sensor composed of a sensor wafer and a filter wafer, wherein the sensor wafer is provided with a thermal isolation groove, a through hole and an A isolation wall, the filter wafer is provided with a B isolation wall, the sensor wafer is bonded to the filter wafer, and packaged into an infrared thermopile array sensor; the through hole is connected to the PAD device of the thermopile sensor and introduced to the back of the wafer; the A isolation wall is arranged in the thermal isolation groove to surround the thermopile pixel; the thermal isolation groove is arranged between two adjacent thermopile pixels, so that each pixel is isolated by the A isolation wall; the wall surfaces of the A isolation wall and the B isolation wall are respectively provided with a reflective layer, and a bonding layer is provided on the top thereof, and the two bonding layers bond the sensor wafer and the filter wafer together through vacuum hot pressing to package into an infrared thermopile array sensor.

[0007] The reflective layer may reflect infrared radiation to the absorber layer of the thermopile pixel.

[0008] The A isolation wall and the B isolation wall are respectively arranged on the two wafers in pairs, and the viewing angle of the infrared thermopile array sensor can be adjusted by changing the height of the isolation wall.

[0009] A method for preparing a wafer-level packaged infrared thermopile array sensor, wherein the preparation of the infrared thermopile array sensor specifically comprises the following steps:

[0010] Step 1: Select a silicon wafer as a sensor wafer and generate a passivation layer on its surface;

[0011] Step 2: Prepare thermal isolation grooves and through holes by dry or wet etching;

[0012] Step 3: Fill the through hole with conductive metal and grow the bottom layer A isolation wall in the thermal isolation groove;

[0013] Step 4: The first thermocouple layer, the insulating layer, the second thermocouple layer and the absorption layer are sequentially generated on the surface of the support layer (passivation layer), and the A isolation wall of the bottom layer also continues to grow in this step;

[0014] Step 5: Continue to grow the A isolation wall to reach the designed height;

[0015] Step 6: Generate an A bonding layer on the top layer of the A isolation wall, and generate an A reflection layer on the wall surface;

[0016] Step 7: Generate a PAD device on the back of the sensor wafer to make electrical connections with the conductive vias;

[0017] Step 8: Select a silicon wafer as a filter wafer, generate a B bonding layer or a B isolation wall on the surface, generate a B reflection layer on the wall surface, and generate a B bonding layer on the top of the wall;

[0018] Step 9: Bond the two bonding layers between the sensor wafer and the filter wafer together by vacuum hot pressing;

[0019] Step 10: Etch a cavity on the back of the sensor wafer to release the structure of the thermopile pixel.

[0020] The through hole is prepared by TSV technology and connected to the PAD device, which introduces the thermopile sensor signal to the back side of the sensor wafer so that it can be connected to the PCB board of the back-end circuit through the surface mounting technology.

[0021] The number of the thermopile pixels depends on the array number of the array sensor, and the thermopile release structure is back-etched.

[0022] The filter wafer is a silicon wafer or a silicon wafer coated with an anti-reflection film, and the transmission band of the anti-reflection film is not limited.

[0023] The A bonding layer and the B bonding layer are made of materials compatible with CMOS process, such as gold or copper.

[0024] The first thermocouple layer is a polysilicon layer, the second thermocouple layer is an aluminum layer; and the absorption layer is a silicon nitride layer.

[0025] The A reflection layer and the B reflection layer are made of materials with high reflectivity to infrared radiation, such as gold.

[0026] The conductive metal is tungsten or aluminum.

[0027] Compared with the prior art, the present invention has the technical effect of reducing thermal crosstalk and infrared radiation crosstalk and significant progress. The thermal isolation groove and isolation wall of the present invention solve the thermal crosstalk and infrared radiation crosstalk, and propose a process flow of integrating the above structure into the thermopile array sensor, so that the sensor itself and the isolation structure are integrated. A coating with good reflectivity for infrared radiation is provided on the isolation wall. If the reflective layer material is gold, since the gold layer has good reflectivity for infrared radiation, when the infrared radiation is incident on the gold layer on the surface of the wall, due to reflection, the infrared rays enter the infrared absorption layer of the thermopile sensor surrounded by it, thereby not only solving the radiation crosstalk but also improving the energy utilization rate of the sensor. At the same time, the wall itself will change the viewing angle of the sensor. By adjusting the height of the wall, the viewing angle can be adjusted. If the viewing angle is to be further reduced, a similar wall can be made for the filter wafer to increase the height of the wall. The reduction in the viewing angle will increase the detection distance of the sensor. And by introducing TSV technology to establish a through hole to lead the signal of the thermopile pixel from the through hole to the back of the sensor wafer, surface mount packaging can be realized. The present invention uses wafer-level packaging to bond the filter wafer to the sensor wafer through vacuum hot pressing. If the average transmittance of the filter is 75% in the range of 5um-14u, and the peak wavelength of infrared radiation of the human body is 10um, the structure can be directly applied to the scene where the infrared target is the human body. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the process flow chart of steps 1 to 5 of the present invention;

[0029] Figure 2 This is a process flow chart of steps 6 to 8 of the present invention;

[0030] Figure 3 It is the process flow chart of steps 9 to 10 of the present invention;

[0031] Figure 4 This is a process flow chart of steps 1 to 5 of Example 1;

[0032] Figure 5 This is a process flow chart of steps 6 to 10 of Example 1;

[0033] Figure 6 This is a process flow chart of steps 11 to 13 of Example 1;

[0034] Figure 7 This is a schematic diagram of the structure of the infrared thermopile array sensor prepared in Example 1;

[0035] Figure 8 This is a process flow chart of steps 1 to 3 of Example 2;

[0036] Fig. 9 This is a process flow chart of steps 4 to 5 of Example 2. DETAILED DESCRIPTION

[0037] See also Figure 1~Figure 3 The present invention comprises: a thermopile pixel 18, an A isolation wall 6, a B isolation wall 16, a thermal isolation groove 3, a filter wafer 15, a through hole 4, a sensor wafer 1, a PAD device 13, an A reflection layer 12, a B reflection layer 22, an A bonding layer 11 and a B bonding layer 21, wherein the thermopile pixel 18 is located on the sensor wafer 1, and each pixel is isolated by the A isolation wall 6; the A isolation wall 6 is located on the sensor wafer 1, and surrounds each thermopile pixel 18; the thermal isolation groove 3 is formed by dry or wet etching, and is located below the A isolation wall 6, and surrounds the thermopile pixel 18. The conductive through hole 4 runs through the entire sensor wafer 1, is located near the thermopile pixel 18 and forms an electrical connection with it, and introduces the signal into the PAD device 13 on the back of the wafer; the B isolation wall 16 is located on the filter wafer 15; the A and B bonding layers 11 and 21 are respectively located on the top layers of the A and B isolation walls 6 and 16, and are used to bond the two isolation walls; the A and B reflective layers 12 and 22 are respectively arranged on the surfaces of the two isolation wall walls; the PAD device 13 is located on the back of the sensor wafer 1 and contacts with the conductive through hole 4 to achieve electrical connection.

[0038] Furthermore, the thermal isolation groove 3 consists of two parts, one part is used to grow the A isolation wall, and the other part is used to achieve thermal isolation and is located in the interval part of adjacent thermopile pixels 18.

[0039] Furthermore, the A isolation wall 6 can be divided into a lower isolation wall and a top isolation wall, and the isolation wall surrounds the thermopile pixel 18 .

[0040] Furthermore, the materials of the two reflective layers 12 and 22 A and B have high infrared reflectivity and are compatible with CMOS technology.

[0041] Furthermore, the sensor wafer 1 is a P-type bulk silicon wafer with a crystal orientation of 100.

[0042] Furthermore, one side of the filter wafer 15 is covered with an infrared anti-reflection film, which selectively passes infrared radiation in a specific band, and the other side of the wafer is used to generate the B isolation wall 16 and the B bonding layer 21.

[0043] Furthermore, the thermopile pixel 18 is composed of a support layer (passivation layer) 2 , a first thermocouple layer 7 , an insulating layer 10 , a second thermocouple layer 8 , an absorption layer 9 and a cavity 17 .

[0044] See also Figure 1In step 4, the support layer 2 is used to support the remaining four layers, and their positions from top to bottom are respectively the absorption layer 9, the second thermocouple layer 8, the insulation layer 10, the first thermocouple layer 7, and the support layer 2. The insulation layer 10 electrically isolates the two thermocouple layers and connects only one end thereof. The absorption layer 9 is used to absorb infrared radiation, and the cavity 17 is located below the support layer 2.

[0045] Furthermore, the through hole 4 is formed by TSV technology and is filled with conductive metal 5. The PAD device 13 is located directly below the through hole 4, and the two are in contact to form an electrical connection, thereby introducing the output signal of the thermopile pixel 18 into the back of the sensor wafer 1, so that it can be connected to the PCB through surface mounting technology.

[0046] See also Figure 1~Figure 3 The preparation process of the present invention specifically comprises the following steps:

[0047] Step 1: Select a silicon wafer as the sensor wafer 1 and generate a passivation layer 2 on the surface, such as Figure 1 As shown in step 1 of ;

[0048] Step 2: obtain the thermal isolation groove 3 and the through hole 4 by dry or wet etching, such as Figure 1 As shown in step 2 of ;

[0049] Step 3: Fill the through hole 4 with conductive metal 5, and grow the bottom layer A isolation wall 6 inside the thermal isolation groove 3, as shown in FIG. Figure 1 As shown in step 3, the conductive metal 5 is tungsten or aluminum;

[0050] Step 4: The first thermocouple layer 7, the second thermocouple layer 8, the absorption layer 9, and the insulating layer 10 are generated on the surface of the support layer 2 (passivation layer). At the same time, the A isolation wall 6 of the bottom layer also continues to grow in this step, as shown in FIG. Figure 1 As shown in step 4 of ;

[0051] Step 5: Continue growing the A isolation wall 6 until it reaches the required height, such as Figure 1 As shown in step 5 of ;

[0052] Step 6: Generate a bonding layer 11 on the top layer of the A isolation wall 6, and then generate a reflective layer 12 on the wall surface of the A isolation wall 6, as shown in FIG. Figure 2 As shown in step 1 of ;

[0053] Step 7: Generate a PAD device 13 on the back of the sensor wafer 1 to form an electrical connection with the through hole 4, such as Figure 2 As shown in step 2 of ;

[0054] Step 8: Generate a B bonding layer 21 or generate a B isolation wall 16 on the uncoated surface of the filter wafer 15 coated with the infrared anti-reflection film, then generate a B bonding layer 21 on the top layer of the B isolation wall 16, and generate a B reflection layer 22 on its wall, such as Figure 2 As shown in step 3 of ;

[0055] Step 9: The sensor wafer 1 and the filter wafer 15 are bonded together by vacuum hot pressing of the two bonding layers A and B, as shown in FIG. Figure 3 As shown in step 1 of ;

[0056] Step 10: Etch a cavity 17 on the back of the sensor wafer 1 to release the structure of the thermopile pixel 18, such as Figure 3 as shown in step 2 of .

[0057] The present invention is further described below in conjunction with the drawings and specific preferred embodiments of the specification, but the scope of protection of the present invention is not limited thereby. The present invention has two implementation forms, one is to build an isolation wall on the sensor wafer, and then vacuum bond it with the filter coated with an anti-reflection film, and finally release the thermopile structure by back etching; the other is to build an isolation wall on the sensor wafer on the basis of the process of the first implementation form, and then build an isolation wall for the filter coated with an anti-reflection film, and then vacuum bond the two, and finally release the thermopile structure by back etching. In this embodiment, the absorption layer and the insulating layer are selected to be silicon nitride, the first thermocouple and the second thermocouple are thermopile pixels of polysilicon and aluminum respectively, the reflective layer, the bonding layer, and the PAD material are gold, and the through-hole filling material is tungsten.

[0058] Embodiment 1:

[0059] See also Figure 4~Figure 6 The preparation process of the present invention is mainly divided into three parts. The first part of the process completes the structure of the thermopile sensor absorption layer, thermocouple, support layer and isolation wall. The process flow is as follows:

[0060] Step 1: Generation of support layer

[0061] First, a silicon dioxide layer 20 is formed on the surface of the sensor wafer 1 by thermal oxidation, and then a silicon nitride layer 19 is deposited by LPCVD. The structure obtained in this step is as follows Figure 4 as shown in step 1 of .

[0062] Step 2: Etching Grooves and Vias

[0063] Through-holes 4 and thermal isolation grooves 3 are formed by dry etching. The structure of this step is as follows: Figure 4 The purpose of the through hole 4 is to lead the thermopile output signal to the back of the wafer, which can be used for surface mount packaging; the purpose of the thermal isolation groove 3 is to achieve thermal isolation between the thermopile pixels 18.

[0064] Step 3: Deposit BPSG

[0065] The BPSG layer 22 is deposited by PECVD to fill the through hole 4 and the thermal isolation groove 3, and then the BPSG layer 22 on the surface is removed by CMP. The structure obtained in this step is as follows: Figure 4 as shown in step 3 of .

[0066] Step 4: Photolithography

[0067] The BPSG layer 22 filled in the through hole 4 is removed by dry etching, and a titanium nitride layer 23 and a tungsten layer 24 are deposited on the surface thereof, so that the middle part of the through hole 4 and the thermal isolation groove 3 is filled with the tungsten layer 24, and then the tungsten layer 24 and the titanium nitride layer 23 on the surface are removed by CMP. The tungsten layer 24 is used as the filling material of the through hole 4, and the titanium nitride layer 23 is used as the barrier layer of tungsten. The structure obtained in this step is as shown in FIG. Figure 4 as shown in step 4 of .

[0068] Step 5: Preparation of the First Thermocouple Layer

[0069] A titanium nitride layer 23 is deposited on the surface by PVD, a polysilicon layer 25 is deposited by LPCVD, the polysilicon layer 25 is flattened by CMP, and the layer is patterned, and the titanium nitride layer 23 and the polysilicon layer 25 except the through hole 4 and the top layer of the wall are etched away. The polysilicon layer 25 except the top layer of the wall is the first thermocouple layer 7. The structure obtained in this step is as follows: Figure 4 as shown in step 5 of .

[0070] Step 6: Preparation of the insulation layer

[0071] The polysilicon layer 25 in step 5 is the first thermocouple layer 7. A layer of silicon nitride is deposited by LPCVD, the surface is flattened by CMP, and then patterned. The silicon nitride above the polysilicon layer 25 is the insulating layer 10 of the thermopile pixel 18, isolating the two thermoelectric materials. The silicon nitride layer other than this is used as part of the A isolation wall 6. The structure obtained in this step is as follows: Figure 5 as shown in step 1 of .

[0072] Step 7: Preparation of the Second Thermocouple Layer

[0073] The surface is cleaned with argon ions, titanium nitride and aluminum layer 21 are deposited by PVD, and then patterned. The structure obtained in this step is as follows: Figure 2-7 The aluminum layer 21 in the dotted box is the second thermocouple layer 8. The aluminum layer 21 above the through hole 4 is electrically connected to the second thermocouple layer 8, and the thermoelectric signal is led to the back of the wafer through the through hole 4. The aluminum layer 21 other than this serves as a part of the isolation wall. The structure obtained in this step is as shown in FIG. Figure 5as shown in step 2 of .

[0074] Step 8: Preparation of the Absorbent Layer

[0075] A layer of silicon nitride is deposited by LPCVD and patterned. The silicon nitride layer on the top of the dotted frame is the absorption layer 9 of the infrared thermopile pixel 18. The silicon nitride layer above the through hole 4 can protect the through hole 4. In addition, the silicon nitride layer as part of the isolation wall also plays a role in protecting the bottom material of the A isolation wall 6. The structure obtained in this step is as follows: Figure 5 as shown in step 3 of .

[0076] Step 9: Preparation of the bonding layer

[0077] A layer of BPSG is deposited by PECVD, the surface is flattened by CMP, and then a layer of titanium nitride and gold is deposited by PVD and patterned, retaining the titanium nitride and gold layer 26 on the top layer of the A isolation wall 6. In addition, all other layers are removed by dry etching. The gold layer 26 will be used for bonding with the filter wafer 15, that is, the A bonding layer 11 set on the top layer of the A isolation wall 6. The structure obtained in this step is as follows: Figure 5 as shown in step 4 of .

[0078] Step 10: Preparation of the reflective layer

[0079] The boron phosphorus silicon glass layer on the surface is etched by wet etching, so that the gold layer 26 is slightly higher than the absorption layer 9 of the thermopile pixel 18, and the surface is covered with a layer of gold by electroplating. At the same time, the wall surface of the exposed A isolation wall 6 is also covered with a layer of gold. The gold layer on the wall surface is the A reflection layer 12. Since gold has a good reflection effect on infrared radiation, when infrared radiation enters the wall, it will be reflected to make the infrared rays enter the absorption layer 9 of the thermopile pixel 18, thereby improving the sensor responsiveness. The structure obtained in this step is as follows: Figure 5 as shown in step 5 of .

[0080] Step 11: Preparation of PAD

[0081] The remaining BPSG is etched away, and a layer of titanium nitride and gold is deposited on the back of the wafer. After patterning, the titanium nitride and gold layers below the through hole 4 are retained and used as the PAD device 13 of the sensor pixel. The titanium nitride and gold layers other than these are etched away by dry etching. At the same time, the A isolation wall 6 is also completely generated in this step. The structure obtained in this step is as shown in FIG. Figure 6 as shown in step 1 of .

[0082] The thermopile pixel 18 and the A isolation wall 6 structure of the unreleased structure are obtained through the above 11 steps. The processing steps of the filter wafer 15 will be described below. In this example, the filter wafer 15 is selected as a 5.5um infrared long-wave pass filter, and the average transmittance in the 7-13nm band is 70%. It consists of two parts, namely, a silicon wafer thinned by back etching technology and an infrared anti-reflection film.

[0083] The second process completes the bonding on the surface of the filter wafer 15, and the process flow is as follows:

[0084] Step 1: On the filter wafer 15 without the infrared anti-reflection film 14, a layer of titanium nitride and gold is deposited by PVD, and the gold layer and titanium nitride layer at a specific position are retained by dry etching. The retained gold layer is used as the B bonding layer 21 for vacuum bonding with the A isolation wall 6 of the sensor wafer 1. The structure obtained in this step is as shown Figure 6 as shown in step 2 of .

[0085] The third part of the process bonds the two wafers and releases the thermopile structure. The process flow is as follows:

[0086] Step 1: B bonding layer 21 on filter wafer 15 is brought into contact with A bonding layer 11 on sensor wafer 1, and the two wafers are bonded by hot pressing vacuum bonding technology. The structure obtained in this step is as follows: Figure 6 as shown in step 3 of .

[0087] Step 2: After bonding, anisotropic wet etching is used to obtain a cavity 17 to form a structure of a thermopile pixel 18. The structure obtained in this step is as follows: Figure 7 shown.

[0088] See also Figure 7 , a wafer-level packaged infrared thermopile array sensor structure is obtained, which can achieve thermal isolation and infrared radiation isolation for any number of arrays.

[0089] Example 2

[0090] The main difference between this embodiment 2 and embodiment 1 is that the B isolation wall is generated on the filter wafer. Compared with embodiment 1, this embodiment can reduce the viewing angle of the array sensor and increase the detection distance. The reduction in viewing angle will also reduce thermal crosstalk and infrared radiation crosstalk. The difference between this embodiment and embodiment 1 is mainly in the filter wafer isolation wall part, so only the process flow of the filter wafer isolation wall is described here, and the other processes are exactly the same as embodiment 1.

[0091] See also Figure 8~Figure 9 The process flow and preparation steps of this embodiment are as follows:

[0092] Step 1: Generate a layer of silicon dioxide and titanium nitride on the surface of the filter wafer 15, then use PECVD to deposit a thick layer of borophosphosilicate glass, and perform patterning. Perform patterning, use dry etching to etch away the borophosphosilicate glass at a specific location, deposit a layer of titanium nitride, then fill the tungsten layer 5 to form a B isolation wall 16, and then deposit a layer of titanium nitride, and pattern the titanium nitride. The structure obtained in this step is as follows: Figure 8 as shown in step 1 of .

[0093] Step 2: Deposit a layer of titanium nitride by PVD, and then deposit a tungsten layer 5 by LPCVD to fill the etched holes, and remove the tungsten layer 5 on the surface by CMP; then deposit a layer of titanium nitride and gold, and perform patterning on them, retaining the corresponding gold and titanium nitride above the tungsten layer 5, to obtain the B isolation wall 16 and its B bonding layer 21. The structure obtained in this step is as follows: Figure 8 as shown in step 2 of .

[0094] Step 3: deposit a layer of gold on the surface and perform patterning on it, retain the gold layer surrounding the tungsten layer 5, and obtain the B reflective layer 12. The structure obtained in this step is as follows: Figure 8 as shown in step 3 of .

[0095] Step 4: Vacuum bonding the filter wafer 15 and the sensor wafer 1. The structure obtained in this step is as follows: Fig. 9 as shown in step 1 of .

[0096] Step 5: After bonding, anisotropic wet etching is used to obtain the cavity 17 to form the structure of the thermopile pixel 18. The structure obtained in this step is as follows: Fig. 9 As shown in step 2 of the above, a wafer-level packaged infrared thermopile array sensor structure is obtained, which can achieve thermal isolation and infrared radiation isolation for any number of arrays.

[0097] The invention adds a thermal isolation groove and an isolation wall on the basis of the existing infrared thermopile array sensor, which can reduce the problem of resolution reduction caused by thermal crosstalk and infrared radiation crosstalk; a conductive through hole is established by TSV technology, and the PAD of the thermopile sensor is introduced into the back side of the wafer, so that it can be connected with the PCB board of the back-end circuit through the surface mounting technology; the thermocouple material of the thermopile sensor is polysilicon and aluminum, the absorption layer is silicon nitride, and the thermopile structure is released by back etching, and the thermopile material is compatible with the CMOS process; the filter wafer coated with an infrared anti-reflection film and the sensor wafer are wafer-level packaged by vacuum bonding technology, which greatly reduces the sensor area; the sensor viewing angle can be changed by changing the height of the isolation wall, and if the viewing angle is to be further reduced, an isolation wall can be established on the filter wafer, and the isolation wall of the wafer is bonded to the isolation wall of the sensor wafer to achieve the reduction of the viewing angle.

[0098] The above is only a further explanation of the present invention and is not intended to limit this patent. Any equivalent implementation of the present invention should be included in the scope of the claims of this patent.

Claims

1. A wafer-level packaged infrared thermopile array sensor, comprising an infrared thermopile array sensor composed of a sensor wafer and a filter wafer, characterized in that The sensor wafer is provided with a thermal isolation groove, a conductive through hole and an isolation wall A, the filter wafer is provided with an isolation wall B, and the sensor wafer and the filter wafer are bonded together through a bonding layer arranged on the two isolation walls to be packaged into an infrared thermopile array sensor; The conductive through hole is connected to the PAD device of the thermopile sensor and introduced into the back of the wafer; the A isolation wall is arranged in the thermal isolation groove to surround the thermopile pixel; the thermal isolation groove is arranged between two adjacent thermopile pixels so that each pixel is isolated by the A isolation wall; the wall surfaces of the A isolation wall and the B isolation wall are respectively provided with a reflective layer, and a bonding layer is provided on the top thereof, and the two bonding layers bond the sensor wafer and the filter wafer together through vacuum hot pressing to encapsulate them into an infrared thermopile array sensor.

2. The wafer-level packaged infrared thermopile array sensor according to claim 1, characterized in that The reflective layer may reflect infrared radiation to the absorber layer of the thermopile pixel.

3. The wafer-level packaged infrared thermopile array sensor according to claim 1, characterized in that The A isolation wall and the B isolation wall are respectively arranged in pairs, and the viewing angle of the sensor can be adjusted by changing the height of the isolation wall.

4. A method for preparing the wafer-level packaged infrared thermopile array sensor according to claim 1, characterized in that The preparation of the infrared thermopile array sensor specifically includes the following steps: Step 1: Generate a passivation layer on the sensor wafer surface; Step 2: Prepare thermal isolation grooves and through holes by dry or wet etching; Step 3: Fill the through hole with conductive metal and grow an isolation wall A in the thermal isolation groove; Step 4: Generate a first thermocouple layer, an insulating layer, a second thermocouple layer, and an absorption layer on the surface of the passivation layer in sequence, while the A isolation wall of the bottom layer continues to grow; Step 5: Continue to grow the A isolation wall of the bottom layer to reach the designed height; Step 6: Generate a reflection layer on the surface of the A isolation wall and generate a bonding layer A on the top of the wall; Step 7: Generate a PAD device on the back of the sensor wafer to make electrical connections with the conductive vias; Step 8: Generate a B bonding layer or generate a B isolation wall on the surface of the filter wafer, generate a B reflection layer on the wall surface, and generate a B bonding layer on the top of the wall; Step 9: Bond the two bonding layers of the sensor wafer and the filter wafer together by vacuum hot pressing; Step 10: Etch a cavity on the back of the sensor wafer to release the structure of the thermopile pixel.

5. The method for preparing the wafer-level packaged infrared thermopile array sensor according to claim 4, characterized in that The first thermocouple layer is a polysilicon layer, the second thermocouple layer is an aluminum layer; and the absorption layer is a silicon nitride layer.

6. The method for preparing the wafer-level packaged infrared thermopile array sensor according to claim 4, characterized in that The filter wafer is a silicon wafer or a silicon wafer coated with an anti-reflection film, and the transmission band of the anti-reflection film is not limited. The sensor wafer is a silicon wafer.

7. The method for preparing the wafer-level packaged infrared thermopile array sensor according to claim 4, characterized in that The through hole is prepared by TSV technology and connected to PAD, which introduces the thermopile sensor signal to the back side of the sensor wafer so that it can be connected to the PCB board of the back-end circuit through surface mounting technology.

8. The method for preparing the wafer-level packaged infrared thermopile array sensor according to claim 4, characterized in that The release of the thermopile pixels is back etching, and the number of thermopile pixels depends on the array number of the array sensor.

9. The method for preparing the wafer-level packaged infrared thermopile array sensor according to claim 4, characterized in that The A bonding layer and the B bonding layer are made of materials compatible with CMOS process.

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